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From: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
To: "Joel Stanley" <joel@jms.id.au>, "Cédric Le Goater" <clg@kaod.org>
Cc: openbmc@lists.ozlabs.org,
	Graeme Gregory <quic_ggregory@quicinc.com>,
	Jamie Iles <quic_jiles@quicinc.com>
Subject: Re: [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1
Date: Wed, 8 Jun 2022 13:35:07 -0700	[thread overview]
Message-ID: <4f8f72fa-6dfc-1617-4e43-5715926f9d96@quicinc.com> (raw)
In-Reply-To: <20220607142845.1123692-1-quic_jaehyoo@quicinc.com>

On 6/7/2022 7:28 AM, Jae Hyun Yoo wrote:
> From: Graeme Gregory <quic_ggregory@quicinc.com>
> 
> Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
> equipped with Aspeed AST2600 BMC SoC.
> 
> Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> ---
> Changes in v3:
> * Dropped compatible string of flash memory - Joel / Cedric
> * Dropped I2C pinctrl settings - Joel
> 
> Changes in v2:
> * Changed vendor name from Nuvia to Qualcomm.
> 
>   arch/arm/dts/Makefile                   |   1 +
>   arch/arm/dts/ast2600-qcom-dc-scm-v1.dts | 172 ++++++++++++++++++++++++
>   2 files changed, 173 insertions(+)
>   create mode 100644 arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8f876a0aa0d7..952c3d776adc 100755
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -687,6 +687,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>   	ast2600-ncsi.dtb \
>   	ast2600-p10bmc.dtb \
>   	ast2600-pfr.dtb \
> +	ast2600-qcom-dc-scm-v1.dts \

Please hold it off. It should have s/dts/dtb/
Will submit v4.

Thanks,
Jae

[...]

      parent reply	other threads:[~2022-06-08 20:35 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-07 14:28 [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1 Jae Hyun Yoo
2022-06-08  6:51 ` Jae Hyun Yoo
2022-06-08 20:35 ` Jae Hyun Yoo [this message]

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