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* [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1
@ 2022-06-07 14:28 Jae Hyun Yoo
  2022-06-08  6:51 ` Jae Hyun Yoo
  2022-06-08 20:35 ` Jae Hyun Yoo
  0 siblings, 2 replies; 3+ messages in thread
From: Jae Hyun Yoo @ 2022-06-07 14:28 UTC (permalink / raw)
  To: Joel Stanley, Cédric Le Goater
  Cc: openbmc, Graeme Gregory, Jae Hyun Yoo, Jamie Iles

From: Graeme Gregory <quic_ggregory@quicinc.com>

Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
equipped with Aspeed AST2600 BMC SoC.

Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
* Dropped compatible string of flash memory - Joel / Cedric
* Dropped I2C pinctrl settings - Joel

Changes in v2:
* Changed vendor name from Nuvia to Qualcomm.

 arch/arm/dts/Makefile                   |   1 +
 arch/arm/dts/ast2600-qcom-dc-scm-v1.dts | 172 ++++++++++++++++++++++++
 2 files changed, 173 insertions(+)
 create mode 100644 arch/arm/dts/ast2600-qcom-dc-scm-v1.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8f876a0aa0d7..952c3d776adc 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -687,6 +687,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	ast2600-ncsi.dtb \
 	ast2600-p10bmc.dtb \
 	ast2600-pfr.dtb \
+	ast2600-qcom-dc-scm-v1.dts \
 	ast2600-s6q.dtb \
 	ast2600-slt.dtb \
 	ast2600-tacoma.dtb
diff --git a/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts b/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
new file mode 100644
index 000000000000..bbfb4c7e9e0d
--- /dev/null
+++ b/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+	model = "Qualcomm DC-SCM V1 BMC";
+	compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	aliases {
+		spi0 = &fmc;
+		spi1 = &spi1;
+		spi2 = &spi2;
+	};
+
+	cpus {
+		cpu@0 {
+			clock-frequency = <800000000>;
+		};
+		cpu@1 {
+			clock-frequency = <800000000>;
+		};
+	};
+};
+
+&uart5 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdrammc {
+	clock-frequency = <400000000>;
+};
+
+&wdt1 {
+	status = "okay";
+};
+
+&wdt2 {
+	status = "okay";
+};
+
+&wdt3 {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mdio4_default>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	ethphy3: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&mac2 {
+	status = "okay";
+	reg = <0x1e670000 0x180>, <0x1e650018 0x4>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&fmc {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fmcquad_default>;
+
+	flash@0 {
+		status = "okay";
+		spi-max-frequency = <133000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+
+	flash@1 {
+		status = "okay";
+		spi-max-frequency = <133000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
+			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
+			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
+
+	flash@0 {
+		status = "okay";
+		spi-max-frequency = <133000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&scu {
+	mac0-clk-delay = <0x1d 0x1c
+			  0x10 0x17
+			  0x10 0x17>;
+	mac1-clk-delay = <0x1d 0x10
+			  0x10 0x10
+			  0x10 0x10>;
+	mac2-clk-delay = <0x0a 0x04
+			  0x08 0x04
+			  0x08 0x04>;
+	mac3-clk-delay = <0x0a 0x04
+			  0x08 0x04
+			  0x08 0x04>;
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1
  2022-06-07 14:28 [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1 Jae Hyun Yoo
@ 2022-06-08  6:51 ` Jae Hyun Yoo
  2022-06-08 20:35 ` Jae Hyun Yoo
  1 sibling, 0 replies; 3+ messages in thread
From: Jae Hyun Yoo @ 2022-06-08  6:51 UTC (permalink / raw)
  To: Joel Stanley, Cédric Le Goater; +Cc: openbmc, Graeme Gregory, Jamie Iles

On 6/7/2022 7:28 AM, Jae Hyun Yoo wrote:
> From: Graeme Gregory <quic_ggregory@quicinc.com>
> 
> Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
> equipped with Aspeed AST2600 BMC SoC.
> 
> Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> ---

Tested it again on a real hardware and QEMU.
Worked with Cedric's patch:
https://lore.kernel.org/openbmc/20220608061455.365123-1-clg@kaod.org/T/#t

Thanks,
Jae

> Changes in v3:
> * Dropped compatible string of flash memory - Joel / Cedric
> * Dropped I2C pinctrl settings - Joel
> 
> Changes in v2:
> * Changed vendor name from Nuvia to Qualcomm.
> 
>   arch/arm/dts/Makefile                   |   1 +
>   arch/arm/dts/ast2600-qcom-dc-scm-v1.dts | 172 ++++++++++++++++++++++++
>   2 files changed, 173 insertions(+)
>   create mode 100644 arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8f876a0aa0d7..952c3d776adc 100755
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -687,6 +687,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>   	ast2600-ncsi.dtb \
>   	ast2600-p10bmc.dtb \
>   	ast2600-pfr.dtb \
> +	ast2600-qcom-dc-scm-v1.dts \
>   	ast2600-s6q.dtb \
>   	ast2600-slt.dtb \
>   	ast2600-tacoma.dtb
> diff --git a/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts b/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
> new file mode 100644
> index 000000000000..bbfb4c7e9e0d
> --- /dev/null
> +++ b/arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
> +/dts-v1/;
> +
> +#include "ast2600-u-boot.dtsi"
> +
> +/ {
> +	model = "Qualcomm DC-SCM V1 BMC";
> +	compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x80000000 0x40000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart5;
> +	};
> +
> +	aliases {
> +		spi0 = &fmc;
> +		spi1 = &spi1;
> +		spi2 = &spi2;
> +	};
> +
> +	cpus {
> +		cpu@0 {
> +			clock-frequency = <800000000>;
> +		};
> +		cpu@1 {
> +			clock-frequency = <800000000>;
> +		};
> +	};
> +};
> +
> +&uart5 {
> +	u-boot,dm-pre-reloc;
> +	status = "okay";
> +};
> +
> +&sdrammc {
> +	clock-frequency = <400000000>;
> +};
> +
> +&wdt1 {
> +	status = "okay";
> +};
> +
> +&wdt2 {
> +	status = "okay";
> +};
> +
> +&wdt3 {
> +	status = "okay";
> +};
> +
> +&mdio {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_mdio4_default>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	ethphy3: ethernet-phy@1 {
> +		reg = <1>;
> +	};
> +};
> +
> +&mac2 {
> +	status = "okay";
> +	reg = <0x1e670000 0x180>, <0x1e650018 0x4>;
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_rgmii3_default>;
> +};
> +
> +&fmc {
> +	status = "okay";
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fmcquad_default>;
> +
> +	flash@0 {
> +		status = "okay";
> +		spi-max-frequency = <133000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +
> +	flash@1 {
> +		status = "okay";
> +		spi-max-frequency = <133000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&spi1 {
> +	status = "okay";
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
> +			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
> +			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
> +
> +	flash@0 {
> +		status = "okay";
> +		spi-max-frequency = <133000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&i2c4 {
> +	status = "okay";
> +};
> +
> +&i2c5 {
> +	status = "okay";
> +};
> +
> +&i2c6 {
> +	status = "okay";
> +};
> +
> +&i2c7 {
> +	status = "okay";
> +};
> +
> +&i2c8 {
> +	status = "okay";
> +};
> +
> +&i2c9 {
> +	status = "okay";
> +};
> +
> +&i2c10 {
> +	status = "okay";
> +};
> +
> +&i2c12 {
> +	status = "okay";
> +};
> +
> +&i2c13 {
> +	status = "okay";
> +};
> +
> +&i2c14 {
> +	status = "okay";
> +};
> +
> +&i2c15 {
> +	status = "okay";
> +};
> +
> +&scu {
> +	mac0-clk-delay = <0x1d 0x1c
> +			  0x10 0x17
> +			  0x10 0x17>;
> +	mac1-clk-delay = <0x1d 0x10
> +			  0x10 0x10
> +			  0x10 0x10>;
> +	mac2-clk-delay = <0x0a 0x04
> +			  0x08 0x04
> +			  0x08 0x04>;
> +	mac3-clk-delay = <0x0a 0x04
> +			  0x08 0x04
> +			  0x08 0x04>;
> +};

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1
  2022-06-07 14:28 [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1 Jae Hyun Yoo
  2022-06-08  6:51 ` Jae Hyun Yoo
@ 2022-06-08 20:35 ` Jae Hyun Yoo
  1 sibling, 0 replies; 3+ messages in thread
From: Jae Hyun Yoo @ 2022-06-08 20:35 UTC (permalink / raw)
  To: Joel Stanley, Cédric Le Goater; +Cc: openbmc, Graeme Gregory, Jamie Iles

On 6/7/2022 7:28 AM, Jae Hyun Yoo wrote:
> From: Graeme Gregory <quic_ggregory@quicinc.com>
> 
> Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
> equipped with Aspeed AST2600 BMC SoC.
> 
> Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> ---
> Changes in v3:
> * Dropped compatible string of flash memory - Joel / Cedric
> * Dropped I2C pinctrl settings - Joel
> 
> Changes in v2:
> * Changed vendor name from Nuvia to Qualcomm.
> 
>   arch/arm/dts/Makefile                   |   1 +
>   arch/arm/dts/ast2600-qcom-dc-scm-v1.dts | 172 ++++++++++++++++++++++++
>   2 files changed, 173 insertions(+)
>   create mode 100644 arch/arm/dts/ast2600-qcom-dc-scm-v1.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8f876a0aa0d7..952c3d776adc 100755
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -687,6 +687,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>   	ast2600-ncsi.dtb \
>   	ast2600-p10bmc.dtb \
>   	ast2600-pfr.dtb \
> +	ast2600-qcom-dc-scm-v1.dts \

Please hold it off. It should have s/dts/dtb/
Will submit v4.

Thanks,
Jae

[...]

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-06-08 20:35 UTC | newest]

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2022-06-07 14:28 [PATCH u-boot v2019.04-aspeed-openbmc v3] ARM: dts: aspeed: add Qualcomm DC-SCM V1 Jae Hyun Yoo
2022-06-08  6:51 ` Jae Hyun Yoo
2022-06-08 20:35 ` Jae Hyun Yoo

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