[PATCH] drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)

[PATCH] drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)

[Monk Liu]

to support SRIOV preemption.

v2:
fix emit_frame_size

Change-Id: I9f3534149b132756e5cd9292d48474e50306936b
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index fdc2cb5..52cb37d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6703,6 +6703,10 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 {
 	uint32_t dw2 = 0;
 
+	if (amdgpu_sriov_vf(ring->adev))
+		gfx_v8_0_ring_emit_ce_meta_init(ring,
+			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
+
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
 		gfx_v8_0_ring_emit_vgt_flush(ring);
@@ -6727,6 +6731,10 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 	amdgpu_ring_write(ring, dw2);
 	amdgpu_ring_write(ring, 0);
+
+	if (amdgpu_sriov_vf(ring->adev))
+		gfx_v8_0_ring_emit_de_meta_init(ring,
+			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
 }
 
 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
@@ -6976,7 +6984,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
 		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
 		128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
 		2 + /* gfx_v8_ring_emit_sb */
-		3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
+		3 + 4 + 29, /* gfx_v8_ring_emit_cntxcntl including vgt flush/meta-data */
 	.emit_ib_size =	4, /* gfx_v8_0_ring_emit_ib_gfx */
 	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
 	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
-- 
2.7.4

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Re: [PATCH] drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)

[Christian König]

Am 17.01.2017 um 04:19 schrieb Monk Liu:
> to support SRIOV preemption.
>
> v2:
> fix emit_frame_size
>
> Change-Id: I9f3534149b132756e5cd9292d48474e50306936b
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Sorry didn't saw this patch before writing my review mail on the set.

This one is Reviewed-by: Christian König <christian.koenig@amd.com>.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index fdc2cb5..52cb37d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6703,6 +6703,10 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
>   {
>   	uint32_t dw2 = 0;
>   
> +	if (amdgpu_sriov_vf(ring->adev))
> +		gfx_v8_0_ring_emit_ce_meta_init(ring,
> +			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
> +
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
>   		gfx_v8_0_ring_emit_vgt_flush(ring);
> @@ -6727,6 +6731,10 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
>   	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
>   	amdgpu_ring_write(ring, dw2);
>   	amdgpu_ring_write(ring, 0);
> +
> +	if (amdgpu_sriov_vf(ring->adev))
> +		gfx_v8_0_ring_emit_de_meta_init(ring,
> +			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
>   }
>   
>   static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
> @@ -6976,7 +6984,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
>   		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
>   		128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
>   		2 + /* gfx_v8_ring_emit_sb */
> -		3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
> +		3 + 4 + 29, /* gfx_v8_ring_emit_cntxcntl including vgt flush/meta-data */
>   	.emit_ib_size =	4, /* gfx_v8_0_ring_emit_ib_gfx */
>   	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
>   	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,


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