[RFC] Add support for Aurora L2 Cache Controller

[RFC] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

Hello,

The purpose of this patch set is to add support for Aurora L2 Cache
Controller used by Armada 370 and Armada XP SoCs. As it was initially
designed by Marvell engineer to be compatible with the ARM L2 Cache
Controller, we chose to reuse the existing code and to just extend it
to support the differences and improvements brought by the Aurora
controller.The diffstat looks like:

 Documentation/devicetree/bindings/arm/l2cc.txt  |    9 +
 arch/arm/boot/dts/armada-370.dtsi               |    6 +
 arch/arm/boot/dts/armada-xp.dtsi                |    7 +
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 ++++
 arch/arm/include/asm/hardware/cache-l2x0.h      |    1 +
 arch/arm/mach-mvebu/Kconfig                     |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c         |    4 +
 arch/arm/mm/cache-l2x0.c                        |  297 +++++++++++++++++++++--
 8 files changed, 362 insertions(+), 14 deletions(-)

The main differences and improvements are:

- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller 'outer cache' and 'system cache' (the
  last one meaning maintenance operations on L1 are broadcasted to the
  L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved
  and can be done on a range inside a page and are not limited to a
  cache line.
- during resume the controller need to restore the ctrl register.

The first patch adds some modifications in the driver
infrastructure. As most of the outer cache functions can use the
Aurora improvements, we had to introduce new functions. So we thought
it was better to use a outer_cache_fns field inside l2x0_of_data and
just memcopy it into outer_cache depending of the type of the l2x0
cache.

If the change we have made in the l2x0 driver are judged too invasive
we are perfectly fine to submit a dedicated driver for the Aurora
Cache Controller.

For interested people you can find the results of the cache benchmarks
which was ran for validate the driver:
htps://github.com/MISL-EBU-System-SW/mainline-public/wiki/Cache-bench-results-for-Aurora-L2-cache-controller-on-Armada-XP-and-Armada-370

All the data related to this benchmark are hosted at:
http://free-electrons.com/%7Egregory/pub/Armada-370-xp/cachebench-results/

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Regards,

Gregory

[RFC 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data

[Gregory CLEMENT]

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/mm/cache-l2x0.c |   38 ++++++++++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380..3591940 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -39,7 +39,7 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
@@ -376,6 +376,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
+#ifndef CONFIG_OF
 	outer_cache.inv_range = l2x0_inv_range;
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
@@ -383,6 +384,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+#endif
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -533,15 +535,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
@@ -583,7 +604,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 
 	l2x0_init(l2x0_base, aux_val, aux_mask);
 
-	outer_cache.resume = data->resume;
+	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
 	return 0;
 }
 #endif
-- 
1.7.9.5

[RFC 2/6] arm: cache-l2x0: add an optional register to save/restore

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c4c87bc..5f2c7b4 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -126,6 +126,7 @@ struct l2x0_regs {
 	unsigned long filter_end;
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
+	unsigned long ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
-- 
1.7.9.5

[RFC 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/boot/dts/armada-370.dtsi |    6 ++++++
 arch/arm/boot/dts/armada-xp.dtsi  |    7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..43fa832 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-with-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
 
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..f045a63 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,13 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-no-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
+
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021870 0x58>;
-- 
1.7.9.5

[RFC 4/6] arm: mvebu: add L2 cache support

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/mach-mvebu/Kconfig             |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..e20c5e9 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CACHE_L2X0
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..570be84 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -130,4 +131,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }
-- 
1.7.9.5

[RFC 6/6] arm: l2x0: add aurora related properties to OF binding

[Gregory CLEMENT]

Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 7ca5216..1e41b8e 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-cache-no-outer": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,aurora-cache-with-outer": Marvell Controller designed to
+	be compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example:
 
-- 
1.7.9.5

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 +++++
 arch/arm/mm/cache-l2x0.c                        |  259 ++++++++++++++++++++++-
 2 files changed, 304 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/hardware/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
new file mode 100644
index 0000000..65dad20
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -0,0 +1,51 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3591940..25a41df 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-aurora-l2.h>
 
 #define CACHE_LINE_SIZE		32
 
@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -275,6 +281,130 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	unsigned long range_end;
+
+	BUG_ON(start & (CACHE_LINE_SIZE - 1));
+	BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+	/*
+	 * Try to process all cache lines between 'start' and 'end'.
+	 */
+	range_end = end;
+
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (range_end > start + MAX_RANGE_SIZE)
+		range_end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+		range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+	return range_end;
+}
+
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	/*
+	 * Make sure 'start' and 'end' reference the same page, as
+	 * L2 is PIPT and range operations only do a TLB lookup on
+	 * the start address.
+	 */
+	BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * Clean and invalidate partial first cache line.
+	 */
+	if (start & (CACHE_LINE_SIZE - 1)) {
+		writel((start & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+	}
+
+	/*
+	 * Clean and invalidate partial last cache line.
+	 */
+	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
+		writel((end & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		end &= ~(CACHE_LINE_SIZE - 1);
+	}
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+
+	dsb();
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+
+	dsb();
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+	dsb();
+}
+
+
 
 static void l2x0_disable(void)
 {
@@ -292,11 +422,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +449,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = 3;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -340,6 +481,30 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+
+		switch ((aux >> 13) & 0xf) {
+		case 3:
+			ways = 4;
+			break;
+		case 7:
+			ways = 8;
+			break;
+		case 11:
+			ways = 16;
+			break;
+		case 15:
+			ways = 32;
+			break;
+		default:
+			ways = 8;
+			break;
+		}
+		way_size_shift = 2;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -353,7 +518,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -489,6 +655,12 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
@@ -534,6 +706,48 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	u32 u;
+
+	u = readl(l2x0_base + L2X0_CTRL);
+	if (!(u & 1)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands()
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= 0x100;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -565,10 +779,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-cache-no-outer",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-cache-with-outer",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -597,6 +838,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5

[RFC] Add support for Aurora L2 Cache Controller

[Catalin Marinas]

On 8 August 2012 16:05, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> - two flavors of the controller 'outer cache' and 'system cache' (the
>   last one meaning maintenance operations on L1 are broadcasted to the
>   L2 and L2 performs the same operation).

BTW, is the DSB also transparently handled by the L2 in 'system cache' mode?

-- 
Catalin

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Will Deacon]

On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
> +static void aurora_pa_range(unsigned long start, unsigned long end,
> +                       unsigned long offset)
> +{

This controller is used by Armada XP right? I think that SoC supports LPAE,
so please tell me that the above is a mistake and the controller can support
physical addresses > 32 bits!

If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
instead of unsigned longs.

Will

[RFC] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

On 08/08/2012 05:05 PM, Gregory CLEMENT wrote:
> Hello,
> 
> The purpose of this patch set is to add support for Aurora L2 Cache

I am surprised because all the patches are awaiting for moderator approval
with the reason "Message has a suspicious header".
As I used the same "git send-email" command as for my previous
submissions I am puzzled.

I hope to receive an explanation soon to be able to fix it.

Now waiting for the arrivals of the patches, the commits are still
available on branch aurora-L2-cache-ctrl located at
https://github.com/MISL-EBU-System-SW/mainline-public.git

regards,

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 08/08/2012 05:19 PM, Will Deacon wrote:
> On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
>> +static void aurora_pa_range(unsigned long start, unsigned long end,
>> +                       unsigned long offset)
>> +{
> 
> This controller is used by Armada XP right? I think that SoC supports LPAE,
> so please tell me that the above is a mistake and the controller can support
> physical addresses > 32 bits!

Yes indeed this SoC support LPAE.

> 
> If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
> instead of unsigned longs.

Ok I will look at this.

> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
> On 08/08/2012 05:19 PM, Will Deacon wrote:
>> On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
>>> +static void aurora_pa_range(unsigned long start, unsigned long end,
>>> +                       unsigned long offset)
>>> +{
>>
>> This controller is used by Armada XP right? I think that SoC supports LPAE,
>> so please tell me that the above is a mistake and the controller can support
>> physical addresses > 32 bits!
> 
> Yes indeed this SoC support LPAE.

Well Armada XP supports LPAE but don't use any outer cache functions, he works
with the Aurora cache controller on 'system cache'.
Armada 370 uses this outer cache functions but doesn't support LPAE.

But it seem possible to use the Aurora controller as an 'outer cache' on an
Armada XP. In this case we need to handle this case, even if I am not sure when
someone wanted to select this use case.

> 
>>
>> If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
>> instead of unsigned longs.
> 
> Ok I will look at this.
> 
>>
>> Will
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
> 
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl)

[Gregory CLEMENT]

Hi Will,

You will find an updated version of this patch with LPAE support. I've
tested with and without LPAE selected.

Now I get some warning during compilation: "initialization from
incompatible pointer type [enabled by default]"

It is because the outer_cache_fns struct still embed functions with
unsigned long for address instead of phys_addr_t. You are aware of
it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions".

So a first step would be to update the definitions in struct
outer_cache_fns and also in the files using this prototype, I found
only 4 files:

git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
arch/arm/mm/cache-feroceon-l2.c:
arch/arm/mm/cache-l2x0.c:
arch/arm/mm/cache-tauros2.c:
arch/arm/mm/cache-xsc3l2.c:

But it is not enough we also fixed the call to theses functions:
git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
arch/arm/include/asm/outercache.h
arch/arm/kernel/smp.c
arch/arm/kernel/suspend.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-highbank/highbank.c
arch/arm/mach-msm/platsmp.c
arch/arm/mach-omap2/omap-secure.c
arch/arm/mach-ux500/platsmp.c
arch/arm/mm/dma-mapping.c
arch/arm/mm/fault-armv.c
arch/arm/plat-versatile/platsmp.c

Most of them use __pa or directly __virt_to_phys, so once the patch
"[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
conversion" will be merged the correct type will be used.

Finally the last file which need some change will be
arch/arm/mm/dma-mapping.c.

Does it sound correct?

If it does, then I can prepare a patch for it.

Regards,

Gregory

[RFC 2 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 +++++
 arch/arm/mm/cache-l2x0.c                        |  274 ++++++++++++++++++++++-
 2 files changed, 319 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/hardware/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
new file mode 100644
index 0000000..65dad20
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -0,0 +1,51 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3591940..036ad71 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,14 +25,33 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-aurora-l2.h>
 
 #define CACHE_LINE_SIZE		32
 
+#ifdef CONFIG_ARM_LPAE
+/*
+ * On Aurora if LPAE is activated then when writting in a 32bits
+ * adress in regsiter actual physical address is
+ * {bits[3:0],bits[31:5],00000}. And if not bits[4:0] must be set to
+ * 0x0.
+ */
+
+#define AURORA_LPAE(addr)   ((((addr)>>32)&0xf)|((addr)&~0xf))
+#else
+#define AURORA_LPAE(addr)   (addr)
+#endif
+
 static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -275,6 +294,132 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static phys_addr_t calc_range_end(phys_addr_t start, phys_addr_t end)
+{
+	phys_addr_t range_end;
+
+	BUG_ON(start & (CACHE_LINE_SIZE - 1));
+	BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+	/*
+	 * Try to process all cache lines between 'start' and 'end'.
+	 */
+	range_end = end;
+
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (range_end > start + MAX_RANGE_SIZE)
+		range_end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+		range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+	return range_end;
+}
+
+static void aurora_pa_range(phys_addr_t start, phys_addr_t end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	/*
+	 * Make sure 'start' and 'end' reference the same page, as
+	 * L2 is PIPT and range operations only do a TLB lookup on
+	 * the start address.
+	 */
+	BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+
+
+	writel_relaxed(AURORA_LPAE(start), l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel_relaxed(AURORA_LPAE(end), l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(phys_addr_t start, phys_addr_t end)
+{
+	/*
+	 * Clean and invalidate partial first cache line.
+	 */
+	if (start & (CACHE_LINE_SIZE - 1)) {
+		writel_relaxed(AURORA_LPAE((start & ~(CACHE_LINE_SIZE - 1)) & ~0x1f),
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+	}
+
+	/*
+	 * Clean and invalidate partial last cache line.
+	 */
+	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
+		writel_relaxed(AURORA_LPAE((end & ~(CACHE_LINE_SIZE - 1)) & ~0x1f),
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		end &= ~(CACHE_LINE_SIZE - 1);
+	}
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		phys_addr_t range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+
+	dsb();
+}
+
+static void aurora_clean_range(phys_addr_t start, phys_addr_t end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			phys_addr_t range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+
+	dsb();
+}
+
+static void aurora_flush_range(phys_addr_t start, phys_addr_t end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			phys_addr_t range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+	dsb();
+}
+
+
 
 static void l2x0_disable(void)
 {
@@ -292,11 +437,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +464,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = 3;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -340,6 +496,30 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+
+		switch ((aux >> 13) & 0xf) {
+		case 3:
+			ways = 4;
+			break;
+		case 7:
+			ways = 8;
+			break;
+		case 11:
+			ways = 16;
+			break;
+		case 15:
+			ways = 32;
+			break;
+		default:
+			ways = 8;
+			break;
+		}
+		way_size_shift = 2;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -353,7 +533,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -489,6 +670,12 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
@@ -534,6 +721,48 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	u32 u;
+
+	u = readl(l2x0_base + L2X0_CTRL);
+	if (!(u & 1)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= 0x100;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -565,10 +794,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-cache-no-outer",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-cache-with-outer",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -597,6 +853,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5

LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl)

[Will Deacon]

On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
> Hi Will,

Hi Gregory,

> You will find an updated version of this patch with LPAE support. I've
> tested with and without LPAE selected.

Thanks for the patches.

> Now I get some warning during compilation: "initialization from
> incompatible pointer type [enabled by default]"
> 
> It is because the outer_cache_fns struct still embed functions with
> unsigned long for address instead of phys_addr_t. You are aware of
> it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
> use phys_addr_t instead of unsigned long in outercache functions".

Correct, I just fixed up the wrapper functions in that patch since no outer
cache implementations required >32 bits of physical address. You're the
lucky guy with the first implementation of such a controller :)

> So a first step would be to update the definitions in struct
> outer_cache_fns and also in the files using this prototype, I found
> only 4 files:
> 
> git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
> arch/arm/mm/cache-feroceon-l2.c:
> arch/arm/mm/cache-l2x0.c:
> arch/arm/mm/cache-tauros2.c:
> arch/arm/mm/cache-xsc3l2.c:
> 
> But it is not enough we also fixed the call to theses functions:
> git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
> arch/arm/include/asm/outercache.h
> arch/arm/kernel/smp.c
> arch/arm/kernel/suspend.c
> arch/arm/mach-exynos/platsmp.c
> arch/arm/mach-highbank/highbank.c
> arch/arm/mach-msm/platsmp.c
> arch/arm/mach-omap2/omap-secure.c
> arch/arm/mach-ux500/platsmp.c
> arch/arm/mm/dma-mapping.c
> arch/arm/mm/fault-armv.c
> arch/arm/plat-versatile/platsmp.c
> 
> Most of them use __pa or directly __virt_to_phys, so once the patch
> "[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
> conversion" will be merged the correct type will be used.

Which patch is this? part of the keystone series?

> Finally the last file which need some change will be
> arch/arm/mm/dma-mapping.c.
> 
> Does it sound correct?
> 
> If it does, then I can prepare a patch for it.

Yes please, that sounds like the right direction for this. We should use
phys_addr_t wherever we're dealing with physical addresses.

Cheers,

Will

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Will Deacon]

On Wed, Aug 08, 2012 at 05:52:20PM +0100, Gregory CLEMENT wrote:
> On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
> > Yes indeed this SoC support LPAE.
> 
> Well Armada XP supports LPAE but don't use any outer cache functions, he works
> with the Aurora cache controller on 'system cache'.
> Armada 370 uses this outer cache functions but doesn't support LPAE.

Can the Armada 370 be configured to use the co-processor interface to the
L2, or does only the Armada XP support that feature? What happens if you
build a single zImage supporting both of the SoCs?

Will

LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl)

[Gregory CLEMENT]

On 08/10/2012 04:47 PM, Will Deacon wrote:
> On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
>> Hi Will,
> 
> Hi Gregory,
> 
>> You will find an updated version of this patch with LPAE support. I've
>> tested with and without LPAE selected.

Just a rectification, in fact I managed to build in both case, and to run
only without LPAE support. I didn't have the support for LPAE yet. I was
surprised that it worked out of the box, but in fact I tested the wrong
kernel! I realized this this morning.

> 
> Thanks for the patches.
> 
>> Now I get some warning during compilation: "initialization from
>> incompatible pointer type [enabled by default]"
>>
>> It is because the outer_cache_fns struct still embed functions with
>> unsigned long for address instead of phys_addr_t. You are aware of
>> it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
>> use phys_addr_t instead of unsigned long in outercache functions".
> 
> Correct, I just fixed up the wrapper functions in that patch since no outer
> cache implementations required >32 bits of physical address. You're the
> lucky guy with the first implementation of such a controller :)
> 
>> So a first step would be to update the definitions in struct
>> outer_cache_fns and also in the files using this prototype, I found
>> only 4 files:
>>
>> git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
>> arch/arm/mm/cache-feroceon-l2.c:
>> arch/arm/mm/cache-l2x0.c:
>> arch/arm/mm/cache-tauros2.c:
>> arch/arm/mm/cache-xsc3l2.c:
>>
>> But it is not enough we also fixed the call to theses functions:
>> git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
>> arch/arm/include/asm/outercache.h
>> arch/arm/kernel/smp.c
>> arch/arm/kernel/suspend.c
>> arch/arm/mach-exynos/platsmp.c
>> arch/arm/mach-highbank/highbank.c
>> arch/arm/mach-msm/platsmp.c
>> arch/arm/mach-omap2/omap-secure.c
>> arch/arm/mach-ux500/platsmp.c
>> arch/arm/mm/dma-mapping.c
>> arch/arm/mm/fault-armv.c
>> arch/arm/plat-versatile/platsmp.c
>>
>> Most of them use __pa or directly __virt_to_phys, so once the patch
>> "[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
>> conversion" will be merged the correct type will be used.
> 
> Which patch is this? part of the keystone series?

yes it is!

> 
>> Finally the last file which need some change will be
>> arch/arm/mm/dma-mapping.c.
>>
>> Does it sound correct?
>>
>> If it does, then I can prepare a patch for it.
> 
> Yes please, that sounds like the right direction for this. We should use
> phys_addr_t wherever we're dealing with physical addresses.
> 
> Cheers,
> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 08/10/2012 04:49 PM, Will Deacon wrote:
> On Wed, Aug 08, 2012 at 05:52:20PM +0100, Gregory CLEMENT wrote:
>> On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
>>> Yes indeed this SoC support LPAE.
>>
>> Well Armada XP supports LPAE but don't use any outer cache functions, he works
>> with the Aurora cache controller on 'system cache'.
>> Armada 370 uses this outer cache functions but doesn't support LPAE.
> 
> Can the Armada 370 be configured to use the co-processor interface to the
> L2, or does only the Armada XP support that feature? What happens if you
> build a single zImage supporting both of the SoCs?

About L2 cache we already use the same kernel on Armada 370 and Armada XP
and the differences are in the device tree.

Now if I understood correctly what the LPAE involved, I guess we can't have
a kernel with LAPE running on Armada 370.

> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Will Deacon]

On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
> On 08/10/2012 04:49 PM, Will Deacon wrote:
> > Can the Armada 370 be configured to use the co-processor interface to the
> > L2, or does only the Armada XP support that feature? What happens if you
> > build a single zImage supporting both of the SoCs?
> 
> About L2 cache we already use the same kernel on Armada 370 and Armada XP
> and the differences are in the device tree.

Right, but I wonder whether you can end up using both the outer_cache
functions *and* the co-processor interface on the Armada XP by accident.
Ideally, we'd just use the co-processor interface on all platforms and
ignore the memory-mapped one. Is that possible on the 370?

> Now if I understood correctly what the LPAE involved, I guess we can't have
> a kernel with LAPE running on Armada 370.

Indeed, but you could still run with 2-level page tables on both SoCs (with
less memory on the XP).

Will

[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 08/10/2012 05:20 PM, Will Deacon wrote:
> On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
>> On 08/10/2012 04:49 PM, Will Deacon wrote:
>>> Can the Armada 370 be configured to use the co-processor interface to the
>>> L2, or does only the Armada XP support that feature? What happens if you
>>> build a single zImage supporting both of the SoCs?
>>
>> About L2 cache we already use the same kernel on Armada 370 and Armada XP
>> and the differences are in the device tree.
> 
> Right, but I wonder whether you can end up using both the outer_cache
> functions *and* the co-processor interface on the Armada XP by accident.

Well from what I know it should be possible to have both in the same time.
However we implement the support in a way that you won't have both in the
same time: if we use the "system cache" mode then we don't use any outer_cache
functions.

> Ideally, we'd just use the co-processor interface on all platforms and
> ignore the memory-mapped one. Is that possible on the 370?
> 
The 370 can't use the "system cache" mode (ie the co-processor).


__________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl)

[Will Deacon]

On Fri, Aug 10, 2012 at 04:02:50PM +0100, Gregory CLEMENT wrote:
> On 08/10/2012 04:47 PM, Will Deacon wrote:
> > On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
> >> You will find an updated version of this patch with LPAE support. I've
> >> tested with and without LPAE selected.
> 
> Just a rectification, in fact I managed to build in both case, and to run
> only without LPAE support. I didn't have the support for LPAE yet. I was
> surprised that it worked out of the box, but in fact I tested the wrong
> kernel! I realized this this morning.

Ok, please keep me updated with how you get on. I can't shake this nagging
feeling that the memory-mapped interface is restricted to 32-bit addresses,
which is why the XP has the option to treat the L2 as an inner-cache...

</speculation>

Will

[RFC] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

On 08/08/2012 05:16 PM, Catalin Marinas wrote:> On 8 August 2012 16:05, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> - two flavors of the controller 'outer cache' and 'system cache' (the
>>   last one meaning maintenance operations on L1 are broadcasted to the
>>   L2 and L2 performs the same operation).
>
> BTW, is the DSB also transparently handled by the L2 in 'system cache' mode?
>

The information I have is that from the point view of the software
there is no need to take any extra actions when using this kind of
command, everything is handle by the hardware. So I guess that the
answer to your question should be yes.

---
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com