[Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Peter Maydell]

Now that the sparc tcg backend has finally had guest-base support
added, we can declare that it is mandatory. This lets us (a)
drop the configure script support for a host CPU type not actually
supporting guest-base (b) remove the now unnecessary compile time
check for whether the TCG backend supports guest-base.

A possible future Part II would be to make guest-base mandatory
for the -user targets (rather than merely the default, as now).
That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
a practical use case for the --disable-guest-base configuration?

Peter Maydell (2):
  configure: Remove unnecessary host_guest_base code
  tcg: Remove TCG_TARGET_HAS_GUEST_BASE define

 configure              |   31 ++-----------------------------
 tcg/arm/tcg-target.h   |    2 --
 tcg/hppa/tcg-target.h  |    2 --
 tcg/i386/tcg-target.h  |    2 --
 tcg/ia64/tcg-target.h  |    3 ---
 tcg/mips/tcg-target.h  |    3 ---
 tcg/ppc/tcg-target.h   |    2 --
 tcg/ppc64/tcg-target.h |    1 -
 tcg/s390/tcg-target.h  |    2 --
 tcg/sparc/tcg-target.h |    2 --
 tcg/tcg.c              |    4 ----
 tcg/tci/tcg-target.h   |    3 ---
 12 files changed, 2 insertions(+), 55 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH 1/2] configure: Remove unnecessary host_guest_base code

[Peter Maydell]

All TCG hosts now support guest-base functionality, so we can
remove the setting of host_guest_base to 'yes' in every arm
of the case "$cpu" statement, and simply set guest_base to
default to 'yes'.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 configure |   31 ++-----------------------------
 1 file changed, 2 insertions(+), 29 deletions(-)

diff --git a/configure b/configure
index c4a7837..a6bdf9a 100755
--- a/configure
+++ b/configure
@@ -198,7 +198,7 @@ cocoa="no"
 softmmu="yes"
 linux_user="no"
 bsd_user="no"
-guest_base=""
+guest_base="yes"
 uname_release=""
 mixemu="no"
 aix="no"
@@ -867,63 +867,36 @@ for opt do
   esac
 done
 
-host_guest_base="no"
 case "$cpu" in
     sparc)
            LDFLAGS="-m32 $LDFLAGS"
            QEMU_CFLAGS="-m32 -mcpu=ultrasparc $QEMU_CFLAGS"
-           host_guest_base="yes"
            ;;
     sparc64)
            LDFLAGS="-m64 $LDFLAGS"
            QEMU_CFLAGS="-m64 -mcpu=ultrasparc $QEMU_CFLAGS"
-           host_guest_base="yes"
            ;;
     s390)
            QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS"
            LDFLAGS="-m31 $LDFLAGS"
-           host_guest_base="yes"
            ;;
     s390x)
            QEMU_CFLAGS="-m64 -march=z990 $QEMU_CFLAGS"
            LDFLAGS="-m64 $LDFLAGS"
-           host_guest_base="yes"
            ;;
     i386)
            QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
            LDFLAGS="-m32 $LDFLAGS"
            cc_i386='$(CC) -m32'
-           host_guest_base="yes"
            ;;
     x86_64)
            QEMU_CFLAGS="-m64 $QEMU_CFLAGS"
            LDFLAGS="-m64 $LDFLAGS"
            cc_i386='$(CC) -m32'
-           host_guest_base="yes"
-           ;;
-    arm*)
-           host_guest_base="yes"
-           ;;
-    ppc*)
-           host_guest_base="yes"
-           ;;
-    mips*)
-           host_guest_base="yes"
-           ;;
-    ia64*)
-           host_guest_base="yes"
-           ;;
-    hppa*)
-           host_guest_base="yes"
-           ;;
-    unicore32*)
-           host_guest_base="yes"
            ;;
+    # No special flags required for other host CPUs
 esac
 
-[ -z "$guest_base" ] && guest_base="$host_guest_base"
-
-
 default_target_list=""
 
 # these targets are portable
-- 
1.7.9.5

[Qemu-devel] [PATCH 2/2] tcg: Remove TCG_TARGET_HAS_GUEST_BASE define

[Peter Maydell]

GUEST_BASE support is now supported by all TCG backends, and is
now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE
define (set by every backend) and the error if it is unset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tcg/arm/tcg-target.h   |    2 --
 tcg/hppa/tcg-target.h  |    2 --
 tcg/i386/tcg-target.h  |    2 --
 tcg/ia64/tcg-target.h  |    3 ---
 tcg/mips/tcg-target.h  |    3 ---
 tcg/ppc/tcg-target.h   |    2 --
 tcg/ppc64/tcg-target.h |    1 -
 tcg/s390/tcg-target.h  |    2 --
 tcg/sparc/tcg-target.h |    2 --
 tcg/tcg.c              |    4 ----
 tcg/tci/tcg-target.h   |    3 ---
 11 files changed, 26 deletions(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index e2299ca..2bc7dff 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -75,8 +75,6 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i32      0
 #define TCG_TARGET_HAS_movcond_i32      0
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 enum {
     TCG_AREG0 = TCG_REG_R6,
 };
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index 5351353..f43fb41 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -103,8 +103,6 @@ typedef enum {
 #define TCG_TARGET_HAS_ext8u_i32        0 /* and rd, rs, 0xff */
 #define TCG_TARGET_HAS_ext16u_i32       0 /* and rd, rs, 0xffff */
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 #define TCG_AREG0 TCG_REG_R17
 
 
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index ace63ba..dbc6756 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -125,8 +125,6 @@ typedef enum {
      ((ofs) == 0 && (len) == 16))
 #define TCG_TARGET_deposit_i64_valid    TCG_TARGET_deposit_i32_valid
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 #if TCG_TARGET_REG_BITS == 64
 # define TCG_AREG0 TCG_REG_R14
 #else
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 368aee4..b7e01b2 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -144,9 +144,6 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_R7
 
-/* Guest base is supported */
-#define TCG_TARGET_HAS_GUEST_BASE
-
 static inline void flush_icache_range(tcg_target_ulong start,
                                       tcg_target_ulong stop)
 {
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 7020d65..65b5c59 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -116,9 +116,6 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_S0
 
-/* guest base is supported */
-#define TCG_TARGET_HAS_GUEST_BASE
-
 #ifdef __OpenBSD__
 #include <machine/sysarch.h>
 #else
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 3259d89..ad433ae 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -96,8 +96,6 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_R27
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 #define tcg_qemu_tb_exec(env, tb_ptr) \
     ((long __attribute__ ((longcall)) \
       (*)(void *, void *))code_gen_prologue)(env, tb_ptr)
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 57569e8..97fc5c9 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -108,5 +108,4 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_R27
 
-#define TCG_TARGET_HAS_GUEST_BASE
 #define TCG_TARGET_EXTEND_ARGS 1
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index ed55c33..a0181ae 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -88,8 +88,6 @@ typedef enum TCGReg {
 #define TCG_TARGET_HAS_movcond_i64      0
 #endif
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R15
 #define TCG_TARGET_STACK_ALIGN		8
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 6314ffb..4a17f1e 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -124,8 +124,6 @@ typedef enum {
 #define TCG_TARGET_HAS_movcond_i64      0
 #endif
 
-#define TCG_TARGET_HAS_GUEST_BASE
-
 #define TCG_AREG0 TCG_REG_I0
 
 static inline void flush_icache_range(tcg_target_ulong start,
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 32cd0c6..a171f78 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -62,10 +62,6 @@
 
 #include "elf.h"
 
-#if defined(CONFIG_USE_GUEST_BASE) && !defined(TCG_TARGET_HAS_GUEST_BASE)
-#error GUEST_BASE not supported on this host.
-#endif
-
 /* Forward declarations for functions declared in tcg-target.c and used here. */
 static void tcg_target_init(TCGContext *s);
 static void tcg_target_qemu_prologue(TCGContext *s);
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 6d89495..37f28c0 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -102,9 +102,6 @@
 #define TCG_TARGET_HAS_movcond_i64      0
 #endif /* TCG_TARGET_REG_BITS == 64 */
 
-/* Offset to user memory in user mode. */
-#define TCG_TARGET_HAS_GUEST_BASE
-
 /* Number of registers available.
    For 32 bit hosts, we need more than 8 registers (call arguments). */
 /* #define TCG_TARGET_NB_REGS 8 */
-- 
1.7.9.5

Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Richard Henderson]

On 10/09/2012 06:16 AM, Peter Maydell wrote:
> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
> a practical use case for the --disable-guest-base configuration?

Nope, because the backends are good at eliminating the overhead
during tcg_target_qemu_prologue if guest_base turns out to be zero.


r~

Re: [Qemu-devel] [PATCH 1/2] configure: Remove unnecessary host_guest_base code

[Richard Henderson]

On 10/09/2012 06:16 AM, Peter Maydell wrote:
> All TCG hosts now support guest-base functionality, so we can
> remove the setting of host_guest_base to 'yes' in every arm
> of the case "$cpu" statement, and simply set guest_base to
> default to 'yes'.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 2/2] tcg: Remove TCG_TARGET_HAS_GUEST_BASE define

[Richard Henderson]

On 10/09/2012 06:16 AM, Peter Maydell wrote:
> GUEST_BASE support is now supported by all TCG backends, and is
> now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE
> define (set by every backend) and the error if it is unset.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Aurelien Jarno]

On Tue, Oct 09, 2012 at 02:16:48PM +0100, Peter Maydell wrote:
> Now that the sparc tcg backend has finally had guest-base support
> added, we can declare that it is mandatory. This lets us (a)
> drop the configure script support for a host CPU type not actually
> supporting guest-base (b) remove the now unnecessary compile time
> check for whether the TCG backend supports guest-base.
> 
> A possible future Part II would be to make guest-base mandatory
> for the -user targets (rather than merely the default, as now).
> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
> a practical use case for the --disable-guest-base configuration?
> 
> Peter Maydell (2):
>   configure: Remove unnecessary host_guest_base code
>   tcg: Remove TCG_TARGET_HAS_GUEST_BASE define
> 
>  configure              |   31 ++-----------------------------
>  tcg/arm/tcg-target.h   |    2 --
>  tcg/hppa/tcg-target.h  |    2 --
>  tcg/i386/tcg-target.h  |    2 --
>  tcg/ia64/tcg-target.h  |    3 ---
>  tcg/mips/tcg-target.h  |    3 ---
>  tcg/ppc/tcg-target.h   |    2 --
>  tcg/ppc64/tcg-target.h |    1 -
>  tcg/s390/tcg-target.h  |    2 --
>  tcg/sparc/tcg-target.h |    2 --
>  tcg/tcg.c              |    4 ----
>  tcg/tci/tcg-target.h   |    3 ---
>  12 files changed, 2 insertions(+), 55 deletions(-)
> 

Both patches:

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

I think they should go through the linux-user branch.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Laurent Desnogues]

On Tue, Oct 9, 2012 at 3:28 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 10/09/2012 06:16 AM, Peter Maydell wrote:
>> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
>> a practical use case for the --disable-guest-base configuration?
>
> Nope, because the backends are good at eliminating the overhead
> during tcg_target_qemu_prologue if guest_base turns out to be zero.

I had some difficulties getting the same code generated with
--enable-guest-base as the one generated with --disable-guest-base,
for ARM on x86_64.  One has to play with -B 0 and -R, and that was
not obvious, while --disable-guest-base was obvious for me :-).

Guest ARM, host x86_64.

$ ./arm-linux-user/qemu-arm -singlestep -d in_asm,out_asm
/work/qemu/Tests/arm/gcc-a9-O3 x

IN:
0x00008138:  e59fc010      ldr	ip, [pc, #16]	; 0x8150

OUT: [size=53]
0x602296c0:  mov    $0x8150,%ebp
0x602296c5:  mov    $0x2ac1f9b61000,%rdi
0x602296cf:  add    %rbp,%rdi
0x602296d2:  mov    (%rdi),%ebp
0x602296d4:  mov    %ebp,0x30(%r14)
0x602296d8:  jmpq   0x602296dd
0x602296dd:  mov    $0x813c,%ebp
0x602296e2:  mov    %ebp,0x3c(%r14)
0x602296e6:  mov    $0x2ac1f6760281,%rax
0x602296f0:  jmpq   0x6226d6b6

Running with -B 0 and playing with -R values until the program
succeeds in loading finally produces the same code as when
compiling QEMU with --disable-guest-base

OUT: [size=41]
0x602281a0:  mov    $0x8150,%ebp
0x602281a5:  mov    0x0(%rbp),%ebp
0x602281a8:  mov    %ebp,0x30(%r14)
0x602281ac:  jmpq   0x602281b1
0x602281b1:  mov    $0x813c,%ebp
0x602281b6:  mov    %ebp,0x3c(%r14)
0x602281ba:  mov    $0x2b9b26096281,%rax
0x602281c4:  jmpq   0x6226c1b6

I know the reason why reserved_va was set to the current value
(cf 288e65b9eea0c9b3cbe21be46f3e24e4e8b2a090), but I
thought it was interesting to point out the above.


Laurent

Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Paolo Bonzini]

Il 09/10/2012 16:50, Laurent Desnogues ha scritto:
> On Tue, Oct 9, 2012 at 3:28 PM, Richard Henderson <rth@twiddle.net> wrote:
>> On 10/09/2012 06:16 AM, Peter Maydell wrote:
>>> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
>>> a practical use case for the --disable-guest-base configuration?
>>
>> Nope, because the backends are good at eliminating the overhead
>> during tcg_target_qemu_prologue if guest_base turns out to be zero.
> 
> I had some difficulties getting the same code generated with
> --enable-guest-base as the one generated with --disable-guest-base,
> for ARM on x86_64.  One has to play with -B 0 and -R, and that was
> not obvious, while --disable-guest-base was obvious for me :-).
> 
> Guest ARM, host x86_64.
> 
> $ ./arm-linux-user/qemu-arm -singlestep -d in_asm,out_asm
> /work/qemu/Tests/arm/gcc-a9-O3 x
> 
> IN:
> 0x00008138:  e59fc010      ldr	ip, [pc, #16]	; 0x8150
> 
> OUT: [size=53]
> 0x602296c0:  mov    $0x8150,%ebp
> 0x602296c5:  mov    $0x2ac1f9b61000,%rdi
> 0x602296cf:  add    %rbp,%rdi
> 0x602296d2:  mov    (%rdi),%ebp
> 0x602296d4:  mov    %ebp,0x30(%r14)
> 0x602296d8:  jmpq   0x602296dd
> 0x602296dd:  mov    $0x813c,%ebp
> 0x602296e2:  mov    %ebp,0x3c(%r14)
> 0x602296e6:  mov    $0x2ac1f6760281,%rax
> 0x602296f0:  jmpq   0x6226d6b6
> 
> Running with -B 0 and playing with -R values until the program
> succeeds in loading finally produces the same code as when
> compiling QEMU with --disable-guest-base
> 
> OUT: [size=41]
> 0x602281a0:  mov    $0x8150,%ebp
> 0x602281a5:  mov    0x0(%rbp),%ebp
> 0x602281a8:  mov    %ebp,0x30(%r14)
> 0x602281ac:  jmpq   0x602281b1
> 0x602281b1:  mov    $0x813c,%ebp
> 0x602281b6:  mov    %ebp,0x3c(%r14)
> 0x602281ba:  mov    $0x2b9b26096281,%rax
> 0x602281c4:  jmpq   0x6226c1b6
> 
> I know the reason why reserved_va was set to the current value
> (cf 288e65b9eea0c9b3cbe21be46f3e24e4e8b2a090), but I
> thought it was interesting to point out the above.

Perhaps you want to revive this patch:

http://lists.gnu.org/archive/html/qemu-devel/2010-06/msg00509.html

Paolo

Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends

[Richard Henderson]

On 10/09/2012 07:58 AM, Paolo Bonzini wrote:
> Perhaps you want to revive this patch:
> 
> http://lists.gnu.org/archive/html/qemu-devel/2010-06/msg00509.html

That needs careful benchmarking.

For i686 it's a small code size optimization.  It's unlikely to pay
off for guest_base.  A variant of this that sets the bounds of the
segment for -R size properly could be interesting for a different
reason: ensuring that the guest cannot access host memory.

I once had a patch that used %gs for i686 env (aka areg0).  With that
we get to free up a register for use by TCG, potentially mitigating
any slowdown from segmentation.

I suspect that the different semantics for 64-bit segments mean
that it's more likely to pay off there.  And when running on
very recent silicon we may not even need to rely on OS support.
See the wrfsbase insn that becomes available with Ivy Bridge.


r~