[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.

The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
sound.

Still some things like onboard NAND support missing, but should be a
good base for further development.

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/tegra.txt |   1 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      | 505 ++++++++++++++++++++++++
 2 files changed, 506 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index a5d3353..ccd4ef4 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -30,3 +30,4 @@ board-specific compatible values:
   nvidia,seaboard
   nvidia,ventana
   nvidia,whistler
+  toradex,colibri_t20-512
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 0000000..334ff02
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,505 @@
+/include/ "tegra20.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB";
+	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&i2c_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			audio_refclk {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			crt {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			displaya {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+					"ld4", "ld5", "ld6", "ld7", "ld8",
+					"ld9", "ld10", "ld11", "ld12", "ld13",
+					"ld14", "ld15", "ld16", "ld17",
+					"lhs", "lpw0", "lpw2", "lsc0",
+					"lsc1", "lsck", "lsda", "lspi", "lvs";
+				nvidia,function = "displaya";
+				nvidia,tristate = <1>;
+			};
+			gpio_dte {
+				nvidia,pins = "dte";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_gmi {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"dap1", "dap2", "dap4", "gpu", "irrx",
+					"irtx", "spia", "spib", "spic";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_uac {
+				nvidia,pins = "uac";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+				nvidia,tristate = <1>;
+			};
+			i2c1 {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2c3 {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2cddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			irda {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			nand {
+				nvidia,pins = "kbca", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "nand";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+				nvidia,tristate = <0>;
+			};
+			pwm {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+				nvidia,tristate = <1>;
+			};
+			sdio4 {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi1 {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi4 {
+				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+				nvidia,function = "spi4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uarta {
+				nvidia,pins = "sdio1";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uartd {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			ulpi {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			ulpi_refclk {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			usb_gpio {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			vi {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,function = "vi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			vi_sc {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+		};
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <400000>;
+	};
+
+	i2c_ddc: i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator@0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator@1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1275000>;
+					regulator-max-microvolt = <1275000>;
+					regulator-always-on;
+				};
+
+				regulator@2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator@3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator@5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator@6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				regulator@8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: regulator@9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator@10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: regulator@11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: regulator@12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator@13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator@14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "national,lm95245";
+			reg = <0x4c>;
+		};
+	};
+
+	memory-controller@7000f400 {
+		emc-table@83250 {
+			reg = <83250>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <83250>;
+			nvidia,emc-registers =  < 0x00000005 0x00000011
+				0x00000004 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000001 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000025f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000005 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00520006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@133200 {
+			reg = <133200>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <133200>;
+			nvidia,emc-registers =  < 0x00000008 0x00000019
+				0x00000006 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000039f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000007 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00510006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@166500 {
+			reg = <166500>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <166500>;
+			nvidia,emc-registers =  < 0x0000000a 0x00000021
+				0x00000008 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000a 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000004df
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x00000009 0x000000c8
+				0x00000003 0x00000009 0x00000004 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x004f0006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <333000>;
+			nvidia,emc-registers =  < 0x00000014 0x00000041
+				0x0000000f 0x00000005 0x00000004 0x00000005
+				0x00000003 0x0000000a 0x00000005 0x00000005
+				0x00000004 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000009ff
+				0x00000000 0x00000003 0x00000003 0x00000005
+				0x00000005 0x00000001 0x0000000e 0x000000c8
+				0x00000003 0x00000011 0x00000006 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00380006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+	};
+
+	ac97: ac97 {
+		status = "okay";
+		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+	};
+
+	serial@70006000 {
+		clock-frequency = <216000000>;
+	};
+
+	serial@70006300 {
+		clock-frequency = <216000000>;
+	};
+
+	usb@c5000000 {
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
+
+	sdhci@c8000600 {
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+		vmmc-supply = <&ldo5_reg>;
+		vqmmc-supply = <&vcc_sd_reg>;
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+			         "nvidia,tegra-audio-wm9712";
+		nvidia,model = "Colibri T20 AC97 Audio";
+
+		nvidia,audio-routing =
+			"Headphone", "HPOUTL",
+			"Headphone", "HPOUTR",
+			"LineIn", "LINEINL",
+			"LineIn", "LINEINR",
+			"Mic", "MIC1";
+
+		nvidia,ac97-controller = <&ac97>;
+	};
+
+	com_regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: com_reg0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		int_usb_reg: com_reg1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 217 0>;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.

The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
sound.

Still some things like onboard NAND support missing, but should be a
good base for further development.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 Documentation/devicetree/bindings/arm/tegra.txt |   1 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      | 505 ++++++++++++++++++++++++
 2 files changed, 506 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index a5d3353..ccd4ef4 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -30,3 +30,4 @@ board-specific compatible values:
   nvidia,seaboard
   nvidia,ventana
   nvidia,whistler
+  toradex,colibri_t20-512
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 0000000..334ff02
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,505 @@
+/include/ "tegra20.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB";
+	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&i2c_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			audio_refclk {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			crt {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			displaya {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+					"ld4", "ld5", "ld6", "ld7", "ld8",
+					"ld9", "ld10", "ld11", "ld12", "ld13",
+					"ld14", "ld15", "ld16", "ld17",
+					"lhs", "lpw0", "lpw2", "lsc0",
+					"lsc1", "lsck", "lsda", "lspi", "lvs";
+				nvidia,function = "displaya";
+				nvidia,tristate = <1>;
+			};
+			gpio_dte {
+				nvidia,pins = "dte";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_gmi {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"dap1", "dap2", "dap4", "gpu", "irrx",
+					"irtx", "spia", "spib", "spic";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_uac {
+				nvidia,pins = "uac";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+				nvidia,tristate = <1>;
+			};
+			i2c1 {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2c3 {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2cddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			irda {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			nand {
+				nvidia,pins = "kbca", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "nand";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+				nvidia,tristate = <0>;
+			};
+			pwm {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+				nvidia,tristate = <1>;
+			};
+			sdio4 {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi1 {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi4 {
+				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+				nvidia,function = "spi4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uarta {
+				nvidia,pins = "sdio1";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uartd {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			ulpi {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			ulpi_refclk {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			usb_gpio {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			vi {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,function = "vi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			vi_sc {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+		};
+	};
+
+	i2c at 7000c000 {
+		clock-frequency = <400000>;
+	};
+
+	i2c_ddc: i2c at 7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c500 {
+		clock-frequency = <400000>;
+	};
+
+	i2c at 7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1275000>;
+					regulator-max-microvolt = <1275000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor at 4c {
+			compatible = "national,lm95245";
+			reg = <0x4c>;
+		};
+	};
+
+	memory-controller at 7000f400 {
+		emc-table at 83250 {
+			reg = <83250>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <83250>;
+			nvidia,emc-registers =  < 0x00000005 0x00000011
+				0x00000004 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000001 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000025f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000005 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00520006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table at 133200 {
+			reg = <133200>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <133200>;
+			nvidia,emc-registers =  < 0x00000008 0x00000019
+				0x00000006 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000039f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000007 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00510006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table at 166500 {
+			reg = <166500>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <166500>;
+			nvidia,emc-registers =  < 0x0000000a 0x00000021
+				0x00000008 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000a 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000004df
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x00000009 0x000000c8
+				0x00000003 0x00000009 0x00000004 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x004f0006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table at 333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <333000>;
+			nvidia,emc-registers =  < 0x00000014 0x00000041
+				0x0000000f 0x00000005 0x00000004 0x00000005
+				0x00000003 0x0000000a 0x00000005 0x00000005
+				0x00000004 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000009ff
+				0x00000000 0x00000003 0x00000003 0x00000005
+				0x00000005 0x00000001 0x0000000e 0x000000c8
+				0x00000003 0x00000011 0x00000006 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00380006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+	};
+
+	ac97: ac97 {
+		status = "okay";
+		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+	};
+
+	serial at 70006000 {
+		clock-frequency = <216000000>;
+	};
+
+	serial at 70006300 {
+		clock-frequency = <216000000>;
+	};
+
+	usb at c5000000 {
+		dr_mode = "otg";
+	};
+
+	usb at c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
+
+	sdhci at c8000600 {
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+		vmmc-supply = <&ldo5_reg>;
+		vqmmc-supply = <&vcc_sd_reg>;
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+			         "nvidia,tegra-audio-wm9712";
+		nvidia,model = "Colibri T20 AC97 Audio";
+
+		nvidia,audio-routing =
+			"Headphone", "HPOUTL",
+			"Headphone", "HPOUTR",
+			"LineIn", "LINEINL",
+			"LineIn", "LINEINR",
+			"Mic", "MIC1";
+
+		nvidia,ac97-controller = <&ac97>;
+	};
+
+	com_regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: com_reg0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		int_usb_reg: com_reg1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 217 0>;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH 2/2] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Lucas Stach]

This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.

The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports  (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/tegra.txt |  1 +
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/tegra20-iris-512.dts          | 88 +++++++++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index ccd4ef4..ed9c853 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -31,3 +31,4 @@ board-specific compatible values:
   nvidia,ventana
   nvidia,whistler
   toradex,colibri_t20-512
+  toradex,iris
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5c13de2..b756c51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
 	sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+	tegra20-iris-512.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 0000000..22959a1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,88 @@
+/dts-v1/;
+
+/include/ "tegra20-colibri-512.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB on Iris";
+	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	host1x {
+		hdmi {
+			status = "okay";
+		};
+	};
+
+	pinmux {
+		state_default: pinmux {
+			hdint {
+				nvidia,tristate = <0>;
+			};
+
+			i2cddc {
+				nvidia,tristate = <0>;
+			};
+
+			sdio4 {
+				nvidia,tristate = <0>;
+			};
+
+			uarta {
+				nvidia,tristate = <0>;
+			};
+
+			uartd {
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	usb@c5000000 {
+		status = "okay";
+	};
+
+	usb@c5008000 {
+		status = "okay";
+	};
+
+	serial@70006000 {
+		status = "okay";
+	};
+
+	serial@70006300 {
+		status = "okay";
+	};
+
+	i2c_ddc: i2c@7000c400 {
+		status = "okay";
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <4>;
+	};
+
+	board_regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		
+		usb_host_vbus {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_host_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 178 0>;
+		};
+
+		vcc_sd_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vcc_sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH 2/2] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Lucas Stach]

This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.

The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports  (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 Documentation/devicetree/bindings/arm/tegra.txt |  1 +
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/tegra20-iris-512.dts          | 88 +++++++++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index ccd4ef4..ed9c853 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -31,3 +31,4 @@ board-specific compatible values:
   nvidia,ventana
   nvidia,whistler
   toradex,colibri_t20-512
+  toradex,iris
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5c13de2..b756c51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
 	sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+	tegra20-iris-512.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 0000000..22959a1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,88 @@
+/dts-v1/;
+
+/include/ "tegra20-colibri-512.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB on Iris";
+	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	host1x {
+		hdmi {
+			status = "okay";
+		};
+	};
+
+	pinmux {
+		state_default: pinmux {
+			hdint {
+				nvidia,tristate = <0>;
+			};
+
+			i2cddc {
+				nvidia,tristate = <0>;
+			};
+
+			sdio4 {
+				nvidia,tristate = <0>;
+			};
+
+			uarta {
+				nvidia,tristate = <0>;
+			};
+
+			uartd {
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	usb at c5000000 {
+		status = "okay";
+	};
+
+	usb at c5008000 {
+		status = "okay";
+	};
+
+	serial at 70006000 {
+		status = "okay";
+	};
+
+	serial at 70006300 {
+		status = "okay";
+	};
+
+	i2c_ddc: i2c at 7000c400 {
+		status = "okay";
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		bus-width = <4>;
+	};
+
+	board_regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		
+		usb_host_vbus {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_host_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 178 0>;
+		};
+
+		vcc_sd_reg: regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vcc_sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
-- 
1.8.0.2

Re: [PATCH 2/2] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Stephen Warren]

On 01/17/2013 04:59 AM, Lucas Stach wrote:
> This adds the device tree for the Toradex Iris carrier board used
> together with a Colibri T20 512MB COM.

> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts

> +	board_regulators {

Similarly, name that node just regulators

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;

Those properties will then already exist, so no need to duplicate them here.

> +		usb_host_vbus {

That would be regulator@3

> +			compatible = "regulator-fixed";
> +			reg = <0>;

That reg = <3>;

(or start numbering the board entries at say 100 to leave room for
changes in the COM include file)

> +			regulator-name = "usb_host_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-boot-on;
> +			regulator-always-on;
> +			gpio = <&gpio 178 0>;
> +		};
> +
> +		vcc_sd_reg: regulator@3 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;

And the node name and reg property here would be 4.

> +			regulator-name = "vcc_sd";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +		};
> +	};
> +};

Oh and in patch 1, I noticed spaces after < or before >; could you
remove those while you're at it. Thanks.

[PATCH 2/2] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Stephen Warren]

On 01/17/2013 04:59 AM, Lucas Stach wrote:
> This adds the device tree for the Toradex Iris carrier board used
> together with a Colibri T20 512MB COM.

> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts

> +	board_regulators {

Similarly, name that node just regulators

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;

Those properties will then already exist, so no need to duplicate them here.

> +		usb_host_vbus {

That would be regulator at 3

> +			compatible = "regulator-fixed";
> +			reg = <0>;

That reg = <3>;

(or start numbering the board entries at say 100 to leave room for
changes in the COM include file)

> +			regulator-name = "usb_host_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-boot-on;
> +			regulator-always-on;
> +			gpio = <&gpio 178 0>;
> +		};
> +
> +		vcc_sd_reg: regulator at 3 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;

And the node name and reg property here would be 4.

> +			regulator-name = "vcc_sd";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +		};
> +	};
> +};

Oh and in patch 1, I noticed spaces after < or before >; could you
remove those while you're at it. Thanks.

Re: [PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Stephen Warren]

On 01/17/2013 04:59 AM, Lucas Stach wrote:
> This adds the device tree include file for the Toradex Colibri T20
> Computer on Module (COM). It's only valid for the 512MB RAM version of
> the module, as the 256MB version needs different EMC tables and flash
> configuration. To make this clear the suffix -512 was added to the board
> compatible string.
> 
> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> sound.
> 
> Still some things like onboard NAND support missing, but should be a
> good base for further development.

> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi

> +		temperature-sensor@4c {
> +			compatible = "national,lm95245";

You should probably add that compatible value to
Documentation/devicetree/bindings/i2c/trivial-devices.txt.

> +	i2c@7000c000 {
> +		clock-frequency = <400000>;
> +	};
> +
> +	i2c_ddc: i2c@7000c400 {
> +		clock-frequency = <100000>;
> +	};
> +
> +	i2c@7000c500 {
> +		clock-frequency = <400000>;
> +	};

> +	serial@70006000 {
> +		clock-frequency = <216000000>;
> +	};
> +
> +	serial@70006300 {
> +		clock-frequency = <216000000>;
> +	};
> +
> +	usb@c5000000 {
> +		dr_mode = "otg";
> +	};
> +
> +	usb@c5004000 {
> +		status = "okay";
> +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> +	};
> +
> +	sdhci@c8000600 {
> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> +		vmmc-supply = <&ldo5_reg>;
> +		vqmmc-supply = <&vcc_sd_reg>;
> +	};

I assume that all of those nodes are meant to have status="okay"?

Oh, I see those are in the top-level board .dts file. You may as well
put all the properties there; stuff like the GPIOs and regulators at
least would be purely specific to the individual board, and not the COM.

I guess we should really move the serial node's clock-frequency property
in the SoC .dtsi files.

> +	com_regulators {

I think just call that "regulators"; the final board .dts file can
easily add more sub-nodes to this node, so there's no need to try and
avoid any naming conflict here. See Cardhu as an example.

> +		vdd_5v0_reg: com_reg0 {

Those should be named regulator@0, regulator@1, etc.

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Stephen Warren]

On 01/17/2013 04:59 AM, Lucas Stach wrote:
> This adds the device tree include file for the Toradex Colibri T20
> Computer on Module (COM). It's only valid for the 512MB RAM version of
> the module, as the 256MB version needs different EMC tables and flash
> configuration. To make this clear the suffix -512 was added to the board
> compatible string.
> 
> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> sound.
> 
> Still some things like onboard NAND support missing, but should be a
> good base for further development.

> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi

> +		temperature-sensor at 4c {
> +			compatible = "national,lm95245";

You should probably add that compatible value to
Documentation/devicetree/bindings/i2c/trivial-devices.txt.

> +	i2c at 7000c000 {
> +		clock-frequency = <400000>;
> +	};
> +
> +	i2c_ddc: i2c at 7000c400 {
> +		clock-frequency = <100000>;
> +	};
> +
> +	i2c at 7000c500 {
> +		clock-frequency = <400000>;
> +	};

> +	serial at 70006000 {
> +		clock-frequency = <216000000>;
> +	};
> +
> +	serial at 70006300 {
> +		clock-frequency = <216000000>;
> +	};
> +
> +	usb at c5000000 {
> +		dr_mode = "otg";
> +	};
> +
> +	usb at c5004000 {
> +		status = "okay";
> +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> +	};
> +
> +	sdhci at c8000600 {
> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> +		vmmc-supply = <&ldo5_reg>;
> +		vqmmc-supply = <&vcc_sd_reg>;
> +	};

I assume that all of those nodes are meant to have status="okay"?

Oh, I see those are in the top-level board .dts file. You may as well
put all the properties there; stuff like the GPIOs and regulators at
least would be purely specific to the individual board, and not the COM.

I guess we should really move the serial node's clock-frequency property
in the SoC .dtsi files.

> +	com_regulators {

I think just call that "regulators"; the final board .dts file can
easily add more sub-nodes to this node, so there's no need to try and
avoid any naming conflict here. See Cardhu as an example.

> +		vdd_5v0_reg: com_reg0 {

Those should be named regulator at 0, regulator at 1, etc.

Re: [PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
> On 01/17/2013 04:59 AM, Lucas Stach wrote:
> > This adds the device tree include file for the Toradex Colibri T20
> > Computer on Module (COM). It's only valid for the 512MB RAM version of
> > the module, as the 256MB version needs different EMC tables and flash
> > configuration. To make this clear the suffix -512 was added to the board
> > compatible string.
> > 
> > The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> > sound.
> > 
> > Still some things like onboard NAND support missing, but should be a
> > good base for further development.
> 
> > diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> 
> > +		temperature-sensor@4c {
> > +			compatible = "national,lm95245";
> 
> You should probably add that compatible value to
> Documentation/devicetree/bindings/i2c/trivial-devices.txt.
> 
Yep, will send a separate patch for this.

> > +	i2c@7000c000 {
> > +		clock-frequency = <400000>;
> > +	};
> > +
> > +	i2c_ddc: i2c@7000c400 {
> > +		clock-frequency = <100000>;
> > +	};
> > +
> > +	i2c@7000c500 {
> > +		clock-frequency = <400000>;
> > +	};
> 
> > +	serial@70006000 {
> > +		clock-frequency = <216000000>;
> > +	};
> > +
> > +	serial@70006300 {
> > +		clock-frequency = <216000000>;
> > +	};
> > +
> > +	usb@c5000000 {
> > +		dr_mode = "otg";
> > +	};
> > +
> > +	usb@c5004000 {
> > +		status = "okay";
> > +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> > +	};
> > +
> > +	sdhci@c8000600 {
> > +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> > +		vmmc-supply = <&ldo5_reg>;
> > +		vqmmc-supply = <&vcc_sd_reg>;
> > +	};
> 
> I assume that all of those nodes are meant to have status="okay"?
> 
> Oh, I see those are in the top-level board .dts file. You may as well
> put all the properties there; stuff like the GPIOs and regulators at
> least would be purely specific to the individual board, and not the COM.
> 
I would like to keep everything that is defined by the COM to reside in
the COM dtsi. You are right that the regulator in this case is board
specific and should be moved to the board file, I missed this while
splitting things out. But at least the GPIO is defined by the fixed COM
pinout.

> I guess we should really move the serial node's clock-frequency property
> in the SoC .dtsi files.
> 
Might be a nice cleanup.

> > +	com_regulators {
> 
> I think just call that "regulators"; the final board .dts file can
> easily add more sub-nodes to this node, so there's no need to try and
> avoid any naming conflict here. See Cardhu as an example.
> 
I don't really see the benefit of merging those nodes. They are separate
regulators, some are located on the COM, others on the carrier board. So
I would like to keep them in separate nodes, unless you have strong
feelings to change this.

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
> On 01/17/2013 04:59 AM, Lucas Stach wrote:
> > This adds the device tree include file for the Toradex Colibri T20
> > Computer on Module (COM). It's only valid for the 512MB RAM version of
> > the module, as the 256MB version needs different EMC tables and flash
> > configuration. To make this clear the suffix -512 was added to the board
> > compatible string.
> > 
> > The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> > sound.
> > 
> > Still some things like onboard NAND support missing, but should be a
> > good base for further development.
> 
> > diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> 
> > +		temperature-sensor at 4c {
> > +			compatible = "national,lm95245";
> 
> You should probably add that compatible value to
> Documentation/devicetree/bindings/i2c/trivial-devices.txt.
> 
Yep, will send a separate patch for this.

> > +	i2c at 7000c000 {
> > +		clock-frequency = <400000>;
> > +	};
> > +
> > +	i2c_ddc: i2c at 7000c400 {
> > +		clock-frequency = <100000>;
> > +	};
> > +
> > +	i2c at 7000c500 {
> > +		clock-frequency = <400000>;
> > +	};
> 
> > +	serial at 70006000 {
> > +		clock-frequency = <216000000>;
> > +	};
> > +
> > +	serial at 70006300 {
> > +		clock-frequency = <216000000>;
> > +	};
> > +
> > +	usb at c5000000 {
> > +		dr_mode = "otg";
> > +	};
> > +
> > +	usb at c5004000 {
> > +		status = "okay";
> > +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> > +	};
> > +
> > +	sdhci at c8000600 {
> > +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> > +		vmmc-supply = <&ldo5_reg>;
> > +		vqmmc-supply = <&vcc_sd_reg>;
> > +	};
> 
> I assume that all of those nodes are meant to have status="okay"?
> 
> Oh, I see those are in the top-level board .dts file. You may as well
> put all the properties there; stuff like the GPIOs and regulators at
> least would be purely specific to the individual board, and not the COM.
> 
I would like to keep everything that is defined by the COM to reside in
the COM dtsi. You are right that the regulator in this case is board
specific and should be moved to the board file, I missed this while
splitting things out. But at least the GPIO is defined by the fixed COM
pinout.

> I guess we should really move the serial node's clock-frequency property
> in the SoC .dtsi files.
> 
Might be a nice cleanup.

> > +	com_regulators {
> 
> I think just call that "regulators"; the final board .dts file can
> easily add more sub-nodes to this node, so there's no need to try and
> avoid any naming conflict here. See Cardhu as an example.
> 
I don't really see the benefit of merging those nodes. They are separate
regulators, some are located on the COM, others on the carrier board. So
I would like to keep them in separate nodes, unless you have strong
feelings to change this.

Re: [PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Stephen Warren]

On 01/17/2013 02:29 PM, Lucas Stach wrote:
> Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
>> On 01/17/2013 04:59 AM, Lucas Stach wrote:
>>> This adds the device tree include file for the Toradex Colibri T20
>>> Computer on Module (COM). It's only valid for the 512MB RAM version of
>>> the module, as the 256MB version needs different EMC tables and flash
>>> configuration. To make this clear the suffix -512 was added to the board
>>> compatible string.
>>>
>>> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
>>> sound.
>>>
>>> Still some things like onboard NAND support missing, but should be a
>>> good base for further development.
>>
>>> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>
>>> +		temperature-sensor@4c {
>>> +			compatible = "national,lm95245";
>>
>> You should probably add that compatible value to
>> Documentation/devicetree/bindings/i2c/trivial-devices.txt.
>>
> Yep, will send a separate patch for this.
> 
>>> +	i2c@7000c000 {
>>> +		clock-frequency = <400000>;
>>> +	};
>>> +
>>> +	i2c_ddc: i2c@7000c400 {
>>> +		clock-frequency = <100000>;
>>> +	};
>>> +
>>> +	i2c@7000c500 {
>>> +		clock-frequency = <400000>;
>>> +	};
>>
>>> +	serial@70006000 {
>>> +		clock-frequency = <216000000>;
>>> +	};
>>> +
>>> +	serial@70006300 {
>>> +		clock-frequency = <216000000>;
>>> +	};
>>> +
>>> +	usb@c5000000 {
>>> +		dr_mode = "otg";
>>> +	};
>>> +
>>> +	usb@c5004000 {
>>> +		status = "okay";
>>> +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
>>> +	};
>>> +
>>> +	sdhci@c8000600 {
>>> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
>>> +		vmmc-supply = <&ldo5_reg>;
>>> +		vqmmc-supply = <&vcc_sd_reg>;
>>> +	};
>>
>> I assume that all of those nodes are meant to have status="okay"?
>>
>> Oh, I see those are in the top-level board .dts file. You may as well
>> put all the properties there; stuff like the GPIOs and regulators at
>> least would be purely specific to the individual board, and not the COM.
>
> I would like to keep everything that is defined by the COM to reside in
> the COM dtsi. You are right that the regulator in this case is board
> specific and should be moved to the board file, I missed this while
> splitting things out. But at least the GPIO is defined by the fixed COM
> pinout.

If these are really defined by the COM itself, it does indeed make sense
for the COM .dtsi file to define those properties. But, I have a hard
time understanding how the COM design can force the carrier module into
using a particular GPIO for the SD controller CD functionality; couldn't
the carrier use any GPIO passed through the COM<->carrier connector for
any purpose?

>>> +	com_regulators {
>>
>> I think just call that "regulators"; the final board .dts file can
>> easily add more sub-nodes to this node, so there's no need to try and
>> avoid any naming conflict here. See Cardhu as an example.
>
> I don't really see the benefit of merging those nodes. They are separate
> regulators, some are located on the COM, others on the carrier board. So
> I would like to keep them in separate nodes, unless you have strong
> feelings to change this.

The issue here is that if we don't do this, we end up with wierd node
names; plain "regulators" is a fairly canonical name for what the name
contains, and purely indicates the type of the node. "com_regulators" is
unusual, and starts to encode identity into the node name itself, which
is something not usually done in the node name (differentiation between
identities is usually done using the unit address; "@nnn"),

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Stephen Warren]

On 01/17/2013 02:29 PM, Lucas Stach wrote:
> Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
>> On 01/17/2013 04:59 AM, Lucas Stach wrote:
>>> This adds the device tree include file for the Toradex Colibri T20
>>> Computer on Module (COM). It's only valid for the 512MB RAM version of
>>> the module, as the 256MB version needs different EMC tables and flash
>>> configuration. To make this clear the suffix -512 was added to the board
>>> compatible string.
>>>
>>> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
>>> sound.
>>>
>>> Still some things like onboard NAND support missing, but should be a
>>> good base for further development.
>>
>>> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>
>>> +		temperature-sensor at 4c {
>>> +			compatible = "national,lm95245";
>>
>> You should probably add that compatible value to
>> Documentation/devicetree/bindings/i2c/trivial-devices.txt.
>>
> Yep, will send a separate patch for this.
> 
>>> +	i2c at 7000c000 {
>>> +		clock-frequency = <400000>;
>>> +	};
>>> +
>>> +	i2c_ddc: i2c at 7000c400 {
>>> +		clock-frequency = <100000>;
>>> +	};
>>> +
>>> +	i2c at 7000c500 {
>>> +		clock-frequency = <400000>;
>>> +	};
>>
>>> +	serial at 70006000 {
>>> +		clock-frequency = <216000000>;
>>> +	};
>>> +
>>> +	serial at 70006300 {
>>> +		clock-frequency = <216000000>;
>>> +	};
>>> +
>>> +	usb at c5000000 {
>>> +		dr_mode = "otg";
>>> +	};
>>> +
>>> +	usb at c5004000 {
>>> +		status = "okay";
>>> +		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
>>> +	};
>>> +
>>> +	sdhci at c8000600 {
>>> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
>>> +		vmmc-supply = <&ldo5_reg>;
>>> +		vqmmc-supply = <&vcc_sd_reg>;
>>> +	};
>>
>> I assume that all of those nodes are meant to have status="okay"?
>>
>> Oh, I see those are in the top-level board .dts file. You may as well
>> put all the properties there; stuff like the GPIOs and regulators at
>> least would be purely specific to the individual board, and not the COM.
>
> I would like to keep everything that is defined by the COM to reside in
> the COM dtsi. You are right that the regulator in this case is board
> specific and should be moved to the board file, I missed this while
> splitting things out. But at least the GPIO is defined by the fixed COM
> pinout.

If these are really defined by the COM itself, it does indeed make sense
for the COM .dtsi file to define those properties. But, I have a hard
time understanding how the COM design can force the carrier module into
using a particular GPIO for the SD controller CD functionality; couldn't
the carrier use any GPIO passed through the COM<->carrier connector for
any purpose?

>>> +	com_regulators {
>>
>> I think just call that "regulators"; the final board .dts file can
>> easily add more sub-nodes to this node, so there's no need to try and
>> avoid any naming conflict here. See Cardhu as an example.
>
> I don't really see the benefit of merging those nodes. They are separate
> regulators, some are located on the COM, others on the carrier board. So
> I would like to keep them in separate nodes, unless you have strong
> feelings to change this.

The issue here is that if we don't do this, we end up with wierd node
names; plain "regulators" is a fairly canonical name for what the name
contains, and purely indicates the type of the node. "com_regulators" is
unusual, and starts to encode identity into the node name itself, which
is something not usually done in the node name (differentiation between
identities is usually done using the unit address; "@nnn"),

Re: [PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

Am Donnerstag, den 17.01.2013, 15:13 -0700 schrieb Stephen Warren:
> On 01/17/2013 02:29 PM, Lucas Stach wrote:
> > Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
> >> On 01/17/2013 04:59 AM, Lucas Stach wrote:
> >>> This adds the device tree include file for the Toradex Colibri T20
> >>> Computer on Module (COM). It's only valid for the 512MB RAM version of
> >>> the module, as the 256MB version needs different EMC tables and flash
> >>> configuration. To make this clear the suffix -512 was added to the board
> >>> compatible string.
> >>>
> >>> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> >>> sound.
> >>>
> >>> Still some things like onboard NAND support missing, but should be a
> >>> good base for further development.
> >>> +
> >>> +	sdhci@c8000600 {
> >>> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> >>> +		vmmc-supply = <&ldo5_reg>;
> >>> +		vqmmc-supply = <&vcc_sd_reg>;
> >>> +	};
> >>
> >> I assume that all of those nodes are meant to have status="okay"?
> >>
> >> Oh, I see those are in the top-level board .dts file. You may as well
> >> put all the properties there; stuff like the GPIOs and regulators at
> >> least would be purely specific to the individual board, and not the COM.
> >
> > I would like to keep everything that is defined by the COM to reside in
> > the COM dtsi. You are right that the regulator in this case is board
> > specific and should be moved to the board file, I missed this while
> > splitting things out. But at least the GPIO is defined by the fixed COM
> > pinout.
> 
> If these are really defined by the COM itself, it does indeed make sense
> for the COM .dtsi file to define those properties. But, I have a hard
> time understanding how the COM design can force the carrier module into
> using a particular GPIO for the SD controller CD functionality; couldn't
> the carrier use any GPIO passed through the COM<->carrier connector for
> any purpose?
> 
It's not a GPIO anymore as soon as it hits the COM<->carrier connector.
The connector pin assignment is strictly specified. There are a lot of
freely assignable GPIOs on the connector, everything related to a
specific function is not part of this.

The Colibri specification dictates which pin to use if you want to
realize a SDcard CD. This is done so that modules and carrier boards are
interchangeable. In fact you can just as well run a new Colibri T30
module on a years old carrier designed for the ColibriPXA series of
modules.

> >>> +	com_regulators {
> >>
> >> I think just call that "regulators"; the final board .dts file can
> >> easily add more sub-nodes to this node, so there's no need to try and
> >> avoid any naming conflict here. See Cardhu as an example.
> >
> > I don't really see the benefit of merging those nodes. They are separate
> > regulators, some are located on the COM, others on the carrier board. So
> > I would like to keep them in separate nodes, unless you have strong
> > feelings to change this.
> 
> The issue here is that if we don't do this, we end up with wierd node
> names; plain "regulators" is a fairly canonical name for what the name
> contains, and purely indicates the type of the node. "com_regulators" is
> unusual, and starts to encode identity into the node name itself, which
> is something not usually done in the node name (differentiation between
> identities is usually done using the unit address; "@nnn"),

Hm, ok. Keeping some space in between module and carrier regulator
addresses should do as well.

[PATCH 1/2] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

Am Donnerstag, den 17.01.2013, 15:13 -0700 schrieb Stephen Warren:
> On 01/17/2013 02:29 PM, Lucas Stach wrote:
> > Am Donnerstag, den 17.01.2013, 13:55 -0700 schrieb Stephen Warren:
> >> On 01/17/2013 04:59 AM, Lucas Stach wrote:
> >>> This adds the device tree include file for the Toradex Colibri T20
> >>> Computer on Module (COM). It's only valid for the 512MB RAM version of
> >>> the module, as the 256MB version needs different EMC tables and flash
> >>> configuration. To make this clear the suffix -512 was added to the board
> >>> compatible string.
> >>>
> >>> The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
> >>> sound.
> >>>
> >>> Still some things like onboard NAND support missing, but should be a
> >>> good base for further development.
> >>> +
> >>> +	sdhci at c8000600 {
> >>> +		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> >>> +		vmmc-supply = <&ldo5_reg>;
> >>> +		vqmmc-supply = <&vcc_sd_reg>;
> >>> +	};
> >>
> >> I assume that all of those nodes are meant to have status="okay"?
> >>
> >> Oh, I see those are in the top-level board .dts file. You may as well
> >> put all the properties there; stuff like the GPIOs and regulators at
> >> least would be purely specific to the individual board, and not the COM.
> >
> > I would like to keep everything that is defined by the COM to reside in
> > the COM dtsi. You are right that the regulator in this case is board
> > specific and should be moved to the board file, I missed this while
> > splitting things out. But at least the GPIO is defined by the fixed COM
> > pinout.
> 
> If these are really defined by the COM itself, it does indeed make sense
> for the COM .dtsi file to define those properties. But, I have a hard
> time understanding how the COM design can force the carrier module into
> using a particular GPIO for the SD controller CD functionality; couldn't
> the carrier use any GPIO passed through the COM<->carrier connector for
> any purpose?
> 
It's not a GPIO anymore as soon as it hits the COM<->carrier connector.
The connector pin assignment is strictly specified. There are a lot of
freely assignable GPIOs on the connector, everything related to a
specific function is not part of this.

The Colibri specification dictates which pin to use if you want to
realize a SDcard CD. This is done so that modules and carrier boards are
interchangeable. In fact you can just as well run a new Colibri T30
module on a years old carrier designed for the ColibriPXA series of
modules.

> >>> +	com_regulators {
> >>
> >> I think just call that "regulators"; the final board .dts file can
> >> easily add more sub-nodes to this node, so there's no need to try and
> >> avoid any naming conflict here. See Cardhu as an example.
> >
> > I don't really see the benefit of merging those nodes. They are separate
> > regulators, some are located on the COM, others on the carrier board. So
> > I would like to keep them in separate nodes, unless you have strong
> > feelings to change this.
> 
> The issue here is that if we don't do this, we end up with wierd node
> names; plain "regulators" is a fairly canonical name for what the name
> contains, and purely indicates the type of the node. "com_regulators" is
> unusual, and starts to encode identity into the node name itself, which
> is something not usually done in the node name (differentiation between
> identities is usually done using the unit address; "@nnn"),

Hm, ok. Keeping some space in between module and carrier regulator
addresses should do as well.

[PATCH v2 1/3] ARM: DT: tegra: move serial clock-frequency attr into the SoC dtsi

[Lucas Stach]

No Tegra Platform is running PLL_P at another rate than 216MHz, nor is
any using an other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
v2:
- initial revision
---
 arch/arm/boot/dts/tegra20-harmony.dts   | 1 -
 arch/arm/boot/dts/tegra20-paz00.dts     | 2 --
 arch/arm/boot/dts/tegra20-seaboard.dts  | 1 -
 arch/arm/boot/dts/tegra20-tamonten.dtsi | 1 -
 arch/arm/boot/dts/tegra20-trimslice.dts | 1 -
 arch/arm/boot/dts/tegra20-ventana.dts   | 1 -
 arch/arm/boot/dts/tegra20-whistler.dts  | 1 -
 arch/arm/boot/dts/tegra20.dtsi          | 5 +++++
 8 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 54295e3..96f4ccd 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -252,7 +252,6 @@
 
 	serial@70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 80d9635..7744c8b 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -244,12 +244,10 @@
 
 	serial@70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	serial@70006200 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index d4e4ff2..0b48359 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -303,7 +303,6 @@
 
 	serial@70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index a239ccd..4766aba 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -276,7 +276,6 @@
 	};
 
 	serial@70006300 {
-		clock-frequency = <216000000>;
 		status = "okay";
 	};
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4b6c486..adf6024 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -263,7 +263,6 @@
 
 	serial@70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	dvi_ddc: i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index e3d3b29..5b15c30 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -300,7 +300,6 @@
 
 	serial@70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index b8e0ee1..ea57c0f 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -255,7 +255,6 @@
 
 	serial@70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	hdmi_ddc: i2c@7000c400 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c4870f..8324ef4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -223,6 +223,7 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 36 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
 	};
@@ -232,6 +233,7 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 37 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
 	};
@@ -241,6 +243,7 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 46 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
 	};
@@ -250,6 +253,7 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 90 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
 	};
@@ -259,6 +263,7 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 91 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		status = "disabled";
 	};
-- 
1.8.0.2

[PATCH v2 1/3] ARM: DT: tegra: move serial clock-frequency attr into the SoC dtsi

[Lucas Stach]

No Tegra Platform is running PLL_P at another rate than 216MHz, nor is
any using an other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
v2:
- initial revision
---
 arch/arm/boot/dts/tegra20-harmony.dts   | 1 -
 arch/arm/boot/dts/tegra20-paz00.dts     | 2 --
 arch/arm/boot/dts/tegra20-seaboard.dts  | 1 -
 arch/arm/boot/dts/tegra20-tamonten.dtsi | 1 -
 arch/arm/boot/dts/tegra20-trimslice.dts | 1 -
 arch/arm/boot/dts/tegra20-ventana.dts   | 1 -
 arch/arm/boot/dts/tegra20-whistler.dts  | 1 -
 arch/arm/boot/dts/tegra20.dtsi          | 5 +++++
 8 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 54295e3..96f4ccd 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -252,7 +252,6 @@
 
 	serial at 70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 80d9635..7744c8b 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -244,12 +244,10 @@
 
 	serial at 70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	serial at 70006200 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index d4e4ff2..0b48359 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -303,7 +303,6 @@
 
 	serial at 70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index a239ccd..4766aba 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -276,7 +276,6 @@
 	};
 
 	serial at 70006300 {
-		clock-frequency = <216000000>;
 		status = "okay";
 	};
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4b6c486..adf6024 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -263,7 +263,6 @@
 
 	serial at 70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	dvi_ddc: i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index e3d3b29..5b15c30 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -300,7 +300,6 @@
 
 	serial at 70006300 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index b8e0ee1..ea57c0f 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -255,7 +255,6 @@
 
 	serial at 70006000 {
 		status = "okay";
-		clock-frequency = <216000000>;
 	};
 
 	hdmi_ddc: i2c at 7000c400 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c4870f..8324ef4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -223,6 +223,7 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 36 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
 	};
@@ -232,6 +233,7 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 37 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
 	};
@@ -241,6 +243,7 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 46 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
 	};
@@ -250,6 +253,7 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 90 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
 	};
@@ -259,6 +263,7 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 91 0x04>;
+		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		status = "disabled";
 	};
-- 
1.8.0.2

[PATCH v2 2/3] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.

The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
sound.

Still some things like onboard NAND support missing, but should be a
good base for further development.

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
v2:
- remove some whitespace
- remove nodes that don't carry any additional info
- unify regulator node between module and carrier board
---
 Documentation/devicetree/bindings/arm/tegra.txt |   1 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      | 491 ++++++++++++++++++++++++
 2 files changed, 492 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index a5d3353..ccd4ef4 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -30,3 +30,4 @@ board-specific compatible values:
   nvidia,seaboard
   nvidia,ventana
   nvidia,whistler
+  toradex,colibri_t20-512
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 0000000..4441620
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,491 @@
+/include/ "tegra20.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB";
+	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&i2c_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			audio_refclk {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			crt {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			displaya {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+					"ld4", "ld5", "ld6", "ld7", "ld8",
+					"ld9", "ld10", "ld11", "ld12", "ld13",
+					"ld14", "ld15", "ld16", "ld17",
+					"lhs", "lpw0", "lpw2", "lsc0",
+					"lsc1", "lsck", "lsda", "lspi", "lvs";
+				nvidia,function = "displaya";
+				nvidia,tristate = <1>;
+			};
+			gpio_dte {
+				nvidia,pins = "dte";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_gmi {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"dap1", "dap2", "dap4", "gpu", "irrx",
+					"irtx", "spia", "spib", "spic";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_uac {
+				nvidia,pins = "uac";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+				nvidia,tristate = <1>;
+			};
+			i2c1 {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2c3 {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2cddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			irda {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			nand {
+				nvidia,pins = "kbca", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "nand";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+				nvidia,tristate = <0>;
+			};
+			pwm {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+				nvidia,tristate = <1>;
+			};
+			sdio4 {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi1 {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi4 {
+				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+				nvidia,function = "spi4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uarta {
+				nvidia,pins = "sdio1";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uartd {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			ulpi {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			ulpi_refclk {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			usb_gpio {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			vi {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,function = "vi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			vi_sc {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+		};
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <400000>;
+	};
+
+	i2c_ddc: i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator@0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator@1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1275000>;
+					regulator-max-microvolt = <1275000>;
+					regulator-always-on;
+				};
+
+				regulator@2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator@3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator@5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator@6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				regulator@8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: regulator@9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator@10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: regulator@11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: regulator@12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator@13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator@14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "national,lm95245";
+			reg = <0x4c>;
+		};
+	};
+
+	memory-controller@7000f400 {
+		emc-table@83250 {
+			reg = <83250>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <83250>;
+			nvidia,emc-registers =   <0x00000005 0x00000011
+				0x00000004 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000001 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000025f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000005 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00520006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table@133200 {
+			reg = <133200>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <133200>;
+			nvidia,emc-registers =   <0x00000008 0x00000019
+				0x00000006 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000039f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000007 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00510006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table@166500 {
+			reg = <166500>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <166500>;
+			nvidia,emc-registers =   <0x0000000a 0x00000021
+				0x00000008 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000a 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000004df
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x00000009 0x000000c8
+				0x00000003 0x00000009 0x00000004 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x004f0006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table@333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <333000>;
+			nvidia,emc-registers =   <0x00000014 0x00000041
+				0x0000000f 0x00000005 0x00000004 0x00000005
+				0x00000003 0x0000000a 0x00000005 0x00000005
+				0x00000004 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000009ff
+				0x00000000 0x00000003 0x00000003 0x00000005
+				0x00000005 0x00000001 0x0000000e 0x000000c8
+				0x00000003 0x00000011 0x00000006 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00380006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+	};
+
+	ac97: ac97 {
+		status = "okay";
+		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+	};
+
+	usb@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
+
+	sdhci@c8000600 {
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+			         "nvidia,tegra-audio-wm9712";
+		nvidia,model = "Colibri T20 AC97 Audio";
+
+		nvidia,audio-routing =
+			"Headphone", "HPOUTL",
+			"Headphone", "HPOUTR",
+			"LineIn", "LINEINL",
+			"LineIn", "LINEINR",
+			"Mic", "MIC1";
+
+		nvidia,ac97-controller = <&ac97>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@100 {
+			compatible = "regulator-fixed";
+			reg = <100>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@101 {
+			compatible = "regulator-fixed";
+			reg = <101>;
+			regulator-name = "internal_usb";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 217 0>;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH v2 2/3] ARM: DT: tegra: Add Colibri T20 512MB COM

[Lucas Stach]

This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.

The Colibri T20 uses a Tegra2 SoC and has onboard USB Ethernet and AC97
sound.

Still some things like onboard NAND support missing, but should be a
good base for further development.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
v2:
- remove some whitespace
- remove nodes that don't carry any additional info
- unify regulator node between module and carrier board
---
 Documentation/devicetree/bindings/arm/tegra.txt |   1 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi      | 491 ++++++++++++++++++++++++
 2 files changed, 492 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index a5d3353..ccd4ef4 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -30,3 +30,4 @@ board-specific compatible values:
   nvidia,seaboard
   nvidia,ventana
   nvidia,whistler
+  toradex,colibri_t20-512
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 0000000..4441620
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,491 @@
+/include/ "tegra20.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB";
+	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&i2c_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			audio_refclk {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			crt {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			displaya {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+					"ld4", "ld5", "ld6", "ld7", "ld8",
+					"ld9", "ld10", "ld11", "ld12", "ld13",
+					"ld14", "ld15", "ld16", "ld17",
+					"lhs", "lpw0", "lpw2", "lsc0",
+					"lsc1", "lsck", "lsda", "lspi", "lvs";
+				nvidia,function = "displaya";
+				nvidia,tristate = <1>;
+			};
+			gpio_dte {
+				nvidia,pins = "dte";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_gmi {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"dap1", "dap2", "dap4", "gpu", "irrx",
+					"irtx", "spia", "spib", "spic";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			gpio_uac {
+				nvidia,pins = "uac";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+				nvidia,tristate = <1>;
+			};
+			i2c1 {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2c3 {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			i2cddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			irda {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			nand {
+				nvidia,pins = "kbca", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "nand";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+				nvidia,tristate = <0>;
+			};
+			pwm {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+				nvidia,tristate = <1>;
+			};
+			sdio4 {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi1 {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			spi4 {
+				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+				nvidia,function = "spi4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uarta {
+				nvidia,pins = "sdio1";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			uartd {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			ulpi {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			ulpi_refclk {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			usb_gpio {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			vi {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,function = "vi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			vi_sc {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+		};
+	};
+
+	i2c at 7000c000 {
+		clock-frequency = <400000>;
+	};
+
+	i2c_ddc: i2c at 7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c500 {
+		clock-frequency = <400000>;
+	};
+
+	i2c at 7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1275000>;
+					regulator-max-microvolt = <1275000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor at 4c {
+			compatible = "national,lm95245";
+			reg = <0x4c>;
+		};
+	};
+
+	memory-controller at 7000f400 {
+		emc-table at 83250 {
+			reg = <83250>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <83250>;
+			nvidia,emc-registers =   <0x00000005 0x00000011
+				0x00000004 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000001 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000025f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000005 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00520006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table at 133200 {
+			reg = <133200>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <133200>;
+			nvidia,emc-registers =   <0x00000008 0x00000019
+				0x00000006 0x00000002 0x00000004 0x00000004
+				0x00000001 0x0000000a 0x00000002 0x00000002
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x0000039f
+				0x00000000 0x00000003 0x00000003 0x00000002
+				0x00000002 0x00000001 0x00000008 0x000000c8
+				0x00000003 0x00000007 0x00000003 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00510006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table at 166500 {
+			reg = <166500>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <166500>;
+			nvidia,emc-registers =   <0x0000000a 0x00000021
+				0x00000008 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000a 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000004df
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x00000009 0x000000c8
+				0x00000003 0x00000009 0x00000004 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x004f0006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+		emc-table at 333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = <333000>;
+			nvidia,emc-registers =   <0x00000014 0x00000041
+				0x0000000f 0x00000005 0x00000004 0x00000005
+				0x00000003 0x0000000a 0x00000005 0x00000005
+				0x00000004 0x00000001 0x00000003 0x00000004
+				0x00000003 0x00000009 0x0000000c 0x000009ff
+				0x00000000 0x00000003 0x00000003 0x00000005
+				0x00000005 0x00000001 0x0000000e 0x000000c8
+				0x00000003 0x00000011 0x00000006 0x0000000c
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0x00380006
+				0x00000010 0x00000008 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+	};
+
+	ac97: ac97 {
+		status = "okay";
+		nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+		nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+	};
+
+	usb at c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
+
+	sdhci at c8000600 {
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+			         "nvidia,tegra-audio-wm9712";
+		nvidia,model = "Colibri T20 AC97 Audio";
+
+		nvidia,audio-routing =
+			"Headphone", "HPOUTL",
+			"Headphone", "HPOUTR",
+			"LineIn", "LINEINL",
+			"LineIn", "LINEINR",
+			"Mic", "MIC1";
+
+		nvidia,ac97-controller = <&ac97>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator at 100 {
+			compatible = "regulator-fixed";
+			reg = <100>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator at 101 {
+			compatible = "regulator-fixed";
+			reg = <101>;
+			regulator-name = "internal_usb";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 217 0>;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH v2 3/3] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Lucas Stach]

This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.

The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports  (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
v2:
- unify regulator node between module and carrier
- use correct regulator for sdhci
---
 Documentation/devicetree/bindings/arm/tegra.txt |  1 +
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/tegra20-iris-512.dts          | 89 +++++++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index ccd4ef4..ed9c853 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -31,3 +31,4 @@ board-specific compatible values:
   nvidia,ventana
   nvidia,whistler
   toradex,colibri_t20-512
+  toradex,iris
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5c13de2..b756c51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
 	sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+	tegra20-iris-512.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 0000000..52f1103
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+/include/ "tegra20-colibri-512.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB on Iris";
+	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	host1x {
+		hdmi {
+			status = "okay";
+		};
+	};
+
+	pinmux {
+		state_default: pinmux {
+			hdint {
+				nvidia,tristate = <0>;
+			};
+
+			i2cddc {
+				nvidia,tristate = <0>;
+			};
+
+			sdio4 {
+				nvidia,tristate = <0>;
+			};
+
+			uarta {
+				nvidia,tristate = <0>;
+			};
+
+			uartd {
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	usb@c5000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb@c5008000 {
+		status = "okay";
+	};
+
+	serial@70006000 {
+		status = "okay";
+	};
+
+	serial@70006300 {
+		status = "okay";
+	};
+
+	i2c_ddc: i2c@7000c400 {
+		status = "okay";
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <4>;
+		vmmc-supply = <&vcc_sd_reg>;
+		vqmmc-supply = <&vcc_sd_reg>;
+	};
+
+	regulators {
+		regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_host_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 178 0>;
+		};
+
+		vcc_sd_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vcc_sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
-- 
1.8.0.2

[PATCH v2 3/3] ARM: DT: tegra: Add Toradex Iris carrier board with T20 512MB COM

[Lucas Stach]

This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.

The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports  (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
v2:
- unify regulator node between module and carrier
- use correct regulator for sdhci
---
 Documentation/devicetree/bindings/arm/tegra.txt |  1 +
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/tegra20-iris-512.dts          | 89 +++++++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts

diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index ccd4ef4..ed9c853 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -31,3 +31,4 @@ board-specific compatible values:
   nvidia,ventana
   nvidia,whistler
   toradex,colibri_t20-512
+  toradex,iris
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5c13de2..b756c51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
 	sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+	tegra20-iris-512.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 0000000..52f1103
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+/include/ "tegra20-colibri-512.dtsi"
+
+/ {
+	model = "Toradex Colibri T20 512MB on Iris";
+	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+
+	host1x {
+		hdmi {
+			status = "okay";
+		};
+	};
+
+	pinmux {
+		state_default: pinmux {
+			hdint {
+				nvidia,tristate = <0>;
+			};
+
+			i2cddc {
+				nvidia,tristate = <0>;
+			};
+
+			sdio4 {
+				nvidia,tristate = <0>;
+			};
+
+			uarta {
+				nvidia,tristate = <0>;
+			};
+
+			uartd {
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	usb at c5000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb at c5008000 {
+		status = "okay";
+	};
+
+	serial at 70006000 {
+		status = "okay";
+	};
+
+	serial at 70006300 {
+		status = "okay";
+	};
+
+	i2c_ddc: i2c at 7000c400 {
+		status = "okay";
+	};
+
+	sdhci at c8000600 {
+		status = "okay";
+		bus-width = <4>;
+		vmmc-supply = <&vcc_sd_reg>;
+		vqmmc-supply = <&vcc_sd_reg>;
+	};
+
+	regulators {
+		regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_host_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			gpio = <&gpio 178 0>;
+		};
+
+		vcc_sd_reg: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vcc_sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
-- 
1.8.0.2

Re: [PATCH v2 1/3] ARM: DT: tegra: move serial clock-frequency attr into the SoC dtsi

[Stephen Warren]

On 01/22/2013 02:46 PM, Lucas Stach wrote:
> No Tegra Platform is running PLL_P at another rate than 216MHz, nor is
> any using an other PLL as UART source clock. Move attribute into SoC
> level dtsi file to slim down board DT files.

I've applied the series to Tegra's for-3.9/dt branch.

[PATCH v2 1/3] ARM: DT: tegra: move serial clock-frequency attr into the SoC dtsi

[Stephen Warren]

On 01/22/2013 02:46 PM, Lucas Stach wrote:
> No Tegra Platform is running PLL_P at another rate than 216MHz, nor is
> any using an other PLL as UART source clock. Move attribute into SoC
> level dtsi file to slim down board DT files.

I've applied the series to Tegra's for-3.9/dt branch.