* [PATCH 0/5] i.MXRT1020 add basic support
@ 2020-02-18 19:02 Giulio Benetti
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Add Soc i.MXRT1020 to i.MXRT family and its evk support.
This Soc has many in common with i.MXRT1050 except clock init and pins
listing.
Giulio Benetti (5):
clk: imx: add i.IMXRT1020 clk driver
Add i.MXRT1020 support
ARM: dts: imxrt1020: add dtsi file
dt-bindings: pinctrl: add i.MXRT1020 pins definition
Add support for i.MXRT1020-EVK board
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 44 +
arch/arm/dts/imxrt1020-evk.dts | 198 +++++
arch/arm/dts/imxrt1020.dtsi | 133 +++
arch/arm/mach-imx/imxrt/Kconfig | 9 +
board/freescale/imxrt1020-evk/Kconfig | 22 +
board/freescale/imxrt1020-evk/MAINTAINERS | 6 +
board/freescale/imxrt1020-evk/Makefile | 6 +
board/freescale/imxrt1020-evk/README | 31 +
board/freescale/imxrt1020-evk/imximage.cfg | 36 +
board/freescale/imxrt1020-evk/imxrt1020-evk.c | 81 ++
configs/imxrt1020-evk_defconfig | 67 ++
drivers/clk/imx/Kconfig | 16 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1020.c | 227 ++++++
include/configs/imxrt1020-evk.h | 46 ++
include/dt-bindings/clock/imxrt1020-clock.h | 52 ++
include/dt-bindings/pinctrl/pins-imxrt1020.h | 763 ++++++++++++++++++
18 files changed, 1740 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1020-evk.dts
create mode 100644 arch/arm/dts/imxrt1020.dtsi
create mode 100644 board/freescale/imxrt1020-evk/Kconfig
create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1020-evk/Makefile
create mode 100644 board/freescale/imxrt1020-evk/README
create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg
create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c
create mode 100644 configs/imxrt1020-evk_defconfig
create mode 100644 drivers/clk/imx/clk-imxrt1020.c
create mode 100644 include/configs/imxrt1020-evk.h
create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
--
2.20.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
@ 2020-02-18 19:02 ` Giulio Benetti
2020-02-20 22:33 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 2/5] Add i.MXRT1020 support Giulio Benetti
` (4 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Add i.MXRT1020 clk driver support.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/clk/imx/Kconfig | 16 ++
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1020.c | 227 ++++++++++++++++++++
include/dt-bindings/clock/imxrt1020-clock.h | 52 +++++
4 files changed, 296 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1020.c
create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 059bc2fbb9..96721bcbf3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -69,6 +69,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMXRT1020
+ bool "SPL clock support for i.MXRT1020"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1020
+
+config CLK_IMXRT1020
+ bool "Clock support for i.MXRT1020"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1020 platforms.
+
config SPL_CLK_IMXRT1050
bool "SPL clock support for i.MXRT1050"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 1e8a49d0f3..01bbbdf3ae 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
new file mode 100644
index 0000000000..840f783940
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imxrt1020-clock.h>
+
+#include "clk.h"
+
+static ulong imxrt1020_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1020_clk_disable(struct clk *clk)
+{
+ return __imxrt1020_clk_enable(clk, 0);
+}
+
+static int imxrt1020_clk_enable(struct clk *clk)
+{
+ return __imxrt1020_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1020_clk_ops = {
+ .set_rate = imxrt1020_clk_set_rate,
+ .get_rate = imxrt1020_clk_get_rate,
+ .enable = imxrt1020_clk_enable,
+ .disable = imxrt1020_clk_disable,
+};
+
+static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
+static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
+
+static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
+static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
+static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
+static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+
+static int imxrt1020_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMXRT1020_CLK_PLL2_SYS,
+ imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+ base + 0x30, 0x1));
+ clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
+ imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x1));
+
+ /* PLL bypass out */
+ clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
+ imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+ pll2_bypass_sels,
+ ARRAY_SIZE(pll2_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
+ imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+ pll3_bypass_sels,
+ ARRAY_SIZE(pll3_bypass_sels),
+ CLK_SET_RATE_PARENT));
+
+ clk_dm(IMXRT1020_CLK_PLL3_80M,
+ imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+
+ clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
+ imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
+ clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
+ imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
+ clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
+ imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
+ clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
+ imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
+ clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
+ imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
+ clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
+ imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
+
+ /* CCM clocks */
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
+ imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+ pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
+ clk_dm(IMXRT1020_CLK_PERIPH_SEL,
+ imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+ periph_sels, ARRAY_SIZE(periph_sels)));
+ clk_dm(IMXRT1020_CLK_USDHC1_SEL,
+ imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMXRT1020_CLK_USDHC2_SEL,
+ imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMXRT1020_CLK_LPUART_SEL,
+ imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+ lpuart_sels, ARRAY_SIZE(lpuart_sels)));
+ clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
+ imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+ semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
+ clk_dm(IMXRT1020_CLK_SEMC_SEL,
+ imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+ semc_sels, ARRAY_SIZE(semc_sels)));
+
+ clk_dm(IMXRT1020_CLK_AHB_PODF,
+ imx_clk_divider("ahb_podf", "periph_sel",
+ base + 0x14, 10, 3));
+ clk_dm(IMXRT1020_CLK_USDHC1_PODF,
+ imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ base + 0x24, 11, 3));
+ clk_dm(IMXRT1020_CLK_USDHC2_PODF,
+ imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ base + 0x24, 16, 3));
+ clk_dm(IMXRT1020_CLK_LPUART_PODF,
+ imx_clk_divider("lpuart_podf", "lpuart_sel",
+ base + 0x24, 0, 6));
+ clk_dm(IMXRT1020_CLK_SEMC_PODF,
+ imx_clk_divider("semc_podf", "semc_sel",
+ base + 0x14, 16, 3));
+
+ clk_dm(IMXRT1020_CLK_USDHC1,
+ imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ clk_dm(IMXRT1020_CLK_USDHC2,
+ imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ clk_dm(IMXRT1020_CLK_LPUART1,
+ imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+ clk_dm(IMXRT1020_CLK_SEMC,
+ imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+
+#ifdef CONFIG_SPL_BUILD
+ struct clk *clk, *clk1;
+
+ clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
+ clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
+ clk_set_parent(clk1, clk);
+
+ /* Configure PLL3_USB_OTG to 480MHz */
+ clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
+ clk_enable(clk);
+ clk_set_rate(clk, 480000000UL);
+
+ clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+ clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
+ clk_set_rate(clk, 297000000UL);
+
+ clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
+ clk_enable(clk);
+ clk_set_rate(clk, 528000000UL);
+
+ clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id imxrt1020_clk_ids[] = {
+ { .compatible = "fsl,imxrt1020-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imxrt1020_clk) = {
+ .name = "clk_imxrt1020",
+ .id = UCLASS_CLK,
+ .of_match = imxrt1020_clk_ids,
+ .ops = &imxrt1020_clk_ops,
+ .probe = imxrt1020_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/imxrt1020-clock.h b/include/dt-bindings/clock/imxrt1020-clock.h
new file mode 100644
index 0000000000..836244358b
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt1020-clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
+#define __DT_BINDINGS_CLOCK_IMXRT1020_H
+
+#define IMXRT1020_CLK_DUMMY 0
+#define IMXRT1020_CLK_CKIL 1
+#define IMXRT1020_CLK_CKIH 2
+#define IMXRT1020_CLK_OSC 3
+#define IMXRT1020_CLK_PLL2_PFD0_352M 4
+#define IMXRT1020_CLK_PLL2_PFD1_594M 5
+#define IMXRT1020_CLK_PLL2_PFD2_396M 6
+#define IMXRT1020_CLK_PLL2_PFD3_297M 7
+#define IMXRT1020_CLK_PLL3_PFD0_720M 8
+#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
+#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
+#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
+#define IMXRT1020_CLK_PLL2_198M 12
+#define IMXRT1020_CLK_PLL3_120M 13
+#define IMXRT1020_CLK_PLL3_80M 14
+#define IMXRT1020_CLK_PLL3_60M 15
+#define IMXRT1020_CLK_PLL2_BYPASS 16
+#define IMXRT1020_CLK_PLL3_BYPASS 17
+#define IMXRT1020_CLK_PLL6_BYPASS 18
+#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
+#define IMXRT1020_CLK_PERIPH_SEL 20
+#define IMXRT1020_CLK_SEMC_ALT_SEL 21
+#define IMXRT1020_CLK_SEMC_SEL 22
+#define IMXRT1020_CLK_USDHC1_SEL 23
+#define IMXRT1020_CLK_USDHC2_SEL 24
+#define IMXRT1020_CLK_LPUART_SEL 25
+#define IMXRT1020_CLK_ARM_PODF 26
+#define IMXRT1020_CLK_LPUART_PODF 27
+#define IMXRT1020_CLK_USDHC1_PODF 28
+#define IMXRT1020_CLK_USDHC2_PODF 29
+#define IMXRT1020_CLK_SEMC_PODF 30
+#define IMXRT1020_CLK_AHB_PODF 31
+#define IMXRT1020_CLK_USDHC1 32
+#define IMXRT1020_CLK_USDHC2 33
+#define IMXRT1020_CLK_LPUART1 34
+#define IMXRT1020_CLK_SEMC 35
+#define IMXRT1020_CLK_PLL2_SYS 36
+#define IMXRT1020_CLK_PLL3_USB_OTG 37
+#define IMXRT1020_CLK_PLL4_AUDIO 38
+#define IMXRT1020_CLK_PLL6_ENET 39
+#define IMXRT1020_CLK_END 40
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/5] Add i.MXRT1020 support
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
@ 2020-02-18 19:02 ` Giulio Benetti
2020-02-20 22:35 ` Lukasz Majewski
2020-04-19 9:09 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file Giulio Benetti
` (3 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
arch/arm/mach-imx/imxrt/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index e3aff11d48..f28d52d3b7 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -3,6 +3,10 @@ if ARCH_IMXRT
config IMXRT
bool
+config IMXRT1020
+ bool
+ select IMXRT
+
config IMXRT1050
bool
select IMXRT
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
2020-02-18 19:02 ` [PATCH 2/5] Add i.MXRT1020 support Giulio Benetti
@ 2020-02-18 19:02 ` Giulio Benetti
2020-02-20 22:45 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition Giulio Benetti
` (2 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Add dtsi file for i.MXRT1020.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
arch/arm/dts/imxrt1020.dtsi | 133 ++++++++++++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
create mode 100644 arch/arm/dts/imxrt1020.dtsi
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
new file mode 100644
index 0000000000..97f3cec9f3
--- /dev/null
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1020-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ u-boot,dm-spl;
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc at 402f0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f0000 0x4000>;
+ clocks = <&clks IMXRT1020_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial at 40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT1020_CLK_LPUART1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc at 401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm at 400fc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt1020-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ usdhc1: usdhc at 402c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-usdhc";
+ reg = <0x402c0000 0x10000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT1020_CLK_USDHC1>;
+ clock-names = "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio at 401b8000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 401bc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 401c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
` (2 preceding siblings ...)
2020-02-18 19:02 ` [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file Giulio Benetti
@ 2020-02-18 19:02 ` Giulio Benetti
2020-02-20 22:51 ` Lukasz Majewski
2020-04-19 9:09 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 5/5] Add support for i.MXRT1020-EVK board Giulio Benetti
2020-04-18 12:32 ` [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
5 siblings, 2 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Add i.MXRT1020 pins definition.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
include/dt-bindings/pinctrl/pins-imxrt1020.h | 763 +++++++++++++++++++
1 file changed, 763 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h b/include/dt-bindings/pinctrl/pins-imxrt1020.h
new file mode 100644
index 0000000000..c6bacb7378
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
@@ -0,0 +1,763 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
+
+/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
+
+#define IMX_PAD_SION 0x40000000
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x188 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x014 0x188 0x420 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x014 0x188 0x3E0 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014 0x188 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x188 0x3B0 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x014 0x188 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x014 0x188 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x014 0x188 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x18C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x018 0x18C 0x424 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x018 0x18C 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x018 0x18C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x18C 0x3AC 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x018 0x18C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x018 0x18C 0x320 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x018 0x18C 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x190 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x01C 0x190 0x428 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX 0x01C 0x190 0x3E8 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x01C 0x190 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x190 0x3B8 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x01C 0x190 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x01C 0x190 0x37C 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x194 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x020 0x194 0x42C 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX 0x020 0x194 0x3E4 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x020 0x194 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x194 0x3B4 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x020 0x194 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x020 0x194 0x380 0x6 0x1
+
+#define MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x198 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x024 0x198 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x024 0x198 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024 0x198 0x464 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x024 0x198 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x024 0x198 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x19C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x028 0x19C 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN 0x028 0x19C 0x488 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x19C 0x468 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x028 0x19C 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x028 0x19C 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x1A0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x02C 0x1A0 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX 0x02C 0x1A0 0x3DC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C 0x1A0 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x02C 0x1A0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x02C 0x1A0 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x1A4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x030 0x1A4 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX 0x030 0x1A4 0x3D8 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030 0x1A4 0x460 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x030 0x1A4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x030 0x1A4 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x1A8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x034 0x1A8 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x034 0x1A8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x1A8 0x45C 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x034 0x1A8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x034 0x1A8 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x1AC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x038 0x1AC 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x038 0x1AC 0x324 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038 0x1AC 0x458 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x038 0x1AC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x038 0x1AC 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS 0x03C 0x1B0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x03C 0x1B0 0x4B0 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x03C 0x1B0 0x398 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C 0x1B0 0x450 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x03C 0x1B0 0x3B0 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x03C 0x1B0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x03C 0x1B0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS 0x040 0x1B4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x040 0x1B4 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x040 0x1B4 0x394 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040 0x1B4 0x44C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x040 0x1B4 0x3AC 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x040 0x1B4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x040 0x1B4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0 0x044 0x1B8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x044 0x1B8 0x4B4 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX 0x044 0x1B8 0x3F8 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x044 0x1B8 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x044 0x1B8 0x3B8 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x044 0x1B8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x044 0x1B8 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0 0x048 0x1BC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x048 0x1BC 0x4B8 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX 0x048 0x1BC 0x3F4 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x048 0x1BC 0x438 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x048 0x1BC 0x3B4 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x048 0x1BC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x048 0x1BC 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048 0x1BC 0x300 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1 0x04C 0x1C0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x04C 0x1C0 0x4A0 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x04C 0x1C0 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C 0x1C0 0x434 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x1C0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x04C 0x1C0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x04C 0x1C0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x050 0x1C4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x050 0x1C4 0x4A4 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x050 0x1C4 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050 0x1C4 0x448 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B 0x050 0x1C4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x050 0x1C4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x050 0x1C4 0x320 0x6 0x3
+
+#define MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x054 0x1C8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x054 0x1C8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x054 0x1C8 0x454 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x054 0x1C8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x054 0x1C8 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x058 0x1CC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT 0x058 0x1CC 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x058 0x1CC 0x46C 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x058 0x1CC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x058 0x1CC 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x05C 0x1D0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x05C 0x1D0 0x4A8 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x05C 0x1D0 0x388 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C 0x1D0 0x448 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x05C 0x1D0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x05C 0x1D0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C 0x1D0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x060 0x1D4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x060 0x1D4 0x4AC 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x060 0x1D4 0x384 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060 0x1D4 0x434 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x060 0x1D4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x060 0x1D4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060 0x1D4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x064 0x1D8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x064 0x1D8 0x334 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x064 0x1D8 0x3CC 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x064 0x1D8 0x430 0x3 0x3
+#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x064 0x1D8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x064 0x1D8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064 0x1D8 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x068 0x1DC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x068 0x1DC 0x344 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x068 0x1DC 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x068 0x1DC 0x438 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x068 0x1DC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x068 0x1DC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068 0x1DC 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x06C 0x1E0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x06C 0x1E0 0x330 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX 0x06C 0x1E0 0x3D4 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x06C 0x1E0 0x43C 0x3 0x1
+
+#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x06C 0x1E0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x06C 0x1E0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C 0x1E0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x070 0x1E4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x070 0x1E4 0x340 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX 0x070 0x1E4 0x3D0 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x070 0x1E4 0x440 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x070 0x1E4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x070 0x1E4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070 0x1E4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x074 0x1E8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x074 0x1E8 0x32C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x074 0x1E8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x074 0x1E8 0x444 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x074 0x1E8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x074 0x1E8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074 0x1E8 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x078 0x1EC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x078 0x1EC 0x33C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x078 0x1EC 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x078 0x1EC 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x078 0x1EC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x078 0x1EC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078 0x1EC 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x07C 0x1F0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x07C 0x1F0 0x328 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX 0x07C 0x1F0 0x408 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C 0x1F0 0x44C 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x07C 0x1F0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x07C 0x1F0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C 0x1F0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x080 0x1F4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x080 0x1F4 0x338 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX 0x080 0x1F4 0x404 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080 0x1F4 0x450 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x080 0x1F4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x080 0x1F4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080 0x1F4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS 0x084 0x1F8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x084 0x1F8 0x354 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x084 0x1F8 0x4BC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x084 0x1F8 0x46C 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x084 0x1F8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x084 0x1F8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x084 0x1F8 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x084 0x1F8 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE 0x088 0x1FC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x088 0x1FC 0x364 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x088 0x1FC 0x4C0 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088 0x1FC 0x470 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x088 0x1FC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x088 0x1FC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x088 0x1FC 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x088 0x1FC 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK 0x08C 0x200 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x08C 0x200 0x350 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x08C 0x200 0x3E0 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C 0x200 0x478 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x08C 0x200 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x08C 0x200 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x08C 0x200 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x08C 0x200 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01 0x090 0x204 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x090 0x204 0x360 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x090 0x204 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090 0x204 0x474 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B 0x090 0x204 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x090 0x204 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK 0x090 0x204 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x090 0x204 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x094 0x208 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x094 0x208 0x410 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX 0x094 0x208 0x3E8 0x2 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094 0x208 0x000 0x3 0x4
+#define MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x094 0x208 0x3C0 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x094 0x208 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x094 0x208 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x098 0x20C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x098 0x20C 0x414 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX 0x098 0x20C 0x3E4 0x2 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098 0x20C 0x47C 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x098 0x20C 0x3BC 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x098 0x20C 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x09C 0x210 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x09C 0x210 0x418 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX 0x09C 0x210 0x400 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C 0x210 0x480 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x09C 0x210 0x3C8 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x09C 0x210 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS 0x09C 0x210 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x0A0 0x214 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x0A0 0x214 0x41C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX 0x0A0 0x214 0x3FC 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP 0x0A0 0x214 0x49C 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x0A0 0x214 0x3C4 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x0A0 0x214 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL 0x0A0 0x214 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x0A4 0x218 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x0A4 0x218 0x34C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x0A4 0x218 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4 0x218 0x300 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x0A4 0x218 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x0A4 0x218 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x0A4 0x218 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x218 0x494 0x7 0x4
+
+#define MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x0A8 0x21C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x0A8 0x21C 0x35C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x0A8 0x21C 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x0A8 0x21C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x0A8 0x21C 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x0A8 0x21C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8 0x21C 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x0A8 0x21C 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x0AC 0x220 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x0AC 0x220 0x348 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX 0x0AC 0x220 0x3F0 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT 0x0AC 0x220 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x0AC 0x220 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x0AC 0x220 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC 0x220 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x0AC 0x220 0x490 0x7 0x3
+
+#define MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x0B0 0x224 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x0B0 0x224 0x358 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX 0x0B0 0x224 0x3EC 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x0B0 0x224 0x48C 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x224 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x0B0 0x224 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x0B0 0x224 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK 0x0B0 0x224 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x0B4 0x228 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x0B4 0x228 0x4BC 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x0B4 0x228 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x0B4 0x228 0x2FC 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO 0x0B4 0x228 0x308 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x0B4 0x228 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4 0x228 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x0B4 0x228 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY 0x0B8 0x22C 0x484 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x0B8 0x22C 0x4C0 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN 0x0B8 0x22C 0x488 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8 0x22C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC 0x0B8 0x22C 0x000 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x0B8 0x22C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8 0x22C 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x0B8 0x22C 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x0BC 0x230 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x230 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x0BC 0x230 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x0C0 0x234 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x234 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x0C0 0x234 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x0C4 0x238 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x238 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x0C4 0x238 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x0C8 0x23C 0x000 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x0C8 0x23C 0x498 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x0C8 0x23C 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x0C8 0x23C 0x430 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x0C8 0x23C 0x494 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x23C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x23C 0x48C 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x0C8 0x23C 0x300 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x0CC 0x240 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x0CC 0x240 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x0CC 0x240 0x494 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x0CC 0x240 0x420 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x0CC 0x240 0x308 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x240 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x0CC 0x240 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x0CC 0x240 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0 0x244 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x0D0 0x244 0x320 0x1 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x0D0 0x244 0x490 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x0D0 0x244 0x424 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x0D0 0x244 0x000 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x244 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x0D0 0x244 0x2FC 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x0D0 0x244 0x40C 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x0D4 0x248 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x0D4 0x248 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4 0x248 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x0D4 0x248 0x428 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x0D4 0x248 0x354 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x248 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x0D4 0x248 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x0D8 0x24C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x0D8 0x24C 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8 0x24C 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x0D8 0x24C 0x42C 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x0D8 0x24C 0x364 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x24C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x0D8 0x24C 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x0DC 0x250 0x31C 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC 0x250 0x38C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x0DC 0x250 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x0DC 0x250 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x0DC 0x250 0x304 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x250 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x0DC 0x250 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x0E0 0x254 0x310 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0 0x254 0x390 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x0E0 0x254 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x0E0 0x254 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x254 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x0E0 0x254 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x0E4 0x258 0x30C 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4 0x258 0x3A0 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4 0x258 0x3F0 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x0E4 0x258 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x0E4 0x258 0x350 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x258 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x0E4 0x258 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8 0x25C 0x314 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x0E8 0x25C 0x39C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8 0x25C 0x3EC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x0E8 0x25C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x0E8 0x25C 0x360 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x25C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x0E8 0x25C 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC 0x260 0x318 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC 0x260 0x3A8 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x0EC 0x260 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x0EC 0x260 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x0EC 0x260 0x34C 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x260 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x0EC 0x260 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x0EC 0x260 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0 0x264 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0 0x264 0x3A4 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x0F0 0x264 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x0F0 0x264 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x0F0 0x264 0x35C 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x264 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x0F0 0x264 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x0F0 0x264 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x0F4 0x268 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x268 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4 0x268 0x3DC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x0F4 0x268 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x0F4 0x268 0x348 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x268 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x0F4 0x268 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x0F4 0x268 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x0F8 0x26C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x26C 0x324 0x1 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8 0x26C 0x3D8 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x0F8 0x26C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x0F8 0x26C 0x358 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x26C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x0F8 0x26C 0x000 0x6 0x2
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC 0x270 0x484 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x0FC 0x270 0x374 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX 0x0FC 0x270 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK 0x0FC 0x270 0x430 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 0x0FC 0x270 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x270 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT 0x0FC 0x270 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04 0x0FC 0x270 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100 0x274 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x100 0x274 0x378 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX 0x100 0x274 0x324 0x2 0x3
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK 0x100 0x274 0x44C 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 0x100 0x274 0x000 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x274 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN 0x100 0x274 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04 0x100 0x274 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104 0x278 0x000 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x104 0x278 0x368 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104 0x278 0x3C0 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC 0x104 0x278 0x450 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 0x104 0x278 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x278 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT 0x104 0x278 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05 0x104 0x278 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108 0x27C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x108 0x27C 0x370 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 0x108 0x27C 0x3BC 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00 0x108 0x27C 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 0x108 0x27C 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x27C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN 0x108 0x27C 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05 0x108 0x27C 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C 0x280 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x10C 0x280 0x36C 0x1 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C 0x280 0x3C8 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC 0x10C 0x280 0x448 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 0x10C 0x280 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x280 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 0x10C 0x280 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06 0x10C 0x280 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP 0x110 0x284 0x494 0x0 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x110 0x284 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110 0x284 0x3C4 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00 0x110 0x284 0x438 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 0x110 0x284 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x284 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 0x110 0x284 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06 0x110 0x284 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x114 0x288 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x114 0x288 0x328 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x114 0x288 0x3CC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x114 0x288 0x434 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x114 0x288 0x000 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x288 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x114 0x288 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x114 0x288 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x118 0x28C 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x118 0x28C 0x338 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x118 0x28C 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x118 0x28C 0x444 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x118 0x28C 0x000 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x28C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x118 0x28C 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x118 0x28C 0x000 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C 0x290 0x384 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x11C 0x290 0x32C 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C 0x290 0x3D4 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x11C 0x290 0x440 0x3 0x3
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x11C 0x290 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x290 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x11C 0x290 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x11C 0x290 0x4B4 0x7 0x1
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120 0x294 0x388 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x120 0x294 0x33C 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120 0x294 0x3D0 0x2 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x120 0x294 0x43C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26 0x120 0x294 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x294 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x120 0x294 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x120 0x294 0x4B8 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x124 0x298 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x124 0x298 0x330 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124 0x298 0x3E8 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x124 0x298 0x490 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x124 0x298 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x298 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x124 0x298 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x128 0x29C 0x2FC 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x128 0x29C 0x340 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128 0x29C 0x3E4 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x128 0x29C 0x494 0x3 0x3
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x128 0x29C 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x29C 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x128 0x29C 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x12C 0x2A0 0x48C 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x2A0 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C 0x2A0 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x12C 0x2A0 0x498 0x3 0x2
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x12C 0x2A0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x2A0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x12C 0x2A0 0x334 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x130 0x2A4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x2A4 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x130 0x2A4 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x130 0x2A4 0x49C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x130 0x2A4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x2A4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x130 0x2A4 0x344 0x6 0x1
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134 0x2A8 0x37C 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x2A8 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x2A8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x134 0x2A8 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x134 0x2A8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x2A8 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138 0x2AC 0x380 0x0 0x1
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x2AC 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138 0x2AC 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x138 0x2AC 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x138 0x2AC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x2AC 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x13C 0x2B0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x13C 0x2B0 0x410 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x13C 0x2B0 0x430 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x13C 0x2B0 0x454 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C 0x2B0 0x38C 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C 0x2B0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x13C 0x2B0 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x13C 0x2B0 0x4A0 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x140 0x2B4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x140 0x2B4 0x414 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x140 0x2B4 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x140 0x2B4 0x460 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140 0x2B4 0x390 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140 0x2B4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x140 0x2B4 0x000 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x140 0x2B4 0x4A4 0x7 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144 0x2B8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x144 0x2B8 0x418 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x144 0x2B8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x144 0x2B8 0x458 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144 0x2B8 0x3A0 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144 0x2B8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x144 0x2B8 0x308 0x6 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x144 0x2B8 0x4A8 0x7 0x1
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148 0x2BC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x148 0x2BC 0x41C 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x148 0x2BC 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x148 0x2BC 0x45C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x148 0x2BC 0x39C 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148 0x2BC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x148 0x2BC 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x14C 0x2C0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x14C 0x2C0 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C 0x2C0 0x400 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x14C 0x2C0 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C 0x2C0 0x3A8 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C 0x2C0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x14C 0x2C0 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x150 0x2C4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x150 0x2C4 0x324 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150 0x2C4 0x3FC 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x150 0x2C4 0x464 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150 0x2C4 0x3A4 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150 0x2C4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x150 0x2C4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x154 0x2C8 0x490 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x154 0x2C8 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x154 0x2C8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x154 0x2C8 0x468 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x154 0x2C8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154 0x2C8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x154 0x2C8 0x4AC 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x158 0x2CC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x158 0x2CC 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158 0x2CC 0x3F8 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x158 0x2CC 0x4B0 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x158 0x2CC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158 0x2CC 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x15C 0x2D0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x15C 0x2D0 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C 0x2D0 0x3F4 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x15C 0x2D0 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x15C 0x2D0 0x320 0x4 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C 0x2D0 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160 0x2D4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x160 0x2D4 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160 0x2D4 0x408 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160 0x2D4 0x394 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x160 0x2D4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160 0x2D4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x160 0x2D4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164 0x2D8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x164 0x2D8 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164 0x2D8 0x404 0x2 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164 0x2D8 0x398 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x164 0x2D8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164 0x2D8 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x164 0x2D8 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x168 0x2DC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x168 0x2DC 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x168 0x2DC 0x31C 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x168 0x2DC 0x304 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x168 0x2DC 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168 0x2DC 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x168 0x2DC 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x16C 0x2E0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x16C 0x2E0 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x16C 0x2E0 0x310 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x16C 0x2E0 0x46C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x16C 0x2E0 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C 0x2E0 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x16C 0x2E0 0x300 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x170 0x2E4 0x498 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x170 0x2E4 0x374 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x170 0x2E4 0x30C 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x170 0x2E4 0x47C 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x170 0x2E4 0x3AC 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170 0x2E4 0x000 0x5 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x170 0x2E4 0x000 0x6 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x174 0x2E8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x174 0x2E8 0x378 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174 0x2E8 0x314 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x174 0x2E8 0x480 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174 0x2E8 0x3B0 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174 0x2E8 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x178 0x2EC 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x178 0x2EC 0x368 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178 0x2EC 0x318 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x178 0x2EC 0x000 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178 0x2EC 0x3B8 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178 0x2EC 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x17C 0x2F0 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x17C 0x2F0 0x370 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C 0x2F0 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x17C 0x2F0 0x470 0x3 0x1
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C 0x2F0 0x3B4 0x4 0x2
+#define MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C 0x2F0 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x180 0x2F4 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x180 0x2F4 0x36C 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x180 0x2F4 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x180 0x2F4 0x478 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x180 0x2F4 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180 0x2F4 0x000 0x5 0x0
+
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x184 0x2F8 0x000 0x0 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x184 0x2F8 0x000 0x1 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x184 0x2F8 0x000 0x2 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x184 0x2F8 0x474 0x3 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x184 0x2F8 0x000 0x4 0x0
+#define MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184 0x2F8 0x000 0x5 0x0
+
+#endif /* _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/5] Add support for i.MXRT1020-EVK board
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
` (3 preceding siblings ...)
2020-02-18 19:02 ` [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition Giulio Benetti
@ 2020-02-18 19:02 ` Giulio Benetti
2020-02-20 23:00 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
2020-04-18 12:32 ` [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
5 siblings, 2 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-18 19:02 UTC (permalink / raw)
To: u-boot
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 44 ++++
arch/arm/dts/imxrt1020-evk.dts | 198 ++++++++++++++++++
arch/arm/mach-imx/imxrt/Kconfig | 5 +
board/freescale/imxrt1020-evk/Kconfig | 22 ++
board/freescale/imxrt1020-evk/MAINTAINERS | 6 +
board/freescale/imxrt1020-evk/Makefile | 6 +
board/freescale/imxrt1020-evk/README | 31 +++
board/freescale/imxrt1020-evk/imximage.cfg | 36 ++++
board/freescale/imxrt1020-evk/imxrt1020-evk.c | 81 +++++++
configs/imxrt1020-evk_defconfig | 67 ++++++
include/configs/imxrt1020-evk.h | 46 ++++
12 files changed, 544 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1020-evk.dts
create mode 100644 board/freescale/imxrt1020-evk/Kconfig
create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1020-evk/Makefile
create mode 100644 board/freescale/imxrt1020-evk/README
create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg
create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c
create mode 100644 configs/imxrt1020-evk_defconfig
create mode 100644 include/configs/imxrt1020-evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index be4cf029d0..1116c44cf4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -723,7 +723,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-evk.dtb \
imx8mp-evk.dtb
-dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
+ imxrt1020-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
new file mode 100644
index 0000000000..d32c98de9c
--- /dev/null
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ bank1: bank at 0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1020-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
new file mode 100644
index 0000000000..ece13601bd
--- /dev/null
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1020.dtsi"
+#include "imxrt1020-evk-u-boot.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1020.h>
+
+/ {
+ model = "NXP IMXRT1020-evk board";
+ compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x80000000 0x2000000>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+ * Memory configuration from sdram datasheet IS42S16160J-6TLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank at 0 {
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ imxrt1020-evk {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
+ 0xf1
+ MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
+ 0xf1
+ >;
+ };
+
+ pinctrl_semc: semcgrp {
+ fsl,pins = <
+ MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1 /* SEMC_D0 */
+ MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1 /* SEMC_D3 */
+ MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1 /* SEMC_D4 */
+ MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1 /* SEMC_D5 */
+ MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1 /* SEMC_D6 */
+ MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1 /* SEMC_D7 */
+ MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1 /* SEMC_DM0 */
+ MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1 /* SEMC_A0 */
+ MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
+ 0xf1 /* SEMC_CAS */
+ MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
+ 0xf1 /* SEMC_RAS */
+ MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
+ 0xf1 /* SEMC_CS0 */
+ MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
+ 0xf1 /* SEMC_BA0 */
+ MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
+ 0xf1 /* SEMC_BA1 */
+ MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
+ 0xf1 /* SEMC_A10 */
+ MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
+ 0xf1 /* SEMC_A0 */
+ MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
+ 0xf1 /* SEMC_A1 */
+ MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
+ 0xf1 /* SEMC_A2 */
+ MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
+ 0xf1 /* SEMC_A3 */
+ MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
+ 0xf1 /* SEMC_A4 */
+ MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
+ 0xf1 /* SEMC_A5 */
+ MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
+ 0xf1 /* SEMC_A6 */
+ MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
+ 0xf1 /* SEMC_A7 */
+ MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
+ 0xf1 /* SEMC_A8 */
+ MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
+ 0xf1 /* SEMC_A9 */
+ MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
+ 0xf1 /* SEMC_A11 */
+ MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
+ 0xf1 /* SEMC_A12 */
+ MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
+ (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
+ 0xf1 /* SEMC_CKE */
+ MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
+ 0xf1 /* SEMC_CLK */
+ MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
+ 0xf1 /* SEMC_DM01 */
+ MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
+ 0xf1 /* SEMC_D8 */
+ MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
+ 0xf1 /* SEMC_D9 */
+ MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
+ 0xf1 /* SEMC_D10 */
+ MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
+ 0xf1 /* SEMC_D11 */
+ MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
+ 0xf1 /* SEMC_D12 */
+ MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
+ 0xf1 /* SEMC_D13 */
+ MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
+ 0xf1 /* SEMC_D14 */
+ MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
+ 0xf1 /* SEMC_D15 */
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
+ 0x1B000
+ MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
+ 0x17061
+ MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
+ 0x17061
+ MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
+ 0x17061
+ MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
+ 0x17061
+ MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
+ 0x17061
+ MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
+ 0x17061
+ >;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+
+ cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index f28d52d3b7..d275fdf72e 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -18,12 +18,17 @@ choice
prompt "NXP i.MXRT board select"
optional
+config TARGET_IMXRT1020_EVK
+ bool "Support imxrt1020 EVK board"
+ select IMXRT1020
+
config TARGET_IMXRT1050_EVK
bool "Support imxrt1050 EVK board"
select IMXRT1050
endchoice
+source "board/freescale/imxrt1020-evk/Kconfig"
source "board/freescale/imxrt1050-evk/Kconfig"
endif
diff --git a/board/freescale/imxrt1020-evk/Kconfig b/board/freescale/imxrt1020-evk/Kconfig
new file mode 100644
index 0000000000..d00cbff094
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMXRT1020_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1020-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt1020"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1020-evk"
+
+config IMX_CONFIG
+ default "board/freescale/imxrt1020-evk/imximage.cfg"
+
+endif
diff --git a/board/freescale/imxrt1020-evk/MAINTAINERS b/board/freescale/imxrt1020-evk/MAINTAINERS
new file mode 100644
index 0000000000..05f017b2ba
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1020 EVALUATION KIT
+M: Giulio Benetti <giulio.benetti@benettiengineering.com>
+S: Maintained
+F: board/freescale/imxrt1020-evk
+F: include/configs/imxrt1020-evk.h
+F: configs/imxrt1020-evk_defconfig
diff --git a/board/freescale/imxrt1020-evk/Makefile b/board/freescale/imxrt1020-evk/Makefile
new file mode 100644
index 0000000000..807dc7c35e
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y := imxrt1020-evk.o
diff --git a/board/freescale/imxrt1020-evk/README b/board/freescale/imxrt1020-evk/README
new file mode 100644
index 0000000000..3da72fdad2
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/README
@@ -0,0 +1,31 @@
+How to use U-Boot on NXP i.MXRT1020 EVK
+-----------------------------------------------
+
+- Build U-Boot for i.MXRT1020 EVK:
+
+$ make mrproper
+$ make imxrt1020-evk_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+
+- Jumper settings:
+
+SW8: 0 1 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the ethernet connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/freescale/imxrt1020-evk/imximage.cfg b/board/freescale/imxrt1020-evk/imximage.cfg
new file mode 100644
index 0000000000..9bcc2c1590
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/imximage.cfg
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Set all FlexRAM as OCRAM(01b) */
+DATA 4 0x400AC044 0x00005555
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c
new file mode 100644
index 0000000000..06ad524d5d
--- /dev/null
+++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
new file mode 100644
index 0000000000..2f35df1896
--- /dev/null
+++ b/configs/imxrt1020-evk_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMXRT=y
+CONFIG_SYS_TEXT_BASE=0x80002000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMXRT1020_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_SIZE_LIMIT=131072
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x20209000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
+# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_DM_GPIO is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMXRT1020=y
+CONFIG_CLK_IMXRT1020=y
+CONFIG_MXC_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
new file mode 100644
index 0000000000..8e54565f1a
--- /dev/null
+++ b/include/configs/imxrt1020-evk.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __IMXRT1020_EVK_H
+#define __IMXRT1020_EVK_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR 0x20209000
+#else
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_LOADADDR 0x80000000
+#endif
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
+
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
+
+#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
+#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
+ DMAMEM_SZ_ALL)
+
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x800023FD
+#endif
+/* For SPL ends */
+
+#endif /* __IMXRT1020_EVK_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
@ 2020-02-20 22:33 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: Lukasz Majewski @ 2020-02-20 22:33 UTC (permalink / raw)
To: u-boot
On Tue, 18 Feb 2020 20:02:51 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
> Add i.MXRT1020 clk driver support.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/clk/imx/Kconfig | 16 ++
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-imxrt1020.c | 227
> ++++++++++++++++++++ include/dt-bindings/clock/imxrt1020-clock.h |
> 52 +++++ 4 files changed, 296 insertions(+)
> create mode 100644 drivers/clk/imx/clk-imxrt1020.c
> create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
>
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 059bc2fbb9..96721bcbf3 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -69,6 +69,22 @@ config CLK_IMX8MP
> help
> This enables support clock driver for i.MX8MP platforms.
>
> +config SPL_CLK_IMXRT1020
> + bool "SPL clock support for i.MXRT1020"
> + depends on ARCH_IMXRT && SPL
> + select SPL_CLK
> + select SPL_CLK_CCF
> + help
> + This enables SPL DM/DTS support for clock driver in
> i.MXRT1020 +
> +config CLK_IMXRT1020
> + bool "Clock support for i.MXRT1020"
> + depends on ARCH_IMXRT
> + select CLK
> + select CLK_CCF
> + help
> + This enables support clock driver for i.MXRT1020 platforms.
> +
> config SPL_CLK_IMXRT1050
> bool "SPL clock support for i.MXRT1050"
> depends on ARCH_IMXRT && SPL
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 1e8a49d0f3..01bbbdf3ae 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
> clk-pll14xx.o \ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o
> clk-pll14xx.o \ clk-composite-8m.o
>
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
> obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> diff --git a/drivers/clk/imx/clk-imxrt1020.c
> b/drivers/clk/imx/clk-imxrt1020.c new file mode 100644
> index 0000000000..840f783940
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1020.c
> @@ -0,0 +1,227 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <dt-bindings/clock/imxrt1020-clock.h>
> +
> +#include "clk.h"
> +
> +static ulong imxrt1020_clk_get_rate(struct clk *clk)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu)\n", __func__, clk->id);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + return clk_get_rate(c);
> +}
> +
> +static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long
> rate) +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + return clk_set_rate(c, rate);
> +}
> +
> +static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + if (enable)
> + ret = clk_enable(c);
> + else
> + ret = clk_disable(c);
> +
> + return ret;
> +}
> +
> +static int imxrt1020_clk_disable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 0);
> +}
> +
> +static int imxrt1020_clk_enable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 1);
> +}
> +
> +static struct clk_ops imxrt1020_clk_ops = {
> + .set_rate = imxrt1020_clk_set_rate,
> + .get_rate = imxrt1020_clk_get_rate,
> + .enable = imxrt1020_clk_enable,
> + .disable = imxrt1020_clk_disable,
> +};
> +
> +static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
> +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg",
> "osc", }; +
> +static const char *const pre_periph_sels[] = { "pll2_sys",
> "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", }; +static const
> char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static
> const char *const usdhc_sels[] = { "pll2_pfd2_396m",
> "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = {
> "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = {
> "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const
> semc_sels[] = { "periph_sel", "semc_alt_sel", }; + +static int
> imxrt1020_clk_probe(struct udevice *dev) +{
> + void *base;
> +
> + /* Anatop clocks */
> + base = (void *)ANATOP_BASE_ADDR;
> +
> + clk_dm(IMXRT1020_CLK_PLL2_SYS,
> + imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
> + base + 0x30, 0x1));
> + clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
> + imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
> + base + 0x10, 0x1));
> +
> + /* PLL bypass out */
> + clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
> + imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
> + pll2_bypass_sels,
> + ARRAY_SIZE(pll2_bypass_sels),
> + CLK_SET_RATE_PARENT));
> + clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
> + imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
> + pll3_bypass_sels,
> + ARRAY_SIZE(pll3_bypass_sels),
> + CLK_SET_RATE_PARENT));
> +
> + clk_dm(IMXRT1020_CLK_PLL3_80M,
> + imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg",
> 1, 6)); +
> + clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
> + imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base +
> 0x100, 0));
> + clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
> + imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base +
> 0x100, 1));
> + clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
> + imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base +
> 0x100, 2));
> + clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
> + imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base +
> 0x100, 3));
> + clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
> + imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base
> + 0xf0, 1));
> + clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
> + imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base
> + 0xf0, 3)); +
> + /* CCM clocks */
> + base = dev_read_addr_ptr(dev);
> + if (base == (void *)FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
> + imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
> + pre_periph_sels,
> ARRAY_SIZE(pre_periph_sels)));
> + clk_dm(IMXRT1020_CLK_PERIPH_SEL,
> + imx_clk_mux("periph_sel", base + 0x14, 25, 1,
> + periph_sels, ARRAY_SIZE(periph_sels)));
> + clk_dm(IMXRT1020_CLK_USDHC1_SEL,
> + imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
> + usdhc_sels, ARRAY_SIZE(usdhc_sels)));
> + clk_dm(IMXRT1020_CLK_USDHC2_SEL,
> + imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
> + usdhc_sels, ARRAY_SIZE(usdhc_sels)));
> + clk_dm(IMXRT1020_CLK_LPUART_SEL,
> + imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
> + lpuart_sels, ARRAY_SIZE(lpuart_sels)));
> + clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
> + imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
> + semc_alt_sels,
> ARRAY_SIZE(semc_alt_sels)));
> + clk_dm(IMXRT1020_CLK_SEMC_SEL,
> + imx_clk_mux("semc_sel", base + 0x14, 6, 1,
> + semc_sels, ARRAY_SIZE(semc_sels)));
> +
> + clk_dm(IMXRT1020_CLK_AHB_PODF,
> + imx_clk_divider("ahb_podf", "periph_sel",
> + base + 0x14, 10, 3));
> + clk_dm(IMXRT1020_CLK_USDHC1_PODF,
> + imx_clk_divider("usdhc1_podf", "usdhc1_sel",
> + base + 0x24, 11, 3));
> + clk_dm(IMXRT1020_CLK_USDHC2_PODF,
> + imx_clk_divider("usdhc2_podf", "usdhc2_sel",
> + base + 0x24, 16, 3));
> + clk_dm(IMXRT1020_CLK_LPUART_PODF,
> + imx_clk_divider("lpuart_podf", "lpuart_sel",
> + base + 0x24, 0, 6));
> + clk_dm(IMXRT1020_CLK_SEMC_PODF,
> + imx_clk_divider("semc_podf", "semc_sel",
> + base + 0x14, 16, 3));
> +
> + clk_dm(IMXRT1020_CLK_USDHC1,
> + imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80,
> 2));
> + clk_dm(IMXRT1020_CLK_USDHC2,
> + imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80,
> 4));
> + clk_dm(IMXRT1020_CLK_LPUART1,
> + imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c,
> 24));
> + clk_dm(IMXRT1020_CLK_SEMC,
> + imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
> +
> +#ifdef CONFIG_SPL_BUILD
> + struct clk *clk, *clk1;
> +
> + clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
> + clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
> + clk_set_parent(clk1, clk);
> +
> + /* Configure PLL3_USB_OTG to 480MHz */
> + clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
> + clk_enable(clk);
> + clk_set_rate(clk, 480000000UL);
> +
> + clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
> + clk_set_parent(clk1, clk);
> +
> + clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
> + clk_set_rate(clk, 297000000UL);
> +
> + clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
> + clk_enable(clk);
> + clk_set_rate(clk, 528000000UL);
> +
> + clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
> + clk_set_parent(clk1, clk);
> +
> +#endif
> +
> + return 0;
> +}
> +
> +static const struct udevice_id imxrt1020_clk_ids[] = {
> + { .compatible = "fsl,imxrt1020-ccm" },
> + { },
> +};
> +
> +U_BOOT_DRIVER(imxrt1020_clk) = {
> + .name = "clk_imxrt1020",
> + .id = UCLASS_CLK,
> + .of_match = imxrt1020_clk_ids,
> + .ops = &imxrt1020_clk_ops,
> + .probe = imxrt1020_clk_probe,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/dt-bindings/clock/imxrt1020-clock.h
> b/include/dt-bindings/clock/imxrt1020-clock.h new file mode 100644
> index 0000000000..836244358b
> --- /dev/null
> +++ b/include/dt-bindings/clock/imxrt1020-clock.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
> +#define __DT_BINDINGS_CLOCK_IMXRT1020_H
> +
> +#define IMXRT1020_CLK_DUMMY 0
> +#define IMXRT1020_CLK_CKIL 1
> +#define IMXRT1020_CLK_CKIH 2
> +#define IMXRT1020_CLK_OSC 3
> +#define IMXRT1020_CLK_PLL2_PFD0_352M 4
> +#define IMXRT1020_CLK_PLL2_PFD1_594M 5
> +#define IMXRT1020_CLK_PLL2_PFD2_396M 6
> +#define IMXRT1020_CLK_PLL2_PFD3_297M 7
> +#define IMXRT1020_CLK_PLL3_PFD0_720M 8
> +#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
> +#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
> +#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
> +#define IMXRT1020_CLK_PLL2_198M 12
> +#define IMXRT1020_CLK_PLL3_120M 13
> +#define IMXRT1020_CLK_PLL3_80M 14
> +#define IMXRT1020_CLK_PLL3_60M 15
> +#define IMXRT1020_CLK_PLL2_BYPASS 16
> +#define IMXRT1020_CLK_PLL3_BYPASS 17
> +#define IMXRT1020_CLK_PLL6_BYPASS 18
> +#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
> +#define IMXRT1020_CLK_PERIPH_SEL 20
> +#define IMXRT1020_CLK_SEMC_ALT_SEL 21
> +#define IMXRT1020_CLK_SEMC_SEL 22
> +#define IMXRT1020_CLK_USDHC1_SEL 23
> +#define IMXRT1020_CLK_USDHC2_SEL 24
> +#define IMXRT1020_CLK_LPUART_SEL 25
> +#define IMXRT1020_CLK_ARM_PODF 26
> +#define IMXRT1020_CLK_LPUART_PODF 27
> +#define IMXRT1020_CLK_USDHC1_PODF 28
> +#define IMXRT1020_CLK_USDHC2_PODF 29
> +#define IMXRT1020_CLK_SEMC_PODF 30
> +#define IMXRT1020_CLK_AHB_PODF 31
> +#define IMXRT1020_CLK_USDHC1 32
> +#define IMXRT1020_CLK_USDHC2 33
> +#define IMXRT1020_CLK_LPUART1 34
> +#define IMXRT1020_CLK_SEMC 35
> +#define IMXRT1020_CLK_PLL2_SYS 36
> +#define IMXRT1020_CLK_PLL3_USB_OTG 37
> +#define IMXRT1020_CLK_PLL4_AUDIO 38
> +#define IMXRT1020_CLK_PLL6_ENET 39
> +#define IMXRT1020_CLK_END 40
> +
> +#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH 2/5] Add i.MXRT1020 support
2020-02-18 19:02 ` [PATCH 2/5] Add i.MXRT1020 support Giulio Benetti
@ 2020-02-20 22:35 ` Lukasz Majewski
2020-04-19 9:09 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: Lukasz Majewski @ 2020-02-20 22:35 UTC (permalink / raw)
To: u-boot
On Tue, 18 Feb 2020 20:02:52 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> arch/arm/mach-imx/imxrt/Kconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
> b/arch/arm/mach-imx/imxrt/Kconfig index e3aff11d48..f28d52d3b7 100644
> --- a/arch/arm/mach-imx/imxrt/Kconfig
> +++ b/arch/arm/mach-imx/imxrt/Kconfig
> @@ -3,6 +3,10 @@ if ARCH_IMXRT
> config IMXRT
> bool
>
> +config IMXRT1020
> + bool
> + select IMXRT
> +
> config IMXRT1050
> bool
> select IMXRT
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file
2020-02-18 19:02 ` [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file Giulio Benetti
@ 2020-02-20 22:45 ` Lukasz Majewski
2020-02-20 22:50 ` Giulio Benetti
2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 1 reply; 22+ messages in thread
From: Lukasz Majewski @ 2020-02-20 22:45 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> Add dtsi file for i.MXRT1020.
>
Has this file been ported from Linux kernel? Or is it only available in
U-Boot?
Reviewed-by: Lukasz Majewski <lukma@denx.de>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> arch/arm/dts/imxrt1020.dtsi | 133
> ++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+)
> create mode 100644 arch/arm/dts/imxrt1020.dtsi
>
> diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
> new file mode 100644
> index 0000000000..97f3cec9f3
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include "armv7-m.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/imxrt1020-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/memory/imxrt-sdram.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + mmc0 = &usdhc1;
> + serial0 = &lpuart1;
> + };
> +
> + clocks {
> + u-boot,dm-spl;
> + ckil {
> + compatible = "fsl,imx-ckil", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + ckih1 {
> + compatible = "fsl,imx-ckih1", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + osc {
> + u-boot,dm-spl;
> + compatible = "fsl,imx-osc", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + semc: semc at 402f0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-semc";
> + reg = <0x402f0000 0x4000>;
> + clocks = <&clks IMXRT1020_CLK_SEMC>;
> + pinctrl-0 = <&pinctrl_semc>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +
> + lpuart1: serial at 40184000 {
> + compatible = "fsl,imxrt-lpuart";
> + reg = <0x40184000 0x4000>;
> + interrupts = <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT1020_CLK_LPUART1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + iomuxc: iomuxc at 401f8000 {
> + compatible = "fsl,imxrt-iomuxc";
> + reg = <0x401f8000 0x4000>;
> + fsl,mux_mask = <0x7>;
> + };
> +
> + clks: ccm at 400fc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt1020-ccm";
> + reg = <0x400fc000 0x4000>;
> + interrupts = <GIC_SPI 95
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> +
> + usdhc1: usdhc at 402c0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-usdhc";
> + reg = <0x402c0000 0x10000>;
> + interrupts = <GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT1020_CLK_USDHC1>;
> + clock-names = "per";
> + bus-width = <4>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> +
> + gpio1: gpio at 401b8000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401b8000 0x4000>;
> + interrupts = <GIC_SPI 80
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio at 401bc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401bc000 0x4000>;
> + interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio at 401c0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401c0000 0x4000>;
> + interrupts = <GIC_SPI 84
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file
2020-02-20 22:45 ` Lukasz Majewski
@ 2020-02-20 22:50 ` Giulio Benetti
0 siblings, 0 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-20 22:50 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
On 2/20/20 11:45 PM, Lukasz Majewski wrote:
> Hi Giulio,
>
>> Add dtsi file for i.MXRT1020.
>>
>
> Has this file been ported from Linux kernel? Or is it only available in
> U-Boot?
Only available in U-Boot at the moment.
And thank you for reviewing!
Best regards
--
Giulio Benetti
Benetti Engineering sas
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> arch/arm/dts/imxrt1020.dtsi | 133
>> ++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+)
>> create mode 100644 arch/arm/dts/imxrt1020.dtsi
>>
>> diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
>> new file mode 100644
>> index 0000000000..97f3cec9f3
>> --- /dev/null
>> +++ b/arch/arm/dts/imxrt1020.dtsi
>> @@ -0,0 +1,133 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) 2020
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#include "armv7-m.dtsi"
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/imxrt1020-clock.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/memory/imxrt-sdram.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + gpio0 = &gpio1;
>> + gpio1 = &gpio2;
>> + gpio2 = &gpio3;
>> + mmc0 = &usdhc1;
>> + serial0 = &lpuart1;
>> + };
>> +
>> + clocks {
>> + u-boot,dm-spl;
>> + ckil {
>> + compatible = "fsl,imx-ckil", "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32768>;
>> + };
>> +
>> + ckih1 {
>> + compatible = "fsl,imx-ckih1", "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <0>;
>> + };
>> +
>> + osc {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imx-osc", "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + };
>> + };
>> +
>> + soc {
>> + u-boot,dm-spl;
>> +
>> + semc: semc at 402f0000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt-semc";
>> + reg = <0x402f0000 0x4000>;
>> + clocks = <&clks IMXRT1020_CLK_SEMC>;
>> + pinctrl-0 = <&pinctrl_semc>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> + };
>> +
>> + lpuart1: serial at 40184000 {
>> + compatible = "fsl,imxrt-lpuart";
>> + reg = <0x40184000 0x4000>;
>> + interrupts = <GIC_SPI 20
>> IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks IMXRT1020_CLK_LPUART1>;
>> + clock-names = "per";
>> + status = "disabled";
>> + };
>> +
>> + iomuxc: iomuxc at 401f8000 {
>> + compatible = "fsl,imxrt-iomuxc";
>> + reg = <0x401f8000 0x4000>;
>> + fsl,mux_mask = <0x7>;
>> + };
>> +
>> + clks: ccm at 400fc000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt1020-ccm";
>> + reg = <0x400fc000 0x4000>;
>> + interrupts = <GIC_SPI 95
>> IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 96
>> IRQ_TYPE_LEVEL_HIGH>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + usdhc1: usdhc at 402c0000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt-usdhc";
>> + reg = <0x402c0000 0x10000>;
>> + interrupts = <GIC_SPI 110
>> IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks IMXRT1020_CLK_USDHC1>;
>> + clock-names = "per";
>> + bus-width = <4>;
>> + fsl,tuning-start-tap = <20>;
>> + fsl,tuning-step= <2>;
>> + status = "disabled";
>> + };
>> +
>> + gpio1: gpio at 401b8000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> + reg = <0x401b8000 0x4000>;
>> + interrupts = <GIC_SPI 80
>> IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 81
>> IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpio2: gpio at 401bc000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> + reg = <0x401bc000 0x4000>;
>> + interrupts = <GIC_SPI 82
>> IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpio3: gpio at 401c0000 {
>> + u-boot,dm-spl;
>> + compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> + reg = <0x401c0000 0x4000>;
>> + interrupts = <GIC_SPI 84
>> IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +};
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition
2020-02-18 19:02 ` [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition Giulio Benetti
@ 2020-02-20 22:51 ` Lukasz Majewski
2020-02-20 22:55 ` Giulio Benetti
2020-02-25 13:59 ` Giulio Benetti
2020-04-19 9:09 ` sbabic at denx.de
1 sibling, 2 replies; 22+ messages in thread
From: Lukasz Majewski @ 2020-02-20 22:51 UTC (permalink / raw)
To: u-boot
On Tue, 18 Feb 2020 20:02:54 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
> Add i.MXRT1020 pins definition.
Are those definitions ported from Linux kernel?
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> include/dt-bindings/pinctrl/pins-imxrt1020.h | 763
> +++++++++++++++++++ 1 file changed, 763 insertions(+)
> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
>
> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
> b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644
> index 0000000000..c6bacb7378
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
> @@ -0,0 +1,763 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
> +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
> +
> +/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
> +
> +#define IMX_PAD_SION 0x40000000
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
> 0x014 0x188 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0
> 0x014 0x188 0x420 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B
> 0x014 0x188 0x3E0 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014
> 0x188 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
> 0x014 0x188 0x3B0 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00
> 0x014 0x188 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX
> 0x014 0x188 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02
> 0x014 0x188 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
> 0x018 0x18C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1
> 0x018 0x18C 0x424 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B
> 0x018 0x18C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT
> 0x018 0x18C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
> 0x018 0x18C 0x3AC 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01
> 0x018 0x18C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX
> 0x018 0x18C 0x320 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03
> 0x018 0x18C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
> 0x01C 0x190 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2
> 0x01C 0x190 0x428 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX
> 0x01C 0x190 0x3E8 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK
> 0x01C 0x190 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
> 0x01C 0x190 0x3B8 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02
> 0x01C 0x190 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL
> 0x01C 0x190 0x37C 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
> 0x020 0x194 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3
> 0x020 0x194 0x42C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX
> 0x020 0x194 0x3E4 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK
> 0x020 0x194 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
> 0x020 0x194 0x3B4 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03
> 0x020 0x194 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA
> 0x020 0x194 0x380 0x6 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
> 0x024 0x198 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04
> 0x024 0x198 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT
> 0x024 0x198 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024
> 0x198 0x464 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16
> 0x024 0x198 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04
> 0x024 0x198 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
> 0x028 0x19C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05
> 0x028 0x19C 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN
> 0x028 0x19C 0x488 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028
> 0x19C 0x468 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17
> 0x028 0x19C 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05
> 0x028 0x19C 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
> 0x02C 0x1A0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06
> 0x02C 0x1A0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX
> 0x02C 0x1A0 0x3DC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C
> 0x1A0 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18
> 0x02C 0x1A0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06
> 0x02C 0x1A0 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
> 0x030 0x1A4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07
> 0x030 0x1A4 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX
> 0x030 0x1A4 0x3D8 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030
> 0x1A4 0x460 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19
> 0x030 0x1A4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07
> 0x030 0x1A4 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
> 0x034 0x1A8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08
> 0x034 0x1A8 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX
> 0x034 0x1A8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034
> 0x1A8 0x45C 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20
> 0x034 0x1A8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08
> 0x034 0x1A8 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> 0x038 0x1AC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09
> 0x038 0x1AC 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX
> 0x038 0x1AC 0x324 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038
> 0x1AC 0x458 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21
> 0x038 0x1AC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09
> 0x038 0x1AC 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
> 0x03C 0x1B0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10
> 0x03C 0x1B0 0x4B0 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA
> 0x03C 0x1B0 0x398 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C
> 0x1B0 0x450 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK
> 0x03C 0x1B0 0x3B0 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10
> 0x03C 0x1B0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00
> 0x03C 0x1B0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
> 0x040 0x1B4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11
> 0x040 0x1B4 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL
> 0x040 0x1B4 0x394 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040
> 0x1B4 0x44C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0
> 0x040 0x1B4 0x3AC 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11
> 0x040 0x1B4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01
> 0x040 0x1B4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
> 0x044 0x1B8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12
> 0x044 0x1B8 0x4B4 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX
> 0x044 0x1B8 0x3F8 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00
> 0x044 0x1B8 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO
> 0x044 0x1B8 0x3B8 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12
> 0x044 0x1B8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02
> 0x044 0x1B8 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
> 0x048 0x1BC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13
> 0x048 0x1BC 0x4B8 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX
> 0x048 0x1BC 0x3F4 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00
> 0x048 0x1BC 0x438 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI
> 0x048 0x1BC 0x3B4 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13
> 0x048 0x1BC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03
> 0x048 0x1BC 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048
> 0x1BC 0x300 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
> 0x04C 0x1C0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14
> 0x04C 0x1C0 0x4A0 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B
> 0x04C 0x1C0 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C
> 0x1C0 0x434 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
> 0x04C 0x1C0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14
> 0x04C 0x1C0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX
> 0x04C 0x1C0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
> 0x050 0x1C4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15
> 0x050 0x1C4 0x4A4 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B
> 0x050 0x1C4 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050
> 0x1C4 0x448 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B
> 0x050 0x1C4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15
> 0x050 0x1C4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX
> 0x050 0x1C4 0x320 0x6 0x3 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
> 0x054 0x1C8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT
> 0x054 0x1C8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK
> 0x054 0x1C8 0x454 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16
> 0x054 0x1C8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00
> 0x054 0x1C8 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
> 0x058 0x1CC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT
> 0x058 0x1CC 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK
> 0x058 0x1CC 0x46C 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17
> 0x058 0x1CC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01
> 0x058 0x1CC 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
> 0x05C 0x1D0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16
> 0x05C 0x1D0 0x4A8 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA
> 0x05C 0x1D0 0x388 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C
> 0x1D0 0x448 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22
> 0x05C 0x1D0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18
> 0x05C 0x1D0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C
> 0x1D0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
> 0x060 0x1D4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17
> 0x060 0x1D4 0x4AC 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL
> 0x060 0x1D4 0x384 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060
> 0x1D4 0x434 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23
> 0x060 0x1D4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19
> 0x060 0x1D4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060
> 0x1D4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
> 0x064 0x1D8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03
> 0x064 0x1D8 0x334 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B
> 0x064 0x1D8 0x3CC 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK
> 0x064 0x1D8 0x430 0x3 0x3 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24
> 0x064 0x1D8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20
> 0x064 0x1D8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064
> 0x1D8 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
> 0x068 0x1DC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03
> 0x068 0x1DC 0x344 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B
> 0x068 0x1DC 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00
> 0x068 0x1DC 0x438 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25
> 0x068 0x1DC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21
> 0x068 0x1DC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068
> 0x1DC 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
> 0x06C 0x1E0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02
> 0x06C 0x1E0 0x330 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX
> 0x06C 0x1E0 0x3D4 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03
> 0x06C 0x1E0 0x43C 0x3 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26
> 0x06C 0x1E0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22
> 0x06C 0x1E0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C
> 0x1E0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
> 0x070 0x1E4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02
> 0x070 0x1E4 0x340 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX
> 0x070 0x1E4 0x3D0 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02
> 0x070 0x1E4 0x440 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27
> 0x070 0x1E4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23
> 0x070 0x1E4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070
> 0x1E4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
> 0x074 0x1E8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01
> 0x074 0x1E8 0x32C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B
> 0x074 0x1E8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01
> 0x074 0x1E8 0x444 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28
> 0x074 0x1E8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24
> 0x074 0x1E8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074
> 0x1E8 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
> 0x078 0x1EC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01
> 0x078 0x1EC 0x33C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B
> 0x078 0x1EC 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00
> 0x078 0x1EC 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29
> 0x078 0x1EC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25
> 0x078 0x1EC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078
> 0x1EC 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
> 0x07C 0x1F0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00
> 0x07C 0x1F0 0x328 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX
> 0x07C 0x1F0 0x408 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C
> 0x1F0 0x44C 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30
> 0x07C 0x1F0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26
> 0x07C 0x1F0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C
> 0x1F0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
> 0x080 0x1F4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00
> 0x080 0x1F4 0x338 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX
> 0x080 0x1F4 0x404 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080
> 0x1F4 0x450 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31
> 0x080 0x1F4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27
> 0x080 0x1F4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080
> 0x1F4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
> 0x084 0x1F8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03
> 0x084 0x1F8 0x354 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18
> 0x084 0x1F8 0x4BC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK
> 0x084 0x1F8 0x46C 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B
> 0x084 0x1F8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28
> 0x084 0x1F8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2
> 0x084 0x1F8 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00
> 0x084 0x1F8 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
> 0x088 0x1FC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03
> 0x088 0x1FC 0x364 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19
> 0x088 0x1FC 0x4C0 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088
> 0x1FC 0x470 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB
> 0x088 0x1FC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29
> 0x088 0x1FC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2
> 0x088 0x1FC 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01
> 0x088 0x1FC 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
> 0x08C 0x200 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02
> 0x08C 0x200 0x350 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B
> 0x08C 0x200 0x3E0 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C
> 0x200 0x478 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB
> 0x08C 0x200 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30
> 0x08C 0x200 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3
> 0x08C 0x200 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02
> 0x08C 0x200 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
> 0x090 0x204 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02
> 0x090 0x204 0x360 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B
> 0x090 0x204 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090
> 0x204 0x474 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B
> 0x090 0x204 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31
> 0x090 0x204 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK
> 0x090 0x204 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03
> 0x090 0x204 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
> 0x094 0x208 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0
> 0x094 0x208 0x410 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX
> 0x094 0x208 0x3E8 0x2 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094
> 0x208 0x000 0x3 0x4 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK
> 0x094 0x208 0x3C0 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00
> 0x094 0x208 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT
> 0x094 0x208 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
> 0x098 0x20C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1
> 0x098 0x20C 0x414 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX
> 0x098 0x20C 0x3E4 0x2 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098
> 0x20C 0x47C 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0
> 0x098 0x20C 0x3BC 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01
> 0x098 0x20C 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
> 0x09C 0x210 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2
> 0x09C 0x210 0x418 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX
> 0x09C 0x210 0x400 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C
> 0x210 0x480 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO
> 0x09C 0x210 0x3C8 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02
> 0x09C 0x210 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS
> 0x09C 0x210 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
> 0x0A0 0x214 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3
> 0x0A0 0x214 0x41C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX
> 0x0A0 0x214 0x3FC 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP
> 0x0A0 0x214 0x49C 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI
> 0x0A0 0x214 0x3C4 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03
> 0x0A0 0x214 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL
> 0x0A0 0x214 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
> 0x0A4 0x218 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01
> 0x0A4 0x218 0x34C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B
> 0x0A4 0x218 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4
> 0x218 0x300 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1
> 0x0A4 0x218 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04
> 0x0A4 0x218 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK
> 0x0A4 0x218 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP
> 0x0A4 0x218 0x494 0x7 0x4 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
> 0x0A8 0x21C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01
> 0x0A8 0x21C 0x35C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B
> 0x0A8 0x21C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT
> 0x0A8 0x21C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2
> 0x0A8 0x21C 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05
> 0x0A8 0x21C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8
> 0x21C 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT
> 0x0A8 0x21C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
> 0x0AC 0x220 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00
> 0x0AC 0x220 0x348 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX
> 0x0AC 0x220 0x3F0 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT
> 0x0AC 0x220 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3
> 0x0AC 0x220 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06
> 0x0AC 0x220 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC
> 0x220 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B
> 0x0AC 0x220 0x490 0x7 0x3 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
> 0x0B0 0x224 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00
> 0x0B0 0x224 0x358 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX
> 0x0B0 0x224 0x3EC 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC
> 0x0B0 0x224 0x48C 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B
> 0x0B0 0x224 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07
> 0x0B0 0x224 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER
> 0x0B0 0x224 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK
> 0x0B0 0x224 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00
> 0x0B4 0x228 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18
> 0x0B4 0x228 0x4BC 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT
> 0x0B4 0x228 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID
> 0x0B4 0x228 0x2FC 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO
> 0x0B4 0x228 0x308 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08
> 0x0B4 0x228 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4
> 0x228 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3
> 0x0B4 0x228 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY
> 0x0B8 0x22C 0x484 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19
> 0x0B8 0x22C 0x4C0 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN
> 0x0B8 0x22C 0x488 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8
> 0x22C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC
> 0x0B8 0x22C 0x000 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09
> 0x0B8 0x22C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8
> 0x22C 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2
> 0x0B8 0x22C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS
> 0x0BC 0x230 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC
> 0x230 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1
> 0x0BC 0x230 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK
> 0x0C0 0x234 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0
> 0x234 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2
> 0x0C0 0x234 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD
> 0x0C4 0x238 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4
> 0x238 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1
> 0x0C4 0x238 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI
> 0x0C8 0x23C 0x000 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B
> 0x0C8 0x23C 0x498 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B
> 0x0C8 0x23C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK
> 0x0C8 0x23C 0x430 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP
> 0x0C8 0x23C 0x494 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8
> 0x23C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
> 0x0C8 0x23C 0x48C 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY
> 0x0C8 0x23C 0x300 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO
> 0x0CC 0x240 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX
> 0x0CC 0x240 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP
> 0x0CC 0x240 0x494 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0
> 0x0CC 0x240 0x420 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO
> 0x0CC 0x240 0x308 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC
> 0x240 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR
> 0x0CC 0x240 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B
> 0x0CC 0x240 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0
> 0x244 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX
> 0x0D0 0x244 0x320 0x1 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B
> 0x0D0 0x244 0x490 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1
> 0x0D0 0x244 0x424 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC
> 0x0D0 0x244 0x000 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0
> 0x244 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID
> 0x0D0 0x244 0x2FC 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI
> 0x0D0 0x244 0x40C 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00
> 0x0D4 0x248 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT
> 0x0D4 0x248 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4
> 0x248 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2
> 0x0D4 0x248 0x428 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03
> 0x0D4 0x248 0x354 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4
> 0x248 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT
> 0x0D4 0x248 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01
> 0x0D8 0x24C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT
> 0x0D8 0x24C 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8
> 0x24C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3
> 0x0D8 0x24C 0x42C 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03
> 0x0D8 0x24C 0x364 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8
> 0x24C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT
> 0x0D8 0x24C 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK
> 0x0DC 0x250 0x31C 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC
> 0x250 0x38C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B
> 0x0DC 0x250 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00
> 0x0DC 0x250 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1
> 0x0DC 0x250 0x304 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC
> 0x250 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV
> 0x0DC 0x250 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01
> 0x0E0 0x254 0x310 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0
> 0x254 0x390 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B
> 0x0E0 0x254 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00
> 0x0E0 0x254 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0
> 0x254 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV
> 0x0E0 0x254 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00
> 0x0E4 0x258 0x30C 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4
> 0x258 0x3A0 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4
> 0x258 0x3F0 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01
> 0x0E4 0x258 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02
> 0x0E4 0x258 0x350 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4
> 0x258 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK
> 0x0E4 0x258 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8
> 0x25C 0x314 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0
> 0x0E8 0x25C 0x39C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8
> 0x25C 0x3EC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01
> 0x0E8 0x25C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02
> 0x0E8 0x25C 0x360 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8
> 0x25C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO
> 0x0E8 0x25C 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC
> 0x260 0x318 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC
> 0x260 0x3A8 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B
> 0x0EC 0x260 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02
> 0x0EC 0x260 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01
> 0x0EC 0x260 0x34C 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC
> 0x260 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00
> 0x0EC 0x260 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL
> 0x0EC 0x260 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0
> 0x264 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0
> 0x264 0x3A4 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B
> 0x0F0 0x264 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02
> 0x0F0 0x264 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01
> 0x0F0 0x264 0x35C 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0
> 0x264 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01
> 0x0F0 0x264 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B
> 0x0F0 0x264 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00
> 0x0F4 0x268 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
> 0x0F4 0x268 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4
> 0x268 0x3DC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03
> 0x0F4 0x268 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00
> 0x0F4 0x268 0x348 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4
> 0x268 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02
> 0x0F4 0x268 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY
> 0x0F4 0x268 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01
> 0x0F8 0x26C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
> 0x0F8 0x26C 0x324 0x1 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8
> 0x26C 0x3D8 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03
> 0x0F8 0x26C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00
> 0x0F8 0x26C 0x358 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8
> 0x26C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03
> 0x0F8 0x26C 0x000 0x6 0x2 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC
> 0x270 0x484 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03
> 0x0FC 0x270 0x374 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX
> 0x0FC 0x270 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK
> 0x0FC 0x270 0x430 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15
> 0x0FC 0x270 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC
> 0x270 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT
> 0x0FC 0x270 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04
> 0x0FC 0x270 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100
> 0x274 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK
> 0x100 0x274 0x378 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX
> 0x100 0x274 0x324 0x2 0x3 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK
> 0x100 0x274 0x44C 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14
> 0x100 0x274 0x000 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100
> 0x274 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN
> 0x100 0x274 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04
> 0x100 0x274 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104
> 0x278 0x000 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00
> 0x104 0x278 0x368 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104
> 0x278 0x3C0 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC
> 0x104 0x278 0x450 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13
> 0x104 0x278 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104
> 0x278 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT
> 0x104 0x278 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05
> 0x104 0x278 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108
> 0x27C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02
> 0x108 0x27C 0x370 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0
> 0x108 0x27C 0x3BC 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00
> 0x108 0x27C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12
> 0x108 0x27C 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108
> 0x27C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN
> 0x108 0x27C 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05
> 0x108 0x27C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C
> 0x280 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01
> 0x10C 0x280 0x36C 0x1 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C
> 0x280 0x3C8 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC
> 0x10C 0x280 0x448 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11
> 0x10C 0x280 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C
> 0x280 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1
> 0x10C 0x280 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06
> 0x10C 0x280 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP
> 0x110 0x284 0x494 0x0 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B
> 0x110 0x284 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110
> 0x284 0x3C4 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00
> 0x110 0x284 0x438 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10
> 0x110 0x284 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110
> 0x284 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2
> 0x110 0x284 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06
> 0x110 0x284 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B
> 0x114 0x288 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00
> 0x114 0x288 0x328 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B
> 0x114 0x288 0x3CC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK
> 0x114 0x288 0x434 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09
> 0x114 0x288 0x000 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114
> 0x288 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3
> 0x114 0x288 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07
> 0x114 0x288 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT
> 0x118 0x28C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00
> 0x118 0x28C 0x338 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B
> 0x118 0x28C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01
> 0x118 0x28C 0x444 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08
> 0x118 0x28C 0x000 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118
> 0x28C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3
> 0x118 0x28C 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07
> 0x118 0x28C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C
> 0x290 0x384 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01
> 0x11C 0x290 0x32C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C
> 0x290 0x3D4 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02
> 0x11C 0x290 0x440 0x3 0x3 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07
> 0x11C 0x290 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C
> 0x290 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2
> 0x11C 0x290 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12
> 0x11C 0x290 0x4B4 0x7 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120
> 0x294 0x388 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01
> 0x120 0x294 0x33C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120
> 0x294 0x3D0 0x2 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03
> 0x120 0x294 0x43C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26
> 0x120 0x294 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120
> 0x294 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1
> 0x120 0x294 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13
> 0x120 0x294 0x4B8 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR
> 0x124 0x298 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02
> 0x124 0x298 0x330 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124
> 0x298 0x3E8 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B
> 0x124 0x298 0x490 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05
> 0x124 0x298 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124
> 0x298 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1
> 0x124 0x298 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID
> 0x128 0x29C 0x2FC 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02
> 0x128 0x29C 0x340 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128
> 0x29C 0x3E4 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP
> 0x128 0x29C 0x494 0x3 0x3 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04
> 0x128 0x29C 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128
> 0x29C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1
> 0x128 0x29C 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC
> 0x12C 0x2A0 0x48C 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
> 0x12C 0x2A0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C
> 0x2A0 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B
> 0x12C 0x2A0 0x498 0x3 0x2 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03
> 0x12C 0x2A0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C
> 0x2A0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03
> 0x12C 0x2A0 0x334 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ
> 0x130 0x2A4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
> 0x130 0x2A4 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0
> 0x130 0x2A4 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP
> 0x130 0x2A4 0x49C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02
> 0x130 0x2A4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130
> 0x2A4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03
> 0x130 0x2A4 0x344 0x6 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134
> 0x2A8 0x37C 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
> 0x134 0x2A8 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134
> 0x2A8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT
> 0x134 0x2A8 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01
> 0x134 0x2A8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134
> 0x2A8 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138
> 0x2AC 0x380 0x0 0x1 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
> 0x138 0x2AC 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138
> 0x2AC 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN
> 0x138 0x2AC 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00
> 0x138 0x2AC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138
> 0x2AC 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
> 0x13C 0x2B0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0
> 0x13C 0x2B0 0x410 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK
> 0x13C 0x2B0 0x430 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK
> 0x13C 0x2B0 0x454 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C
> 0x2B0 0x38C 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C
> 0x2B0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
> 0x13C 0x2B0 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14
> 0x13C 0x2B0 0x4A0 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
> 0x140 0x2B4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1
> 0x140 0x2B4 0x414 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT
> 0x140 0x2B4 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC
> 0x140 0x2B4 0x460 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140
> 0x2B4 0x390 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140
> 0x2B4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
> 0x140 0x2B4 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15
> 0x140 0x2B4 0x4A4 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144
> 0x2B8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2
> 0x144 0x2B8 0x418 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B
> 0x144 0x2B8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK
> 0x144 0x2B8 0x458 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144
> 0x2B8 0x3A0 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144
> 0x2B8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO
> 0x144 0x2B8 0x308 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16
> 0x144 0x2B8 0x4A8 0x7 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148
> 0x2BC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3
> 0x148 0x2BC 0x41C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B
> 0x148 0x2BC 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA
> 0x148 0x2BC 0x45C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0
> 0x148 0x2BC 0x39C 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148
> 0x2BC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC
> 0x148 0x2BC 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
> 0x14C 0x2C0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX
> 0x14C 0x2C0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C
> 0x2C0 0x400 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA
> 0x14C 0x2C0 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C
> 0x2C0 0x3A8 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C
> 0x2C0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
> 0x14C 0x2C0 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
> 0x150 0x2C4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX
> 0x150 0x2C4 0x324 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150
> 0x2C4 0x3FC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK
> 0x150 0x2C4 0x464 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150
> 0x2C4 0x3A4 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150
> 0x2C4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
> 0x150 0x2C4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
> 0x154 0x2C8 0x490 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B
> 0x154 0x2C8 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT
> 0x154 0x2C8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC
> 0x154 0x2C8 0x468 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B
> 0x154 0x2C8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154
> 0x2C8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17
> 0x154 0x2C8 0x4AC 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2
> 0x158 0x2CC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03
> 0x158 0x2CC 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158
> 0x2CC 0x3F8 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10
> 0x158 0x2CC 0x4B0 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX
> 0x158 0x2CC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158
> 0x2CC 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3
> 0x15C 0x2D0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK
> 0x15C 0x2D0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C
> 0x2D0 0x3F4 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B
> 0x15C 0x2D0 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX
> 0x15C 0x2D0 0x320 0x4 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C
> 0x2D0 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160
> 0x2D4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00
> 0x160 0x2D4 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160
> 0x2D4 0x408 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160
> 0x2D4 0x394 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT
> 0x160 0x2D4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160
> 0x2D4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1
> 0x160 0x2D4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164
> 0x2D8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02
> 0x164 0x2D8 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164
> 0x2D8 0x404 0x2 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164
> 0x2D8 0x398 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN
> 0x164 0x2D8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164
> 0x2D8 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2
> 0x164 0x2D8 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0
> 0x168 0x2DC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01
> 0x168 0x2DC 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK
> 0x168 0x2DC 0x31C 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1
> 0x168 0x2DC 0x304 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B
> 0x168 0x2DC 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168
> 0x2DC 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT
> 0x168 0x2DC 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1
> 0x16C 0x2E0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
> 0x16C 0x2E0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01
> 0x16C 0x2E0 0x310 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK
> 0x16C 0x2E0 0x46C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B
> 0x16C 0x2E0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C
> 0x2E0 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY
> 0x16C 0x2E0 0x300 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B
> 0x170 0x2E4 0x498 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03
> 0x170 0x2E4 0x374 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00
> 0x170 0x2E4 0x30C 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK
> 0x170 0x2E4 0x47C 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
> 0x170 0x2E4 0x3AC 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170
> 0x2E4 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP
> 0x170 0x2E4 0x000 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B
> 0x174 0x2E8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
> 0x174 0x2E8 0x378 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174
> 0x2E8 0x314 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC
> 0x174 0x2E8 0x480 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174
> 0x2E8 0x3B0 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174
> 0x2E8 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
> 0x178 0x2EC 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00
> 0x178 0x2EC 0x368 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178
> 0x2EC 0x318 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA
> 0x178 0x2EC 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178
> 0x2EC 0x3B8 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178
> 0x2EC 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
> 0x17C 0x2F0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02
> 0x17C 0x2F0 0x370 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C
> 0x2F0 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK
> 0x17C 0x2F0 0x470 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C
> 0x2F0 0x3B4 0x4 0x2 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C
> 0x2F0 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
> 0x180 0x2F4 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01
> 0x180 0x2F4 0x36C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00
> 0x180 0x2F4 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC
> 0x180 0x2F4 0x478 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
> 0x180 0x2F4 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180
> 0x2F4 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
> 0x184 0x2F8 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B
> 0x184 0x2F8 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01
> 0x184 0x2F8 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA
> 0x184 0x2F8 0x474 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
> 0x184 0x2F8 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184
> 0x2F8 0x000 0x5 0x0 + +#endif /*
> _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition
2020-02-20 22:51 ` Lukasz Majewski
@ 2020-02-20 22:55 ` Giulio Benetti
2020-02-25 13:59 ` Giulio Benetti
1 sibling, 0 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-20 22:55 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
On 2/20/20 11:51 PM, Lukasz Majewski wrote:
> On Tue, 18 Feb 2020 20:02:54 +0100
> Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
>
>> Add i.MXRT1020 pins definition.
>
> Are those definitions ported from Linux kernel?
No, this is the first implementation for U-Boot, I'll do it for Linux later.
Best regards
--
Giulio Benetti
Benetti Engineering sas
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> include/dt-bindings/pinctrl/pins-imxrt1020.h | 763
>> +++++++++++++++++++ 1 file changed, 763 insertions(+)
>> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
>>
>> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
>> b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644
>> index 0000000000..c6bacb7378
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
>> @@ -0,0 +1,763 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2020
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
>> +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
>> +
>> +/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
>> +
>> +#define IMX_PAD_SION 0x40000000
>> +
>> +/*
>> + * The pin function ID is a tuple of
>> + * <mux_reg conf_reg input_reg mux_mode input_val>
>> + */
>> +
>> +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
>> 0x014 0x188 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0
>> 0x014 0x188 0x420 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B
>> 0x014 0x188 0x3E0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014
>> 0x188 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
>> 0x014 0x188 0x3B0 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00
>> 0x014 0x188 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX
>> 0x014 0x188 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02
>> 0x014 0x188 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
>> 0x018 0x18C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1
>> 0x018 0x18C 0x424 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B
>> 0x018 0x18C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT
>> 0x018 0x18C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
>> 0x018 0x18C 0x3AC 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01
>> 0x018 0x18C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX
>> 0x018 0x18C 0x320 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03
>> 0x018 0x18C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
>> 0x01C 0x190 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2
>> 0x01C 0x190 0x428 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX
>> 0x01C 0x190 0x3E8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK
>> 0x01C 0x190 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
>> 0x01C 0x190 0x3B8 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02
>> 0x01C 0x190 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL
>> 0x01C 0x190 0x37C 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
>> 0x020 0x194 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3
>> 0x020 0x194 0x42C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX
>> 0x020 0x194 0x3E4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK
>> 0x020 0x194 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
>> 0x020 0x194 0x3B4 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03
>> 0x020 0x194 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA
>> 0x020 0x194 0x380 0x6 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
>> 0x024 0x198 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04
>> 0x024 0x198 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT
>> 0x024 0x198 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024
>> 0x198 0x464 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16
>> 0x024 0x198 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04
>> 0x024 0x198 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
>> 0x028 0x19C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05
>> 0x028 0x19C 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN
>> 0x028 0x19C 0x488 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028
>> 0x19C 0x468 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17
>> 0x028 0x19C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05
>> 0x028 0x19C 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
>> 0x02C 0x1A0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06
>> 0x02C 0x1A0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX
>> 0x02C 0x1A0 0x3DC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C
>> 0x1A0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18
>> 0x02C 0x1A0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06
>> 0x02C 0x1A0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
>> 0x030 0x1A4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07
>> 0x030 0x1A4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX
>> 0x030 0x1A4 0x3D8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030
>> 0x1A4 0x460 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19
>> 0x030 0x1A4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07
>> 0x030 0x1A4 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
>> 0x034 0x1A8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08
>> 0x034 0x1A8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX
>> 0x034 0x1A8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034
>> 0x1A8 0x45C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20
>> 0x034 0x1A8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08
>> 0x034 0x1A8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>> 0x038 0x1AC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09
>> 0x038 0x1AC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX
>> 0x038 0x1AC 0x324 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038
>> 0x1AC 0x458 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21
>> 0x038 0x1AC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09
>> 0x038 0x1AC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
>> 0x03C 0x1B0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10
>> 0x03C 0x1B0 0x4B0 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA
>> 0x03C 0x1B0 0x398 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C
>> 0x1B0 0x450 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK
>> 0x03C 0x1B0 0x3B0 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10
>> 0x03C 0x1B0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00
>> 0x03C 0x1B0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
>> 0x040 0x1B4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11
>> 0x040 0x1B4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL
>> 0x040 0x1B4 0x394 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040
>> 0x1B4 0x44C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0
>> 0x040 0x1B4 0x3AC 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11
>> 0x040 0x1B4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01
>> 0x040 0x1B4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
>> 0x044 0x1B8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12
>> 0x044 0x1B8 0x4B4 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX
>> 0x044 0x1B8 0x3F8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00
>> 0x044 0x1B8 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO
>> 0x044 0x1B8 0x3B8 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12
>> 0x044 0x1B8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02
>> 0x044 0x1B8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
>> 0x048 0x1BC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13
>> 0x048 0x1BC 0x4B8 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX
>> 0x048 0x1BC 0x3F4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00
>> 0x048 0x1BC 0x438 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI
>> 0x048 0x1BC 0x3B4 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13
>> 0x048 0x1BC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03
>> 0x048 0x1BC 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048
>> 0x1BC 0x300 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
>> 0x04C 0x1C0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14
>> 0x04C 0x1C0 0x4A0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B
>> 0x04C 0x1C0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C
>> 0x1C0 0x434 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
>> 0x04C 0x1C0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14
>> 0x04C 0x1C0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX
>> 0x04C 0x1C0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
>> 0x050 0x1C4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15
>> 0x050 0x1C4 0x4A4 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B
>> 0x050 0x1C4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050
>> 0x1C4 0x448 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B
>> 0x050 0x1C4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15
>> 0x050 0x1C4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX
>> 0x050 0x1C4 0x320 0x6 0x3 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
>> 0x054 0x1C8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT
>> 0x054 0x1C8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK
>> 0x054 0x1C8 0x454 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16
>> 0x054 0x1C8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00
>> 0x054 0x1C8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
>> 0x058 0x1CC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT
>> 0x058 0x1CC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK
>> 0x058 0x1CC 0x46C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17
>> 0x058 0x1CC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01
>> 0x058 0x1CC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
>> 0x05C 0x1D0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16
>> 0x05C 0x1D0 0x4A8 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA
>> 0x05C 0x1D0 0x388 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C
>> 0x1D0 0x448 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22
>> 0x05C 0x1D0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18
>> 0x05C 0x1D0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C
>> 0x1D0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
>> 0x060 0x1D4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17
>> 0x060 0x1D4 0x4AC 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL
>> 0x060 0x1D4 0x384 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060
>> 0x1D4 0x434 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23
>> 0x060 0x1D4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19
>> 0x060 0x1D4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060
>> 0x1D4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
>> 0x064 0x1D8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03
>> 0x064 0x1D8 0x334 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B
>> 0x064 0x1D8 0x3CC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK
>> 0x064 0x1D8 0x430 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24
>> 0x064 0x1D8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20
>> 0x064 0x1D8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064
>> 0x1D8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
>> 0x068 0x1DC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03
>> 0x068 0x1DC 0x344 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B
>> 0x068 0x1DC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00
>> 0x068 0x1DC 0x438 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25
>> 0x068 0x1DC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21
>> 0x068 0x1DC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068
>> 0x1DC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
>> 0x06C 0x1E0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02
>> 0x06C 0x1E0 0x330 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX
>> 0x06C 0x1E0 0x3D4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03
>> 0x06C 0x1E0 0x43C 0x3 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26
>> 0x06C 0x1E0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22
>> 0x06C 0x1E0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C
>> 0x1E0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
>> 0x070 0x1E4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02
>> 0x070 0x1E4 0x340 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX
>> 0x070 0x1E4 0x3D0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02
>> 0x070 0x1E4 0x440 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27
>> 0x070 0x1E4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23
>> 0x070 0x1E4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070
>> 0x1E4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
>> 0x074 0x1E8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01
>> 0x074 0x1E8 0x32C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B
>> 0x074 0x1E8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01
>> 0x074 0x1E8 0x444 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28
>> 0x074 0x1E8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24
>> 0x074 0x1E8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074
>> 0x1E8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
>> 0x078 0x1EC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01
>> 0x078 0x1EC 0x33C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B
>> 0x078 0x1EC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00
>> 0x078 0x1EC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29
>> 0x078 0x1EC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25
>> 0x078 0x1EC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078
>> 0x1EC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
>> 0x07C 0x1F0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00
>> 0x07C 0x1F0 0x328 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX
>> 0x07C 0x1F0 0x408 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C
>> 0x1F0 0x44C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30
>> 0x07C 0x1F0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26
>> 0x07C 0x1F0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C
>> 0x1F0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
>> 0x080 0x1F4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00
>> 0x080 0x1F4 0x338 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX
>> 0x080 0x1F4 0x404 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080
>> 0x1F4 0x450 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31
>> 0x080 0x1F4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27
>> 0x080 0x1F4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080
>> 0x1F4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
>> 0x084 0x1F8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03
>> 0x084 0x1F8 0x354 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18
>> 0x084 0x1F8 0x4BC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK
>> 0x084 0x1F8 0x46C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B
>> 0x084 0x1F8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28
>> 0x084 0x1F8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2
>> 0x084 0x1F8 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00
>> 0x084 0x1F8 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
>> 0x088 0x1FC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03
>> 0x088 0x1FC 0x364 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19
>> 0x088 0x1FC 0x4C0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088
>> 0x1FC 0x470 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB
>> 0x088 0x1FC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29
>> 0x088 0x1FC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2
>> 0x088 0x1FC 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01
>> 0x088 0x1FC 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
>> 0x08C 0x200 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02
>> 0x08C 0x200 0x350 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B
>> 0x08C 0x200 0x3E0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C
>> 0x200 0x478 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB
>> 0x08C 0x200 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30
>> 0x08C 0x200 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3
>> 0x08C 0x200 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02
>> 0x08C 0x200 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
>> 0x090 0x204 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02
>> 0x090 0x204 0x360 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B
>> 0x090 0x204 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090
>> 0x204 0x474 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B
>> 0x090 0x204 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31
>> 0x090 0x204 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK
>> 0x090 0x204 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03
>> 0x090 0x204 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
>> 0x094 0x208 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0
>> 0x094 0x208 0x410 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX
>> 0x094 0x208 0x3E8 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094
>> 0x208 0x000 0x3 0x4 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK
>> 0x094 0x208 0x3C0 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00
>> 0x094 0x208 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT
>> 0x094 0x208 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
>> 0x098 0x20C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1
>> 0x098 0x20C 0x414 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX
>> 0x098 0x20C 0x3E4 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098
>> 0x20C 0x47C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0
>> 0x098 0x20C 0x3BC 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01
>> 0x098 0x20C 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
>> 0x09C 0x210 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2
>> 0x09C 0x210 0x418 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX
>> 0x09C 0x210 0x400 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C
>> 0x210 0x480 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO
>> 0x09C 0x210 0x3C8 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02
>> 0x09C 0x210 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS
>> 0x09C 0x210 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
>> 0x0A0 0x214 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3
>> 0x0A0 0x214 0x41C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX
>> 0x0A0 0x214 0x3FC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP
>> 0x0A0 0x214 0x49C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI
>> 0x0A0 0x214 0x3C4 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03
>> 0x0A0 0x214 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL
>> 0x0A0 0x214 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
>> 0x0A4 0x218 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01
>> 0x0A4 0x218 0x34C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B
>> 0x0A4 0x218 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4
>> 0x218 0x300 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1
>> 0x0A4 0x218 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04
>> 0x0A4 0x218 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK
>> 0x0A4 0x218 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP
>> 0x0A4 0x218 0x494 0x7 0x4 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
>> 0x0A8 0x21C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01
>> 0x0A8 0x21C 0x35C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B
>> 0x0A8 0x21C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT
>> 0x0A8 0x21C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2
>> 0x0A8 0x21C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05
>> 0x0A8 0x21C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8
>> 0x21C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT
>> 0x0A8 0x21C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
>> 0x0AC 0x220 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00
>> 0x0AC 0x220 0x348 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX
>> 0x0AC 0x220 0x3F0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT
>> 0x0AC 0x220 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3
>> 0x0AC 0x220 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06
>> 0x0AC 0x220 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC
>> 0x220 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B
>> 0x0AC 0x220 0x490 0x7 0x3 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
>> 0x0B0 0x224 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00
>> 0x0B0 0x224 0x358 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX
>> 0x0B0 0x224 0x3EC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC
>> 0x0B0 0x224 0x48C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B
>> 0x0B0 0x224 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07
>> 0x0B0 0x224 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER
>> 0x0B0 0x224 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK
>> 0x0B0 0x224 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00
>> 0x0B4 0x228 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18
>> 0x0B4 0x228 0x4BC 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT
>> 0x0B4 0x228 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID
>> 0x0B4 0x228 0x2FC 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO
>> 0x0B4 0x228 0x308 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08
>> 0x0B4 0x228 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4
>> 0x228 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3
>> 0x0B4 0x228 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY
>> 0x0B8 0x22C 0x484 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19
>> 0x0B8 0x22C 0x4C0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN
>> 0x0B8 0x22C 0x488 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8
>> 0x22C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC
>> 0x0B8 0x22C 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09
>> 0x0B8 0x22C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8
>> 0x22C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2
>> 0x0B8 0x22C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS
>> 0x0BC 0x230 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC
>> 0x230 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1
>> 0x0BC 0x230 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK
>> 0x0C0 0x234 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0
>> 0x234 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2
>> 0x0C0 0x234 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD
>> 0x0C4 0x238 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4
>> 0x238 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1
>> 0x0C4 0x238 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI
>> 0x0C8 0x23C 0x000 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B
>> 0x0C8 0x23C 0x498 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B
>> 0x0C8 0x23C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK
>> 0x0C8 0x23C 0x430 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP
>> 0x0C8 0x23C 0x494 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8
>> 0x23C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
>> 0x0C8 0x23C 0x48C 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY
>> 0x0C8 0x23C 0x300 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO
>> 0x0CC 0x240 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX
>> 0x0CC 0x240 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP
>> 0x0CC 0x240 0x494 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0
>> 0x0CC 0x240 0x420 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO
>> 0x0CC 0x240 0x308 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC
>> 0x240 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR
>> 0x0CC 0x240 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B
>> 0x0CC 0x240 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0
>> 0x244 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX
>> 0x0D0 0x244 0x320 0x1 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B
>> 0x0D0 0x244 0x490 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1
>> 0x0D0 0x244 0x424 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC
>> 0x0D0 0x244 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0
>> 0x244 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID
>> 0x0D0 0x244 0x2FC 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI
>> 0x0D0 0x244 0x40C 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00
>> 0x0D4 0x248 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT
>> 0x0D4 0x248 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4
>> 0x248 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2
>> 0x0D4 0x248 0x428 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03
>> 0x0D4 0x248 0x354 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4
>> 0x248 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT
>> 0x0D4 0x248 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01
>> 0x0D8 0x24C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT
>> 0x0D8 0x24C 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8
>> 0x24C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3
>> 0x0D8 0x24C 0x42C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03
>> 0x0D8 0x24C 0x364 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8
>> 0x24C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT
>> 0x0D8 0x24C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK
>> 0x0DC 0x250 0x31C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC
>> 0x250 0x38C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B
>> 0x0DC 0x250 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00
>> 0x0DC 0x250 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1
>> 0x0DC 0x250 0x304 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC
>> 0x250 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV
>> 0x0DC 0x250 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01
>> 0x0E0 0x254 0x310 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0
>> 0x254 0x390 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B
>> 0x0E0 0x254 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00
>> 0x0E0 0x254 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0
>> 0x254 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV
>> 0x0E0 0x254 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00
>> 0x0E4 0x258 0x30C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4
>> 0x258 0x3A0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4
>> 0x258 0x3F0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01
>> 0x0E4 0x258 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02
>> 0x0E4 0x258 0x350 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4
>> 0x258 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK
>> 0x0E4 0x258 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8
>> 0x25C 0x314 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0
>> 0x0E8 0x25C 0x39C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8
>> 0x25C 0x3EC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01
>> 0x0E8 0x25C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02
>> 0x0E8 0x25C 0x360 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8
>> 0x25C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO
>> 0x0E8 0x25C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC
>> 0x260 0x318 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC
>> 0x260 0x3A8 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B
>> 0x0EC 0x260 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02
>> 0x0EC 0x260 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01
>> 0x0EC 0x260 0x34C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC
>> 0x260 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00
>> 0x0EC 0x260 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL
>> 0x0EC 0x260 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0
>> 0x264 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0
>> 0x264 0x3A4 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B
>> 0x0F0 0x264 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02
>> 0x0F0 0x264 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01
>> 0x0F0 0x264 0x35C 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0
>> 0x264 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01
>> 0x0F0 0x264 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B
>> 0x0F0 0x264 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00
>> 0x0F4 0x268 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
>> 0x0F4 0x268 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4
>> 0x268 0x3DC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03
>> 0x0F4 0x268 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00
>> 0x0F4 0x268 0x348 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4
>> 0x268 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02
>> 0x0F4 0x268 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY
>> 0x0F4 0x268 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01
>> 0x0F8 0x26C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
>> 0x0F8 0x26C 0x324 0x1 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8
>> 0x26C 0x3D8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03
>> 0x0F8 0x26C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00
>> 0x0F8 0x26C 0x358 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8
>> 0x26C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03
>> 0x0F8 0x26C 0x000 0x6 0x2 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC
>> 0x270 0x484 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03
>> 0x0FC 0x270 0x374 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX
>> 0x0FC 0x270 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK
>> 0x0FC 0x270 0x430 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15
>> 0x0FC 0x270 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC
>> 0x270 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT
>> 0x0FC 0x270 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04
>> 0x0FC 0x270 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100
>> 0x274 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK
>> 0x100 0x274 0x378 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX
>> 0x100 0x274 0x324 0x2 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK
>> 0x100 0x274 0x44C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14
>> 0x100 0x274 0x000 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100
>> 0x274 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN
>> 0x100 0x274 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04
>> 0x100 0x274 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104
>> 0x278 0x000 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00
>> 0x104 0x278 0x368 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104
>> 0x278 0x3C0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC
>> 0x104 0x278 0x450 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13
>> 0x104 0x278 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104
>> 0x278 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT
>> 0x104 0x278 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05
>> 0x104 0x278 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108
>> 0x27C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02
>> 0x108 0x27C 0x370 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0
>> 0x108 0x27C 0x3BC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00
>> 0x108 0x27C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12
>> 0x108 0x27C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108
>> 0x27C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN
>> 0x108 0x27C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05
>> 0x108 0x27C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C
>> 0x280 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01
>> 0x10C 0x280 0x36C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C
>> 0x280 0x3C8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC
>> 0x10C 0x280 0x448 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11
>> 0x10C 0x280 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C
>> 0x280 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1
>> 0x10C 0x280 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06
>> 0x10C 0x280 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP
>> 0x110 0x284 0x494 0x0 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B
>> 0x110 0x284 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110
>> 0x284 0x3C4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00
>> 0x110 0x284 0x438 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10
>> 0x110 0x284 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110
>> 0x284 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2
>> 0x110 0x284 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06
>> 0x110 0x284 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B
>> 0x114 0x288 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00
>> 0x114 0x288 0x328 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B
>> 0x114 0x288 0x3CC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK
>> 0x114 0x288 0x434 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09
>> 0x114 0x288 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114
>> 0x288 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3
>> 0x114 0x288 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07
>> 0x114 0x288 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT
>> 0x118 0x28C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00
>> 0x118 0x28C 0x338 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B
>> 0x118 0x28C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01
>> 0x118 0x28C 0x444 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08
>> 0x118 0x28C 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118
>> 0x28C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3
>> 0x118 0x28C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07
>> 0x118 0x28C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C
>> 0x290 0x384 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01
>> 0x11C 0x290 0x32C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C
>> 0x290 0x3D4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02
>> 0x11C 0x290 0x440 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07
>> 0x11C 0x290 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C
>> 0x290 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2
>> 0x11C 0x290 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12
>> 0x11C 0x290 0x4B4 0x7 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120
>> 0x294 0x388 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01
>> 0x120 0x294 0x33C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120
>> 0x294 0x3D0 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03
>> 0x120 0x294 0x43C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26
>> 0x120 0x294 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120
>> 0x294 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1
>> 0x120 0x294 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13
>> 0x120 0x294 0x4B8 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR
>> 0x124 0x298 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02
>> 0x124 0x298 0x330 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124
>> 0x298 0x3E8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B
>> 0x124 0x298 0x490 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05
>> 0x124 0x298 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124
>> 0x298 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1
>> 0x124 0x298 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID
>> 0x128 0x29C 0x2FC 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02
>> 0x128 0x29C 0x340 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128
>> 0x29C 0x3E4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP
>> 0x128 0x29C 0x494 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04
>> 0x128 0x29C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128
>> 0x29C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1
>> 0x128 0x29C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC
>> 0x12C 0x2A0 0x48C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
>> 0x12C 0x2A0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C
>> 0x2A0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B
>> 0x12C 0x2A0 0x498 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03
>> 0x12C 0x2A0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C
>> 0x2A0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03
>> 0x12C 0x2A0 0x334 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ
>> 0x130 0x2A4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
>> 0x130 0x2A4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0
>> 0x130 0x2A4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP
>> 0x130 0x2A4 0x49C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02
>> 0x130 0x2A4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130
>> 0x2A4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03
>> 0x130 0x2A4 0x344 0x6 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134
>> 0x2A8 0x37C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
>> 0x134 0x2A8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134
>> 0x2A8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT
>> 0x134 0x2A8 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01
>> 0x134 0x2A8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134
>> 0x2A8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138
>> 0x2AC 0x380 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
>> 0x138 0x2AC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138
>> 0x2AC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN
>> 0x138 0x2AC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00
>> 0x138 0x2AC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138
>> 0x2AC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
>> 0x13C 0x2B0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0
>> 0x13C 0x2B0 0x410 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK
>> 0x13C 0x2B0 0x430 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK
>> 0x13C 0x2B0 0x454 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C
>> 0x2B0 0x38C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C
>> 0x2B0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
>> 0x13C 0x2B0 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14
>> 0x13C 0x2B0 0x4A0 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
>> 0x140 0x2B4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1
>> 0x140 0x2B4 0x414 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT
>> 0x140 0x2B4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC
>> 0x140 0x2B4 0x460 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140
>> 0x2B4 0x390 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140
>> 0x2B4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
>> 0x140 0x2B4 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15
>> 0x140 0x2B4 0x4A4 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144
>> 0x2B8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2
>> 0x144 0x2B8 0x418 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B
>> 0x144 0x2B8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK
>> 0x144 0x2B8 0x458 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144
>> 0x2B8 0x3A0 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144
>> 0x2B8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO
>> 0x144 0x2B8 0x308 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16
>> 0x144 0x2B8 0x4A8 0x7 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148
>> 0x2BC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3
>> 0x148 0x2BC 0x41C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B
>> 0x148 0x2BC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA
>> 0x148 0x2BC 0x45C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0
>> 0x148 0x2BC 0x39C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148
>> 0x2BC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC
>> 0x148 0x2BC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
>> 0x14C 0x2C0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX
>> 0x14C 0x2C0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C
>> 0x2C0 0x400 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA
>> 0x14C 0x2C0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C
>> 0x2C0 0x3A8 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C
>> 0x2C0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
>> 0x14C 0x2C0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
>> 0x150 0x2C4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX
>> 0x150 0x2C4 0x324 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150
>> 0x2C4 0x3FC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK
>> 0x150 0x2C4 0x464 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150
>> 0x2C4 0x3A4 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150
>> 0x2C4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
>> 0x150 0x2C4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
>> 0x154 0x2C8 0x490 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B
>> 0x154 0x2C8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT
>> 0x154 0x2C8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC
>> 0x154 0x2C8 0x468 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B
>> 0x154 0x2C8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154
>> 0x2C8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17
>> 0x154 0x2C8 0x4AC 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2
>> 0x158 0x2CC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03
>> 0x158 0x2CC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158
>> 0x2CC 0x3F8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10
>> 0x158 0x2CC 0x4B0 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX
>> 0x158 0x2CC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158
>> 0x2CC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3
>> 0x15C 0x2D0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK
>> 0x15C 0x2D0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C
>> 0x2D0 0x3F4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B
>> 0x15C 0x2D0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX
>> 0x15C 0x2D0 0x320 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C
>> 0x2D0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160
>> 0x2D4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00
>> 0x160 0x2D4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160
>> 0x2D4 0x408 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160
>> 0x2D4 0x394 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT
>> 0x160 0x2D4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160
>> 0x2D4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1
>> 0x160 0x2D4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164
>> 0x2D8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02
>> 0x164 0x2D8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164
>> 0x2D8 0x404 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164
>> 0x2D8 0x398 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN
>> 0x164 0x2D8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164
>> 0x2D8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2
>> 0x164 0x2D8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0
>> 0x168 0x2DC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01
>> 0x168 0x2DC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK
>> 0x168 0x2DC 0x31C 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1
>> 0x168 0x2DC 0x304 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B
>> 0x168 0x2DC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168
>> 0x2DC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT
>> 0x168 0x2DC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1
>> 0x16C 0x2E0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
>> 0x16C 0x2E0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01
>> 0x16C 0x2E0 0x310 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK
>> 0x16C 0x2E0 0x46C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B
>> 0x16C 0x2E0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C
>> 0x2E0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY
>> 0x16C 0x2E0 0x300 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B
>> 0x170 0x2E4 0x498 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03
>> 0x170 0x2E4 0x374 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00
>> 0x170 0x2E4 0x30C 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK
>> 0x170 0x2E4 0x47C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
>> 0x170 0x2E4 0x3AC 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170
>> 0x2E4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP
>> 0x170 0x2E4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B
>> 0x174 0x2E8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
>> 0x174 0x2E8 0x378 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174
>> 0x2E8 0x314 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC
>> 0x174 0x2E8 0x480 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174
>> 0x2E8 0x3B0 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174
>> 0x2E8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
>> 0x178 0x2EC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00
>> 0x178 0x2EC 0x368 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178
>> 0x2EC 0x318 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA
>> 0x178 0x2EC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178
>> 0x2EC 0x3B8 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178
>> 0x2EC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
>> 0x17C 0x2F0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02
>> 0x17C 0x2F0 0x370 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C
>> 0x2F0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK
>> 0x17C 0x2F0 0x470 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C
>> 0x2F0 0x3B4 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C
>> 0x2F0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
>> 0x180 0x2F4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01
>> 0x180 0x2F4 0x36C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00
>> 0x180 0x2F4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC
>> 0x180 0x2F4 0x478 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
>> 0x180 0x2F4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180
>> 0x2F4 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
>> 0x184 0x2F8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B
>> 0x184 0x2F8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01
>> 0x184 0x2F8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA
>> 0x184 0x2F8 0x474 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
>> 0x184 0x2F8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184
>> 0x2F8 0x000 0x5 0x0 + +#endif /*
>> _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/5] Add support for i.MXRT1020-EVK board
2020-02-18 19:02 ` [PATCH 5/5] Add support for i.MXRT1020-EVK board Giulio Benetti
@ 2020-02-20 23:00 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: Lukasz Majewski @ 2020-02-20 23:00 UTC (permalink / raw)
To: u-boot
On Tue, 18 Feb 2020 20:02:55 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 44 ++++
> arch/arm/dts/imxrt1020-evk.dts | 198
> ++++++++++++++++++ arch/arm/mach-imx/imxrt/Kconfig |
> 5 + board/freescale/imxrt1020-evk/Kconfig | 22 ++
> board/freescale/imxrt1020-evk/MAINTAINERS | 6 +
> board/freescale/imxrt1020-evk/Makefile | 6 +
> board/freescale/imxrt1020-evk/README | 31 +++
> board/freescale/imxrt1020-evk/imximage.cfg | 36 ++++
> board/freescale/imxrt1020-evk/imxrt1020-evk.c | 81 +++++++
> configs/imxrt1020-evk_defconfig | 67 ++++++
> include/configs/imxrt1020-evk.h | 46 ++++
> 12 files changed, 544 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imxrt1020-evk.dts
> create mode 100644 board/freescale/imxrt1020-evk/Kconfig
> create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS
> create mode 100644 board/freescale/imxrt1020-evk/Makefile
> create mode 100644 board/freescale/imxrt1020-evk/README
> create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg
> create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c
> create mode 100644 configs/imxrt1020-evk_defconfig
> create mode 100644 include/configs/imxrt1020-evk.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index be4cf029d0..1116c44cf4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -723,7 +723,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mq-evk.dtb \
> imx8mp-evk.dtb
>
> -dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
> +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
> + imxrt1020-evk.dtb
>
> dtb-$(CONFIG_RCAR_GEN2) += \
> r8a7790-lager-u-boot.dtb \
> diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi new file mode 100644
> index 0000000000..d32c98de9c
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +/ {
> + chosen {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + u-boot,dm-spl;
> +};
> +
> +&semc {
> + bank1: bank at 0 {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&iomuxc {
> + u-boot,dm-spl;
> +
> + imxrt1020-evk {
> + u-boot,dm-spl;
> + pinctrl_lpuart1: lpuart1grp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_semc: semcgrp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_usdhc0: usdhc0grp {
> + u-boot,dm-spl;
> + };
> + };
> +};
> +
> +&usdhc1 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imxrt1020-evk.dts
> b/arch/arm/dts/imxrt1020-evk.dts new file mode 100644
> index 0000000000..ece13601bd
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020-evk.dts
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +/dts-v1/;
> +#include "imxrt1020.dtsi"
> +#include "imxrt1020-evk-u-boot.dtsi"
> +#include <dt-bindings/pinctrl/pins-imxrt1020.h>
> +
> +/ {
> + model = "NXP IMXRT1020-evk board";
> + compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
> +
> + chosen {
> + bootargs = "root=/dev/ram";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + reg = <0x80000000 0x2000000>;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart1>;
> + status = "okay";
> +};
> +
> +&semc {
> + /*
> + * Memory configuration from sdram datasheet IS42S16160J-6TLI
> + */
> + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> + MUX_CSX0_SDRAM_CS1
> + 0
> + 0
> + 0
> + 0>;
> + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> + BL_8
> + COL_9BITS
> + CL_3>;
> + fsl,sdram-timing = /bits/ 8 <0x2
> + 0x2
> + 0x9
> + 0x1
> + 0x5
> + 0x6
> +
> + 0x20
> + 0x09
> + 0x01
> + 0x00
> +
> + 0x04
> + 0x0A
> + 0x21
> + 0x50>;
> +
> + bank1: bank at 0 {
> + fsl,base-address = <0x80000000>;
> + fsl,memory-size = <MEM_SIZE_32M>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart1>;
> +
> + imxrt1020-evk {
> + pinctrl_lpuart1: lpuart1grp {
> + fsl,pins = <
> +
> MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
> + 0xf1
> +
> MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
> + 0xf1
> + >;
> + };
> +
> + pinctrl_semc: semcgrp {
> + fsl,pins = <
> + MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
> + 0xf1 /* SEMC_D0 */
> + MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
> + 0xf1 /* SEMC_D1 */
> + MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
> + 0xf1 /* SEMC_D2 */
> + MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
> + 0xf1 /* SEMC_D3 */
> + MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
> + 0xf1 /* SEMC_D4 */
> + MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
> + 0xf1 /* SEMC_D5 */
> + MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
> + 0xf1 /* SEMC_D6 */
> + MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
> + 0xf1 /* SEMC_D7 */
> + MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
> + 0xf1 /* SEMC_DM0 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> + 0xf1 /* SEMC_A0 */
> + MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
> + 0xf1 /* SEMC_CAS */
> + MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
> + 0xf1 /* SEMC_RAS */
> + MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
> + 0xf1 /* SEMC_CS0 */
> + MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
> + 0xf1 /* SEMC_BA0 */
> + MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
> + 0xf1 /* SEMC_BA1 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
> + 0xf1 /* SEMC_A10 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
> + 0xf1 /* SEMC_A0 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
> + 0xf1 /* SEMC_A1 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
> + 0xf1 /* SEMC_A2 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
> + 0xf1 /* SEMC_A3 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
> + 0xf1 /* SEMC_A4 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
> + 0xf1 /* SEMC_A5 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
> + 0xf1 /* SEMC_A6 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
> + 0xf1 /* SEMC_A7 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
> + 0xf1 /* SEMC_A8 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
> + 0xf1 /* SEMC_A9 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
> + 0xf1 /* SEMC_A11 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
> + 0xf1 /* SEMC_A12 */
> + MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
> + (IMX_PAD_SION | 0xf1)
> /* SEMC_DQS */
> + MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
> + 0xf1 /* SEMC_CKE */
> + MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
> + 0xf1 /* SEMC_CLK */
> + MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
> + 0xf1 /* SEMC_DM01 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
> + 0xf1 /* SEMC_D8 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
> + 0xf1 /* SEMC_D9 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
> + 0xf1 /* SEMC_D10 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
> + 0xf1 /* SEMC_D11 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
> + 0xf1 /* SEMC_D12 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
> + 0xf1 /* SEMC_D13 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
> + 0xf1 /* SEMC_D14 */
> +
> MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
> + 0xf1 /* SEMC_D15 */
> + >;
> + };
> +
> + pinctrl_usdhc0: usdhc0grp {
> + fsl,pins = <
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
> + 0x1B000
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
> + 0x17061
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
> + 0x17061
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
> + 0x17061
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
> + 0x17061
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
> + 0x17061
> +
> MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
> + 0x17061
> + >;
> + };
> + };
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz",
> "sleep";
> + pinctrl-0 = <&pinctrl_usdhc0>;
> + pinctrl-1 = <&pinctrl_usdhc0>;
> + pinctrl-2 = <&pinctrl_usdhc0>;
> + pinctrl-3 = <&pinctrl_usdhc0>;
> + status = "okay";
> +
> + cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> +};
> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
> b/arch/arm/mach-imx/imxrt/Kconfig index f28d52d3b7..d275fdf72e 100644
> --- a/arch/arm/mach-imx/imxrt/Kconfig
> +++ b/arch/arm/mach-imx/imxrt/Kconfig
> @@ -18,12 +18,17 @@ choice
> prompt "NXP i.MXRT board select"
> optional
>
> +config TARGET_IMXRT1020_EVK
> + bool "Support imxrt1020 EVK board"
> + select IMXRT1020
> +
> config TARGET_IMXRT1050_EVK
> bool "Support imxrt1050 EVK board"
> select IMXRT1050
>
> endchoice
>
> +source "board/freescale/imxrt1020-evk/Kconfig"
> source "board/freescale/imxrt1050-evk/Kconfig"
>
> endif
> diff --git a/board/freescale/imxrt1020-evk/Kconfig
> b/board/freescale/imxrt1020-evk/Kconfig new file mode 100644
> index 0000000000..d00cbff094
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/Kconfig
> @@ -0,0 +1,22 @@
> +if TARGET_IMXRT1020_EVK
> +
> +config SYS_BOARD
> + string
> + default "imxrt1020-evk"
> +
> +config SYS_VENDOR
> + string
> + default "freescale"
> +
> +config SYS_SOC
> + string
> + default "imxrt1020"
> +
> +config SYS_CONFIG_NAME
> + string
> + default "imxrt1020-evk"
> +
> +config IMX_CONFIG
> + default "board/freescale/imxrt1020-evk/imximage.cfg"
> +
> +endif
> diff --git a/board/freescale/imxrt1020-evk/MAINTAINERS
> b/board/freescale/imxrt1020-evk/MAINTAINERS new file mode 100644
> index 0000000000..05f017b2ba
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +IMXRT1020 EVALUATION KIT
> +M: Giulio Benetti <giulio.benetti@benettiengineering.com>
> +S: Maintained
> +F: board/freescale/imxrt1020-evk
> +F: include/configs/imxrt1020-evk.h
> +F: configs/imxrt1020-evk_defconfig
> diff --git a/board/freescale/imxrt1020-evk/Makefile
> b/board/freescale/imxrt1020-evk/Makefile new file mode 100644
> index 0000000000..807dc7c35e
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2020
> +# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> +
> +obj-y := imxrt1020-evk.o
> diff --git a/board/freescale/imxrt1020-evk/README
> b/board/freescale/imxrt1020-evk/README new file mode 100644
> index 0000000000..3da72fdad2
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/README
> @@ -0,0 +1,31 @@
> +How to use U-Boot on NXP i.MXRT1020 EVK
> +-----------------------------------------------
> +
> +- Build U-Boot for i.MXRT1020 EVK:
> +
> +$ make mrproper
> +$ make imxrt1020-evk_defconfig
> +$ make
> +
> +This will generate the SPL image called SPL and the u-boot.img.
> +
> +- Flash the SPL image into the micro SD card:
> +
> +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
> +
> +- Flash the u-boot.img image into the micro SD card:
> +
> +sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
> +
> +- Jumper settings:
> +
> +SW8: 0 1 1 0
> +
> +where 0 means bottom position and 1 means top position (from the
> +switch label numbers reference).
> +
> +- Connect the USB cable between the EVK and the PC for the console.
> +(The USB console connector is the one close the ethernet connector)
> +
> +- Insert the micro SD card in the board, power it up and U-Boot
> messages should +come up.
> diff --git a/board/freescale/imxrt1020-evk/imximage.cfg
> b/board/freescale/imxrt1020-evk/imximage.cfg new file mode 100644
> index 0000000000..9bcc2c1590
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/imximage.cfg
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi/sd/nand/onenand, qspi/nor
> + */
> +
> +BOOT_FROM sd
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +/* Set all FlexRAM as OCRAM(01b) */
> +DATA 4 0x400AC044 0x00005555
> +/* Use FLEXRAM_BANK_CFG to config FlexRAM */
> +SET_BIT 4 0x400AC040 0x4
> diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c
> b/board/freescale/imxrt1020-evk/imxrt1020-evk.c new file mode 100644
> index 0000000000..06ad524d5d
> --- /dev/null
> +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/armv7m.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +#ifndef CONFIG_SUPPORT_SPL
> + int rv;
> + struct udevice *dev;
> +
> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (rv) {
> + debug("DRAM init failed: %d\n", rv);
> + return rv;
> + }
> +
> +#endif
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + return fdtdec_setup_memory_banksize();
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +#ifdef CONFIG_SPL_OS_BOOT
> +int spl_start_uboot(void)
> +{
> + debug("SPL: booting kernel\n");
> + /* break into full u-boot on 'c' */
> + return serial_tstc() && serial_getc() == 'c';
> +}
> +#endif
> +
> +int spl_dram_init(void)
> +{
> + struct udevice *dev;
> + int rv;
> +
> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (rv)
> + debug("DRAM init failed: %d\n", rv);
> + return rv;
> +}
> +
> +void spl_board_init(void)
> +{
> + spl_dram_init();
> + preloader_console_init();
> + arch_cpu_init(); /* to configure mpu for sdram rw
> permissions */ +}
> +
> +u32 spl_boot_device(void)
> +{
> + return BOOT_DEVICE_MMC1;
> +}
> +#endif
> +
> +u32 get_board_rev(void)
> +{
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
> +
> + return 0;
> +}
> diff --git a/configs/imxrt1020-evk_defconfig
> b/configs/imxrt1020-evk_defconfig new file mode 100644
> index 0000000000..2f35df1896
> --- /dev/null
> +++ b/configs/imxrt1020-evk_defconfig
> @@ -0,0 +1,67 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMXRT=y
> +CONFIG_SYS_TEXT_BASE=0x80002000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x8000
> +CONFIG_ENV_OFFSET=0x80000
> +CONFIG_DM_GPIO=y
> +CONFIG_TARGET_IMXRT1020_EVK=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL_SIZE_LIMIT=131072
> +CONFIG_SPL=y
> +CONFIG_SPL_TEXT_BASE=0x20209000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_SD_BOOT=y
> +# CONFIG_USE_BOOTCOMMAND is not set
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_BOARD_INIT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
> +# CONFIG_SPL_CRC32_SUPPORT is not set
> +# CONFIG_SPL_DM_GPIO is not set
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_BOOTM_PLAN9 is not set
> +# CONFIG_BOOTM_RTEMS is not set
> +# CONFIG_BOOTM_VXWORKS is not set
> +# CONFIG_CMD_MII is not set
> +# CONFIG_DOS_PARTITION is not set
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
> +CONFIG_ENV_IS_NOWHERE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_TFTP_BLOCKSIZE=512
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +# CONFIG_OF_TRANSLATE is not set
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMXRT1020=y
> +CONFIG_CLK_IMXRT1020=y
> +CONFIG_MXC_GPIO=y
> +# CONFIG_INPUT is not set
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMXRT=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_IMXRT_SDRAM=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_TIMER=y
> +CONFIG_SPL_TIMER=y
> +CONFIG_SHA1=y
> +CONFIG_SHA256=y
> +CONFIG_HEXDUMP=y
> diff --git a/include/configs/imxrt1020-evk.h
> b/include/configs/imxrt1020-evk.h new file mode 100644
> index 0000000000..8e54565f1a
> --- /dev/null
> +++ b/include/configs/imxrt1020-evk.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __IMXRT1020_EVK_H
> +#define __IMXRT1020_EVK_H
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
> +
> +#ifdef CONFIG_SUPPORT_SPL
> +#define CONFIG_SYS_LOAD_ADDR 0x20209000
> +#else
> +#define CONFIG_SYS_LOAD_ADDR 0x80000000
> +#define CONFIG_LOADADDR 0x80000000
> +#endif
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
> +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
> +
> +#define PHYS_SDRAM 0x80000000
> +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
> +
> +#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
> +#define DMAMEM_BASE (PHYS_SDRAM +
> PHYS_SDRAM_SIZE - \
> + DMAMEM_SZ_ALL)
> +
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
> +
> +/*
> + * Configuration of the external SDRAM memory
> + */
> +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
> +
> +/* For SPL */
> +#ifdef CONFIG_SUPPORT_SPL
> +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> +#define CONFIG_SYS_SPL_LEN 0x00008000
> +#define CONFIG_SYS_UBOOT_START 0x800023FD
> +#endif
> +/* For SPL ends */
> +
> +#endif /* __IMXRT1020_EVK_H */
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition
2020-02-20 22:51 ` Lukasz Majewski
2020-02-20 22:55 ` Giulio Benetti
@ 2020-02-25 13:59 ` Giulio Benetti
1 sibling, 0 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-02-25 13:59 UTC (permalink / raw)
To: u-boot
On 2/20/20 11:51 PM, Lukasz Majewski wrote:
> On Tue, 18 Feb 2020 20:02:54 +0100
> Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
>
>> Add i.MXRT1020 pins definition.
>
> Are those definitions ported from Linux kernel?
>
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> include/dt-bindings/pinctrl/pins-imxrt1020.h | 763
>> +++++++++++++++++++ 1 file changed, 763 insertions(+)
>> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
>>
>> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
>> b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644
>> index 0000000000..c6bacb7378
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
>> @@ -0,0 +1,763 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2020
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
>> +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
>> +
>> +/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
This line ^^^^^^ must be removed, it's only a comment to remind me, is
it possible to remove it when applying? Or do I need to send a v2?
Best regards
--
Giulio Benetti
Benetti Engineering sas
>> +
>> +#define IMX_PAD_SION 0x40000000
>> +
>> +/*
>> + * The pin function ID is a tuple of
>> + * <mux_reg conf_reg input_reg mux_mode input_val>
>> + */
>> +
>> +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
>> 0x014 0x188 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0
>> 0x014 0x188 0x420 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B
>> 0x014 0x188 0x3E0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014
>> 0x188 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
>> 0x014 0x188 0x3B0 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00
>> 0x014 0x188 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX
>> 0x014 0x188 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02
>> 0x014 0x188 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
>> 0x018 0x18C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1
>> 0x018 0x18C 0x424 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B
>> 0x018 0x18C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT
>> 0x018 0x18C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
>> 0x018 0x18C 0x3AC 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01
>> 0x018 0x18C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX
>> 0x018 0x18C 0x320 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03
>> 0x018 0x18C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
>> 0x01C 0x190 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2
>> 0x01C 0x190 0x428 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX
>> 0x01C 0x190 0x3E8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK
>> 0x01C 0x190 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
>> 0x01C 0x190 0x3B8 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02
>> 0x01C 0x190 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL
>> 0x01C 0x190 0x37C 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
>> 0x020 0x194 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3
>> 0x020 0x194 0x42C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX
>> 0x020 0x194 0x3E4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK
>> 0x020 0x194 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
>> 0x020 0x194 0x3B4 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03
>> 0x020 0x194 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA
>> 0x020 0x194 0x380 0x6 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
>> 0x024 0x198 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04
>> 0x024 0x198 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT
>> 0x024 0x198 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024
>> 0x198 0x464 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16
>> 0x024 0x198 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04
>> 0x024 0x198 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
>> 0x028 0x19C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05
>> 0x028 0x19C 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN
>> 0x028 0x19C 0x488 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028
>> 0x19C 0x468 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17
>> 0x028 0x19C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05
>> 0x028 0x19C 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
>> 0x02C 0x1A0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06
>> 0x02C 0x1A0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX
>> 0x02C 0x1A0 0x3DC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C
>> 0x1A0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18
>> 0x02C 0x1A0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06
>> 0x02C 0x1A0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
>> 0x030 0x1A4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07
>> 0x030 0x1A4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX
>> 0x030 0x1A4 0x3D8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030
>> 0x1A4 0x460 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19
>> 0x030 0x1A4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07
>> 0x030 0x1A4 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
>> 0x034 0x1A8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08
>> 0x034 0x1A8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX
>> 0x034 0x1A8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034
>> 0x1A8 0x45C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20
>> 0x034 0x1A8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08
>> 0x034 0x1A8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>> 0x038 0x1AC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09
>> 0x038 0x1AC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX
>> 0x038 0x1AC 0x324 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038
>> 0x1AC 0x458 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21
>> 0x038 0x1AC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09
>> 0x038 0x1AC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
>> 0x03C 0x1B0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10
>> 0x03C 0x1B0 0x4B0 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA
>> 0x03C 0x1B0 0x398 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C
>> 0x1B0 0x450 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK
>> 0x03C 0x1B0 0x3B0 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10
>> 0x03C 0x1B0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00
>> 0x03C 0x1B0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
>> 0x040 0x1B4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11
>> 0x040 0x1B4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL
>> 0x040 0x1B4 0x394 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040
>> 0x1B4 0x44C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0
>> 0x040 0x1B4 0x3AC 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11
>> 0x040 0x1B4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01
>> 0x040 0x1B4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
>> 0x044 0x1B8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12
>> 0x044 0x1B8 0x4B4 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX
>> 0x044 0x1B8 0x3F8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00
>> 0x044 0x1B8 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO
>> 0x044 0x1B8 0x3B8 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12
>> 0x044 0x1B8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02
>> 0x044 0x1B8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
>> 0x048 0x1BC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13
>> 0x048 0x1BC 0x4B8 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX
>> 0x048 0x1BC 0x3F4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00
>> 0x048 0x1BC 0x438 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI
>> 0x048 0x1BC 0x3B4 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13
>> 0x048 0x1BC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03
>> 0x048 0x1BC 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048
>> 0x1BC 0x300 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
>> 0x04C 0x1C0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14
>> 0x04C 0x1C0 0x4A0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B
>> 0x04C 0x1C0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C
>> 0x1C0 0x434 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
>> 0x04C 0x1C0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14
>> 0x04C 0x1C0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX
>> 0x04C 0x1C0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
>> 0x050 0x1C4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15
>> 0x050 0x1C4 0x4A4 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B
>> 0x050 0x1C4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050
>> 0x1C4 0x448 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B
>> 0x050 0x1C4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15
>> 0x050 0x1C4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX
>> 0x050 0x1C4 0x320 0x6 0x3 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
>> 0x054 0x1C8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT
>> 0x054 0x1C8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK
>> 0x054 0x1C8 0x454 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16
>> 0x054 0x1C8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00
>> 0x054 0x1C8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
>> 0x058 0x1CC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT
>> 0x058 0x1CC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK
>> 0x058 0x1CC 0x46C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17
>> 0x058 0x1CC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01
>> 0x058 0x1CC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
>> 0x05C 0x1D0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16
>> 0x05C 0x1D0 0x4A8 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA
>> 0x05C 0x1D0 0x388 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C
>> 0x1D0 0x448 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22
>> 0x05C 0x1D0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18
>> 0x05C 0x1D0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C
>> 0x1D0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
>> 0x060 0x1D4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17
>> 0x060 0x1D4 0x4AC 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL
>> 0x060 0x1D4 0x384 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060
>> 0x1D4 0x434 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23
>> 0x060 0x1D4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19
>> 0x060 0x1D4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060
>> 0x1D4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
>> 0x064 0x1D8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03
>> 0x064 0x1D8 0x334 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B
>> 0x064 0x1D8 0x3CC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK
>> 0x064 0x1D8 0x430 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24
>> 0x064 0x1D8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20
>> 0x064 0x1D8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064
>> 0x1D8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
>> 0x068 0x1DC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03
>> 0x068 0x1DC 0x344 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B
>> 0x068 0x1DC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00
>> 0x068 0x1DC 0x438 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25
>> 0x068 0x1DC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21
>> 0x068 0x1DC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068
>> 0x1DC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
>> 0x06C 0x1E0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02
>> 0x06C 0x1E0 0x330 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX
>> 0x06C 0x1E0 0x3D4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03
>> 0x06C 0x1E0 0x43C 0x3 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26
>> 0x06C 0x1E0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22
>> 0x06C 0x1E0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C
>> 0x1E0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
>> 0x070 0x1E4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02
>> 0x070 0x1E4 0x340 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX
>> 0x070 0x1E4 0x3D0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02
>> 0x070 0x1E4 0x440 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27
>> 0x070 0x1E4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23
>> 0x070 0x1E4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070
>> 0x1E4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
>> 0x074 0x1E8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01
>> 0x074 0x1E8 0x32C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B
>> 0x074 0x1E8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01
>> 0x074 0x1E8 0x444 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28
>> 0x074 0x1E8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24
>> 0x074 0x1E8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074
>> 0x1E8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
>> 0x078 0x1EC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01
>> 0x078 0x1EC 0x33C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B
>> 0x078 0x1EC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00
>> 0x078 0x1EC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29
>> 0x078 0x1EC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25
>> 0x078 0x1EC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078
>> 0x1EC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
>> 0x07C 0x1F0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00
>> 0x07C 0x1F0 0x328 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX
>> 0x07C 0x1F0 0x408 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C
>> 0x1F0 0x44C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30
>> 0x07C 0x1F0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26
>> 0x07C 0x1F0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C
>> 0x1F0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
>> 0x080 0x1F4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00
>> 0x080 0x1F4 0x338 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX
>> 0x080 0x1F4 0x404 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080
>> 0x1F4 0x450 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31
>> 0x080 0x1F4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27
>> 0x080 0x1F4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080
>> 0x1F4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
>> 0x084 0x1F8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03
>> 0x084 0x1F8 0x354 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18
>> 0x084 0x1F8 0x4BC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK
>> 0x084 0x1F8 0x46C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B
>> 0x084 0x1F8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28
>> 0x084 0x1F8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2
>> 0x084 0x1F8 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00
>> 0x084 0x1F8 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
>> 0x088 0x1FC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03
>> 0x088 0x1FC 0x364 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19
>> 0x088 0x1FC 0x4C0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088
>> 0x1FC 0x470 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB
>> 0x088 0x1FC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29
>> 0x088 0x1FC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2
>> 0x088 0x1FC 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01
>> 0x088 0x1FC 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
>> 0x08C 0x200 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02
>> 0x08C 0x200 0x350 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B
>> 0x08C 0x200 0x3E0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C
>> 0x200 0x478 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB
>> 0x08C 0x200 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30
>> 0x08C 0x200 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3
>> 0x08C 0x200 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02
>> 0x08C 0x200 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
>> 0x090 0x204 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02
>> 0x090 0x204 0x360 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B
>> 0x090 0x204 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090
>> 0x204 0x474 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B
>> 0x090 0x204 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31
>> 0x090 0x204 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK
>> 0x090 0x204 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03
>> 0x090 0x204 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
>> 0x094 0x208 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0
>> 0x094 0x208 0x410 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX
>> 0x094 0x208 0x3E8 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094
>> 0x208 0x000 0x3 0x4 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK
>> 0x094 0x208 0x3C0 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00
>> 0x094 0x208 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT
>> 0x094 0x208 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
>> 0x098 0x20C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1
>> 0x098 0x20C 0x414 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX
>> 0x098 0x20C 0x3E4 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098
>> 0x20C 0x47C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0
>> 0x098 0x20C 0x3BC 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01
>> 0x098 0x20C 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
>> 0x09C 0x210 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2
>> 0x09C 0x210 0x418 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX
>> 0x09C 0x210 0x400 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C
>> 0x210 0x480 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO
>> 0x09C 0x210 0x3C8 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02
>> 0x09C 0x210 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS
>> 0x09C 0x210 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
>> 0x0A0 0x214 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3
>> 0x0A0 0x214 0x41C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX
>> 0x0A0 0x214 0x3FC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP
>> 0x0A0 0x214 0x49C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI
>> 0x0A0 0x214 0x3C4 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03
>> 0x0A0 0x214 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL
>> 0x0A0 0x214 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
>> 0x0A4 0x218 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01
>> 0x0A4 0x218 0x34C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B
>> 0x0A4 0x218 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4
>> 0x218 0x300 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1
>> 0x0A4 0x218 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04
>> 0x0A4 0x218 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK
>> 0x0A4 0x218 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP
>> 0x0A4 0x218 0x494 0x7 0x4 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
>> 0x0A8 0x21C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01
>> 0x0A8 0x21C 0x35C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B
>> 0x0A8 0x21C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT
>> 0x0A8 0x21C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2
>> 0x0A8 0x21C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05
>> 0x0A8 0x21C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8
>> 0x21C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT
>> 0x0A8 0x21C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
>> 0x0AC 0x220 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00
>> 0x0AC 0x220 0x348 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX
>> 0x0AC 0x220 0x3F0 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT
>> 0x0AC 0x220 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3
>> 0x0AC 0x220 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06
>> 0x0AC 0x220 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC
>> 0x220 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B
>> 0x0AC 0x220 0x490 0x7 0x3 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
>> 0x0B0 0x224 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00
>> 0x0B0 0x224 0x358 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX
>> 0x0B0 0x224 0x3EC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC
>> 0x0B0 0x224 0x48C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B
>> 0x0B0 0x224 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07
>> 0x0B0 0x224 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER
>> 0x0B0 0x224 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK
>> 0x0B0 0x224 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00
>> 0x0B4 0x228 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18
>> 0x0B4 0x228 0x4BC 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT
>> 0x0B4 0x228 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID
>> 0x0B4 0x228 0x2FC 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO
>> 0x0B4 0x228 0x308 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08
>> 0x0B4 0x228 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4
>> 0x228 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3
>> 0x0B4 0x228 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY
>> 0x0B8 0x22C 0x484 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19
>> 0x0B8 0x22C 0x4C0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN
>> 0x0B8 0x22C 0x488 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8
>> 0x22C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC
>> 0x0B8 0x22C 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09
>> 0x0B8 0x22C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8
>> 0x22C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2
>> 0x0B8 0x22C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS
>> 0x0BC 0x230 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC
>> 0x230 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1
>> 0x0BC 0x230 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK
>> 0x0C0 0x234 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0
>> 0x234 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2
>> 0x0C0 0x234 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD
>> 0x0C4 0x238 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4
>> 0x238 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1
>> 0x0C4 0x238 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI
>> 0x0C8 0x23C 0x000 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B
>> 0x0C8 0x23C 0x498 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B
>> 0x0C8 0x23C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK
>> 0x0C8 0x23C 0x430 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP
>> 0x0C8 0x23C 0x494 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8
>> 0x23C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
>> 0x0C8 0x23C 0x48C 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY
>> 0x0C8 0x23C 0x300 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO
>> 0x0CC 0x240 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX
>> 0x0CC 0x240 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP
>> 0x0CC 0x240 0x494 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0
>> 0x0CC 0x240 0x420 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO
>> 0x0CC 0x240 0x308 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC
>> 0x240 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR
>> 0x0CC 0x240 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B
>> 0x0CC 0x240 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0
>> 0x244 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX
>> 0x0D0 0x244 0x320 0x1 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B
>> 0x0D0 0x244 0x490 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1
>> 0x0D0 0x244 0x424 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC
>> 0x0D0 0x244 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0
>> 0x244 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID
>> 0x0D0 0x244 0x2FC 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI
>> 0x0D0 0x244 0x40C 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00
>> 0x0D4 0x248 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT
>> 0x0D4 0x248 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4
>> 0x248 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2
>> 0x0D4 0x248 0x428 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03
>> 0x0D4 0x248 0x354 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4
>> 0x248 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT
>> 0x0D4 0x248 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01
>> 0x0D8 0x24C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT
>> 0x0D8 0x24C 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8
>> 0x24C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3
>> 0x0D8 0x24C 0x42C 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03
>> 0x0D8 0x24C 0x364 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8
>> 0x24C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT
>> 0x0D8 0x24C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK
>> 0x0DC 0x250 0x31C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC
>> 0x250 0x38C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B
>> 0x0DC 0x250 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00
>> 0x0DC 0x250 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1
>> 0x0DC 0x250 0x304 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC
>> 0x250 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV
>> 0x0DC 0x250 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01
>> 0x0E0 0x254 0x310 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0
>> 0x254 0x390 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B
>> 0x0E0 0x254 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00
>> 0x0E0 0x254 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0
>> 0x254 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV
>> 0x0E0 0x254 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00
>> 0x0E4 0x258 0x30C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4
>> 0x258 0x3A0 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4
>> 0x258 0x3F0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01
>> 0x0E4 0x258 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02
>> 0x0E4 0x258 0x350 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4
>> 0x258 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK
>> 0x0E4 0x258 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8
>> 0x25C 0x314 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0
>> 0x0E8 0x25C 0x39C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8
>> 0x25C 0x3EC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01
>> 0x0E8 0x25C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02
>> 0x0E8 0x25C 0x360 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8
>> 0x25C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO
>> 0x0E8 0x25C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC
>> 0x260 0x318 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC
>> 0x260 0x3A8 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B
>> 0x0EC 0x260 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02
>> 0x0EC 0x260 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01
>> 0x0EC 0x260 0x34C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC
>> 0x260 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00
>> 0x0EC 0x260 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL
>> 0x0EC 0x260 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0
>> 0x264 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0
>> 0x264 0x3A4 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B
>> 0x0F0 0x264 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02
>> 0x0F0 0x264 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01
>> 0x0F0 0x264 0x35C 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0
>> 0x264 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01
>> 0x0F0 0x264 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B
>> 0x0F0 0x264 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00
>> 0x0F4 0x268 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
>> 0x0F4 0x268 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4
>> 0x268 0x3DC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03
>> 0x0F4 0x268 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00
>> 0x0F4 0x268 0x348 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4
>> 0x268 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02
>> 0x0F4 0x268 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY
>> 0x0F4 0x268 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01
>> 0x0F8 0x26C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
>> 0x0F8 0x26C 0x324 0x1 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8
>> 0x26C 0x3D8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03
>> 0x0F8 0x26C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00
>> 0x0F8 0x26C 0x358 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8
>> 0x26C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03
>> 0x0F8 0x26C 0x000 0x6 0x2 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC
>> 0x270 0x484 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03
>> 0x0FC 0x270 0x374 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX
>> 0x0FC 0x270 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK
>> 0x0FC 0x270 0x430 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15
>> 0x0FC 0x270 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC
>> 0x270 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT
>> 0x0FC 0x270 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04
>> 0x0FC 0x270 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100
>> 0x274 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK
>> 0x100 0x274 0x378 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX
>> 0x100 0x274 0x324 0x2 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK
>> 0x100 0x274 0x44C 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14
>> 0x100 0x274 0x000 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100
>> 0x274 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN
>> 0x100 0x274 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04
>> 0x100 0x274 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104
>> 0x278 0x000 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00
>> 0x104 0x278 0x368 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104
>> 0x278 0x3C0 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC
>> 0x104 0x278 0x450 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13
>> 0x104 0x278 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104
>> 0x278 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT
>> 0x104 0x278 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05
>> 0x104 0x278 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108
>> 0x27C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02
>> 0x108 0x27C 0x370 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0
>> 0x108 0x27C 0x3BC 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00
>> 0x108 0x27C 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12
>> 0x108 0x27C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108
>> 0x27C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN
>> 0x108 0x27C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05
>> 0x108 0x27C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C
>> 0x280 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01
>> 0x10C 0x280 0x36C 0x1 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C
>> 0x280 0x3C8 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC
>> 0x10C 0x280 0x448 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11
>> 0x10C 0x280 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C
>> 0x280 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1
>> 0x10C 0x280 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06
>> 0x10C 0x280 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP
>> 0x110 0x284 0x494 0x0 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B
>> 0x110 0x284 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110
>> 0x284 0x3C4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00
>> 0x110 0x284 0x438 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10
>> 0x110 0x284 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110
>> 0x284 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2
>> 0x110 0x284 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06
>> 0x110 0x284 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B
>> 0x114 0x288 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00
>> 0x114 0x288 0x328 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B
>> 0x114 0x288 0x3CC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK
>> 0x114 0x288 0x434 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09
>> 0x114 0x288 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114
>> 0x288 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3
>> 0x114 0x288 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07
>> 0x114 0x288 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT
>> 0x118 0x28C 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00
>> 0x118 0x28C 0x338 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B
>> 0x118 0x28C 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01
>> 0x118 0x28C 0x444 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08
>> 0x118 0x28C 0x000 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118
>> 0x28C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3
>> 0x118 0x28C 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07
>> 0x118 0x28C 0x000 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C
>> 0x290 0x384 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01
>> 0x11C 0x290 0x32C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C
>> 0x290 0x3D4 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02
>> 0x11C 0x290 0x440 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07
>> 0x11C 0x290 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C
>> 0x290 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2
>> 0x11C 0x290 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12
>> 0x11C 0x290 0x4B4 0x7 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120
>> 0x294 0x388 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01
>> 0x120 0x294 0x33C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120
>> 0x294 0x3D0 0x2 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03
>> 0x120 0x294 0x43C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26
>> 0x120 0x294 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120
>> 0x294 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1
>> 0x120 0x294 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13
>> 0x120 0x294 0x4B8 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR
>> 0x124 0x298 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02
>> 0x124 0x298 0x330 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124
>> 0x298 0x3E8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B
>> 0x124 0x298 0x490 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05
>> 0x124 0x298 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124
>> 0x298 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1
>> 0x124 0x298 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID
>> 0x128 0x29C 0x2FC 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02
>> 0x128 0x29C 0x340 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128
>> 0x29C 0x3E4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP
>> 0x128 0x29C 0x494 0x3 0x3 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04
>> 0x128 0x29C 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128
>> 0x29C 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1
>> 0x128 0x29C 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC
>> 0x12C 0x2A0 0x48C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
>> 0x12C 0x2A0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C
>> 0x2A0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B
>> 0x12C 0x2A0 0x498 0x3 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03
>> 0x12C 0x2A0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C
>> 0x2A0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03
>> 0x12C 0x2A0 0x334 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ
>> 0x130 0x2A4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
>> 0x130 0x2A4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0
>> 0x130 0x2A4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP
>> 0x130 0x2A4 0x49C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02
>> 0x130 0x2A4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130
>> 0x2A4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03
>> 0x130 0x2A4 0x344 0x6 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134
>> 0x2A8 0x37C 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
>> 0x134 0x2A8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134
>> 0x2A8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT
>> 0x134 0x2A8 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01
>> 0x134 0x2A8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134
>> 0x2A8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138
>> 0x2AC 0x380 0x0 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
>> 0x138 0x2AC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138
>> 0x2AC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN
>> 0x138 0x2AC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00
>> 0x138 0x2AC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138
>> 0x2AC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
>> 0x13C 0x2B0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0
>> 0x13C 0x2B0 0x410 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK
>> 0x13C 0x2B0 0x430 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK
>> 0x13C 0x2B0 0x454 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C
>> 0x2B0 0x38C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C
>> 0x2B0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
>> 0x13C 0x2B0 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14
>> 0x13C 0x2B0 0x4A0 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
>> 0x140 0x2B4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1
>> 0x140 0x2B4 0x414 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT
>> 0x140 0x2B4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC
>> 0x140 0x2B4 0x460 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140
>> 0x2B4 0x390 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140
>> 0x2B4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
>> 0x140 0x2B4 0x000 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15
>> 0x140 0x2B4 0x4A4 0x7 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144
>> 0x2B8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2
>> 0x144 0x2B8 0x418 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B
>> 0x144 0x2B8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK
>> 0x144 0x2B8 0x458 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144
>> 0x2B8 0x3A0 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144
>> 0x2B8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO
>> 0x144 0x2B8 0x308 0x6 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16
>> 0x144 0x2B8 0x4A8 0x7 0x1 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148
>> 0x2BC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3
>> 0x148 0x2BC 0x41C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B
>> 0x148 0x2BC 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA
>> 0x148 0x2BC 0x45C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0
>> 0x148 0x2BC 0x39C 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148
>> 0x2BC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC
>> 0x148 0x2BC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
>> 0x14C 0x2C0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX
>> 0x14C 0x2C0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C
>> 0x2C0 0x400 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA
>> 0x14C 0x2C0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C
>> 0x2C0 0x3A8 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C
>> 0x2C0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
>> 0x14C 0x2C0 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
>> 0x150 0x2C4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX
>> 0x150 0x2C4 0x324 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150
>> 0x2C4 0x3FC 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK
>> 0x150 0x2C4 0x464 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150
>> 0x2C4 0x3A4 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150
>> 0x2C4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
>> 0x150 0x2C4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
>> 0x154 0x2C8 0x490 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B
>> 0x154 0x2C8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT
>> 0x154 0x2C8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC
>> 0x154 0x2C8 0x468 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B
>> 0x154 0x2C8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154
>> 0x2C8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17
>> 0x154 0x2C8 0x4AC 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2
>> 0x158 0x2CC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03
>> 0x158 0x2CC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158
>> 0x2CC 0x3F8 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10
>> 0x158 0x2CC 0x4B0 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX
>> 0x158 0x2CC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158
>> 0x2CC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3
>> 0x15C 0x2D0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK
>> 0x15C 0x2D0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C
>> 0x2D0 0x3F4 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B
>> 0x15C 0x2D0 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX
>> 0x15C 0x2D0 0x320 0x4 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C
>> 0x2D0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160
>> 0x2D4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00
>> 0x160 0x2D4 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160
>> 0x2D4 0x408 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160
>> 0x2D4 0x394 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT
>> 0x160 0x2D4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160
>> 0x2D4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1
>> 0x160 0x2D4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164
>> 0x2D8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02
>> 0x164 0x2D8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164
>> 0x2D8 0x404 0x2 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164
>> 0x2D8 0x398 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN
>> 0x164 0x2D8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164
>> 0x2D8 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2
>> 0x164 0x2D8 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0
>> 0x168 0x2DC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01
>> 0x168 0x2DC 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK
>> 0x168 0x2DC 0x31C 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1
>> 0x168 0x2DC 0x304 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B
>> 0x168 0x2DC 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168
>> 0x2DC 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT
>> 0x168 0x2DC 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1
>> 0x16C 0x2E0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
>> 0x16C 0x2E0 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01
>> 0x16C 0x2E0 0x310 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK
>> 0x16C 0x2E0 0x46C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B
>> 0x16C 0x2E0 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C
>> 0x2E0 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY
>> 0x16C 0x2E0 0x300 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B
>> 0x170 0x2E4 0x498 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03
>> 0x170 0x2E4 0x374 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00
>> 0x170 0x2E4 0x30C 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK
>> 0x170 0x2E4 0x47C 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
>> 0x170 0x2E4 0x3AC 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170
>> 0x2E4 0x000 0x5 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP
>> 0x170 0x2E4 0x000 0x6 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B
>> 0x174 0x2E8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
>> 0x174 0x2E8 0x378 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174
>> 0x2E8 0x314 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC
>> 0x174 0x2E8 0x480 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174
>> 0x2E8 0x3B0 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174
>> 0x2E8 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
>> 0x178 0x2EC 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00
>> 0x178 0x2EC 0x368 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178
>> 0x2EC 0x318 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA
>> 0x178 0x2EC 0x000 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178
>> 0x2EC 0x3B8 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178
>> 0x2EC 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
>> 0x17C 0x2F0 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02
>> 0x17C 0x2F0 0x370 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C
>> 0x2F0 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK
>> 0x17C 0x2F0 0x470 0x3 0x1 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C
>> 0x2F0 0x3B4 0x4 0x2 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C
>> 0x2F0 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
>> 0x180 0x2F4 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01
>> 0x180 0x2F4 0x36C 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00
>> 0x180 0x2F4 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC
>> 0x180 0x2F4 0x478 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
>> 0x180 0x2F4 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180
>> 0x2F4 0x000 0x5 0x0 + +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
>> 0x184 0x2F8 0x000 0x0 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B
>> 0x184 0x2F8 0x000 0x1 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01
>> 0x184 0x2F8 0x000 0x2 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA
>> 0x184 0x2F8 0x474 0x3 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
>> 0x184 0x2F8 0x000 0x4 0x0 +#define
>> MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184
>> 0x2F8 0x000 0x5 0x0 + +#endif /*
>> _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/5] i.MXRT1020 add basic support
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
` (4 preceding siblings ...)
2020-02-18 19:02 ` [PATCH 5/5] Add support for i.MXRT1020-EVK board Giulio Benetti
@ 2020-04-18 12:32 ` Giulio Benetti
2020-04-18 12:57 ` Stefano Babic
5 siblings, 1 reply; 22+ messages in thread
From: Giulio Benetti @ 2020-04-18 12:32 UTC (permalink / raw)
To: u-boot
Hi Stefano,
I ping you for reviewing this patchset, Lukasz already reviewed his
patches, so it should be ready to be committed.
Thank you
--
Giulio Benetti
Benetti Engineering sas
On 2/18/20 8:02 PM, Giulio Benetti wrote:
> Add Soc i.MXRT1020 to i.MXRT family and its evk support.
> This Soc has many in common with i.MXRT1050 except clock init and pins
> listing.
>
> Giulio Benetti (5):
> clk: imx: add i.IMXRT1020 clk driver
> Add i.MXRT1020 support
> ARM: dts: imxrt1020: add dtsi file
> dt-bindings: pinctrl: add i.MXRT1020 pins definition
> Add support for i.MXRT1020-EVK board
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 44 +
> arch/arm/dts/imxrt1020-evk.dts | 198 +++++
> arch/arm/dts/imxrt1020.dtsi | 133 +++
> arch/arm/mach-imx/imxrt/Kconfig | 9 +
> board/freescale/imxrt1020-evk/Kconfig | 22 +
> board/freescale/imxrt1020-evk/MAINTAINERS | 6 +
> board/freescale/imxrt1020-evk/Makefile | 6 +
> board/freescale/imxrt1020-evk/README | 31 +
> board/freescale/imxrt1020-evk/imximage.cfg | 36 +
> board/freescale/imxrt1020-evk/imxrt1020-evk.c | 81 ++
> configs/imxrt1020-evk_defconfig | 67 ++
> drivers/clk/imx/Kconfig | 16 +
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-imxrt1020.c | 227 ++++++
> include/configs/imxrt1020-evk.h | 46 ++
> include/dt-bindings/clock/imxrt1020-clock.h | 52 ++
> include/dt-bindings/pinctrl/pins-imxrt1020.h | 763 ++++++++++++++++++
> 18 files changed, 1740 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imxrt1020-evk.dts
> create mode 100644 arch/arm/dts/imxrt1020.dtsi
> create mode 100644 board/freescale/imxrt1020-evk/Kconfig
> create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS
> create mode 100644 board/freescale/imxrt1020-evk/Makefile
> create mode 100644 board/freescale/imxrt1020-evk/README
> create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg
> create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c
> create mode 100644 configs/imxrt1020-evk_defconfig
> create mode 100644 drivers/clk/imx/clk-imxrt1020.c
> create mode 100644 include/configs/imxrt1020-evk.h
> create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/5] i.MXRT1020 add basic support
2020-04-18 12:32 ` [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
@ 2020-04-18 12:57 ` Stefano Babic
2020-04-18 15:38 ` Giulio Benetti
0 siblings, 1 reply; 22+ messages in thread
From: Stefano Babic @ 2020-04-18 12:57 UTC (permalink / raw)
To: u-boot
Hi Giulio,
On 18/04/20 14:32, Giulio Benetti wrote:
> Hi Stefano,
>
> I ping you for reviewing this patchset, Lukasz already reviewed his
> patches, so it should be ready to be committed.
>
Yes, I have already merge the big series after Anatolji's ACK, this
series was not yet in. I merged into -next and I restart my Travis' job.
Best regards,
Stefano
> Thank you
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/5] i.MXRT1020 add basic support
2020-04-18 12:57 ` Stefano Babic
@ 2020-04-18 15:38 ` Giulio Benetti
0 siblings, 0 replies; 22+ messages in thread
From: Giulio Benetti @ 2020-04-18 15:38 UTC (permalink / raw)
To: u-boot
On 4/18/20 2:57 PM, Stefano Babic wrote:
> Hi Giulio,
>
> On 18/04/20 14:32, Giulio Benetti wrote:
>> Hi Stefano,
>>
>> I ping you for reviewing this patchset, Lukasz already reviewed his
>> patches, so it should be ready to be committed.
>>
>
> Yes, I have already merge the big series after Anatolji's ACK, this
> series was not yet in. I merged into -next and I restart my Travis' job.
Ok, thank you very much
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/5] Add support for i.MXRT1020-EVK board
2020-02-18 19:02 ` [PATCH 5/5] Add support for i.MXRT1020-EVK board Giulio Benetti
2020-02-20 23:00 ` Lukasz Majewski
@ 2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: sbabic at denx.de @ 2020-04-19 9:08 UTC (permalink / raw)
To: u-boot
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file
2020-02-18 19:02 ` [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file Giulio Benetti
2020-02-20 22:45 ` Lukasz Majewski
@ 2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: sbabic at denx.de @ 2020-04-19 9:08 UTC (permalink / raw)
To: u-boot
> Add dtsi file for i.MXRT1020.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
2020-02-20 22:33 ` Lukasz Majewski
@ 2020-04-19 9:08 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: sbabic at denx.de @ 2020-04-19 9:08 UTC (permalink / raw)
To: u-boot
> Add i.MXRT1020 clk driver support.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 2/5] Add i.MXRT1020 support
2020-02-18 19:02 ` [PATCH 2/5] Add i.MXRT1020 support Giulio Benetti
2020-02-20 22:35 ` Lukasz Majewski
@ 2020-04-19 9:09 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: sbabic at denx.de @ 2020-04-19 9:09 UTC (permalink / raw)
To: u-boot
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition
2020-02-18 19:02 ` [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition Giulio Benetti
2020-02-20 22:51 ` Lukasz Majewski
@ 2020-04-19 9:09 ` sbabic at denx.de
1 sibling, 0 replies; 22+ messages in thread
From: sbabic at denx.de @ 2020-04-19 9:09 UTC (permalink / raw)
To: u-boot
> Add i.MXRT1020 pins definition.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-04-19 9:09 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-18 19:02 [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
2020-02-18 19:02 ` [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver Giulio Benetti
2020-02-20 22:33 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 2/5] Add i.MXRT1020 support Giulio Benetti
2020-02-20 22:35 ` Lukasz Majewski
2020-04-19 9:09 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file Giulio Benetti
2020-02-20 22:45 ` Lukasz Majewski
2020-02-20 22:50 ` Giulio Benetti
2020-04-19 9:08 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition Giulio Benetti
2020-02-20 22:51 ` Lukasz Majewski
2020-02-20 22:55 ` Giulio Benetti
2020-02-25 13:59 ` Giulio Benetti
2020-04-19 9:09 ` sbabic at denx.de
2020-02-18 19:02 ` [PATCH 5/5] Add support for i.MXRT1020-EVK board Giulio Benetti
2020-02-20 23:00 ` Lukasz Majewski
2020-04-19 9:08 ` sbabic at denx.de
2020-04-18 12:32 ` [PATCH 0/5] i.MXRT1020 add basic support Giulio Benetti
2020-04-18 12:57 ` Stefano Babic
2020-04-18 15:38 ` Giulio Benetti
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