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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions
Date: Thu, 25 Jul 2019 11:52:06 -0700	[thread overview]
Message-ID: <50c1c6a3ace8b40f7b9d5395a2c3457cf1852721.1564080680.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564080680.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_plic.c         | 12 ------------
 include/hw/riscv/sifive_plic.h |  3 ---
 2 files changed, 15 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 0950e89e15..864a1bed42 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -161,18 +161,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
     }
 }
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
-    sifive_plic_set_pending(plic, irq, true);
-    sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
-    sifive_plic_set_pending(plic, irq, false);
-    sifive_plic_update(plic);
-}
-
 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 {
     int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index ce8907f6aa..3b8a623919 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
     uint32_t aperture_size;
 } SiFivePLICState;
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t num_sources, uint32_t num_priorities,
     uint32_t priority_base, uint32_t pending_base,
-- 
2.22.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions
Date: Thu, 25 Jul 2019 11:52:06 -0700	[thread overview]
Message-ID: <50c1c6a3ace8b40f7b9d5395a2c3457cf1852721.1564080680.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564080680.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_plic.c         | 12 ------------
 include/hw/riscv/sifive_plic.h |  3 ---
 2 files changed, 15 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 0950e89e15..864a1bed42 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -161,18 +161,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
     }
 }
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
-    sifive_plic_set_pending(plic, irq, true);
-    sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
-    sifive_plic_set_pending(plic, irq, false);
-    sifive_plic_update(plic);
-}
-
 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 {
     int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index ce8907f6aa..3b8a623919 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
     uint32_t aperture_size;
 } SiFivePLICState;
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t num_sources, uint32_t num_priorities,
     uint32_t priority_base, uint32_t pending_base,
-- 
2.22.0



  parent reply	other threads:[~2019-07-25 18:55 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-25 18:51 [Qemu-devel] [PATCH-4.2 v1 0/6] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-25 18:51 ` [Qemu-riscv] " Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 1/6] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-25 18:52   ` [Qemu-riscv] " Alistair Francis
2019-07-29 14:33   ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-07-29 14:33     ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 2/6] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis
2019-07-25 18:52   ` [Qemu-riscv] " Alistair Francis
2019-07-25 21:47   ` [Qemu-devel] " Jonathan Behrens
2019-07-25 21:47     ` Jonathan Behrens
2019-07-26 20:24     ` [Qemu-devel] " Alistair Francis
2019-07-26 20:24       ` Alistair Francis
2019-07-26 21:00       ` [Qemu-devel] " Jonathan Behrens
2019-07-26 21:00         ` Jonathan Behrens
2019-07-26 22:28         ` [Qemu-devel] " Alistair Francis
2019-07-26 22:28           ` Alistair Francis
2019-07-25 18:52 ` Alistair Francis [this message]
2019-07-25 18:52   ` [Qemu-riscv] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-26 15:22   ` [Qemu-devel] " Jonathan Behrens
2019-07-26 15:22     ` Jonathan Behrens
2019-07-29 14:28   ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-07-29 14:28     ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-07-29 17:32   ` Chih-Min Chao
2019-07-29 17:32     ` [Qemu-riscv] " Chih-Min Chao
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-07-25 18:52   ` [Qemu-riscv] " Alistair Francis
2019-07-29 14:31   ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-07-29 14:31     ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-07-29 16:56   ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-07-29 16:56     ` Chih-Min Chao
2019-07-30 18:32     ` [Qemu-devel] " Alistair Francis
2019-07-30 18:32       ` Alistair Francis
2019-07-30  8:49   ` [Qemu-devel] " Christophe de Dinechin
2019-07-30  8:49     ` [Qemu-riscv] " Christophe de Dinechin
2019-07-30 18:33     ` Alistair Francis
2019-07-30 18:33       ` [Qemu-riscv] " Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 5/6] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-07-25 18:52   ` [Qemu-riscv] " Alistair Francis
2019-07-26 17:40   ` [Qemu-devel] " Chih-Min Chao
2019-07-26 17:40     ` [Qemu-riscv] " Chih-Min Chao
2019-07-26 20:20     ` Alistair Francis
2019-07-26 20:20       ` [Qemu-riscv] " Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names Alistair Francis
2019-07-25 18:52   ` [Qemu-riscv] " Alistair Francis
2019-07-29 15:19   ` [Qemu-devel] " Chih-Min Chao
2019-07-29 15:19     ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 18:37     ` Alistair Francis
2019-07-30 18:37       ` [Qemu-riscv] " Alistair Francis
2019-07-31  8:10       ` Chih-Min Chao
2019-07-31  8:10         ` [Qemu-riscv] " Chih-Min Chao
2019-08-05 17:49         ` Alistair Francis
2019-08-05 17:49           ` [Qemu-riscv] " Alistair Francis

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