[PATCH] clk: tegra: initialise parent of uart clocks

* [PATCH] clk: tegra: initialise parent of uart clocks
@ 2013-02-06 10:47 ` Laxman Dewangan
  0 siblings, 0 replies; 14+ messages in thread
From: Laxman Dewangan @ 2013-02-06 10:47 UTC (permalink / raw)
  To: swarren-DDmLM1+adcrQT0dZR+AlfA, mturquette-QSEj5FYQhm4dnm+yROfE0A
  Cc: pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan

Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra20.c |    3 +++
 drivers/clk/tegra/clk-tegra30.c |    4 ++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5d41569..dea94f4 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1252,7 +1252,10 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{emc, clk_max, 0, 1},
 	{cclk, clk_max, 0, 1},
 	{uarta, pll_p, 0, 1},
+	{uartb, pll_p, 0, 0},
+	{uartc, pll_p, 0, 0},
 	{uartd, pll_p, 0, 1},
+	{uarte, pll_p, 0, 0},
 	{usbd, clk_max, 12000000, 0},
 	{usb2, clk_max, 12000000, 0},
 	{usb3, clk_max, 12000000, 0},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a163812..d50146b 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1875,6 +1875,10 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
 
 static __initdata struct tegra_clk_init_table init_table[] = {
 	{uarta, pll_p, 408000000, 1},
+	{uartb, pll_p, 408000000, 0},
+	{uartc, pll_p, 408000000, 0},
+	{uartd, pll_p, 408000000, 0},
+	{uarte, pll_p, 408000000, 0},
 	{pll_a, clk_max, 564480000, 1},
 	{pll_a_out0, clk_max, 11289600, 1},
 	{extern1, pll_a_out0, 0, 1},
-- 
1.7.1.1

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