* [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature
@ 2013-02-07 12:00 Rajeshwari Shinde
2013-02-07 12:00 ` [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's Rajeshwari Shinde
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Rajeshwari Shinde @ 2013-02-07 12:00 UTC (permalink / raw)
To: u-boot
This patchset adds GPIO numbering feature where pinmux setting
can be done just by sending the pin number which is defined as a
enum in asm/gpio.h.
Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass and
supported same for EXYNOS5
Changes in V3:
- New patch added to rename S5P GPIO definitions to
S5P_GPIO
- GPIO Table added to calculate the base address
of input gpio bank.
Rajeshwari Shinde (4):
S5P: GPIO: Add generic pin numbering API's
EXYNOS5: Add gpio pin numbering feature
S5P: Rename GPIO definitions
EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5
arch/arm/cpu/armv7/exynos/pinmux.c | 256 +++++++++++---------
arch/arm/include/asm/arch-exynos/gpio.h | 394 ++++++++++++++++++++++++++++--
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +-
board/samsung/goni/goni.c | 4 +-
board/samsung/origen/origen.c | 8 +-
board/samsung/smdk5250/smdk5250.c | 8 +-
board/samsung/smdkc100/smdkc100.c | 2 +-
board/samsung/smdkv310/smdkv310.c | 10 +-
board/samsung/trats/trats.c | 16 +-
board/samsung/universal_c210/universal.c | 36 ++--
drivers/gpio/s5p_gpio.c | 38 ++-
include/configs/exynos5250-dt.h | 1 +
12 files changed, 597 insertions(+), 202 deletions(-)
--
1.7.4.4
^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's 2013-02-07 12:00 [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature Rajeshwari Shinde @ 2013-02-07 12:00 ` Rajeshwari Shinde 2013-02-08 16:11 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature Rajeshwari Shinde ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Rajeshwari Shinde @ 2013-02-07 12:00 UTC (permalink / raw) To: u-boot This patch adds API's to set config, drive and pull factor in gpio pin numbering feature. Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> --- Changes in V2: - none. Changes in V3: - none. drivers/gpio/s5p_gpio.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 656bf4a..a53bdca 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -196,3 +196,21 @@ int gpio_set_value(unsigned gpio, int value) return 0; } + +void gpio_set_pull(int gpio, int mode) +{ + s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_set_drv(int gpio, int mode) +{ + s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_cfg_pin(int gpio, int cfg) +{ + s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), cfg); +} -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's 2013-02-07 12:00 ` [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's Rajeshwari Shinde @ 2013-02-08 16:11 ` Simon Glass 0 siblings, 0 replies; 13+ messages in thread From: Simon Glass @ 2013-02-08 16:11 UTC (permalink / raw) To: u-boot Hi Rajeshwari, On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote: > This patch adds API's to set config, drive and pull factor in > gpio pin numbering feature. > > Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com> > Acked-by: Simon Glass <sjg@chromium.org> > --- > Changes in V2: > - none. > Changes in V3: > - none. > drivers/gpio/s5p_gpio.c | 18 ++++++++++++++++++ > 1 files changed, 18 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c > index 656bf4a..a53bdca 100644 > --- a/drivers/gpio/s5p_gpio.c > +++ b/drivers/gpio/s5p_gpio.c > @@ -196,3 +196,21 @@ int gpio_set_value(unsigned gpio, int value) > > return 0; > } > + > +void gpio_set_pull(int gpio, int mode) > +{ > + s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), > + s5p_gpio_get_pin(gpio), mode); > +} > + > +void gpio_set_drv(int gpio, int mode) > +{ > + s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), > + s5p_gpio_get_pin(gpio), mode); > +} > + > +void gpio_cfg_pin(int gpio, int cfg) > +{ > + s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), > + s5p_gpio_get_pin(gpio), cfg); > +} Do you intend for these to be generic functions? If so then I think you add a new patch to define this API in include/asm-generic/gpio.h. As mentioned in the other email you may just say that the parameters are arch-specific, but it might be nice to standardise at least the pullup/pulldown mode. Regards, Simon > -- > 1.7.4.4 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature 2013-02-07 12:00 [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature Rajeshwari Shinde 2013-02-07 12:00 ` [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's Rajeshwari Shinde @ 2013-02-07 12:00 ` Rajeshwari Shinde 2013-02-08 3:57 ` Minkyu Kang 2013-02-17 6:21 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions Rajeshwari Shinde 2013-02-07 12:00 ` [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 Rajeshwari Shinde 3 siblings, 2 replies; 13+ messages in thread From: Rajeshwari Shinde @ 2013-02-07 12:00 UTC (permalink / raw) To: u-boot This patch adds support for gpio pin numbering support on EXYNOS5 pinmux. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- Changes in V2: - none. Changes in V3: - none. arch/arm/cpu/armv7/exynos/pinmux.c | 148 +++++-------- arch/arm/include/asm/arch-exynos/gpio.h | 360 ++++++++++++++++++++++++++++++- 2 files changed, 413 insertions(+), 95 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index bd499b4..c79d58e 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -29,89 +29,77 @@ static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = GPIO_A14; count = 2; break; } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, GPIO_PULL_NONE); + gpio_cfg_pin(i, GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; + start = GPIO_C00; + start_ext = GPIO_C10; gpio_func = GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; + start = GPIO_C30; + start_ext = GPIO_C43; gpio_func = GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = GPIO_C40; + start_ext = 0; break; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, GPIO_PULL_UP); + gpio_set_drv(i, GPIO_DRV_4X); } } for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); + gpio_set_pull(start + i, GPIO_PULL_NONE); + gpio_set_drv(start + i, GPIO_DRV_4X); } for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); + gpio_set_pull(start + i, GPIO_PULL_UP); + gpio_set_drv(start + i, GPIO_DRV_4X); } return 0; @@ -119,8 +107,6 @@ static int exynos5_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -138,13 +124,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), + gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -179,55 +165,52 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); break; } } @@ -235,53 +218,42 @@ static void exynos5_i2c_config(int peripheral, int flags) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); } void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; cfg = GPIO_FUNC(0x2); - pin = 0; + pin = GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; cfg = GPIO_FUNC(0x2); - pin = 4; + pin = GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; cfg = GPIO_FUNC(0x5); - pin = 1; + pin = GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; cfg = GPIO_FUNC(0x2); - pin = 0; + pin = GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index cfe1024..af882dd 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -272,15 +272,355 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum exynos5_gpio_pin { + /* GPIO_PART1_STARTS */ + GPIO_A00, + GPIO_A01, + GPIO_A02, + GPIO_A03, + GPIO_A04, + GPIO_A05, + GPIO_A06, + GPIO_A07, + GPIO_A10, + GPIO_A11, + GPIO_A12, + GPIO_A13, + GPIO_A14, + GPIO_A15, + GPIO_A16, + GPIO_A17, + GPIO_A20, + GPIO_A21, + GPIO_A22, + GPIO_A23, + GPIO_A24, + GPIO_A25, + GPIO_A26, + GPIO_A27, + GPIO_B00, + GPIO_B01, + GPIO_B02, + GPIO_B03, + GPIO_B04, + GPIO_B05, + GPIO_B06, + GPIO_B07, + GPIO_B10, + GPIO_B11, + GPIO_B12, + GPIO_B13, + GPIO_B14, + GPIO_B15, + GPIO_B16, + GPIO_B17, + GPIO_B20, + GPIO_B21, + GPIO_B22, + GPIO_B23, + GPIO_B24, + GPIO_B25, + GPIO_B26, + GPIO_B27, + GPIO_B30, + GPIO_B31, + GPIO_B32, + GPIO_B33, + GPIO_B34, + GPIO_B35, + GPIO_B36, + GPIO_B37, + GPIO_C00, + GPIO_C01, + GPIO_C02, + GPIO_C03, + GPIO_C04, + GPIO_C05, + GPIO_C06, + GPIO_C07, + GPIO_C10, + GPIO_C11, + GPIO_C12, + GPIO_C13, + GPIO_C14, + GPIO_C15, + GPIO_C16, + GPIO_C17, + GPIO_C20, + GPIO_C21, + GPIO_C22, + GPIO_C23, + GPIO_C24, + GPIO_C25, + GPIO_C26, + GPIO_C27, + GPIO_C30, + GPIO_C31, + GPIO_C32, + GPIO_C33, + GPIO_C34, + GPIO_C35, + GPIO_C36, + GPIO_C37, + GPIO_D00, + GPIO_D01, + GPIO_D02, + GPIO_D03, + GPIO_D04, + GPIO_D05, + GPIO_D06, + GPIO_D07, + GPIO_D10, + GPIO_D11, + GPIO_D12, + GPIO_D13, + GPIO_D14, + GPIO_D15, + GPIO_D16, + GPIO_D17, + GPIO_Y00, + GPIO_Y01, + GPIO_Y02, + GPIO_Y03, + GPIO_Y04, + GPIO_Y05, + GPIO_Y06, + GPIO_Y07, + GPIO_Y10, + GPIO_Y11, + GPIO_Y12, + GPIO_Y13, + GPIO_Y14, + GPIO_Y15, + GPIO_Y16, + GPIO_Y17, + GPIO_Y20, + GPIO_Y21, + GPIO_Y22, + GPIO_Y23, + GPIO_Y24, + GPIO_Y25, + GPIO_Y26, + GPIO_Y27, + GPIO_Y30, + GPIO_Y31, + GPIO_Y32, + GPIO_Y33, + GPIO_Y34, + GPIO_Y35, + GPIO_Y36, + GPIO_Y37, + GPIO_Y40, + GPIO_Y41, + GPIO_Y42, + GPIO_Y43, + GPIO_Y44, + GPIO_Y45, + GPIO_Y46, + GPIO_Y47, + GPIO_Y50, + GPIO_Y51, + GPIO_Y52, + GPIO_Y53, + GPIO_Y54, + GPIO_Y55, + GPIO_Y56, + GPIO_Y57, + GPIO_Y60, + GPIO_Y61, + GPIO_Y62, + GPIO_Y63, + GPIO_Y64, + GPIO_Y65, + GPIO_Y66, + GPIO_Y67, + RES = GPIO_Y67 + (0x3 * GPIO_PER_BANK), + GPIO_C40, + GPIO_C41, + GPIO_C42, + GPIO_C43, + GPIO_C44, + GPIO_C45, + GPIO_C46, + GPIO_C47, + RES1 = GPIO_C47 + (0x48 * GPIO_PER_BANK), + GPIO_X00, + GPIO_X01, + GPIO_X02, + GPIO_X03, + GPIO_X04, + GPIO_X05, + GPIO_X06, + GPIO_X07, + GPIO_X10, + GPIO_X11, + GPIO_X12, + GPIO_X13, + GPIO_X14, + GPIO_X15, + GPIO_X16, + GPIO_X17, + GPIO_X20, + GPIO_X21, + GPIO_X22, + GPIO_X23, + GPIO_X24, + GPIO_X25, + GPIO_X26, + GPIO_X27, + GPIO_X30, + GPIO_X31, + GPIO_X32, + GPIO_X33, + GPIO_X34, + GPIO_X35, + GPIO_X36, + GPIO_X37, + + /* GPIO_PART2_STARTS */ + GPIO_PART1_MAX, + GPIO_E00 = GPIO_PART1_MAX, + GPIO_E01, + GPIO_E02, + GPIO_E03, + GPIO_E04, + GPIO_E05, + GPIO_E06, + GPIO_E07, + GPIO_E10, + GPIO_E11, + GPIO_E12, + GPIO_E13, + GPIO_E14, + GPIO_E15, + GPIO_E16, + GPIO_E17, + GPIO_F00, + GPIO_F01, + GPIO_F02, + GPIO_F03, + GPIO_F04, + GPIO_F05, + GPIO_F06, + GPIO_F07, + GPIO_F10, + GPIO_F11, + GPIO_F12, + GPIO_F13, + GPIO_F14, + GPIO_F15, + GPIO_F16, + GPIO_F17, + GPIO_G00, + GPIO_G01, + GPIO_G02, + GPIO_G03, + GPIO_G04, + GPIO_G05, + GPIO_G06, + GPIO_G07, + GPIO_G10, + GPIO_G11, + GPIO_G12, + GPIO_G13, + GPIO_G14, + GPIO_G15, + GPIO_G16, + GPIO_G17, + GPIO_G20, + GPIO_G21, + GPIO_G22, + GPIO_G23, + GPIO_G24, + GPIO_G25, + GPIO_G26, + GPIO_G27, + GPIO_H00, + GPIO_H01, + GPIO_H02, + GPIO_H03, + GPIO_H04, + GPIO_H05, + GPIO_H06, + GPIO_H07, + GPIO_H10, + GPIO_H11, + GPIO_H12, + GPIO_H13, + GPIO_H14, + GPIO_H15, + GPIO_H16, + GPIO_H17, + + /* GPIO_PART3_STARTS */ + GPIO_PART2_MAX, + GPIO_V00 = GPIO_PART2_MAX, + GPIO_V01, + GPIO_V02, + GPIO_V03, + GPIO_V04, + GPIO_V05, + GPIO_V06, + GPIO_V07, + GPIO_V10, + GPIO_V11, + GPIO_V12, + GPIO_V13, + GPIO_V14, + GPIO_V15, + GPIO_V16, + GPIO_V17, + RES3 = GPIO_V17 + GPIO_PER_BANK, + GPIO_V20, + GPIO_V21, + GPIO_V22, + GPIO_V23, + GPIO_V24, + GPIO_V25, + GPIO_V26, + GPIO_V27, + GPIO_V30, + GPIO_V31, + GPIO_V32, + GPIO_V33, + GPIO_V34, + GPIO_V35, + GPIO_V36, + GPIO_V37, + RES4 = GPIO_V37 + GPIO_PER_BANK, + GPIO_V40, + GPIO_V41, + GPIO_V42, + GPIO_V43, + GPIO_V44, + GPIO_V45, + GPIO_V46, + GPIO_V47, + + /* GPIO_PART4_STARTS */ + GPIO_PART3_MAX, + GPIO_Z0 = GPIO_PART3_MAX, + GPIO_Z1, + GPIO_Z2, + GPIO_Z3, + GPIO_Z4, + GPIO_Z5, + GPIO_Z6, + GPIO_MAX_PORT +}; + static inline unsigned int s5p_gpio_base(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) + if (nr < GPIO_PART1_MAX) return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) + else if (nr < GPIO_PART2_MAX) return EXYNOS5_GPIO_PART2_BASE; - else + else if (nr < GPIO_PART3_MAX) return EXYNOS5_GPIO_PART3_BASE; + else + return EXYNOS5_GPIO_PART4_BASE; } else if (cpu_is_exynos4()) { if (nr < EXYNOS4_GPIO_PART1_MAX) @@ -295,12 +635,14 @@ static inline unsigned int s5p_gpio_base(int nr) static inline unsigned int s5p_gpio_part_max(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) + if (nr < GPIO_PART1_MAX) return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; + else if (nr < GPIO_PART2_MAX) + return GPIO_PART1_MAX; + else if (nr < GPIO_PART3_MAX) + return GPIO_PART2_MAX; else - return EXYNOS5_GPIO_PART2_MAX; + return GPIO_PART3_MAX; } else if (cpu_is_exynos4()) { if (nr < EXYNOS4_GPIO_PART1_MAX) @@ -311,6 +653,10 @@ static inline unsigned int s5p_gpio_part_max(int nr) return 0; } + +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); #endif /* Pin configurations */ -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature 2013-02-07 12:00 ` [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature Rajeshwari Shinde @ 2013-02-08 3:57 ` Minkyu Kang 2013-02-17 6:21 ` Simon Glass 1 sibling, 0 replies; 13+ messages in thread From: Minkyu Kang @ 2013-02-08 3:57 UTC (permalink / raw) To: u-boot Dear Rajeshwari, On 07/02/13 21:00, Rajeshwari Shinde wrote: > This patch adds support for gpio pin numbering support on EXYNOS5 > pinmux. > > Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > --- > Changes in V2: > - none. > Changes in V3: > - none. > arch/arm/cpu/armv7/exynos/pinmux.c | 148 +++++-------- > arch/arm/include/asm/arch-exynos/gpio.h | 360 ++++++++++++++++++++++++++++++- > 2 files changed, 413 insertions(+), 95 deletions(-) > > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h > index cfe1024..af882dd 100644 > --- a/arch/arm/include/asm/arch-exynos/gpio.h > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > @@ -272,15 +272,355 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); > - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ > * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) > > +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ > +enum exynos5_gpio_pin { Then, how you support exynos4? Maybe we will get redefine error, if we declare exynos4 gpio pins. > + /* GPIO_PART1_STARTS */ > + GPIO_A00, > + GPIO_A01, > + GPIO_A02, > + GPIO_A03, > + GPIO_A04, > + GPIO_A05, > + GPIO_A06, > + GPIO_A07, > + GPIO_A10, > + GPIO_A11, > + GPIO_A12, > + GPIO_A13, > + GPIO_A14, > + GPIO_A15, > + GPIO_A16, > + GPIO_A17, > + GPIO_A20, > + GPIO_A21, > + GPIO_A22, > + GPIO_A23, > + GPIO_A24, > + GPIO_A25, > + GPIO_A26, > + GPIO_A27, > + GPIO_B00, > + GPIO_B01, > + GPIO_B02, > + GPIO_B03, > + GPIO_B04, > + GPIO_B05, > + GPIO_B06, > + GPIO_B07, > + GPIO_B10, > + GPIO_B11, > + GPIO_B12, > + GPIO_B13, > + GPIO_B14, > + GPIO_B15, > + GPIO_B16, > + GPIO_B17, > + GPIO_B20, > + GPIO_B21, > + GPIO_B22, > + GPIO_B23, > + GPIO_B24, > + GPIO_B25, > + GPIO_B26, > + GPIO_B27, > + GPIO_B30, > + GPIO_B31, > + GPIO_B32, > + GPIO_B33, > + GPIO_B34, > + GPIO_B35, > + GPIO_B36, > + GPIO_B37, > + GPIO_C00, > + GPIO_C01, > + GPIO_C02, > + GPIO_C03, > + GPIO_C04, > + GPIO_C05, > + GPIO_C06, > + GPIO_C07, > + GPIO_C10, > + GPIO_C11, > + GPIO_C12, > + GPIO_C13, > + GPIO_C14, > + GPIO_C15, > + GPIO_C16, > + GPIO_C17, > + GPIO_C20, > + GPIO_C21, > + GPIO_C22, > + GPIO_C23, > + GPIO_C24, > + GPIO_C25, > + GPIO_C26, > + GPIO_C27, > + GPIO_C30, > + GPIO_C31, > + GPIO_C32, > + GPIO_C33, > + GPIO_C34, > + GPIO_C35, > + GPIO_C36, > + GPIO_C37, > + GPIO_D00, > + GPIO_D01, > + GPIO_D02, > + GPIO_D03, > + GPIO_D04, > + GPIO_D05, > + GPIO_D06, > + GPIO_D07, > + GPIO_D10, > + GPIO_D11, > + GPIO_D12, > + GPIO_D13, > + GPIO_D14, > + GPIO_D15, > + GPIO_D16, > + GPIO_D17, > + GPIO_Y00, > + GPIO_Y01, > + GPIO_Y02, > + GPIO_Y03, > + GPIO_Y04, > + GPIO_Y05, > + GPIO_Y06, > + GPIO_Y07, > + GPIO_Y10, > + GPIO_Y11, > + GPIO_Y12, > + GPIO_Y13, > + GPIO_Y14, > + GPIO_Y15, > + GPIO_Y16, > + GPIO_Y17, > + GPIO_Y20, > + GPIO_Y21, > + GPIO_Y22, > + GPIO_Y23, > + GPIO_Y24, > + GPIO_Y25, > + GPIO_Y26, > + GPIO_Y27, > + GPIO_Y30, > + GPIO_Y31, > + GPIO_Y32, > + GPIO_Y33, > + GPIO_Y34, > + GPIO_Y35, > + GPIO_Y36, > + GPIO_Y37, > + GPIO_Y40, > + GPIO_Y41, > + GPIO_Y42, > + GPIO_Y43, > + GPIO_Y44, > + GPIO_Y45, > + GPIO_Y46, > + GPIO_Y47, > + GPIO_Y50, > + GPIO_Y51, > + GPIO_Y52, > + GPIO_Y53, > + GPIO_Y54, > + GPIO_Y55, > + GPIO_Y56, > + GPIO_Y57, > + GPIO_Y60, > + GPIO_Y61, > + GPIO_Y62, > + GPIO_Y63, > + GPIO_Y64, > + GPIO_Y65, > + GPIO_Y66, > + GPIO_Y67, > + RES = GPIO_Y67 + (0x3 * GPIO_PER_BANK), > + GPIO_C40, > + GPIO_C41, > + GPIO_C42, > + GPIO_C43, > + GPIO_C44, > + GPIO_C45, > + GPIO_C46, > + GPIO_C47, > + RES1 = GPIO_C47 + (0x48 * GPIO_PER_BANK), > + GPIO_X00, > + GPIO_X01, > + GPIO_X02, > + GPIO_X03, > + GPIO_X04, > + GPIO_X05, > + GPIO_X06, > + GPIO_X07, > + GPIO_X10, > + GPIO_X11, > + GPIO_X12, > + GPIO_X13, > + GPIO_X14, > + GPIO_X15, > + GPIO_X16, > + GPIO_X17, > + GPIO_X20, > + GPIO_X21, > + GPIO_X22, > + GPIO_X23, > + GPIO_X24, > + GPIO_X25, > + GPIO_X26, > + GPIO_X27, > + GPIO_X30, > + GPIO_X31, > + GPIO_X32, > + GPIO_X33, > + GPIO_X34, > + GPIO_X35, > + GPIO_X36, > + GPIO_X37, > + > + /* GPIO_PART2_STARTS */ > + GPIO_PART1_MAX, > + GPIO_E00 = GPIO_PART1_MAX, > + GPIO_E01, > + GPIO_E02, > + GPIO_E03, > + GPIO_E04, > + GPIO_E05, > + GPIO_E06, > + GPIO_E07, > + GPIO_E10, > + GPIO_E11, > + GPIO_E12, > + GPIO_E13, > + GPIO_E14, > + GPIO_E15, > + GPIO_E16, > + GPIO_E17, > + GPIO_F00, > + GPIO_F01, > + GPIO_F02, > + GPIO_F03, > + GPIO_F04, > + GPIO_F05, > + GPIO_F06, > + GPIO_F07, > + GPIO_F10, > + GPIO_F11, > + GPIO_F12, > + GPIO_F13, > + GPIO_F14, > + GPIO_F15, > + GPIO_F16, > + GPIO_F17, > + GPIO_G00, > + GPIO_G01, > + GPIO_G02, > + GPIO_G03, > + GPIO_G04, > + GPIO_G05, > + GPIO_G06, > + GPIO_G07, > + GPIO_G10, > + GPIO_G11, > + GPIO_G12, > + GPIO_G13, > + GPIO_G14, > + GPIO_G15, > + GPIO_G16, > + GPIO_G17, > + GPIO_G20, > + GPIO_G21, > + GPIO_G22, > + GPIO_G23, > + GPIO_G24, > + GPIO_G25, > + GPIO_G26, > + GPIO_G27, > + GPIO_H00, > + GPIO_H01, > + GPIO_H02, > + GPIO_H03, > + GPIO_H04, > + GPIO_H05, > + GPIO_H06, > + GPIO_H07, > + GPIO_H10, > + GPIO_H11, > + GPIO_H12, > + GPIO_H13, > + GPIO_H14, > + GPIO_H15, > + GPIO_H16, > + GPIO_H17, > + > + /* GPIO_PART3_STARTS */ > + GPIO_PART2_MAX, > + GPIO_V00 = GPIO_PART2_MAX, > + GPIO_V01, > + GPIO_V02, > + GPIO_V03, > + GPIO_V04, > + GPIO_V05, > + GPIO_V06, > + GPIO_V07, > + GPIO_V10, > + GPIO_V11, > + GPIO_V12, > + GPIO_V13, > + GPIO_V14, > + GPIO_V15, > + GPIO_V16, > + GPIO_V17, > + RES3 = GPIO_V17 + GPIO_PER_BANK, > + GPIO_V20, > + GPIO_V21, > + GPIO_V22, > + GPIO_V23, > + GPIO_V24, > + GPIO_V25, > + GPIO_V26, > + GPIO_V27, > + GPIO_V30, > + GPIO_V31, > + GPIO_V32, > + GPIO_V33, > + GPIO_V34, > + GPIO_V35, > + GPIO_V36, > + GPIO_V37, > + RES4 = GPIO_V37 + GPIO_PER_BANK, > + GPIO_V40, > + GPIO_V41, > + GPIO_V42, > + GPIO_V43, > + GPIO_V44, > + GPIO_V45, > + GPIO_V46, > + GPIO_V47, > + > + /* GPIO_PART4_STARTS */ > + GPIO_PART3_MAX, > + GPIO_Z0 = GPIO_PART3_MAX, > + GPIO_Z1, > + GPIO_Z2, > + GPIO_Z3, > + GPIO_Z4, > + GPIO_Z5, > + GPIO_Z6, > + GPIO_MAX_PORT > +}; > + Thanks, Minkyu Kang. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature 2013-02-07 12:00 ` [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature Rajeshwari Shinde 2013-02-08 3:57 ` Minkyu Kang @ 2013-02-17 6:21 ` Simon Glass 2013-02-18 12:10 ` Rajeshwari Birje 1 sibling, 1 reply; 13+ messages in thread From: Simon Glass @ 2013-02-17 6:21 UTC (permalink / raw) To: u-boot Hi Rajeshwari, On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote: > This patch adds support for gpio pin numbering support on EXYNOS5 > pinmux. > > Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> If we are going to have GPIO numbering it needs to be continuous. The scheme in the Chrome OS tree does this. It's great to have gpio_cfg_pin() but I can't see the actual definition. Also please carefully check that the GPIO numbers are all correct - it doesn't look right to me. Also for the benefit of people using FDT who still don't have symbols and who don't yet have proper GPIO support in U-Boot (phandle to bank + number within bank, as in the kernel), can you please annotate the first enum value of each GPIO group (A, B, C) with its hex value? That will also provide a check that things are correct. Regards, Simon > --- > Changes in V2: > - none. > Changes in V3: > - none. > arch/arm/cpu/armv7/exynos/pinmux.c | 148 +++++-------- > arch/arm/include/asm/arch-exynos/gpio.h | 360 ++++++++++++++++++++++++++++++- > 2 files changed, 413 insertions(+), 95 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c > index bd499b4..c79d58e 100644 > --- a/arch/arm/cpu/armv7/exynos/pinmux.c > +++ b/arch/arm/cpu/armv7/exynos/pinmux.c > @@ -29,89 +29,77 @@ > > static void exynos5_uart_config(int peripheral) > { > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > - struct s5p_gpio_bank *bank; > int i, start, count; > > switch (peripheral) { > case PERIPH_ID_UART0: > - bank = &gpio1->a0; > - start = 0; > + start = GPIO_A00; > count = 4; > break; > case PERIPH_ID_UART1: > - bank = &gpio1->d0; > - start = 0; > + start = GPIO_D00; > count = 4; > break; > case PERIPH_ID_UART2: > - bank = &gpio1->a1; > - start = 0; > + start = GPIO_A10; > count = 4; > break; > case PERIPH_ID_UART3: > - bank = &gpio1->a1; > - start = 4; > + start = GPIO_A14; > count = 2; > break; > } > for (i = start; i < start + count; i++) { > - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); > - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); > + gpio_set_pull(i, GPIO_PULL_NONE); > + gpio_cfg_pin(i, GPIO_FUNC(0x2)); > } > } > > static int exynos5_mmc_config(int peripheral, int flags) > { > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > - struct s5p_gpio_bank *bank, *bank_ext; > - int i, start = 0, gpio_func = 0; > + int i, start, start_ext, gpio_func = 0; > > switch (peripheral) { > case PERIPH_ID_SDMMC0: > - bank = &gpio1->c0; > - bank_ext = &gpio1->c1; > - start = 0; > + start = GPIO_C00; > + start_ext = GPIO_C10; > gpio_func = GPIO_FUNC(0x2); > break; > case PERIPH_ID_SDMMC1: > - bank = &gpio1->c2; > - bank_ext = NULL; > + start = GPIO_C20; > + start_ext = 0; > break; > case PERIPH_ID_SDMMC2: > - bank = &gpio1->c3; > - bank_ext = &gpio1->c4; > - start = 3; > + start = GPIO_C30; > + start_ext = GPIO_C43; > gpio_func = GPIO_FUNC(0x3); > break; > case PERIPH_ID_SDMMC3: > - bank = &gpio1->c4; > - bank_ext = NULL; > + start = GPIO_C40; > + start_ext = 0; > break; > } > - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { > + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { > debug("SDMMC device %d does not support 8bit mode", > peripheral); > return -1; > } > if (flags & PINMUX_FLAG_8BIT_MODE) { > - for (i = start; i <= (start + 3); i++) { > - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); > - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); > - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); > + for (i = start_ext; i <= (start_ext + 3); i++) { > + gpio_cfg_pin(i, gpio_func); > + gpio_set_pull(i, GPIO_PULL_UP); > + gpio_set_drv(i, GPIO_DRV_4X); > } > } > for (i = 0; i < 2; i++) { > - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); > - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); > - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); > + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); > + gpio_set_pull(start + i, GPIO_PULL_NONE); > + gpio_set_drv(start + i, GPIO_DRV_4X); > } > for (i = 3; i <= 6; i++) { > - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); > - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); > - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); > + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); > + gpio_set_pull(start + i, GPIO_PULL_UP); > + gpio_set_drv(start + i, GPIO_DRV_4X); > } > > return 0; > @@ -119,8 +107,6 @@ static int exynos5_mmc_config(int peripheral, int flags) > > static void exynos5_sromc_config(int flags) > { > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > int i; > > /* > @@ -138,13 +124,13 @@ static void exynos5_sromc_config(int flags) > * GPY1[2] SROM_WAIT(2) > * GPY1[3] EBI_DATA_RDn(2) > */ > - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), > + gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), > GPIO_FUNC(2)); > - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); > - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); > + gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); > + gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); > > for (i = 0; i < 4; i++) > - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); > + gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); > > /* > * EBI: 8 Addrss Lines > @@ -179,55 +165,52 @@ static void exynos5_sromc_config(int flags) > * GPY6[7] EBI_DATA[15](2) > */ > for (i = 0; i < 8; i++) { > - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); > - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); > + gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); > + gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); > > - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); > - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); > + gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); > + gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); > > - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); > - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); > + gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); > + gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); > } > } > > static void exynos5_i2c_config(int peripheral, int flags) > { > > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > - > switch (peripheral) { > case PERIPH_ID_I2C0: > - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); > - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); > + gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); > + gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); > break; > case PERIPH_ID_I2C1: > - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); > - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); > + gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); > + gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); > break; > case PERIPH_ID_I2C2: > - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); > - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); > break; > case PERIPH_ID_I2C3: > - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); > - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); > break; > case PERIPH_ID_I2C4: > - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); > - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); > break; > case PERIPH_ID_I2C5: > - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); > - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); > break; > case PERIPH_ID_I2C6: > - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); > - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); > + gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); > + gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); > break; > case PERIPH_ID_I2C7: > - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); > - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); > + gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); > break; > } > } > @@ -235,53 +218,42 @@ static void exynos5_i2c_config(int peripheral, int flags) > static void exynos5_i2s_config(int peripheral) > { > int i; > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > > for (i = 0; i < 5; i++) > - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); > + gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); > } > > void exynos5_spi_config(int peripheral) > { > int cfg = 0, pin = 0, i; > - struct s5p_gpio_bank *bank = NULL; > - struct exynos5_gpio_part1 *gpio1 = > - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); > - struct exynos5_gpio_part2 *gpio2 = > - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); > > switch (peripheral) { > case PERIPH_ID_SPI0: > - bank = &gpio1->a2; > cfg = GPIO_FUNC(0x2); > - pin = 0; > + pin = GPIO_A20; > break; > case PERIPH_ID_SPI1: > - bank = &gpio1->a2; > cfg = GPIO_FUNC(0x2); > - pin = 4; > + pin = GPIO_A24; > break; > case PERIPH_ID_SPI2: > - bank = &gpio1->b1; > cfg = GPIO_FUNC(0x5); > - pin = 1; > + pin = GPIO_B11; > break; > case PERIPH_ID_SPI3: > - bank = &gpio2->f1; > cfg = GPIO_FUNC(0x2); > - pin = 0; > + pin = GPIO_F10; > break; > case PERIPH_ID_SPI4: > for (i = 0; i < 2; i++) { > - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); > - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); > + gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); > + gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); > } > break; > } > if (peripheral != PERIPH_ID_SPI4) { > for (i = pin; i < pin + 4; i++) > - s5p_gpio_cfg_pin(bank, i, cfg); > + gpio_cfg_pin(i, cfg); > } > } > > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h > index cfe1024..af882dd 100644 > --- a/arch/arm/include/asm/arch-exynos/gpio.h > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > @@ -272,15 +272,355 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); > - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ > * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) > > +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ > +enum exynos5_gpio_pin { > + /* GPIO_PART1_STARTS */ > + GPIO_A00, > + GPIO_A01, > + GPIO_A02, > + GPIO_A03, > + GPIO_A04, > + GPIO_A05, > + GPIO_A06, > + GPIO_A07, > + GPIO_A10, > + GPIO_A11, > + GPIO_A12, > + GPIO_A13, > + GPIO_A14, > + GPIO_A15, > + GPIO_A16, > + GPIO_A17, > + GPIO_A20, > + GPIO_A21, > + GPIO_A22, > + GPIO_A23, > + GPIO_A24, > + GPIO_A25, > + GPIO_A26, > + GPIO_A27, > + GPIO_B00, > + GPIO_B01, > + GPIO_B02, > + GPIO_B03, > + GPIO_B04, > + GPIO_B05, > + GPIO_B06, > + GPIO_B07, > + GPIO_B10, > + GPIO_B11, > + GPIO_B12, > + GPIO_B13, > + GPIO_B14, > + GPIO_B15, > + GPIO_B16, > + GPIO_B17, > + GPIO_B20, > + GPIO_B21, > + GPIO_B22, > + GPIO_B23, > + GPIO_B24, > + GPIO_B25, > + GPIO_B26, > + GPIO_B27, > + GPIO_B30, > + GPIO_B31, > + GPIO_B32, > + GPIO_B33, > + GPIO_B34, > + GPIO_B35, > + GPIO_B36, > + GPIO_B37, > + GPIO_C00, > + GPIO_C01, > + GPIO_C02, > + GPIO_C03, > + GPIO_C04, > + GPIO_C05, > + GPIO_C06, > + GPIO_C07, > + GPIO_C10, > + GPIO_C11, > + GPIO_C12, > + GPIO_C13, > + GPIO_C14, > + GPIO_C15, > + GPIO_C16, > + GPIO_C17, > + GPIO_C20, > + GPIO_C21, > + GPIO_C22, > + GPIO_C23, > + GPIO_C24, > + GPIO_C25, > + GPIO_C26, > + GPIO_C27, > + GPIO_C30, > + GPIO_C31, > + GPIO_C32, > + GPIO_C33, > + GPIO_C34, > + GPIO_C35, > + GPIO_C36, > + GPIO_C37, > + GPIO_D00, > + GPIO_D01, > + GPIO_D02, > + GPIO_D03, > + GPIO_D04, > + GPIO_D05, > + GPIO_D06, > + GPIO_D07, > + GPIO_D10, > + GPIO_D11, > + GPIO_D12, > + GPIO_D13, > + GPIO_D14, > + GPIO_D15, > + GPIO_D16, > + GPIO_D17, > + GPIO_Y00, > + GPIO_Y01, > + GPIO_Y02, > + GPIO_Y03, > + GPIO_Y04, > + GPIO_Y05, > + GPIO_Y06, > + GPIO_Y07, > + GPIO_Y10, > + GPIO_Y11, > + GPIO_Y12, > + GPIO_Y13, > + GPIO_Y14, > + GPIO_Y15, > + GPIO_Y16, > + GPIO_Y17, > + GPIO_Y20, > + GPIO_Y21, > + GPIO_Y22, > + GPIO_Y23, > + GPIO_Y24, > + GPIO_Y25, > + GPIO_Y26, > + GPIO_Y27, > + GPIO_Y30, > + GPIO_Y31, > + GPIO_Y32, > + GPIO_Y33, > + GPIO_Y34, > + GPIO_Y35, > + GPIO_Y36, > + GPIO_Y37, > + GPIO_Y40, > + GPIO_Y41, > + GPIO_Y42, > + GPIO_Y43, > + GPIO_Y44, > + GPIO_Y45, > + GPIO_Y46, > + GPIO_Y47, > + GPIO_Y50, > + GPIO_Y51, > + GPIO_Y52, > + GPIO_Y53, > + GPIO_Y54, > + GPIO_Y55, > + GPIO_Y56, > + GPIO_Y57, > + GPIO_Y60, > + GPIO_Y61, > + GPIO_Y62, > + GPIO_Y63, > + GPIO_Y64, > + GPIO_Y65, > + GPIO_Y66, > + GPIO_Y67, > + RES = GPIO_Y67 + (0x3 * GPIO_PER_BANK), What is happening here? Have you checked that the values are correct? To me it looks like GPIO_C40 will be set to RES + 1, but it should be set to GPIO_Y67 + 1 I think. > + GPIO_C40, > + GPIO_C41, > + GPIO_C42, > + GPIO_C43, > + GPIO_C44, > + GPIO_C45, > + GPIO_C46, > + GPIO_C47, > + RES1 = GPIO_C47 + (0x48 * GPIO_PER_BANK), > + GPIO_X00, > + GPIO_X01, > + GPIO_X02, > + GPIO_X03, > + GPIO_X04, > + GPIO_X05, > + GPIO_X06, > + GPIO_X07, > + GPIO_X10, > + GPIO_X11, > + GPIO_X12, > + GPIO_X13, > + GPIO_X14, > + GPIO_X15, > + GPIO_X16, > + GPIO_X17, > + GPIO_X20, > + GPIO_X21, > + GPIO_X22, > + GPIO_X23, > + GPIO_X24, > + GPIO_X25, > + GPIO_X26, > + GPIO_X27, > + GPIO_X30, > + GPIO_X31, > + GPIO_X32, > + GPIO_X33, > + GPIO_X34, > + GPIO_X35, > + GPIO_X36, > + GPIO_X37, > + > + /* GPIO_PART2_STARTS */ > + GPIO_PART1_MAX, > + GPIO_E00 = GPIO_PART1_MAX, > + GPIO_E01, > + GPIO_E02, > + GPIO_E03, > + GPIO_E04, > + GPIO_E05, > + GPIO_E06, > + GPIO_E07, > + GPIO_E10, > + GPIO_E11, > + GPIO_E12, > + GPIO_E13, > + GPIO_E14, > + GPIO_E15, > + GPIO_E16, > + GPIO_E17, > + GPIO_F00, > + GPIO_F01, > + GPIO_F02, > + GPIO_F03, > + GPIO_F04, > + GPIO_F05, > + GPIO_F06, > + GPIO_F07, > + GPIO_F10, > + GPIO_F11, > + GPIO_F12, > + GPIO_F13, > + GPIO_F14, > + GPIO_F15, > + GPIO_F16, > + GPIO_F17, > + GPIO_G00, > + GPIO_G01, > + GPIO_G02, > + GPIO_G03, > + GPIO_G04, > + GPIO_G05, > + GPIO_G06, > + GPIO_G07, > + GPIO_G10, > + GPIO_G11, > + GPIO_G12, > + GPIO_G13, > + GPIO_G14, > + GPIO_G15, > + GPIO_G16, > + GPIO_G17, > + GPIO_G20, > + GPIO_G21, > + GPIO_G22, > + GPIO_G23, > + GPIO_G24, > + GPIO_G25, > + GPIO_G26, > + GPIO_G27, > + GPIO_H00, > + GPIO_H01, > + GPIO_H02, > + GPIO_H03, > + GPIO_H04, > + GPIO_H05, > + GPIO_H06, > + GPIO_H07, > + GPIO_H10, > + GPIO_H11, > + GPIO_H12, > + GPIO_H13, > + GPIO_H14, > + GPIO_H15, > + GPIO_H16, > + GPIO_H17, > + > + /* GPIO_PART3_STARTS */ > + GPIO_PART2_MAX, > + GPIO_V00 = GPIO_PART2_MAX, > + GPIO_V01, > + GPIO_V02, > + GPIO_V03, > + GPIO_V04, > + GPIO_V05, > + GPIO_V06, > + GPIO_V07, > + GPIO_V10, > + GPIO_V11, > + GPIO_V12, > + GPIO_V13, > + GPIO_V14, > + GPIO_V15, > + GPIO_V16, > + GPIO_V17, > + RES3 = GPIO_V17 + GPIO_PER_BANK, > + GPIO_V20, > + GPIO_V21, > + GPIO_V22, > + GPIO_V23, > + GPIO_V24, > + GPIO_V25, > + GPIO_V26, > + GPIO_V27, > + GPIO_V30, > + GPIO_V31, > + GPIO_V32, > + GPIO_V33, > + GPIO_V34, > + GPIO_V35, > + GPIO_V36, > + GPIO_V37, > + RES4 = GPIO_V37 + GPIO_PER_BANK, > + GPIO_V40, > + GPIO_V41, > + GPIO_V42, > + GPIO_V43, > + GPIO_V44, > + GPIO_V45, > + GPIO_V46, > + GPIO_V47, > + > + /* GPIO_PART4_STARTS */ > + GPIO_PART3_MAX, > + GPIO_Z0 = GPIO_PART3_MAX, > + GPIO_Z1, > + GPIO_Z2, > + GPIO_Z3, > + GPIO_Z4, > + GPIO_Z5, > + GPIO_Z6, > + GPIO_MAX_PORT > +}; > + > static inline unsigned int s5p_gpio_base(int nr) > { > if (cpu_is_exynos5()) { > - if (nr < EXYNOS5_GPIO_PART1_MAX) > + if (nr < GPIO_PART1_MAX) > return EXYNOS5_GPIO_PART1_BASE; > - else if (nr < EXYNOS5_GPIO_PART2_MAX) > + else if (nr < GPIO_PART2_MAX) > return EXYNOS5_GPIO_PART2_BASE; > - else > + else if (nr < GPIO_PART3_MAX) > return EXYNOS5_GPIO_PART3_BASE; > + else > + return EXYNOS5_GPIO_PART4_BASE; > > } else if (cpu_is_exynos4()) { > if (nr < EXYNOS4_GPIO_PART1_MAX) > @@ -295,12 +635,14 @@ static inline unsigned int s5p_gpio_base(int nr) > static inline unsigned int s5p_gpio_part_max(int nr) > { > if (cpu_is_exynos5()) { > - if (nr < EXYNOS5_GPIO_PART1_MAX) > + if (nr < GPIO_PART1_MAX) > return 0; > - else if (nr < EXYNOS5_GPIO_PART2_MAX) > - return EXYNOS5_GPIO_PART1_MAX; > + else if (nr < GPIO_PART2_MAX) > + return GPIO_PART1_MAX; > + else if (nr < GPIO_PART3_MAX) > + return GPIO_PART2_MAX; > else > - return EXYNOS5_GPIO_PART2_MAX; > + return GPIO_PART3_MAX; > > } else if (cpu_is_exynos4()) { > if (nr < EXYNOS4_GPIO_PART1_MAX) > @@ -311,6 +653,10 @@ static inline unsigned int s5p_gpio_part_max(int nr) > > return 0; > } > + > +void gpio_cfg_pin(int gpio, int cfg); > +void gpio_set_pull(int gpio, int mode); > +void gpio_set_drv(int gpio, int mode); You set these in the header file but provide no definition, nor any enums/defines for the cfg and mode parameters. > #endif > > /* Pin configurations */ > -- > 1.7.4.4 > Regards, Simon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature 2013-02-17 6:21 ` Simon Glass @ 2013-02-18 12:10 ` Rajeshwari Birje 2013-02-21 20:53 ` Simon Glass 0 siblings, 1 reply; 13+ messages in thread From: Rajeshwari Birje @ 2013-02-18 12:10 UTC (permalink / raw) To: u-boot Hi Simon, Thank you for comments. On Sun, Feb 17, 2013 at 11:51 AM, Simon Glass <sjg@chromium.org> wrote: > Hi Rajeshwari, > > On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde > <rajeshwari.s@samsung.com> wrote: >> This patch adds support for gpio pin numbering support on EXYNOS5 >> pinmux. >> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> >> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > > If we are going to have GPIO numbering it needs to be continuous. The > scheme in the Chrome OS tree does this. -Okay > > It's great to have gpio_cfg_pin() but I can't see the actual definition. The definition for same is in "S5P: GPIO: Add generic pin numbering API's" patch of same patch set. > > Also please carefully check that the GPIO numbers are all correct - it > doesn't look right to me. I had verified for each value. Will recheck the same. > > Also for the benefit of people using FDT who still don't have symbols > and who don't yet have proper GPIO support in U-Boot (phandle to bank > + number within bank, as in the kernel), can you please annotate the > first enum value of each GPIO group (A, B, C) with its hex value? That > will also provide a check that things are correct. So you want me to assign each bank GPIO group with its Base adress in hex? > One more doubt as per Minkyu comment to support the same for EXYNOS4 and avoid error do we have to append EXYNOS5_ at the start of enum values? Or anyother solution you would suggest? > Regards, > Simon > >> --- >> Changes in V2: >> - none. >> Changes in V3: >> - none. >> arch/arm/cpu/armv7/exynos/pinmux.c | 148 +++++-------- >> arch/arm/include/asm/arch-exynos/gpio.h | 360 ++++++++++++++++++++++++++++++- >> 2 files changed, 413 insertions(+), 95 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c >> index bd499b4..c79d58e 100644 >> --- a/arch/arm/cpu/armv7/exynos/pinmux.c >> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c >> @@ -29,89 +29,77 @@ >> >> static void exynos5_uart_config(int peripheral) >> { >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> - struct s5p_gpio_bank *bank; >> int i, start, count; >> >> switch (peripheral) { >> case PERIPH_ID_UART0: >> - bank = &gpio1->a0; >> - start = 0; >> + start = GPIO_A00; >> count = 4; >> break; >> case PERIPH_ID_UART1: >> - bank = &gpio1->d0; >> - start = 0; >> + start = GPIO_D00; >> count = 4; >> break; >> case PERIPH_ID_UART2: >> - bank = &gpio1->a1; >> - start = 0; >> + start = GPIO_A10; >> count = 4; >> break; >> case PERIPH_ID_UART3: >> - bank = &gpio1->a1; >> - start = 4; >> + start = GPIO_A14; >> count = 2; >> break; >> } >> for (i = start; i < start + count; i++) { >> - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> + gpio_set_pull(i, GPIO_PULL_NONE); >> + gpio_cfg_pin(i, GPIO_FUNC(0x2)); >> } >> } >> >> static int exynos5_mmc_config(int peripheral, int flags) >> { >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> - struct s5p_gpio_bank *bank, *bank_ext; >> - int i, start = 0, gpio_func = 0; >> + int i, start, start_ext, gpio_func = 0; >> >> switch (peripheral) { >> case PERIPH_ID_SDMMC0: >> - bank = &gpio1->c0; >> - bank_ext = &gpio1->c1; >> - start = 0; >> + start = GPIO_C00; >> + start_ext = GPIO_C10; >> gpio_func = GPIO_FUNC(0x2); >> break; >> case PERIPH_ID_SDMMC1: >> - bank = &gpio1->c2; >> - bank_ext = NULL; >> + start = GPIO_C20; >> + start_ext = 0; >> break; >> case PERIPH_ID_SDMMC2: >> - bank = &gpio1->c3; >> - bank_ext = &gpio1->c4; >> - start = 3; >> + start = GPIO_C30; >> + start_ext = GPIO_C43; >> gpio_func = GPIO_FUNC(0x3); >> break; >> case PERIPH_ID_SDMMC3: >> - bank = &gpio1->c4; >> - bank_ext = NULL; >> + start = GPIO_C40; >> + start_ext = 0; >> break; >> } >> - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { >> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { >> debug("SDMMC device %d does not support 8bit mode", >> peripheral); >> return -1; >> } >> if (flags & PINMUX_FLAG_8BIT_MODE) { >> - for (i = start; i <= (start + 3); i++) { >> - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); >> - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); >> - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); >> + for (i = start_ext; i <= (start_ext + 3); i++) { >> + gpio_cfg_pin(i, gpio_func); >> + gpio_set_pull(i, GPIO_PULL_UP); >> + gpio_set_drv(i, GPIO_DRV_4X); >> } >> } >> for (i = 0; i < 2; i++) { >> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >> + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); >> + gpio_set_pull(start + i, GPIO_PULL_NONE); >> + gpio_set_drv(start + i, GPIO_DRV_4X); >> } >> for (i = 3; i <= 6; i++) { >> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); >> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >> + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); >> + gpio_set_pull(start + i, GPIO_PULL_UP); >> + gpio_set_drv(start + i, GPIO_DRV_4X); >> } >> >> return 0; >> @@ -119,8 +107,6 @@ static int exynos5_mmc_config(int peripheral, int flags) >> >> static void exynos5_sromc_config(int flags) >> { >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> int i; >> >> /* >> @@ -138,13 +124,13 @@ static void exynos5_sromc_config(int flags) >> * GPY1[2] SROM_WAIT(2) >> * GPY1[3] EBI_DATA_RDn(2) >> */ >> - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), >> + gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), >> GPIO_FUNC(2)); >> - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); >> - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); >> + gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); >> + gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); >> >> for (i = 0; i < 4; i++) >> - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); >> + gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); >> >> /* >> * EBI: 8 Addrss Lines >> @@ -179,55 +165,52 @@ static void exynos5_sromc_config(int flags) >> * GPY6[7] EBI_DATA[15](2) >> */ >> for (i = 0; i < 8; i++) { >> - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); >> - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); >> + gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); >> + gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); >> >> - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); >> - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); >> + gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); >> + gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); >> >> - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); >> - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); >> + gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); >> + gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); >> } >> } >> >> static void exynos5_i2c_config(int peripheral, int flags) >> { >> >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> - >> switch (peripheral) { >> case PERIPH_ID_I2C0: >> - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); >> - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); >> + gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); >> + gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); >> break; >> case PERIPH_ID_I2C1: >> - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); >> - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); >> + gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); >> + gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); >> break; >> case PERIPH_ID_I2C2: >> - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); >> - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); >> break; >> case PERIPH_ID_I2C3: >> - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); >> - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); >> break; >> case PERIPH_ID_I2C4: >> - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); >> - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); >> break; >> case PERIPH_ID_I2C5: >> - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); >> - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); >> break; >> case PERIPH_ID_I2C6: >> - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); >> - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); >> + gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); >> + gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); >> break; >> case PERIPH_ID_I2C7: >> - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); >> - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); >> + gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); >> break; >> } >> } >> @@ -235,53 +218,42 @@ static void exynos5_i2c_config(int peripheral, int flags) >> static void exynos5_i2s_config(int peripheral) >> { >> int i; >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> >> for (i = 0; i < 5; i++) >> - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); >> + gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); >> } >> >> void exynos5_spi_config(int peripheral) >> { >> int cfg = 0, pin = 0, i; >> - struct s5p_gpio_bank *bank = NULL; >> - struct exynos5_gpio_part1 *gpio1 = >> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >> - struct exynos5_gpio_part2 *gpio2 = >> - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); >> >> switch (peripheral) { >> case PERIPH_ID_SPI0: >> - bank = &gpio1->a2; >> cfg = GPIO_FUNC(0x2); >> - pin = 0; >> + pin = GPIO_A20; >> break; >> case PERIPH_ID_SPI1: >> - bank = &gpio1->a2; >> cfg = GPIO_FUNC(0x2); >> - pin = 4; >> + pin = GPIO_A24; >> break; >> case PERIPH_ID_SPI2: >> - bank = &gpio1->b1; >> cfg = GPIO_FUNC(0x5); >> - pin = 1; >> + pin = GPIO_B11; >> break; >> case PERIPH_ID_SPI3: >> - bank = &gpio2->f1; >> cfg = GPIO_FUNC(0x2); >> - pin = 0; >> + pin = GPIO_F10; >> break; >> case PERIPH_ID_SPI4: >> for (i = 0; i < 2; i++) { >> - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); >> - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); >> + gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); >> + gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); >> } >> break; >> } >> if (peripheral != PERIPH_ID_SPI4) { >> for (i = pin; i < pin + 4; i++) >> - s5p_gpio_cfg_pin(bank, i, cfg); >> + gpio_cfg_pin(i, cfg); >> } >> } >> >> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h >> index cfe1024..af882dd 100644 >> --- a/arch/arm/include/asm/arch-exynos/gpio.h >> +++ b/arch/arm/include/asm/arch-exynos/gpio.h >> @@ -272,15 +272,355 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); >> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ >> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) >> >> +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ >> +enum exynos5_gpio_pin { >> + /* GPIO_PART1_STARTS */ >> + GPIO_A00, >> + GPIO_A01, >> + GPIO_A02, >> + GPIO_A03, >> + GPIO_A04, >> + GPIO_A05, >> + GPIO_A06, >> + GPIO_A07, >> + GPIO_A10, >> + GPIO_A11, >> + GPIO_A12, >> + GPIO_A13, >> + GPIO_A14, >> + GPIO_A15, >> + GPIO_A16, >> + GPIO_A17, >> + GPIO_A20, >> + GPIO_A21, >> + GPIO_A22, >> + GPIO_A23, >> + GPIO_A24, >> + GPIO_A25, >> + GPIO_A26, >> + GPIO_A27, >> + GPIO_B00, >> + GPIO_B01, >> + GPIO_B02, >> + GPIO_B03, >> + GPIO_B04, >> + GPIO_B05, >> + GPIO_B06, >> + GPIO_B07, >> + GPIO_B10, >> + GPIO_B11, >> + GPIO_B12, >> + GPIO_B13, >> + GPIO_B14, >> + GPIO_B15, >> + GPIO_B16, >> + GPIO_B17, >> + GPIO_B20, >> + GPIO_B21, >> + GPIO_B22, >> + GPIO_B23, >> + GPIO_B24, >> + GPIO_B25, >> + GPIO_B26, >> + GPIO_B27, >> + GPIO_B30, >> + GPIO_B31, >> + GPIO_B32, >> + GPIO_B33, >> + GPIO_B34, >> + GPIO_B35, >> + GPIO_B36, >> + GPIO_B37, >> + GPIO_C00, >> + GPIO_C01, >> + GPIO_C02, >> + GPIO_C03, >> + GPIO_C04, >> + GPIO_C05, >> + GPIO_C06, >> + GPIO_C07, >> + GPIO_C10, >> + GPIO_C11, >> + GPIO_C12, >> + GPIO_C13, >> + GPIO_C14, >> + GPIO_C15, >> + GPIO_C16, >> + GPIO_C17, >> + GPIO_C20, >> + GPIO_C21, >> + GPIO_C22, >> + GPIO_C23, >> + GPIO_C24, >> + GPIO_C25, >> + GPIO_C26, >> + GPIO_C27, >> + GPIO_C30, >> + GPIO_C31, >> + GPIO_C32, >> + GPIO_C33, >> + GPIO_C34, >> + GPIO_C35, >> + GPIO_C36, >> + GPIO_C37, >> + GPIO_D00, >> + GPIO_D01, >> + GPIO_D02, >> + GPIO_D03, >> + GPIO_D04, >> + GPIO_D05, >> + GPIO_D06, >> + GPIO_D07, >> + GPIO_D10, >> + GPIO_D11, >> + GPIO_D12, >> + GPIO_D13, >> + GPIO_D14, >> + GPIO_D15, >> + GPIO_D16, >> + GPIO_D17, >> + GPIO_Y00, >> + GPIO_Y01, >> + GPIO_Y02, >> + GPIO_Y03, >> + GPIO_Y04, >> + GPIO_Y05, >> + GPIO_Y06, >> + GPIO_Y07, >> + GPIO_Y10, >> + GPIO_Y11, >> + GPIO_Y12, >> + GPIO_Y13, >> + GPIO_Y14, >> + GPIO_Y15, >> + GPIO_Y16, >> + GPIO_Y17, >> + GPIO_Y20, >> + GPIO_Y21, >> + GPIO_Y22, >> + GPIO_Y23, >> + GPIO_Y24, >> + GPIO_Y25, >> + GPIO_Y26, >> + GPIO_Y27, >> + GPIO_Y30, >> + GPIO_Y31, >> + GPIO_Y32, >> + GPIO_Y33, >> + GPIO_Y34, >> + GPIO_Y35, >> + GPIO_Y36, >> + GPIO_Y37, >> + GPIO_Y40, >> + GPIO_Y41, >> + GPIO_Y42, >> + GPIO_Y43, >> + GPIO_Y44, >> + GPIO_Y45, >> + GPIO_Y46, >> + GPIO_Y47, >> + GPIO_Y50, >> + GPIO_Y51, >> + GPIO_Y52, >> + GPIO_Y53, >> + GPIO_Y54, >> + GPIO_Y55, >> + GPIO_Y56, >> + GPIO_Y57, >> + GPIO_Y60, >> + GPIO_Y61, >> + GPIO_Y62, >> + GPIO_Y63, >> + GPIO_Y64, >> + GPIO_Y65, >> + GPIO_Y66, >> + GPIO_Y67, >> + RES = GPIO_Y67 + (0x3 * GPIO_PER_BANK), > > What is happening here? > > Have you checked that the values are correct? To me it looks like > GPIO_C40 will be set to RES + 1, but it should be set to GPIO_Y67 + 1 > I think. As per the User manual there is a gap between these base adresses hence had to add a difference variable. > >> + GPIO_C40, >> + GPIO_C41, >> + GPIO_C42, >> + GPIO_C43, >> + GPIO_C44, >> + GPIO_C45, >> + GPIO_C46, >> + GPIO_C47, >> + RES1 = GPIO_C47 + (0x48 * GPIO_PER_BANK), >> + GPIO_X00, >> + GPIO_X01, >> + GPIO_X02, >> + GPIO_X03, >> + GPIO_X04, >> + GPIO_X05, >> + GPIO_X06, >> + GPIO_X07, >> + GPIO_X10, >> + GPIO_X11, >> + GPIO_X12, >> + GPIO_X13, >> + GPIO_X14, >> + GPIO_X15, >> + GPIO_X16, >> + GPIO_X17, >> + GPIO_X20, >> + GPIO_X21, >> + GPIO_X22, >> + GPIO_X23, >> + GPIO_X24, >> + GPIO_X25, >> + GPIO_X26, >> + GPIO_X27, >> + GPIO_X30, >> + GPIO_X31, >> + GPIO_X32, >> + GPIO_X33, >> + GPIO_X34, >> + GPIO_X35, >> + GPIO_X36, >> + GPIO_X37, >> + >> + /* GPIO_PART2_STARTS */ >> + GPIO_PART1_MAX, >> + GPIO_E00 = GPIO_PART1_MAX, >> + GPIO_E01, >> + GPIO_E02, >> + GPIO_E03, >> + GPIO_E04, >> + GPIO_E05, >> + GPIO_E06, >> + GPIO_E07, >> + GPIO_E10, >> + GPIO_E11, >> + GPIO_E12, >> + GPIO_E13, >> + GPIO_E14, >> + GPIO_E15, >> + GPIO_E16, >> + GPIO_E17, >> + GPIO_F00, >> + GPIO_F01, >> + GPIO_F02, >> + GPIO_F03, >> + GPIO_F04, >> + GPIO_F05, >> + GPIO_F06, >> + GPIO_F07, >> + GPIO_F10, >> + GPIO_F11, >> + GPIO_F12, >> + GPIO_F13, >> + GPIO_F14, >> + GPIO_F15, >> + GPIO_F16, >> + GPIO_F17, >> + GPIO_G00, >> + GPIO_G01, >> + GPIO_G02, >> + GPIO_G03, >> + GPIO_G04, >> + GPIO_G05, >> + GPIO_G06, >> + GPIO_G07, >> + GPIO_G10, >> + GPIO_G11, >> + GPIO_G12, >> + GPIO_G13, >> + GPIO_G14, >> + GPIO_G15, >> + GPIO_G16, >> + GPIO_G17, >> + GPIO_G20, >> + GPIO_G21, >> + GPIO_G22, >> + GPIO_G23, >> + GPIO_G24, >> + GPIO_G25, >> + GPIO_G26, >> + GPIO_G27, >> + GPIO_H00, >> + GPIO_H01, >> + GPIO_H02, >> + GPIO_H03, >> + GPIO_H04, >> + GPIO_H05, >> + GPIO_H06, >> + GPIO_H07, >> + GPIO_H10, >> + GPIO_H11, >> + GPIO_H12, >> + GPIO_H13, >> + GPIO_H14, >> + GPIO_H15, >> + GPIO_H16, >> + GPIO_H17, >> + >> + /* GPIO_PART3_STARTS */ >> + GPIO_PART2_MAX, >> + GPIO_V00 = GPIO_PART2_MAX, >> + GPIO_V01, >> + GPIO_V02, >> + GPIO_V03, >> + GPIO_V04, >> + GPIO_V05, >> + GPIO_V06, >> + GPIO_V07, >> + GPIO_V10, >> + GPIO_V11, >> + GPIO_V12, >> + GPIO_V13, >> + GPIO_V14, >> + GPIO_V15, >> + GPIO_V16, >> + GPIO_V17, >> + RES3 = GPIO_V17 + GPIO_PER_BANK, >> + GPIO_V20, >> + GPIO_V21, >> + GPIO_V22, >> + GPIO_V23, >> + GPIO_V24, >> + GPIO_V25, >> + GPIO_V26, >> + GPIO_V27, >> + GPIO_V30, >> + GPIO_V31, >> + GPIO_V32, >> + GPIO_V33, >> + GPIO_V34, >> + GPIO_V35, >> + GPIO_V36, >> + GPIO_V37, >> + RES4 = GPIO_V37 + GPIO_PER_BANK, >> + GPIO_V40, >> + GPIO_V41, >> + GPIO_V42, >> + GPIO_V43, >> + GPIO_V44, >> + GPIO_V45, >> + GPIO_V46, >> + GPIO_V47, >> + >> + /* GPIO_PART4_STARTS */ >> + GPIO_PART3_MAX, >> + GPIO_Z0 = GPIO_PART3_MAX, >> + GPIO_Z1, >> + GPIO_Z2, >> + GPIO_Z3, >> + GPIO_Z4, >> + GPIO_Z5, >> + GPIO_Z6, >> + GPIO_MAX_PORT >> +}; >> + >> static inline unsigned int s5p_gpio_base(int nr) >> { >> if (cpu_is_exynos5()) { >> - if (nr < EXYNOS5_GPIO_PART1_MAX) >> + if (nr < GPIO_PART1_MAX) >> return EXYNOS5_GPIO_PART1_BASE; >> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >> + else if (nr < GPIO_PART2_MAX) >> return EXYNOS5_GPIO_PART2_BASE; >> - else >> + else if (nr < GPIO_PART3_MAX) >> return EXYNOS5_GPIO_PART3_BASE; >> + else >> + return EXYNOS5_GPIO_PART4_BASE; >> >> } else if (cpu_is_exynos4()) { >> if (nr < EXYNOS4_GPIO_PART1_MAX) >> @@ -295,12 +635,14 @@ static inline unsigned int s5p_gpio_base(int nr) >> static inline unsigned int s5p_gpio_part_max(int nr) >> { >> if (cpu_is_exynos5()) { >> - if (nr < EXYNOS5_GPIO_PART1_MAX) >> + if (nr < GPIO_PART1_MAX) >> return 0; >> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >> - return EXYNOS5_GPIO_PART1_MAX; >> + else if (nr < GPIO_PART2_MAX) >> + return GPIO_PART1_MAX; >> + else if (nr < GPIO_PART3_MAX) >> + return GPIO_PART2_MAX; >> else >> - return EXYNOS5_GPIO_PART2_MAX; >> + return GPIO_PART3_MAX; >> >> } else if (cpu_is_exynos4()) { >> if (nr < EXYNOS4_GPIO_PART1_MAX) >> @@ -311,6 +653,10 @@ static inline unsigned int s5p_gpio_part_max(int nr) >> >> return 0; >> } >> + >> +void gpio_cfg_pin(int gpio, int cfg); >> +void gpio_set_pull(int gpio, int mode); >> +void gpio_set_drv(int gpio, int mode); > > You set these in the header file but provide no definition, nor any > enums/defines for the cfg and mode parameters. > >> #endif >> >> /* Pin configurations */ >> -- >> 1.7.4.4 >> > > Regards, > Simon > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot -- Regards, Rajeshwari Shinde ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature 2013-02-18 12:10 ` Rajeshwari Birje @ 2013-02-21 20:53 ` Simon Glass 0 siblings, 0 replies; 13+ messages in thread From: Simon Glass @ 2013-02-21 20:53 UTC (permalink / raw) To: u-boot Hi Rajeshwari, On Mon, Feb 18, 2013 at 4:10 AM, Rajeshwari Birje <rajeshwari.birje@gmail.com> wrote: > Hi Simon, > > Thank you for comments. > > On Sun, Feb 17, 2013 at 11:51 AM, Simon Glass <sjg@chromium.org> wrote: >> Hi Rajeshwari, >> >> On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde >> <rajeshwari.s@samsung.com> wrote: >>> This patch adds support for gpio pin numbering support on EXYNOS5 >>> pinmux. >>> >>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> >>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >> >> If we are going to have GPIO numbering it needs to be continuous. The >> scheme in the Chrome OS tree does this. > -Okay >> >> It's great to have gpio_cfg_pin() but I can't see the actual definition. > The definition for same is in "S5P: GPIO: Add generic pin numbering API's" > patch of same patch set. >> >> Also please carefully check that the GPIO numbers are all correct - it >> doesn't look right to me. > I had verified for each value. Will recheck the same. >> >> Also for the benefit of people using FDT who still don't have symbols >> and who don't yet have proper GPIO support in U-Boot (phandle to bank >> + number within bank, as in the kernel), can you please annotate the >> first enum value of each GPIO group (A, B, C) with its hex value? That >> will also provide a check that things are correct. > So you want me to assign each bank GPIO group with its Base adress in hex? No, just add a comment with the GPIO number that each bank happens to fall on. See the Chromium tree for what we did there in the exynos5 gpio.h file. It just helps to follow what is going on. >> > One more doubt as per Minkyu comment to support the same for EXYNOS4 > and avoid error do we have to append EXYNOS5_ at the start of enum > values? Or anyother solution you would suggest? I don't think it is needed. GPIO_... should be enough. After all we are only building for one or the other - we will not at present include both header files. Regards, Simon >> Regards, >> Simon >> >>> --- >>> Changes in V2: >>> - none. >>> Changes in V3: >>> - none. >>> arch/arm/cpu/armv7/exynos/pinmux.c | 148 +++++-------- >>> arch/arm/include/asm/arch-exynos/gpio.h | 360 ++++++++++++++++++++++++++++++- >>> 2 files changed, 413 insertions(+), 95 deletions(-) >>> >>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c >>> index bd499b4..c79d58e 100644 >>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c >>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c >>> @@ -29,89 +29,77 @@ >>> >>> static void exynos5_uart_config(int peripheral) >>> { >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> - struct s5p_gpio_bank *bank; >>> int i, start, count; >>> >>> switch (peripheral) { >>> case PERIPH_ID_UART0: >>> - bank = &gpio1->a0; >>> - start = 0; >>> + start = GPIO_A00; >>> count = 4; >>> break; >>> case PERIPH_ID_UART1: >>> - bank = &gpio1->d0; >>> - start = 0; >>> + start = GPIO_D00; >>> count = 4; >>> break; >>> case PERIPH_ID_UART2: >>> - bank = &gpio1->a1; >>> - start = 0; >>> + start = GPIO_A10; >>> count = 4; >>> break; >>> case PERIPH_ID_UART3: >>> - bank = &gpio1->a1; >>> - start = 4; >>> + start = GPIO_A14; >>> count = 2; >>> break; >>> } >>> for (i = start; i < start + count; i++) { >>> - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >>> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >>> + gpio_set_pull(i, GPIO_PULL_NONE); >>> + gpio_cfg_pin(i, GPIO_FUNC(0x2)); >>> } >>> } >>> >>> static int exynos5_mmc_config(int peripheral, int flags) >>> { >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> - struct s5p_gpio_bank *bank, *bank_ext; >>> - int i, start = 0, gpio_func = 0; >>> + int i, start, start_ext, gpio_func = 0; >>> >>> switch (peripheral) { >>> case PERIPH_ID_SDMMC0: >>> - bank = &gpio1->c0; >>> - bank_ext = &gpio1->c1; >>> - start = 0; >>> + start = GPIO_C00; >>> + start_ext = GPIO_C10; >>> gpio_func = GPIO_FUNC(0x2); >>> break; >>> case PERIPH_ID_SDMMC1: >>> - bank = &gpio1->c2; >>> - bank_ext = NULL; >>> + start = GPIO_C20; >>> + start_ext = 0; >>> break; >>> case PERIPH_ID_SDMMC2: >>> - bank = &gpio1->c3; >>> - bank_ext = &gpio1->c4; >>> - start = 3; >>> + start = GPIO_C30; >>> + start_ext = GPIO_C43; >>> gpio_func = GPIO_FUNC(0x3); >>> break; >>> case PERIPH_ID_SDMMC3: >>> - bank = &gpio1->c4; >>> - bank_ext = NULL; >>> + start = GPIO_C40; >>> + start_ext = 0; >>> break; >>> } >>> - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { >>> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { >>> debug("SDMMC device %d does not support 8bit mode", >>> peripheral); >>> return -1; >>> } >>> if (flags & PINMUX_FLAG_8BIT_MODE) { >>> - for (i = start; i <= (start + 3); i++) { >>> - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); >>> - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); >>> - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); >>> + for (i = start_ext; i <= (start_ext + 3); i++) { >>> + gpio_cfg_pin(i, gpio_func); >>> + gpio_set_pull(i, GPIO_PULL_UP); >>> + gpio_set_drv(i, GPIO_DRV_4X); >>> } >>> } >>> for (i = 0; i < 2; i++) { >>> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >>> - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >>> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >>> + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); >>> + gpio_set_pull(start + i, GPIO_PULL_NONE); >>> + gpio_set_drv(start + i, GPIO_DRV_4X); >>> } >>> for (i = 3; i <= 6; i++) { >>> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >>> - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); >>> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >>> + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); >>> + gpio_set_pull(start + i, GPIO_PULL_UP); >>> + gpio_set_drv(start + i, GPIO_DRV_4X); >>> } >>> >>> return 0; >>> @@ -119,8 +107,6 @@ static int exynos5_mmc_config(int peripheral, int flags) >>> >>> static void exynos5_sromc_config(int flags) >>> { >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> int i; >>> >>> /* >>> @@ -138,13 +124,13 @@ static void exynos5_sromc_config(int flags) >>> * GPY1[2] SROM_WAIT(2) >>> * GPY1[3] EBI_DATA_RDn(2) >>> */ >>> - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), >>> + gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), >>> GPIO_FUNC(2)); >>> - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); >>> - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); >>> + gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); >>> + gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); >>> >>> for (i = 0; i < 4; i++) >>> - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); >>> + gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); >>> >>> /* >>> * EBI: 8 Addrss Lines >>> @@ -179,55 +165,52 @@ static void exynos5_sromc_config(int flags) >>> * GPY6[7] EBI_DATA[15](2) >>> */ >>> for (i = 0; i < 8; i++) { >>> - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); >>> - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); >>> + gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); >>> + gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); >>> >>> - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); >>> - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); >>> + gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); >>> + gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); >>> >>> - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); >>> - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); >>> + gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); >>> + gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); >>> } >>> } >>> >>> static void exynos5_i2c_config(int peripheral, int flags) >>> { >>> >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> - >>> switch (peripheral) { >>> case PERIPH_ID_I2C0: >>> - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); >>> - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); >>> + gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); >>> + gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); >>> break; >>> case PERIPH_ID_I2C1: >>> - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); >>> - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); >>> + gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); >>> + gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); >>> break; >>> case PERIPH_ID_I2C2: >>> - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); >>> - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); >>> break; >>> case PERIPH_ID_I2C3: >>> - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); >>> - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); >>> break; >>> case PERIPH_ID_I2C4: >>> - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); >>> - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); >>> break; >>> case PERIPH_ID_I2C5: >>> - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); >>> - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); >>> break; >>> case PERIPH_ID_I2C6: >>> - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); >>> - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); >>> + gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); >>> + gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); >>> break; >>> case PERIPH_ID_I2C7: >>> - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); >>> - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); >>> + gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); >>> break; >>> } >>> } >>> @@ -235,53 +218,42 @@ static void exynos5_i2c_config(int peripheral, int flags) >>> static void exynos5_i2s_config(int peripheral) >>> { >>> int i; >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> >>> for (i = 0; i < 5; i++) >>> - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); >>> + gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); >>> } >>> >>> void exynos5_spi_config(int peripheral) >>> { >>> int cfg = 0, pin = 0, i; >>> - struct s5p_gpio_bank *bank = NULL; >>> - struct exynos5_gpio_part1 *gpio1 = >>> - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); >>> - struct exynos5_gpio_part2 *gpio2 = >>> - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); >>> >>> switch (peripheral) { >>> case PERIPH_ID_SPI0: >>> - bank = &gpio1->a2; >>> cfg = GPIO_FUNC(0x2); >>> - pin = 0; >>> + pin = GPIO_A20; >>> break; >>> case PERIPH_ID_SPI1: >>> - bank = &gpio1->a2; >>> cfg = GPIO_FUNC(0x2); >>> - pin = 4; >>> + pin = GPIO_A24; >>> break; >>> case PERIPH_ID_SPI2: >>> - bank = &gpio1->b1; >>> cfg = GPIO_FUNC(0x5); >>> - pin = 1; >>> + pin = GPIO_B11; >>> break; >>> case PERIPH_ID_SPI3: >>> - bank = &gpio2->f1; >>> cfg = GPIO_FUNC(0x2); >>> - pin = 0; >>> + pin = GPIO_F10; >>> break; >>> case PERIPH_ID_SPI4: >>> for (i = 0; i < 2; i++) { >>> - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); >>> - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); >>> + gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); >>> + gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); >>> } >>> break; >>> } >>> if (peripheral != PERIPH_ID_SPI4) { >>> for (i = pin; i < pin + 4; i++) >>> - s5p_gpio_cfg_pin(bank, i, cfg); >>> + gpio_cfg_pin(i, cfg); >>> } >>> } >>> >>> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h >>> index cfe1024..af882dd 100644 >>> --- a/arch/arm/include/asm/arch-exynos/gpio.h >>> +++ b/arch/arm/include/asm/arch-exynos/gpio.h >>> @@ -272,15 +272,355 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); >>> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ >>> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) >>> >>> +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ >>> +enum exynos5_gpio_pin { >>> + /* GPIO_PART1_STARTS */ >>> + GPIO_A00, >>> + GPIO_A01, >>> + GPIO_A02, >>> + GPIO_A03, >>> + GPIO_A04, >>> + GPIO_A05, >>> + GPIO_A06, >>> + GPIO_A07, >>> + GPIO_A10, >>> + GPIO_A11, >>> + GPIO_A12, >>> + GPIO_A13, >>> + GPIO_A14, >>> + GPIO_A15, >>> + GPIO_A16, >>> + GPIO_A17, >>> + GPIO_A20, >>> + GPIO_A21, >>> + GPIO_A22, >>> + GPIO_A23, >>> + GPIO_A24, >>> + GPIO_A25, >>> + GPIO_A26, >>> + GPIO_A27, >>> + GPIO_B00, >>> + GPIO_B01, >>> + GPIO_B02, >>> + GPIO_B03, >>> + GPIO_B04, >>> + GPIO_B05, >>> + GPIO_B06, >>> + GPIO_B07, >>> + GPIO_B10, >>> + GPIO_B11, >>> + GPIO_B12, >>> + GPIO_B13, >>> + GPIO_B14, >>> + GPIO_B15, >>> + GPIO_B16, >>> + GPIO_B17, >>> + GPIO_B20, >>> + GPIO_B21, >>> + GPIO_B22, >>> + GPIO_B23, >>> + GPIO_B24, >>> + GPIO_B25, >>> + GPIO_B26, >>> + GPIO_B27, >>> + GPIO_B30, >>> + GPIO_B31, >>> + GPIO_B32, >>> + GPIO_B33, >>> + GPIO_B34, >>> + GPIO_B35, >>> + GPIO_B36, >>> + GPIO_B37, >>> + GPIO_C00, >>> + GPIO_C01, >>> + GPIO_C02, >>> + GPIO_C03, >>> + GPIO_C04, >>> + GPIO_C05, >>> + GPIO_C06, >>> + GPIO_C07, >>> + GPIO_C10, >>> + GPIO_C11, >>> + GPIO_C12, >>> + GPIO_C13, >>> + GPIO_C14, >>> + GPIO_C15, >>> + GPIO_C16, >>> + GPIO_C17, >>> + GPIO_C20, >>> + GPIO_C21, >>> + GPIO_C22, >>> + GPIO_C23, >>> + GPIO_C24, >>> + GPIO_C25, >>> + GPIO_C26, >>> + GPIO_C27, >>> + GPIO_C30, >>> + GPIO_C31, >>> + GPIO_C32, >>> + GPIO_C33, >>> + GPIO_C34, >>> + GPIO_C35, >>> + GPIO_C36, >>> + GPIO_C37, >>> + GPIO_D00, >>> + GPIO_D01, >>> + GPIO_D02, >>> + GPIO_D03, >>> + GPIO_D04, >>> + GPIO_D05, >>> + GPIO_D06, >>> + GPIO_D07, >>> + GPIO_D10, >>> + GPIO_D11, >>> + GPIO_D12, >>> + GPIO_D13, >>> + GPIO_D14, >>> + GPIO_D15, >>> + GPIO_D16, >>> + GPIO_D17, >>> + GPIO_Y00, >>> + GPIO_Y01, >>> + GPIO_Y02, >>> + GPIO_Y03, >>> + GPIO_Y04, >>> + GPIO_Y05, >>> + GPIO_Y06, >>> + GPIO_Y07, >>> + GPIO_Y10, >>> + GPIO_Y11, >>> + GPIO_Y12, >>> + GPIO_Y13, >>> + GPIO_Y14, >>> + GPIO_Y15, >>> + GPIO_Y16, >>> + GPIO_Y17, >>> + GPIO_Y20, >>> + GPIO_Y21, >>> + GPIO_Y22, >>> + GPIO_Y23, >>> + GPIO_Y24, >>> + GPIO_Y25, >>> + GPIO_Y26, >>> + GPIO_Y27, >>> + GPIO_Y30, >>> + GPIO_Y31, >>> + GPIO_Y32, >>> + GPIO_Y33, >>> + GPIO_Y34, >>> + GPIO_Y35, >>> + GPIO_Y36, >>> + GPIO_Y37, >>> + GPIO_Y40, >>> + GPIO_Y41, >>> + GPIO_Y42, >>> + GPIO_Y43, >>> + GPIO_Y44, >>> + GPIO_Y45, >>> + GPIO_Y46, >>> + GPIO_Y47, >>> + GPIO_Y50, >>> + GPIO_Y51, >>> + GPIO_Y52, >>> + GPIO_Y53, >>> + GPIO_Y54, >>> + GPIO_Y55, >>> + GPIO_Y56, >>> + GPIO_Y57, >>> + GPIO_Y60, >>> + GPIO_Y61, >>> + GPIO_Y62, >>> + GPIO_Y63, >>> + GPIO_Y64, >>> + GPIO_Y65, >>> + GPIO_Y66, >>> + GPIO_Y67, >>> + RES = GPIO_Y67 + (0x3 * GPIO_PER_BANK), >> >> What is happening here? >> >> Have you checked that the values are correct? To me it looks like >> GPIO_C40 will be set to RES + 1, but it should be set to GPIO_Y67 + 1 >> I think. > As per the User manual there is a gap between these base adresses > hence had to add a difference variable. Yes, but that is a chip feature. It is irrelevant to the API you present. Your GPIO numbering in U-Boot should start at 0 and header up to n-1, where n is the number of available GPIOs. There should be no gaps - they serve no perpose to those using your code, and actually make things harder. Again this is implemented in the Chromium tree. Thanks for your efforts on this. Regards, Simon >> >>> + GPIO_C40, >>> + GPIO_C41, >>> + GPIO_C42, >>> + GPIO_C43, >>> + GPIO_C44, >>> + GPIO_C45, >>> + GPIO_C46, >>> + GPIO_C47, >>> + RES1 = GPIO_C47 + (0x48 * GPIO_PER_BANK), >>> + GPIO_X00, >>> + GPIO_X01, >>> + GPIO_X02, >>> + GPIO_X03, >>> + GPIO_X04, >>> + GPIO_X05, >>> + GPIO_X06, >>> + GPIO_X07, >>> + GPIO_X10, >>> + GPIO_X11, >>> + GPIO_X12, >>> + GPIO_X13, >>> + GPIO_X14, >>> + GPIO_X15, >>> + GPIO_X16, >>> + GPIO_X17, >>> + GPIO_X20, >>> + GPIO_X21, >>> + GPIO_X22, >>> + GPIO_X23, >>> + GPIO_X24, >>> + GPIO_X25, >>> + GPIO_X26, >>> + GPIO_X27, >>> + GPIO_X30, >>> + GPIO_X31, >>> + GPIO_X32, >>> + GPIO_X33, >>> + GPIO_X34, >>> + GPIO_X35, >>> + GPIO_X36, >>> + GPIO_X37, >>> + >>> + /* GPIO_PART2_STARTS */ >>> + GPIO_PART1_MAX, >>> + GPIO_E00 = GPIO_PART1_MAX, >>> + GPIO_E01, >>> + GPIO_E02, >>> + GPIO_E03, >>> + GPIO_E04, >>> + GPIO_E05, >>> + GPIO_E06, >>> + GPIO_E07, >>> + GPIO_E10, >>> + GPIO_E11, >>> + GPIO_E12, >>> + GPIO_E13, >>> + GPIO_E14, >>> + GPIO_E15, >>> + GPIO_E16, >>> + GPIO_E17, >>> + GPIO_F00, >>> + GPIO_F01, >>> + GPIO_F02, >>> + GPIO_F03, >>> + GPIO_F04, >>> + GPIO_F05, >>> + GPIO_F06, >>> + GPIO_F07, >>> + GPIO_F10, >>> + GPIO_F11, >>> + GPIO_F12, >>> + GPIO_F13, >>> + GPIO_F14, >>> + GPIO_F15, >>> + GPIO_F16, >>> + GPIO_F17, >>> + GPIO_G00, >>> + GPIO_G01, >>> + GPIO_G02, >>> + GPIO_G03, >>> + GPIO_G04, >>> + GPIO_G05, >>> + GPIO_G06, >>> + GPIO_G07, >>> + GPIO_G10, >>> + GPIO_G11, >>> + GPIO_G12, >>> + GPIO_G13, >>> + GPIO_G14, >>> + GPIO_G15, >>> + GPIO_G16, >>> + GPIO_G17, >>> + GPIO_G20, >>> + GPIO_G21, >>> + GPIO_G22, >>> + GPIO_G23, >>> + GPIO_G24, >>> + GPIO_G25, >>> + GPIO_G26, >>> + GPIO_G27, >>> + GPIO_H00, >>> + GPIO_H01, >>> + GPIO_H02, >>> + GPIO_H03, >>> + GPIO_H04, >>> + GPIO_H05, >>> + GPIO_H06, >>> + GPIO_H07, >>> + GPIO_H10, >>> + GPIO_H11, >>> + GPIO_H12, >>> + GPIO_H13, >>> + GPIO_H14, >>> + GPIO_H15, >>> + GPIO_H16, >>> + GPIO_H17, >>> + >>> + /* GPIO_PART3_STARTS */ >>> + GPIO_PART2_MAX, >>> + GPIO_V00 = GPIO_PART2_MAX, >>> + GPIO_V01, >>> + GPIO_V02, >>> + GPIO_V03, >>> + GPIO_V04, >>> + GPIO_V05, >>> + GPIO_V06, >>> + GPIO_V07, >>> + GPIO_V10, >>> + GPIO_V11, >>> + GPIO_V12, >>> + GPIO_V13, >>> + GPIO_V14, >>> + GPIO_V15, >>> + GPIO_V16, >>> + GPIO_V17, >>> + RES3 = GPIO_V17 + GPIO_PER_BANK, >>> + GPIO_V20, >>> + GPIO_V21, >>> + GPIO_V22, >>> + GPIO_V23, >>> + GPIO_V24, >>> + GPIO_V25, >>> + GPIO_V26, >>> + GPIO_V27, >>> + GPIO_V30, >>> + GPIO_V31, >>> + GPIO_V32, >>> + GPIO_V33, >>> + GPIO_V34, >>> + GPIO_V35, >>> + GPIO_V36, >>> + GPIO_V37, >>> + RES4 = GPIO_V37 + GPIO_PER_BANK, >>> + GPIO_V40, >>> + GPIO_V41, >>> + GPIO_V42, >>> + GPIO_V43, >>> + GPIO_V44, >>> + GPIO_V45, >>> + GPIO_V46, >>> + GPIO_V47, >>> + >>> + /* GPIO_PART4_STARTS */ >>> + GPIO_PART3_MAX, >>> + GPIO_Z0 = GPIO_PART3_MAX, >>> + GPIO_Z1, >>> + GPIO_Z2, >>> + GPIO_Z3, >>> + GPIO_Z4, >>> + GPIO_Z5, >>> + GPIO_Z6, >>> + GPIO_MAX_PORT >>> +}; >>> + >>> static inline unsigned int s5p_gpio_base(int nr) >>> { >>> if (cpu_is_exynos5()) { >>> - if (nr < EXYNOS5_GPIO_PART1_MAX) >>> + if (nr < GPIO_PART1_MAX) >>> return EXYNOS5_GPIO_PART1_BASE; >>> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >>> + else if (nr < GPIO_PART2_MAX) >>> return EXYNOS5_GPIO_PART2_BASE; >>> - else >>> + else if (nr < GPIO_PART3_MAX) >>> return EXYNOS5_GPIO_PART3_BASE; >>> + else >>> + return EXYNOS5_GPIO_PART4_BASE; >>> >>> } else if (cpu_is_exynos4()) { >>> if (nr < EXYNOS4_GPIO_PART1_MAX) >>> @@ -295,12 +635,14 @@ static inline unsigned int s5p_gpio_base(int nr) >>> static inline unsigned int s5p_gpio_part_max(int nr) >>> { >>> if (cpu_is_exynos5()) { >>> - if (nr < EXYNOS5_GPIO_PART1_MAX) >>> + if (nr < GPIO_PART1_MAX) >>> return 0; >>> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >>> - return EXYNOS5_GPIO_PART1_MAX; >>> + else if (nr < GPIO_PART2_MAX) >>> + return GPIO_PART1_MAX; >>> + else if (nr < GPIO_PART3_MAX) >>> + return GPIO_PART2_MAX; >>> else >>> - return EXYNOS5_GPIO_PART2_MAX; >>> + return GPIO_PART3_MAX; >>> >>> } else if (cpu_is_exynos4()) { >>> if (nr < EXYNOS4_GPIO_PART1_MAX) >>> @@ -311,6 +653,10 @@ static inline unsigned int s5p_gpio_part_max(int nr) >>> >>> return 0; >>> } >>> + >>> +void gpio_cfg_pin(int gpio, int cfg); >>> +void gpio_set_pull(int gpio, int mode); >>> +void gpio_set_drv(int gpio, int mode); >> >> You set these in the header file but provide no definition, nor any >> enums/defines for the cfg and mode parameters. >> >>> #endif >>> >>> /* Pin configurations */ >>> -- >>> 1.7.4.4 >>> >> >> Regards, >> Simon >> _______________________________________________ >> U-Boot mailing list >> U-Boot at lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot > > > > -- > Regards, > Rajeshwari Shinde ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions 2013-02-07 12:00 [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature Rajeshwari Shinde 2013-02-07 12:00 ` [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's Rajeshwari Shinde 2013-02-07 12:00 ` [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature Rajeshwari Shinde @ 2013-02-07 12:00 ` Rajeshwari Shinde 2013-02-08 16:04 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 Rajeshwari Shinde 3 siblings, 1 reply; 13+ messages in thread From: Rajeshwari Shinde @ 2013-02-07 12:00 UTC (permalink / raw) To: u-boot This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... This changes was done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, trats, smdkc100, smdkv310 config files. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- Chnages in V3: - New Patch arch/arm/cpu/armv7/exynos/pinmux.c | 134 +++++++++++++++--------------- arch/arm/include/asm/arch-exynos/gpio.h | 26 +++--- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +++--- board/samsung/goni/goni.c | 4 +- board/samsung/origen/origen.c | 8 +- board/samsung/smdk5250/smdk5250.c | 8 +- board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 10 +- board/samsung/trats/trats.c | 16 ++-- board/samsung/universal_c210/universal.c | 36 ++++---- drivers/gpio/s5p_gpio.c | 20 ++-- 11 files changed, 145 insertions(+), 145 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index c79d58e..28b0306 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -50,8 +50,8 @@ static void exynos5_uart_config(int peripheral) break; } for (i = start; i < start + count; i++) { - gpio_set_pull(i, GPIO_PULL_NONE); - gpio_cfg_pin(i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } @@ -63,7 +63,7 @@ static int exynos5_mmc_config(int peripheral, int flags) case PERIPH_ID_SDMMC0: start = GPIO_C00; start_ext = GPIO_C10; - gpio_func = GPIO_FUNC(0x2); + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: start = GPIO_C20; @@ -72,7 +72,7 @@ static int exynos5_mmc_config(int peripheral, int flags) case PERIPH_ID_SDMMC2: start = GPIO_C30; start_ext = GPIO_C43; - gpio_func = GPIO_FUNC(0x3); + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: start = GPIO_C40; @@ -87,19 +87,19 @@ static int exynos5_mmc_config(int peripheral, int flags) if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = start_ext; i <= (start_ext + 3); i++) { gpio_cfg_pin(i, gpio_func); - gpio_set_pull(i, GPIO_PULL_UP); - gpio_set_drv(i, GPIO_DRV_4X); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } for (i = 0; i < 2; i++) { - gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); - gpio_set_pull(start + i, GPIO_PULL_NONE); - gpio_set_drv(start + i, GPIO_DRV_4X); + gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(start + i, S5P_GPIO_PULL_NONE); + gpio_set_drv(start + i, S5P_GPIO_DRV_4X); } for (i = 3; i <= 6; i++) { - gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); - gpio_set_pull(start + i, GPIO_PULL_UP); - gpio_set_drv(start + i, GPIO_DRV_4X); + gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(start + i, S5P_GPIO_PULL_UP); + gpio_set_drv(start + i, S5P_GPIO_DRV_4X); } return 0; @@ -125,12 +125,12 @@ static void exynos5_sromc_config(int flags) * GPY1[3] EBI_DATA_RDn(2) */ gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); + gpio_cfg_pin(GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -165,14 +165,14 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y30 + i, S5P_GPIO_PULL_UP); - gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y50 + i, S5P_GPIO_PULL_UP); - gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); + gpio_cfg_pin(GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } @@ -181,36 +181,36 @@ static void exynos5_i2c_config(int peripheral, int flags) switch (peripheral) { case PERIPH_ID_I2C0: - gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(GPIO_B23, S5P_GPIO_FUNC(0x3)); break; } } @@ -220,7 +220,7 @@ static void exynos5_i2s_config(int peripheral) int i; for (i = 0; i < 5; i++) - gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); + gpio_cfg_pin(GPIO_B00+i, S5P_GPIO_FUNC(0x02)); } void exynos5_spi_config(int peripheral) @@ -229,25 +229,25 @@ void exynos5_spi_config(int peripheral) switch (peripheral) { case PERIPH_ID_SPI0: - cfg = GPIO_FUNC(0x2); + cfg = S5P_GPIO_FUNC(0x2); pin = GPIO_A20; break; case PERIPH_ID_SPI1: - cfg = GPIO_FUNC(0x2); + cfg = S5P_GPIO_FUNC(0x2); pin = GPIO_A24; break; case PERIPH_ID_SPI2: - cfg = GPIO_FUNC(0x5); + cfg = S5P_GPIO_FUNC(0x5); pin = GPIO_B11; break; case PERIPH_ID_SPI3: - cfg = GPIO_FUNC(0x2); + cfg = S5P_GPIO_FUNC(0x2); pin = GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } @@ -309,36 +309,36 @@ static void exynos4_i2c_config(int peripheral, int flags) switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 0, S5P_GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 1, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 2, S5P_GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 3, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 6, S5P_GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 2, S5P_GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 2, S5P_GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 6, S5P_GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 3, S5P_GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 4, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 2, S5P_GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 3, S5P_GPIO_FUNC(0x3)); break; } } @@ -365,15 +365,15 @@ static int exynos4_mmc_config(int peripheral, int flags) for (i = 0; i < 7; i++) { if (i == 2) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_cfg_pin(bank, i, S5P_GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + s5p_gpio_cfg_pin(bank_ext, i, S5P_GPIO_FUNC(0x3)); + s5p_gpio_set_pull(bank_ext, i, S5P_GPIO_PULL_NONE); + s5p_gpio_set_drv(bank_ext, i, S5P_GPIO_DRV_4X); } } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index af882dd..38b959d 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -660,21 +660,21 @@ void gpio_set_drv(int gpio, int mode); #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x3 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 00e498d..e0605a2 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -155,22 +155,22 @@ static inline unsigned int s5p_gpio_part_max(int nr) #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x2 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index ff76963..daa0faa 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -102,9 +102,9 @@ int board_mmc_init(bd_t *bis) /* GPG0[0:6] special function 2 */ s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&s5pc110_gpio->g0, i, S5P_GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&s5pc110_gpio->g0, i, S5P_GPIO_DRV_4X); } return s5p_mmc_init(0, 4); diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 638e7b1..1c82ac6 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -88,19 +88,19 @@ int board_mmc_init(bd_t *bis) */ for (i = 0; i < 7; i++) { /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X); /* GPK2[0:1] pull disable */ if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 6f2e067..61cac1c 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -64,7 +64,7 @@ static void board_enable_audio_codec(void) /* Enable MAX98095 Codec */ s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->x1, 7, S5P_GPIO_PULL_NONE); } #endif @@ -412,15 +412,15 @@ void cfg_lcd_gpio(void) (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); + s5p_gpio_cfg_pin(&gpio1->b2, 0, S5P_GPIO_OUTPUT); s5p_gpio_set_value(&gpio1->b2, 0, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); + s5p_gpio_cfg_pin(&gpio1->x1, 5, S5P_GPIO_OUTPUT); s5p_gpio_set_value(&gpio1->x1, 5, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->x0, 7, S5P_GPIO_FUNC(0x3)); } vidinfo_t panel_info = { diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index c41e610..87a8f5a 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -41,7 +41,7 @@ static void smc9115_pre_init(void) (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 81ac8f6..24e8f18 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -37,7 +37,7 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -119,19 +119,19 @@ int board_mmc_init(bd_t *bis) */ for (i = 0; i < 7; i++) { /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X); /* GPK2[0:1] pull disable */ if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 88d193d..13f4930 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -390,8 +390,8 @@ static unsigned int get_hw_revision(void) /* hw_rev[3:0] == GPE1[3:0] */ for (i = 0; i < 4; i++) { - s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(&gpio->e1, i, S5P_GPIO_INPUT); + s5p_gpio_set_pull(&gpio->e1, i, S5P_GPIO_PULL_NONE); } udelay(1); @@ -430,7 +430,7 @@ int board_mmc_init(bd_t *bis) /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio->k0, 2, 1); - s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio->k0, 2, S5P_GPIO_PULL_NONE); /* * MMC device init @@ -445,7 +445,7 @@ int board_mmc_init(bd_t *bis) /* T-flash detect */ s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio->x3, 4, S5P_GPIO_PULL_UP); /* * Check the T-flash detect pin @@ -522,7 +522,7 @@ static void pmic_reset(void) (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); s5p_gpio_direction_output(&gpio->x0, 7, 1); - s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio->x2, 7, S5P_GPIO_PULL_NONE); } static void board_clock_init(void) @@ -614,12 +614,12 @@ static void board_uart_init(void) */ for (i = 0; i < 4; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); + s5p_gpio_set_pull(&gpio1->a1, i, S5P_GPIO_PULL_NONE); + s5p_gpio_cfg_pin(&gpio1->a1, i, S5P_GPIO_FUNC((i > 1) ? 0x3 : 0x2)); } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->y4, 7, S5P_GPIO_PULL_UP); s5p_gpio_direction_output(&gpio2->y4, 7, 1); } diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index e742707..6ade3f2 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -216,7 +216,7 @@ int board_mmc_init(bd_t *bis) /* T-flash detect */ s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->x3, 4, S5P_GPIO_PULL_UP); /* * Check the T-flash detect pin @@ -390,35 +390,35 @@ static void lcd_cfg_gpio(void) for (i = 0; i < 8; i++) { /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f0, i, S5P_GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f1, i, S5P_GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f2, i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f0, i, S5P_GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f1, i, S5P_GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f2, i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + s5p_gpio_set_drv(&gpio1->f0, i, S5P_GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW); + s5p_gpio_set_drv(&gpio1->f1, i, S5P_GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f1, i, S5P_GPIO_DRV_SLOW); + s5p_gpio_set_drv(&gpio1->f2, i, S5P_GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW); } for (i = 0; i < f3_end; i++) { /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f3, i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f3, i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); + + s5p_gpio_set_rate(&gpio1->f3, i, S5P_GPIO_DRV_SLOW); } /* gpio pad configuration for LCD reset. */ - s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); + s5p_gpio_cfg_pin(&gpio2->y4, 5, S5P_GPIO_OUTPUT); spi_init(); } diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index a53bdca..1c8c774 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -50,7 +50,7 @@ void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; - s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT); value = readl(&bank->dat); value &= ~DAT_MASK(gpio); @@ -61,7 +61,7 @@ void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) { - s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT); + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT); } void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) @@ -91,8 +91,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~PULL_MASK(gpio); switch (mode) { - case GPIO_PULL_DOWN: - case GPIO_PULL_UP: + case S5P_GPIO_PULL_DOWN: + case S5P_GPIO_PULL_UP: value |= PULL_MODE(gpio, mode); break; default: @@ -110,10 +110,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~DRV_MASK(gpio); switch (mode) { - case GPIO_DRV_1X: - case GPIO_DRV_2X: - case GPIO_DRV_3X: - case GPIO_DRV_4X: + case S5P_GPIO_DRV_1X: + case S5P_GPIO_DRV_2X: + case S5P_GPIO_DRV_3X: + case S5P_GPIO_DRV_4X: value |= DRV_SET(gpio, mode); break; default: @@ -131,8 +131,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~RATE_MASK(gpio); switch (mode) { - case GPIO_DRV_FAST: - case GPIO_DRV_SLOW: + case S5P_GPIO_DRV_FAST: + case S5P_GPIO_DRV_SLOW: value |= RATE_SET(gpio); break; default: -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions 2013-02-07 12:00 ` [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions Rajeshwari Shinde @ 2013-02-08 16:04 ` Simon Glass 0 siblings, 0 replies; 13+ messages in thread From: Simon Glass @ 2013-02-08 16:04 UTC (permalink / raw) To: u-boot Hi Rajeshwari, On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote: > This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... > This changes was done to enable cmd_gpio for EXYNOS and > cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence > getting a error during compilation. > > Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, > trats, smdkc100, smdkv310 config files. > > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> This looks right to me. It would be useful to standardise the GPIO functions a little more - so for example we could have a generic gpio_set_pull() which calls the Samsung one, a little like the generic GPIO calls today. That API would go in asm-generic/gpio.h. However I'm not sure how far we can standardise this - pullup/pulldown probably, but I'm not sure about driver strength and slew rate. > --- > Chnages in V3: > - New Patch > arch/arm/cpu/armv7/exynos/pinmux.c | 134 +++++++++++++++--------------- > arch/arm/include/asm/arch-exynos/gpio.h | 26 +++--- > arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +++--- > board/samsung/goni/goni.c | 4 +- > board/samsung/origen/origen.c | 8 +- > board/samsung/smdk5250/smdk5250.c | 8 +- > board/samsung/smdkc100/smdkc100.c | 2 +- > board/samsung/smdkv310/smdkv310.c | 10 +- > board/samsung/trats/trats.c | 16 ++-- > board/samsung/universal_c210/universal.c | 36 ++++---- > drivers/gpio/s5p_gpio.c | 20 ++-- > 11 files changed, 145 insertions(+), 145 deletions(-) > Regards, Simon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 2013-02-07 12:00 [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature Rajeshwari Shinde ` (2 preceding siblings ...) 2013-02-07 12:00 ` [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions Rajeshwari Shinde @ 2013-02-07 12:00 ` Rajeshwari Shinde 2013-02-08 4:31 ` Minkyu Kang 2013-02-08 16:08 ` Simon Glass 3 siblings, 2 replies; 13+ messages in thread From: Rajeshwari Shinde @ 2013-02-07 12:00 UTC (permalink / raw) To: u-boot This patch enables GPIO Command for EXYNOS5. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. example: gpio set gpa00 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- Changes in V2: - New patch Changes in V3: - Created a table to know the base address of input bank. arch/arm/cpu/armv7/exynos/pinmux.c | 50 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/gpio.h | 8 +++++ include/configs/exynos5250-dt.h | 1 + 3 files changed, 59 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 28b0306..a01ce0c 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -27,6 +27,21 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> +struct gpio_name_num_table exynos5_gpio_table[] = { + { 'a', GPIO_A00 }, + { 'b', GPIO_B00 }, + { 'c', GPIO_C00 }, + { 'd', GPIO_D00 }, + { 'y', GPIO_Y00 }, + { 'x', GPIO_X00 }, + { 'e', GPIO_E00 }, + { 'f', GPIO_F00 }, + { 'g', GPIO_G00 }, + { 'h', GPIO_H00 }, + { 'v', GPIO_V00 }, + { 'z', GPIO_Z0 }, +}; + static void exynos5_uart_config(int peripheral) { int i, start, count; @@ -448,3 +463,38 @@ int pinmux_decode_periph_id(const void *blob, int node) return PERIPH_ID_NONE; } #endif + +int name_to_gpio(const char *name) +{ + unsigned int num, i; + + name++; + + if (*name == 'p') + ++name; + + for (i = 0; i < ARRAY_SIZE(exynos5_gpio_table); i++) { + if (*name == exynos5_gpio_table[i].bank) { + if (*name == 'c') { + name++; + num = simple_strtoul(name, NULL, 10); + if (num >= 40) { + num = GPIO_C40 + (num - 40); + } else { + num = simple_strtoul(name, NULL, 8); + num = exynos5_gpio_table[i].base + num; + } + } else { + name++; + num = simple_strtoul(name, NULL, 8); + num = exynos5_gpio_table[i].base + num; + } + break; + } + } + + if (i == ARRAY_SIZE(exynos5_gpio_table)) + return -1; + + return num; +} diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 38b959d..016a112 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -657,6 +657,14 @@ static inline unsigned int s5p_gpio_part_max(int nr) void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); + +struct gpio_name_num_table { + char bank; + unsigned int base; +}; + +int name_to_gpio(const char *name); +#define name_to_gpio(n) name_to_gpio(n) #endif /* Pin configurations */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index b1b24a9..a32cc3e 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -113,6 +113,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_GPIO #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 2013-02-07 12:00 ` [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 Rajeshwari Shinde @ 2013-02-08 4:31 ` Minkyu Kang 2013-02-08 16:08 ` Simon Glass 1 sibling, 0 replies; 13+ messages in thread From: Minkyu Kang @ 2013-02-08 4:31 UTC (permalink / raw) To: u-boot Dear Rajeshwari, On 07/02/13 21:00, Rajeshwari Shinde wrote: > This patch enables GPIO Command for EXYNOS5. > Function has been added to asm/gpio.h to decode the > input gpio name to gpio number. > example: gpio set gpa00 > > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > --- > Changes in V2: > - New patch > Changes in V3: > - Created a table to know the base address of input bank. > arch/arm/cpu/armv7/exynos/pinmux.c | 50 +++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-exynos/gpio.h | 8 +++++ > include/configs/exynos5250-dt.h | 1 + > 3 files changed, 59 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c > index 28b0306..a01ce0c 100644 > --- a/arch/arm/cpu/armv7/exynos/pinmux.c > +++ b/arch/arm/cpu/armv7/exynos/pinmux.c > @@ -27,6 +27,21 @@ > #include <asm/arch/pinmux.h> > #include <asm/arch/sromc.h> > > +struct gpio_name_num_table exynos5_gpio_table[] = { > + { 'a', GPIO_A00 }, > + { 'b', GPIO_B00 }, > + { 'c', GPIO_C00 }, > + { 'd', GPIO_D00 }, > + { 'y', GPIO_Y00 }, > + { 'x', GPIO_X00 }, > + { 'e', GPIO_E00 }, > + { 'f', GPIO_F00 }, > + { 'g', GPIO_G00 }, > + { 'h', GPIO_H00 }, > + { 'v', GPIO_V00 }, > + { 'z', GPIO_Z0 }, > +}; > + > static void exynos5_uart_config(int peripheral) > { > int i, start, count; > @@ -448,3 +463,38 @@ int pinmux_decode_periph_id(const void *blob, int node) > return PERIPH_ID_NONE; > } > #endif > + > +int name_to_gpio(const char *name) This function should be support exynos4 also. > +{ > + unsigned int num, i; > + > + name++; Please check NULL pointer before you use it. And I think you should check length of name. "name++" seems to dangerous. How about parse the string to bank and number before you use? > + > + if (*name == 'p') > + ++name; else? is not error? > + > + for (i = 0; i < ARRAY_SIZE(exynos5_gpio_table); i++) { > + if (*name == exynos5_gpio_table[i].bank) { > + if (*name == 'c') { > + name++; > + num = simple_strtoul(name, NULL, 10); > + if (num >= 40) { > + num = GPIO_C40 + (num - 40); > + } else { > + num = simple_strtoul(name, NULL, 8); > + num = exynos5_gpio_table[i].base + num; > + } > + } else { > + name++; > + num = simple_strtoul(name, NULL, 8); > + num = exynos5_gpio_table[i].base + num; > + } > + break; return num; > + } > + } return -1; > + > + if (i == ARRAY_SIZE(exynos5_gpio_table)) > + return -1; > + > + return num; > +} > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h > index 38b959d..016a112 100644 > --- a/arch/arm/include/asm/arch-exynos/gpio.h > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > @@ -657,6 +657,14 @@ static inline unsigned int s5p_gpio_part_max(int nr) > void gpio_cfg_pin(int gpio, int cfg); > void gpio_set_pull(int gpio, int mode); > void gpio_set_drv(int gpio, int mode); > + > +struct gpio_name_num_table { > + char bank; > + unsigned int base; > +}; > + > +int name_to_gpio(const char *name); > +#define name_to_gpio(n) name_to_gpio(n) > #endif > > /* Pin configurations */ > diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h > index b1b24a9..a32cc3e 100644 > --- a/include/configs/exynos5250-dt.h > +++ b/include/configs/exynos5250-dt.h > @@ -113,6 +113,7 @@ > #define CONFIG_CMD_EXT2 > #define CONFIG_CMD_FAT > #define CONFIG_CMD_NET > +#define CONFIG_CMD_GPIO > > #define CONFIG_BOOTDELAY 3 > #define CONFIG_ZERO_BOOTDELAY_CHECK > Thanks. Minkyu Kang. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 2013-02-07 12:00 ` [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 Rajeshwari Shinde 2013-02-08 4:31 ` Minkyu Kang @ 2013-02-08 16:08 ` Simon Glass 1 sibling, 0 replies; 13+ messages in thread From: Simon Glass @ 2013-02-08 16:08 UTC (permalink / raw) To: u-boot Hi Rajeshwari, On Thu, Feb 7, 2013 at 4:00 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote: > This patch enables GPIO Command for EXYNOS5. > Function has been added to asm/gpio.h to decode the > input gpio name to gpio number. > example: gpio set gpa00 > > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > --- > Changes in V2: > - New patch > Changes in V3: > - Created a table to know the base address of input bank. > arch/arm/cpu/armv7/exynos/pinmux.c | 50 +++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-exynos/gpio.h | 8 +++++ > include/configs/exynos5250-dt.h | 1 + > 3 files changed, 59 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c > index 28b0306..a01ce0c 100644 > --- a/arch/arm/cpu/armv7/exynos/pinmux.c > +++ b/arch/arm/cpu/armv7/exynos/pinmux.c > @@ -27,6 +27,21 @@ > #include <asm/arch/pinmux.h> > #include <asm/arch/sromc.h> > > +struct gpio_name_num_table exynos5_gpio_table[] = { > + { 'a', GPIO_A00 }, > + { 'b', GPIO_B00 }, > + { 'c', GPIO_C00 }, > + { 'd', GPIO_D00 }, > + { 'y', GPIO_Y00 }, > + { 'x', GPIO_X00 }, > + { 'e', GPIO_E00 }, > + { 'f', GPIO_F00 }, > + { 'g', GPIO_G00 }, > + { 'h', GPIO_H00 }, > + { 'v', GPIO_V00 }, > + { 'z', GPIO_Z0 }, > +}; > + > static void exynos5_uart_config(int peripheral) > { > int i, start, count; > @@ -448,3 +463,38 @@ int pinmux_decode_periph_id(const void *blob, int node) > return PERIPH_ID_NONE; > } > #endif > + > +int name_to_gpio(const char *name) > +{ > + unsigned int num, i; > + Perhaps check name is at least 3 chars here? > + name++; > + > + if (*name == 'p') > + ++name; > + > + for (i = 0; i < ARRAY_SIZE(exynos5_gpio_table); i++) { > + if (*name == exynos5_gpio_table[i].bank) { > + if (*name == 'c') { > + name++; > + num = simple_strtoul(name, NULL, 10); > + if (num >= 40) { > + num = GPIO_C40 + (num - 40); > + } else { > + num = simple_strtoul(name, NULL, 8); > + num = exynos5_gpio_table[i].base + num; Here can you somehow check that the number is valid. For example we want 'a99' to give an error. Maybe your table needs to hold the number of GPIOs that each letter has. Then you can return -1 on error. > + } > + } else { > + name++; > + num = simple_strtoul(name, NULL, 8); > + num = exynos5_gpio_table[i].base + num; > + } > + break; > + } > + } > + > + if (i == ARRAY_SIZE(exynos5_gpio_table)) > + return -1; > + > + return num; > +} > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h > index 38b959d..016a112 100644 > --- a/arch/arm/include/asm/arch-exynos/gpio.h > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > @@ -657,6 +657,14 @@ static inline unsigned int s5p_gpio_part_max(int nr) > void gpio_cfg_pin(int gpio, int cfg); > void gpio_set_pull(int gpio, int mode); > void gpio_set_drv(int gpio, int mode); > + > +struct gpio_name_num_table { > + char bank; > + unsigned int base; add comment: this is the starting GPIO number of this bank: e.g. GPIO_A00 > +}; > + > +int name_to_gpio(const char *name); > +#define name_to_gpio(n) name_to_gpio(n) What does this #define do? > #endif > > /* Pin configurations */ > diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h > index b1b24a9..a32cc3e 100644 > --- a/include/configs/exynos5250-dt.h > +++ b/include/configs/exynos5250-dt.h > @@ -113,6 +113,7 @@ > #define CONFIG_CMD_EXT2 > #define CONFIG_CMD_FAT > #define CONFIG_CMD_NET > +#define CONFIG_CMD_GPIO > > #define CONFIG_BOOTDELAY 3 > #define CONFIG_ZERO_BOOTDELAY_CHECK > -- > 1.7.4.4 > Regards, Simon ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2013-02-21 20:53 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-02-07 12:00 [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature Rajeshwari Shinde 2013-02-07 12:00 ` [U-Boot] [PATCH 1/4 V3] S5P: GPIO: Add generic pin numbering API's Rajeshwari Shinde 2013-02-08 16:11 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 2/4 V3] EXYNOS5: Add gpio pin numbering feature Rajeshwari Shinde 2013-02-08 3:57 ` Minkyu Kang 2013-02-17 6:21 ` Simon Glass 2013-02-18 12:10 ` Rajeshwari Birje 2013-02-21 20:53 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 3/4 V3] S5P: Rename GPIO definitions Rajeshwari Shinde 2013-02-08 16:04 ` Simon Glass 2013-02-07 12:00 ` [U-Boot] [PATCH 4/4 V3] EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 Rajeshwari Shinde 2013-02-08 4:31 ` Minkyu Kang 2013-02-08 16:08 ` Simon Glass
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