[PATCH] drm/amdgpu/gfx8: add additional MQD initialization

[PATCH] drm/amdgpu/gfx8: add additional MQD initialization

[Alex Deucher]

Need to properly set the MTYPE and ROQ space setting.
This should fix performance regressions with KIQ enabled.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7adeab3..11ca155 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4855,6 +4855,20 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
 	mqd->cp_hqd_persistent_state = tmp;
 
+	/* set MTYPE */
+	tmp = RREG32(mmCP_HQD_IB_CONTROL);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
+	mqd->cp_hqd_ib_control = tmp;
+
+	tmp = RREG32(mmCP_HQD_IQ_TIMER);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
+	mqd->cp_hqd_iq_timer = tmp;
+
+	tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
+	mqd->cp_hqd_ctx_save_control = tmp;
+
 	/* activate the queue */
 	mqd->cp_hqd_active = 1;
 
-- 
2.5.5

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Re: [PATCH] drm/amdgpu/gfx8: add additional MQD initialization

[Christian König]

Am 08.04.2017 um 00:00 schrieb Alex Deucher:
> Need to properly set the MTYPE and ROQ space setting.
> This should fix performance regressions with KIQ enabled.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 7adeab3..11ca155 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4855,6 +4855,20 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
>   	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
>   	mqd->cp_hqd_persistent_state = tmp;
>   
> +	/* set MTYPE */
> +	tmp = RREG32(mmCP_HQD_IB_CONTROL);
> +	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> +	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
> +	mqd->cp_hqd_ib_control = tmp;
> +
> +	tmp = RREG32(mmCP_HQD_IQ_TIMER);
> +	tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
> +	mqd->cp_hqd_iq_timer = tmp;
> +
> +	tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
> +	tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
> +	mqd->cp_hqd_ctx_save_control = tmp;
> +
>   	/* activate the queue */
>   	mqd->cp_hqd_active = 1;
>   


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