* [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This series converts the Tegra device tree files to use the new feature
of running cpp over .dts files before compiling them with dtc. This
allows GPIOs and other GPIO/IRQ specifier cells to be named for example.
As far as merging goes, I'd anticipate the first 3 patches being useful
to any other ARM sub-arch that wants to convert; perhaps they could go
through some arm-soc common branch. The next 2 patches are Tegra-specific
cleanup that I'd anticipate applying to Tegra's for-3.10/cleanup. The
rest of the patches depend on those 5 previous patches, so would need to
go into a Tegra branch that merges in the previous patches; I'd anticipate
calling it for-3.10/dtc-cpp say.
One issue this raises: The first 2 patches aren't ARM-specific. I put the
files they create into arch/arm/boot/dts, but I wonder if they wouldn't be
better in some arch-agnostic include directory, or even right with the
binding documentation in Documentation/devicetree/bindings. Moving the
files would require adjusting the cpp include path.
Stephen Warren (9):
ARM: dt: add header to define GPIO flags
ARM: dt: add header to define IRQ flags
ARM: dt: create a DT header for the GIC
ARM: tegra: device tree whitespace cleanup
ARM: tegra: fix sort order of USB PHY nodes
ARM: tegra: use pre-processor for all device trees
ARM: tegra: create a DT header defining GPIO IDs
ARM: tegra: convert device tree files to use GPIO defines
ARM: tegra: convert device tree files to use IRQ defines
arch/arm/boot/dts/arm-gic.h | 17 +
arch/arm/boot/dts/gpio.h | 10 +
arch/arm/boot/dts/irq.h | 14 +
arch/arm/boot/dts/tegra-gpio.h | 45 ++
arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
arch/arm/boot/dts/tegra114-pluto.dts | 21 -
arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
arch/arm/boot/dts/tegra114.dtsi | 153 -----
arch/arm/boot/dts/tegra114.dtsip | 161 ++++++
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 495 ++++++++++++++++
arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
arch/arm/boot/dts/tegra20-harmony.dtsp | 666 ++++++++++++++++++++++
arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
arch/arm/boot/dts/tegra20-paz00.dtsp | 509 +++++++++++++++++
arch/arm/boot/dts/tegra20-plutux.dts | 56 --
arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
arch/arm/boot/dts/tegra20-seaboard.dts | 812 --------------------------
arch/arm/boot/dts/tegra20-seaboard.dtsp | 815 +++++++++++++++++++++++++++
arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
arch/arm/boot/dts/tegra20-tamonten.dtsip | 490 ++++++++++++++++
arch/arm/boot/dts/tegra20-tec.dts | 56 --
arch/arm/boot/dts/tegra20-tec.dtsp | 57 ++
arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
arch/arm/boot/dts/tegra20-trimslice.dtsp | 370 ++++++++++++
arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
arch/arm/boot/dts/tegra20-ventana.dtsp | 616 ++++++++++++++++++++
arch/arm/boot/dts/tegra20-whistler.dts | 563 ------------------
arch/arm/boot/dts/tegra20-whistler.dtsp | 564 ++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
arch/arm/boot/dts/tegra20.dtsip | 559 ++++++++++++++++++
arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 ----------------
arch/arm/boot/dts/tegra30-cardhu.dtsip | 501 ++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
arch/arm/boot/dts/tegra30.dtsip | 582 +++++++++++++++++++
46 files changed, 7286 insertions(+), 7157 deletions(-)
create mode 100644 arch/arm/boot/dts/arm-gic.h
create mode 100644 arch/arm/boot/dts/gpio.h
create mode 100644 arch/arm/boot/dts/irq.h
create mode 100644 arch/arm/boot/dts/tegra-gpio.h
delete mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
create mode 100644 arch/arm/boot/dts/tegra114-pluto.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114.dtsi
create mode 100644 arch/arm/boot/dts/tegra114.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-harmony.dts
create mode 100644 arch/arm/boot/dts/tegra20-harmony.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts
create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts
create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-paz00.dts
create mode 100644 arch/arm/boot/dts/tegra20-paz00.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-plutux.dts
create mode 100644 arch/arm/boot/dts/tegra20-plutux.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-seaboard.dts
create mode 100644 arch/arm/boot/dts/tegra20-seaboard.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-tec.dts
create mode 100644 arch/arm/boot/dts/tegra20-tec.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-trimslice.dts
create mode 100644 arch/arm/boot/dts/tegra20-trimslice.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-ventana.dts
create mode 100644 arch/arm/boot/dts/tegra20-ventana.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-whistler.dts
create mode 100644 arch/arm/boot/dts/tegra20-whistler.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20.dtsi
create mode 100644 arch/arm/boot/dts/tegra20.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30-beaver.dts
create mode 100644 arch/arm/boot/dts/tegra30-beaver.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30.dtsi
create mode 100644 arch/arm/boot/dts/tegra30.dtsip
--
1.7.10.4
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
This series converts the Tegra device tree files to use the new feature
of running cpp over .dts files before compiling them with dtc. This
allows GPIOs and other GPIO/IRQ specifier cells to be named for example.
As far as merging goes, I'd anticipate the first 3 patches being useful
to any other ARM sub-arch that wants to convert; perhaps they could go
through some arm-soc common branch. The next 2 patches are Tegra-specific
cleanup that I'd anticipate applying to Tegra's for-3.10/cleanup. The
rest of the patches depend on those 5 previous patches, so would need to
go into a Tegra branch that merges in the previous patches; I'd anticipate
calling it for-3.10/dtc-cpp say.
One issue this raises: The first 2 patches aren't ARM-specific. I put the
files they create into arch/arm/boot/dts, but I wonder if they wouldn't be
better in some arch-agnostic include directory, or even right with the
binding documentation in Documentation/devicetree/bindings. Moving the
files would require adjusting the cpp include path.
Stephen Warren (9):
ARM: dt: add header to define GPIO flags
ARM: dt: add header to define IRQ flags
ARM: dt: create a DT header for the GIC
ARM: tegra: device tree whitespace cleanup
ARM: tegra: fix sort order of USB PHY nodes
ARM: tegra: use pre-processor for all device trees
ARM: tegra: create a DT header defining GPIO IDs
ARM: tegra: convert device tree files to use GPIO defines
ARM: tegra: convert device tree files to use IRQ defines
arch/arm/boot/dts/arm-gic.h | 17 +
arch/arm/boot/dts/gpio.h | 10 +
arch/arm/boot/dts/irq.h | 14 +
arch/arm/boot/dts/tegra-gpio.h | 45 ++
arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
arch/arm/boot/dts/tegra114-pluto.dts | 21 -
arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
arch/arm/boot/dts/tegra114.dtsi | 153 -----
arch/arm/boot/dts/tegra114.dtsip | 161 ++++++
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 495 ++++++++++++++++
arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
arch/arm/boot/dts/tegra20-harmony.dtsp | 666 ++++++++++++++++++++++
arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
arch/arm/boot/dts/tegra20-paz00.dtsp | 509 +++++++++++++++++
arch/arm/boot/dts/tegra20-plutux.dts | 56 --
arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
arch/arm/boot/dts/tegra20-seaboard.dts | 812 --------------------------
arch/arm/boot/dts/tegra20-seaboard.dtsp | 815 +++++++++++++++++++++++++++
arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
arch/arm/boot/dts/tegra20-tamonten.dtsip | 490 ++++++++++++++++
arch/arm/boot/dts/tegra20-tec.dts | 56 --
arch/arm/boot/dts/tegra20-tec.dtsp | 57 ++
arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
arch/arm/boot/dts/tegra20-trimslice.dtsp | 370 ++++++++++++
arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
arch/arm/boot/dts/tegra20-ventana.dtsp | 616 ++++++++++++++++++++
arch/arm/boot/dts/tegra20-whistler.dts | 563 ------------------
arch/arm/boot/dts/tegra20-whistler.dtsp | 564 ++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
arch/arm/boot/dts/tegra20.dtsip | 559 ++++++++++++++++++
arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 ----------------
arch/arm/boot/dts/tegra30-cardhu.dtsip | 501 ++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
arch/arm/boot/dts/tegra30.dtsip | 582 +++++++++++++++++++
46 files changed, 7286 insertions(+), 7157 deletions(-)
create mode 100644 arch/arm/boot/dts/arm-gic.h
create mode 100644 arch/arm/boot/dts/gpio.h
create mode 100644 arch/arm/boot/dts/irq.h
create mode 100644 arch/arm/boot/dts/tegra-gpio.h
delete mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
create mode 100644 arch/arm/boot/dts/tegra114-pluto.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114.dtsi
create mode 100644 arch/arm/boot/dts/tegra114.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-harmony.dts
create mode 100644 arch/arm/boot/dts/tegra20-harmony.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts
create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts
create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-paz00.dts
create mode 100644 arch/arm/boot/dts/tegra20-paz00.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-plutux.dts
create mode 100644 arch/arm/boot/dts/tegra20-plutux.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-seaboard.dts
create mode 100644 arch/arm/boot/dts/tegra20-seaboard.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-tec.dts
create mode 100644 arch/arm/boot/dts/tegra20-tec.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-trimslice.dts
create mode 100644 arch/arm/boot/dts/tegra20-trimslice.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-ventana.dts
create mode 100644 arch/arm/boot/dts/tegra20-ventana.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-whistler.dts
create mode 100644 arch/arm/boot/dts/tegra20-whistler.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20.dtsi
create mode 100644 arch/arm/boot/dts/tegra20.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30-beaver.dts
create mode 100644 arch/arm/boot/dts/tegra30-beaver.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30.dtsi
create mode 100644 arch/arm/boot/dts/tegra30.dtsip
--
1.7.10.4
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Many GPIO device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/gpio.h | 10 ++++++++++
1 file changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/gpio.h
diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
new file mode 100644
index 0000000..4c9da69
--- /dev/null
+++ b/arch/arm/boot/dts/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Many GPIO device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/gpio.h | 10 ++++++++++
1 file changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/gpio.h
diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
new file mode 100644
index 0000000..4c9da69
--- /dev/null
+++ b/arch/arm/boot/dts/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 2/9] ARM: dt: add header to define IRQ flags
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Many IRQ device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/irq.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/irq.h
diff --git a/arch/arm/boot/dts/irq.h b/arch/arm/boot/dts/irq.h
new file mode 100644
index 0000000..165d039
--- /dev/null
+++ b/arch/arm/boot/dts/irq.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 2/9] ARM: dt: add header to define IRQ flags
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Many IRQ device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/irq.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/irq.h
diff --git a/arch/arm/boot/dts/irq.h b/arch/arm/boot/dts/irq.h
new file mode 100644
index 0000000..165d039
--- /dev/null
+++ b/arch/arm/boot/dts/irq.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 3/9] ARM: dt: create a DT header for the GIC
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The ARM GIC binding defines a few custom cells and flags for its IRQ
specifier. Provide names for those.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/arm-gic.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 arch/arm/boot/dts/arm-gic.h
diff --git a/arch/arm/boot/dts/arm-gic.h b/arch/arm/boot/dts/arm-gic.h
new file mode 100644
index 0000000..5b1bc85
--- /dev/null
+++ b/arch/arm/boot/dts/arm-gic.h
@@ -0,0 +1,17 @@
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#include "irq.h"
+
+/* interrupt specific cell 0 */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+/*
+ * Interrupt specifier cell 2.
+ * The flaggs in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 3/9] ARM: dt: create a DT header for the GIC
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
The ARM GIC binding defines a few custom cells and flags for its IRQ
specifier. Provide names for those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/arm-gic.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 arch/arm/boot/dts/arm-gic.h
diff --git a/arch/arm/boot/dts/arm-gic.h b/arch/arm/boot/dts/arm-gic.h
new file mode 100644
index 0000000..5b1bc85
--- /dev/null
+++ b/arch/arm/boot/dts/arm-gic.h
@@ -0,0 +1,17 @@
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#include "irq.h"
+
+/* interrupt specific cell 0 */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+/*
+ * Interrupt specifier cell 2.
+ * The flaggs in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 4/9] ARM: tegra: device tree whitespace cleanup
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Remove white-space from empty line; triggers checkpatch.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index cdb8da0..f3c7681 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,7 +207,7 @@
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
-
+
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 4/9] ARM: tegra: device tree whitespace cleanup
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Remove white-space from empty line; triggers checkpatch.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index cdb8da0..f3c7681 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,7 +207,7 @@
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
-
+
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5/9] ARM: tegra: fix sort order of USB PHY nodes
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The USB PHY nodes are all grouped together rather than being sorted based
on reg address like all other nodes fix this.
I apologize for the churn; I should have noticed this during review of the
patches that caused this.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra20.dtsi | 50 ++++++++++++++++++++--------------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3c7681..5916c93 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -442,31 +442,6 @@
#size-cells = <0>;
};
- phy1: usb-phy@c5000400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5000400 0x3c00>;
- phy_type = "utmi";
- nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- phy2: usb-phy@c5004400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5004400 0x3c00>;
- phy_type = "ulpi";
- clocks = <&tegra_car 94>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- phy3: usb-phy@c5008400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5008400 0x3C00>;
- phy_type = "utmi";
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
@@ -479,6 +454,15 @@
status = "disabled";
};
+ phy1: usb-phy@c5000400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5000400 0x3c00>;
+ phy_type = "utmi";
+ nvidia,has-legacy-mode;
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
@@ -489,6 +473,14 @@
status = "disabled";
};
+ phy2: usb-phy@c5004400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5004400 0x3c00>;
+ phy_type = "ulpi";
+ clocks = <&tegra_car 94>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
@@ -499,6 +491,14 @@
status = "disabled";
};
+ phy3: usb-phy@c5008400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5008400 0x3c00>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5/9] ARM: tegra: fix sort order of USB PHY nodes
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
The USB PHY nodes are all grouped together rather than being sorted based
on reg address like all other nodes fix this.
I apologize for the churn; I should have noticed this during review of the
patches that caused this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra20.dtsi | 50 ++++++++++++++++++++--------------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3c7681..5916c93 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -442,31 +442,6 @@
#size-cells = <0>;
};
- phy1: usb-phy at c5000400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5000400 0x3c00>;
- phy_type = "utmi";
- nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- phy2: usb-phy at c5004400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5004400 0x3c00>;
- phy_type = "ulpi";
- clocks = <&tegra_car 94>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- phy3: usb-phy at c5008400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5008400 0x3C00>;
- phy_type = "utmi";
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
usb at c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
@@ -479,6 +454,15 @@
status = "disabled";
};
+ phy1: usb-phy at c5000400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5000400 0x3c00>;
+ phy_type = "utmi";
+ nvidia,has-legacy-mode;
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
usb at c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
@@ -489,6 +473,14 @@
status = "disabled";
};
+ phy2: usb-phy at c5004400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5004400 0x3c00>;
+ phy_type = "ulpi";
+ clocks = <&tegra_car 94>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
usb at c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
@@ -499,6 +491,14 @@
status = "disabled";
};
+ phy3: usb-phy at c5008400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5008400 0x3c00>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
sdhci at c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
[not found] ` <1360791198-29462-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
` (4 preceding siblings ...)
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
[not found] ` <1360791198-29462-7-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-13 21:33 ` Stephen Warren
` (5 subsequent siblings)
11 siblings, 1 reply; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This enables a C pre-processor pass on all Tegra device trees. This
allows future use of #defines and header files in order to define names
for various constants, such as the IDs and flags in GPIO specifiers.
Use of those features will increase the readability of the device tree
files.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
arch/arm/boot/dts/tegra114-pluto.dts | 21 -
arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
arch/arm/boot/dts/tegra114.dtsi | 153 -----
arch/arm/boot/dts/tegra114.dtsip | 153 +++++
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 491 ++++++++++++++++
arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
arch/arm/boot/dts/tegra20-harmony.dtsp | 660 ++++++++++++++++++++++
arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
arch/arm/boot/dts/tegra20-paz00.dtsp | 505 +++++++++++++++++
arch/arm/boot/dts/tegra20-plutux.dts | 56 --
arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
arch/arm/boot/dts/tegra20-seaboard.dts | 812 ---------------------------
arch/arm/boot/dts/tegra20-seaboard.dtsp | 812 +++++++++++++++++++++++++++
arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
arch/arm/boot/dts/tegra20-tamonten.dtsip | 489 ++++++++++++++++
arch/arm/boot/dts/tegra20-tec.dts | 56 --
arch/arm/boot/dts/tegra20-tec.dtsp | 56 ++
arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
arch/arm/boot/dts/tegra20-trimslice.dtsp | 367 ++++++++++++
arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
arch/arm/boot/dts/tegra20-ventana.dtsp | 611 ++++++++++++++++++++
arch/arm/boot/dts/tegra20-whistler.dts | 563 -------------------
arch/arm/boot/dts/tegra20-whistler.dtsp | 563 +++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
arch/arm/boot/dts/tegra20.dtsip | 556 ++++++++++++++++++
arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 -----------------
arch/arm/boot/dts/tegra30-cardhu.dtsip | 500 +++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
arch/arm/boot/dts/tegra30.dtsip | 579 +++++++++++++++++++
42 files changed, 7157 insertions(+), 7157 deletions(-)
delete mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
create mode 100644 arch/arm/boot/dts/tegra114-pluto.dtsp
delete mode 100644 arch/arm/boot/dts/tegra114.dtsi
create mode 100644 arch/arm/boot/dts/tegra114.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-harmony.dts
create mode 100644 arch/arm/boot/dts/tegra20-harmony.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts
create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts
create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-paz00.dts
create mode 100644 arch/arm/boot/dts/tegra20-paz00.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-plutux.dts
create mode 100644 arch/arm/boot/dts/tegra20-plutux.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-seaboard.dts
create mode 100644 arch/arm/boot/dts/tegra20-seaboard.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsip
delete mode 100644 arch/arm/boot/dts/tegra20-tec.dts
create mode 100644 arch/arm/boot/dts/tegra20-tec.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-trimslice.dts
create mode 100644 arch/arm/boot/dts/tegra20-trimslice.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-ventana.dts
create mode 100644 arch/arm/boot/dts/tegra20-ventana.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20-whistler.dts
create mode 100644 arch/arm/boot/dts/tegra20-whistler.dtsp
delete mode 100644 arch/arm/boot/dts/tegra20.dtsi
create mode 100644 arch/arm/boot/dts/tegra20.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30-beaver.dts
create mode 100644 arch/arm/boot/dts/tegra30-beaver.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dts
create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
delete mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsip
delete mode 100644 arch/arm/boot/dts/tegra30.dtsi
create mode 100644 arch/arm/boot/dts/tegra30.dtsip
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
deleted file mode 100644
index a30aca6..0000000
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra114.dtsi"
-
-/ {
- model = "NVIDIA Tegra114 Dalmore evaluation board";
- compatible = "nvidia,dalmore", "nvidia,tegra114";
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- serial@70006300 {
- status = "okay";
- clock-frequency = <408000000>;
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dtsp b/arch/arm/boot/dts/tegra114-dalmore.dtsp
new file mode 100644
index 0000000..51f67cd
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-dalmore.dtsp
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "tegra114.dtsip"
+
+/ {
+ model = "NVIDIA Tegra114 Dalmore evaluation board";
+ compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ serial@70006300 {
+ status = "okay";
+ clock-frequency = <408000000>;
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
deleted file mode 100644
index 9bea8f5..0000000
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra114.dtsi"
-
-/ {
- model = "NVIDIA Tegra114 Pluto evaluation board";
- compatible = "nvidia,pluto", "nvidia,tegra114";
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- serial@70006300 {
- status = "okay";
- clock-frequency = <408000000>;
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dtsp b/arch/arm/boot/dts/tegra114-pluto.dtsp
new file mode 100644
index 0000000..40a88d1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-pluto.dtsp
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "tegra114.dtsip"
+
+/ {
+ model = "NVIDIA Tegra114 Pluto evaluation board";
+ compatible = "nvidia,pluto", "nvidia,tegra114";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ serial@70006300 {
+ status = "okay";
+ clock-frequency = <408000000>;
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
deleted file mode 100644
index 1dfaf28..0000000
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ /dev/null
@@ -1,153 +0,0 @@
-/include/ "skeleton.dtsi"
-
-/ {
- compatible = "nvidia,tegra114";
- interrupt-parent = <&gic>;
-
- gic: interrupt-controller {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x50041000 0x1000>,
- <0x50042000 0x1000>,
- <0x50044000 0x2000>,
- <0x50046000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- timer@60005000 {
- compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
- reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
- };
-
- tegra_car: clock {
- compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- };
-
- ahb: ahb {
- compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
- reg = <0x6000c004 0x14c>;
- };
-
- gpio: gpio {
- compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
- reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- pinmux: pinmux {
- compatible = "nvidia,tegra114-pinmux";
- reg = <0x70000868 0x148 /* Pad control registers */
- 0x70003000 0x40c>; /* Mux registers */
- };
-
- serial@70006000 {
- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
- reg = <0x70006000 0x40>;
- reg-shift = <2>;
- interrupts = <0 36 0x04>;
- status = "disabled";
- };
-
- serial@70006040 {
- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
- reg = <0x70006040 0x40>;
- reg-shift = <2>;
- interrupts = <0 37 0x04>;
- status = "disabled";
- };
-
- serial@70006200 {
- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
- reg = <0x70006200 0x100>;
- reg-shift = <2>;
- interrupts = <0 46 0x04>;
- status = "disabled";
- };
-
- serial@70006300 {
- compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
- reg = <0x70006300 0x100>;
- reg-shift = <2>;
- interrupts = <0 90 0x04>;
- status = "disabled";
- };
-
- rtc {
- compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
- };
-
- pmc {
- compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
- reg = <0x7000e400 0x400>;
- };
-
- iommu {
- compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
- reg = <0x7000f010 0x02c
- 0x7000f1f0 0x010
- 0x7000f228 0x074>;
- nvidia,#asids = <4>;
- dma-window = <0 0x40000000>;
- nvidia,swgroups = <0x18659fe>;
- nvidia,ahb = <&ahb>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <2>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <3>;
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
new file mode 100644
index 0000000..d2150f0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -0,0 +1,153 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra114";
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x50041000 0x1000>,
+ <0x50042000 0x1000>,
+ <0x50044000 0x2000>,
+ <0x50046000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04
+ 0 121 0x04
+ 0 122 0x04>;
+ };
+
+ tegra_car: clock {
+ compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ahb: ahb {
+ compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
+ reg = <0x6000c004 0x14c>;
+ };
+
+ gpio: gpio {
+ compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ pinmux: pinmux {
+ compatible = "nvidia,tegra114-pinmux";
+ reg = <0x70000868 0x148 /* Pad control registers */
+ 0x70003000 0x40c>; /* Mux registers */
+ };
+
+ serial@70006000 {
+ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = <0 36 0x04>;
+ status = "disabled";
+ };
+
+ serial@70006040 {
+ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+ reg = <0x70006040 0x40>;
+ reg-shift = <2>;
+ interrupts = <0 37 0x04>;
+ status = "disabled";
+ };
+
+ serial@70006200 {
+ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+ reg = <0x70006200 0x100>;
+ reg-shift = <2>;
+ interrupts = <0 46 0x04>;
+ status = "disabled";
+ };
+
+ serial@70006300 {
+ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+ reg = <0x70006300 0x100>;
+ reg-shift = <2>;
+ interrupts = <0 90 0x04>;
+ status = "disabled";
+ };
+
+ rtc {
+ compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ };
+
+ pmc {
+ compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+ reg = <0x7000e400 0x400>;
+ };
+
+ iommu {
+ compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
+ reg = <0x7000f010 0x02c
+ 0x7000f1f0 0x010
+ 0x7000f228 0x074>;
+ nvidia,#asids = <4>;
+ dma-window = <0 0x40000000>;
+ nvidia,swgroups = <0x18659fe>;
+ nvidia,ahb = <&ahb>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
deleted file mode 100644
index 4441620..0000000
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ /dev/null
@@ -1,491 +0,0 @@
-/include/ "tegra20.dtsi"
-
-/ {
- model = "Toradex Colibri T20 512MB";
- compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- host1x {
- hdmi {
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&i2c_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- audio_refclk {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- crt {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- displaya {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3",
- "ld4", "ld5", "ld6", "ld7", "ld8",
- "ld9", "ld10", "ld11", "ld12", "ld13",
- "ld14", "ld15", "ld16", "ld17",
- "lhs", "lpw0", "lpw2", "lsc0",
- "lsc1", "lsck", "lsda", "lspi", "lvs";
- nvidia,function = "displaya";
- nvidia,tristate = <1>;
- };
- gpio_dte {
- nvidia,pins = "dte";
- nvidia,function = "rsvd1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- gpio_gmi {
- nvidia,pins = "ata", "atc", "atd", "ate",
- "dap1", "dap2", "dap4", "gpu", "irrx",
- "irtx", "spia", "spib", "spic";
- nvidia,function = "gmi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- gpio_pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- gpio_uac {
- nvidia,pins = "uac";
- nvidia,function = "rsvd2";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- hdint {
- nvidia,pins = "hdint";
- nvidia,function = "hdmi";
- nvidia,tristate = <1>;
- };
- i2c1 {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- i2c3 {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- i2cddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- irda {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- nand {
- nvidia,pins = "kbca", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "nand";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- owc {
- nvidia,pins = "owc";
- nvidia,function = "owr";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- nvidia,tristate = <0>;
- };
- pwm {
- nvidia,pins = "sdb", "sdc", "sdd";
- nvidia,function = "pwm";
- nvidia,tristate = <1>;
- };
- sdio4 {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- spi1 {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- spi4 {
- nvidia,pins = "slxa", "slxc", "slxd", "slxk";
- nvidia,function = "spi4";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- uarta {
- nvidia,pins = "sdio1";
- nvidia,function = "uarta";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- uartd {
- nvidia,pins = "gmc";
- nvidia,function = "uartd";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- ulpi {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- ulpi_refclk {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- usb_gpio {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- vi {
- nvidia,pins = "dta", "dtb", "dtc", "dtd";
- nvidia,function = "vi";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- vi_sc {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- };
- };
-
- i2c@7000c000 {
- clock-frequency = <400000>;
- };
-
- i2c_ddc: i2c@7000c400 {
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- clock-frequency = <400000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <400000>;
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&vdd_5v0_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sys_reg: regulator@0 {
- reg = <0>;
- regulator-compatible = "sys";
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- regulator@1 {
- reg = <1>;
- regulator-compatible = "sm0";
- regulator-name = "vdd_sm0,vdd_core";
- regulator-min-microvolt = <1275000>;
- regulator-max-microvolt = <1275000>;
- regulator-always-on;
- };
-
- regulator@2 {
- reg = <2>;
- regulator-compatible = "sm1";
- regulator-name = "vdd_sm1,vdd_cpu";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sm2_reg: regulator@3 {
- reg = <3>;
- regulator-compatible = "sm2";
- regulator-name = "vdd_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- /* LDO0 is not connected to anything */
-
- regulator@5 {
- reg = <5>;
- regulator-compatible = "ldo1";
- regulator-name = "vdd_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- regulator@6 {
- reg = <6>;
- regulator-compatible = "ldo2";
- regulator-name = "vdd_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- /* LDO3 is not connected to anything */
-
- regulator@8 {
- reg = <8>;
- regulator-compatible = "ldo4";
- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5_reg: regulator@9 {
- reg = <9>;
- regulator-compatible = "ldo5";
- regulator-name = "vdd_ldo5,vdd_fuse";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- regulator@10 {
- reg = <10>;
- regulator-compatible = "ldo6";
- regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- hdmi_vdd_reg: regulator@11 {
- reg = <11>;
- regulator-compatible = "ldo7";
- regulator-name = "vdd_ldo7,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: regulator@12 {
- reg = <12>;
- regulator-compatible = "ldo8";
- regulator-name = "vdd_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- regulator@13 {
- reg = <13>;
- regulator-compatible = "ldo9";
- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- regulator@14 {
- reg = <14>;
- regulator-compatible = "ldo_rtc";
- regulator-name = "vdd_rtc_out,vdd_cell";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- temperature-sensor@4c {
- compatible = "national,lm95245";
- reg = <0x4c>;
- };
- };
-
- memory-controller@7000f400 {
- emc-table@83250 {
- reg = <83250>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <83250>;
- nvidia,emc-registers = <0x00000005 0x00000011
- 0x00000004 0x00000002 0x00000004 0x00000004
- 0x00000001 0x0000000a 0x00000002 0x00000002
- 0x00000001 0x00000001 0x00000003 0x00000004
- 0x00000003 0x00000009 0x0000000c 0x0000025f
- 0x00000000 0x00000003 0x00000003 0x00000002
- 0x00000002 0x00000001 0x00000008 0x000000c8
- 0x00000003 0x00000005 0x00000003 0x0000000c
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0x00520006
- 0x00000010 0x00000008 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- emc-table@133200 {
- reg = <133200>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <133200>;
- nvidia,emc-registers = <0x00000008 0x00000019
- 0x00000006 0x00000002 0x00000004 0x00000004
- 0x00000001 0x0000000a 0x00000002 0x00000002
- 0x00000002 0x00000001 0x00000003 0x00000004
- 0x00000003 0x00000009 0x0000000c 0x0000039f
- 0x00000000 0x00000003 0x00000003 0x00000002
- 0x00000002 0x00000001 0x00000008 0x000000c8
- 0x00000003 0x00000007 0x00000003 0x0000000c
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0x00510006
- 0x00000010 0x00000008 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- emc-table@166500 {
- reg = <166500>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <166500>;
- nvidia,emc-registers = <0x0000000a 0x00000021
- 0x00000008 0x00000003 0x00000004 0x00000004
- 0x00000002 0x0000000a 0x00000003 0x00000003
- 0x00000002 0x00000001 0x00000003 0x00000004
- 0x00000003 0x00000009 0x0000000c 0x000004df
- 0x00000000 0x00000003 0x00000003 0x00000003
- 0x00000003 0x00000001 0x00000009 0x000000c8
- 0x00000003 0x00000009 0x00000004 0x0000000c
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0x004f0006
- 0x00000010 0x00000008 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- emc-table@333000 {
- reg = <333000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <333000>;
- nvidia,emc-registers = <0x00000014 0x00000041
- 0x0000000f 0x00000005 0x00000004 0x00000005
- 0x00000003 0x0000000a 0x00000005 0x00000005
- 0x00000004 0x00000001 0x00000003 0x00000004
- 0x00000003 0x00000009 0x0000000c 0x000009ff
- 0x00000000 0x00000003 0x00000003 0x00000005
- 0x00000005 0x00000001 0x0000000e 0x000000c8
- 0x00000003 0x00000011 0x00000006 0x0000000c
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0x00380006
- 0x00000010 0x00000008 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- };
-
- ac97: ac97 {
- status = "okay";
- nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- sdhci@c8000600 {
- cd-gpios = <&gpio 23 0>; /* gpio PC7 */
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
- "nvidia,tegra-audio-wm9712";
- nvidia,model = "Colibri T20 AC97 Audio";
-
- nvidia,audio-routing =
- "Headphone", "HPOUTL",
- "Headphone", "HPOUTR",
- "LineIn", "LINEINL",
- "LineIn", "LINEINR",
- "Mic", "MIC1";
-
- nvidia,ac97-controller = <&ac97>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "internal_usb";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-boot-on;
- regulator-always-on;
- gpio = <&gpio 217 0>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
new file mode 100644
index 0000000..bf8865b
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -0,0 +1,491 @@
+#include "tegra20.dtsip"
+
+/ {
+ model = "Toradex Colibri T20 512MB";
+ compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ host1x {
+ hdmi {
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&i2c_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ audio_refclk {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ crt {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ displaya {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+ "ld4", "ld5", "ld6", "ld7", "ld8",
+ "ld9", "ld10", "ld11", "ld12", "ld13",
+ "ld14", "ld15", "ld16", "ld17",
+ "lhs", "lpw0", "lpw2", "lsc0",
+ "lsc1", "lsck", "lsda", "lspi", "lvs";
+ nvidia,function = "displaya";
+ nvidia,tristate = <1>;
+ };
+ gpio_dte {
+ nvidia,pins = "dte";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ gpio_gmi {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "dap1", "dap2", "dap4", "gpu", "irrx",
+ "irtx", "spia", "spib", "spic";
+ nvidia,function = "gmi";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ gpio_pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ gpio_uac {
+ nvidia,pins = "uac";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ nvidia,tristate = <1>;
+ };
+ i2c1 {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ i2c3 {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ i2cddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ irda {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ nand {
+ nvidia,pins = "kbca", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "nand";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ owc {
+ nvidia,pins = "owc";
+ nvidia,function = "owr";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ nvidia,tristate = <0>;
+ };
+ pwm {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "pwm";
+ nvidia,tristate = <1>;
+ };
+ sdio4 {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ spi1 {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ spi4 {
+ nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+ nvidia,function = "spi4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ uarta {
+ nvidia,pins = "sdio1";
+ nvidia,function = "uarta";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ uartd {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ ulpi {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ ulpi_refclk {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ usb_gpio {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ vi {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,function = "vi";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ vi_sc {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ };
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ };
+
+ i2c_ddc: i2c@7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1275000>;
+ regulator-max-microvolt = <1275000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "national,lm95245";
+ reg = <0x4c>;
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-table@83250 {
+ reg = <83250>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <83250>;
+ nvidia,emc-registers = <0x00000005 0x00000011
+ 0x00000004 0x00000002 0x00000004 0x00000004
+ 0x00000001 0x0000000a 0x00000002 0x00000002
+ 0x00000001 0x00000001 0x00000003 0x00000004
+ 0x00000003 0x00000009 0x0000000c 0x0000025f
+ 0x00000000 0x00000003 0x00000003 0x00000002
+ 0x00000002 0x00000001 0x00000008 0x000000c8
+ 0x00000003 0x00000005 0x00000003 0x0000000c
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0x00520006
+ 0x00000010 0x00000008 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ emc-table@133200 {
+ reg = <133200>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <133200>;
+ nvidia,emc-registers = <0x00000008 0x00000019
+ 0x00000006 0x00000002 0x00000004 0x00000004
+ 0x00000001 0x0000000a 0x00000002 0x00000002
+ 0x00000002 0x00000001 0x00000003 0x00000004
+ 0x00000003 0x00000009 0x0000000c 0x0000039f
+ 0x00000000 0x00000003 0x00000003 0x00000002
+ 0x00000002 0x00000001 0x00000008 0x000000c8
+ 0x00000003 0x00000007 0x00000003 0x0000000c
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0x00510006
+ 0x00000010 0x00000008 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000021
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000a 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000003 0x00000004
+ 0x00000003 0x00000009 0x0000000c 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x00000009 0x000000c8
+ 0x00000003 0x00000009 0x00000004 0x0000000c
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0x004f0006
+ 0x00000010 0x00000008 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000014 0x00000041
+ 0x0000000f 0x00000005 0x00000004 0x00000005
+ 0x00000003 0x0000000a 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000003 0x00000004
+ 0x00000003 0x00000009 0x0000000c 0x000009ff
+ 0x00000000 0x00000003 0x00000003 0x00000005
+ 0x00000005 0x00000001 0x0000000e 0x000000c8
+ 0x00000003 0x00000011 0x00000006 0x0000000c
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0x00380006
+ 0x00000010 0x00000008 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+
+ ac97: ac97 {
+ status = "okay";
+ nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ sdhci@c8000600 {
+ cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+ "nvidia,tegra-audio-wm9712";
+ nvidia,model = "Colibri T20 AC97 Audio";
+
+ nvidia,audio-routing =
+ "Headphone", "HPOUTL",
+ "Headphone", "HPOUTR",
+ "LineIn", "LINEINL",
+ "LineIn", "LINEINR",
+ "Mic", "MIC1";
+
+ nvidia,ac97-controller = <&ac97>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ reg = <100>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "internal_usb";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ gpio = <&gpio 217 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
deleted file mode 100644
index 61d027f..0000000
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ /dev/null
@@ -1,660 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "NVIDIA Tegra20 Harmony evaluation board";
- compatible = "nvidia,harmony", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x40000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata";
- nvidia,function = "ide";
- };
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- };
- atc {
- nvidia,pins = "atc";
- nvidia,function = "nand";
- };
- atd {
- nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
- "spia", "spib", "spic";
- nvidia,function = "gmi";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- dta {
- nvidia,pins = "dta", "dtd";
- nvidia,function = "sdio2";
- };
- dtb {
- nvidia,pins = "dtb", "dtc", "dte";
- nvidia,function = "rsvd1";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gmc {
- nvidia,pins = "gmc";
- nvidia,function = "uartd";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint", "pta";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uarta";
- };
- kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- lcsn {
- nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
- "ld3", "ld4", "ld5", "ld6", "ld7",
- "ld8", "ld9", "ld10", "ld11", "ld12",
- "ld13", "ld14", "ld15", "ld16", "ld17",
- "ldc", "ldi", "lhp0", "lhp1", "lhp2",
- "lhs", "lm0", "lm1", "lpp", "lpw0",
- "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
- "lsda", "lsdi", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "spdi", "spdo", "uac";
- nvidia,function = "rsvd2";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd";
- nvidia,function = "pwm";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxc {
- nvidia,pins = "slxc", "slxd";
- nvidia,function = "spdif";
- };
- spid {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "atd", "ate",
- "cdev1", "cdev2", "dap1", "dtb", "gma",
- "gmb", "gmc", "gmd", "gme", "gpu7",
- "gpv", "i2cp", "pta", "rm", "slxa",
- "slxk", "spia", "spib", "uac";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_csus {
- nvidia,pins = "csus", "spid", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_crtp {
- nvidia,pins = "crtp", "dap2", "dap3", "dap4",
- "dtc", "dte", "dtf", "gpu", "sdio1",
- "slxc", "slxd", "spdi", "spdo", "spig",
- "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_ddc {
- nvidia,pins = "ddc", "dta", "dtd", "kbca",
- "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
- "sdc";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
- "lpw1", "lsc1", "lsck", "lsda", "lsdi",
- "lvp0", "owc", "sdb";
- nvidia,tristate = <1>;
- };
- conf_irrx {
- nvidia,pins = "irrx", "irtx", "sdd", "spic",
- "spie", "spih", "uaa", "uab", "uad",
- "uca", "ucb";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lm0", "lpp",
- "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
- "lvs", "pmc";
- nvidia,tristate = <0>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006300 {
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <400000>;
-
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
- };
-
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <400000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <400000>;
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&vdd_5v0_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- sys_reg: sys {
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- sm0 {
- regulator-name = "vdd_sm0,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- sm1 {
- regulator-name = "vdd_sm1,vdd_cpu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sm2_reg: sm2 {
- regulator-name = "vdd_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- ldo0 {
- regulator-name = "vdd_ldo0,vddio_pex_clk";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo1 {
- regulator-name = "vdd_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "vdd_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3 {
- regulator-name = "vdd_ldo3,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "vdd_ldo5,vcore_mmc";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo6 {
- regulator-name = "vdd_ldo6,avdd_vdac";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- hdmi_vdd_reg: ldo7 {
- regulator-name = "vdd_ldo7,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: ldo8 {
- regulator-name = "vdd_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo9 {
- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo_rtc {
- regulator-name = "vdd_rtc_out,vdd_cell";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- temperature-sensor@4c {
- compatible = "adi,adt7461";
- reg = <0x4c>;
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- usb@c5000000 {
- status = "okay";
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- sdhci@c8000200 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
- bus-width = <4>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
- bus-width = <8>;
- };
-
- kbc {
- status = "okay";
- nvidia,debounce-delay-ms = <2>;
- nvidia,repeat-delay-ms = <160>;
- nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
- nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
- linux,keymap = <0x00020011 /* KEY_W */
- 0x0003001F /* KEY_S */
- 0x0004001E /* KEY_A */
- 0x0005002C /* KEY_Z */
- 0x000701D0 /* KEY_FN */
- 0x0107008B /* KEY_MENU */
- 0x02060038 /* KEY_LEFTALT */
- 0x02070064 /* KEY_RIGHTALT */
- 0x03000006 /* KEY_5 */
- 0x03010005 /* KEY_4 */
- 0x03020013 /* KEY_R */
- 0x03030012 /* KEY_E */
- 0x03040021 /* KEY_F */
- 0x03050020 /* KEY_D */
- 0x0306002D /* KEY_X */
- 0x04000008 /* KEY_7 */
- 0x04010007 /* KEY_6 */
- 0x04020014 /* KEY_T */
- 0x04030023 /* KEY_H */
- 0x04040022 /* KEY_G */
- 0x0405002F /* KEY_V */
- 0x0406002E /* KEY_C */
- 0x04070039 /* KEY_SPACE */
- 0x0500000A /* KEY_9 */
- 0x05010009 /* KEY_8 */
- 0x05020016 /* KEY_U */
- 0x05030015 /* KEY_Y */
- 0x05040024 /* KEY_J */
- 0x05050031 /* KEY_N */
- 0x05060030 /* KEY_B */
- 0x0507002B /* KEY_BACKSLASH */
- 0x0600000C /* KEY_MINUS */
- 0x0601000B /* KEY_0 */
- 0x06020018 /* KEY_O */
- 0x06030017 /* KEY_I */
- 0x06040026 /* KEY_L */
- 0x06050025 /* KEY_K */
- 0x06060033 /* KEY_COMMA */
- 0x06070032 /* KEY_M */
- 0x0701000D /* KEY_EQUAL */
- 0x0702001B /* KEY_RIGHTBRACE */
- 0x0703001C /* KEY_ENTER */
- 0x0707008B /* KEY_MENU */
- 0x0804002A /* KEY_LEFTSHIFT */
- 0x08050036 /* KEY_RIGHTSHIFT */
- 0x0905001D /* KEY_LEFTCTRL */
- 0x09070061 /* KEY_RIGHTCTRL */
- 0x0B00001A /* KEY_LEFTBRACE */
- 0x0B010019 /* KEY_P */
- 0x0B020028 /* KEY_APOSTROPHE */
- 0x0B030027 /* KEY_SEMICOLON */
- 0x0B040035 /* KEY_SLASH */
- 0x0B050034 /* KEY_DOT */
- 0x0C000044 /* KEY_F10 */
- 0x0C010043 /* KEY_F9 */
- 0x0C02000E /* KEY_BACKSPACE */
- 0x0C030004 /* KEY_3 */
- 0x0C040003 /* KEY_2 */
- 0x0C050067 /* KEY_UP */
- 0x0C0600D2 /* KEY_PRINT */
- 0x0C070077 /* KEY_PAUSE */
- 0x0D00006E /* KEY_INSERT */
- 0x0D01006F /* KEY_DELETE */
- 0x0D030068 /* KEY_PAGEUP */
- 0x0D04006D /* KEY_PAGEDOWN */
- 0x0D05006A /* KEY_RIGHT */
- 0x0D06006C /* KEY_DOWN */
- 0x0D070069 /* KEY_LEFT */
- 0x0E000057 /* KEY_F11 */
- 0x0E010058 /* KEY_F12 */
- 0x0E020042 /* KEY_F8 */
- 0x0E030010 /* KEY_Q */
- 0x0E04003E /* KEY_F4 */
- 0x0E05003D /* KEY_F3 */
- 0x0E060002 /* KEY_1 */
- 0x0E070041 /* KEY_F7 */
- 0x0F000001 /* KEY_ESC */
- 0x0F010029 /* KEY_GRAVE */
- 0x0F02003F /* KEY_F5 */
- 0x0F03000F /* KEY_TAB */
- 0x0F04003B /* KEY_F1 */
- 0x0F05003C /* KEY_F2 */
- 0x0F06003A /* KEY_CAPSLOCK */
- 0x0F070040 /* KEY_F6 */
- 0x14000047 /* KEY_KP7 */
- 0x15000049 /* KEY_KP9 */
- 0x15010048 /* KEY_KP8 */
- 0x1502004B /* KEY_KP4 */
- 0x1504004F /* KEY_KP1 */
- 0x1601004E /* KEY_KPSLASH */
- 0x1602004D /* KEY_KP6 */
- 0x1603004C /* KEY_KP5 */
- 0x16040051 /* KEY_KP3 */
- 0x16050050 /* KEY_KP2 */
- 0x16070052 /* KEY_KP0 */
- 0x1B010037 /* KEY_KPASTERISK */
- 0x1B03004A /* KEY_KPMINUS */
- 0x1B04004E /* KEY_KPPLUS */
- 0x1B050053 /* KEY_KPDOT */
- 0x1C050073 /* KEY_VOLUMEUP */
- 0x1D030066 /* KEY_HOME */
- 0x1D04006B /* KEY_END */
- 0x1D0500E1 /* KEY_BRIGHTNESSUP */
- 0x1D060072 /* KEY_VOLUMEDOWN */
- 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
- 0x1E000045 /* KEY_NUMLOCK */
- 0x1E010046 /* KEY_SCROLLLOCK */
- 0x1E020071 /* KEY_MUTE */
- 0x1F0400D6>; /* KEY_QUESTION */
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 0>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 0>;
- enable-active-high;
- };
-
- regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_1v05";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&pmic 2 0>;
- enable-active-high;
- /* Hack until board-harmony-pcie.c is removed */
- status = "disabled";
- };
-
- regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_pnl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
- enable-active-high;
- };
-
- regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
- enable-active-high;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-harmony",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "NVIDIA Tegra Harmony";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
new file mode 100644
index 0000000..3fe66c1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -0,0 +1,660 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "NVIDIA Tegra20 Harmony evaluation board";
+ compatible = "nvidia,harmony", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+ "spia", "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtd";
+ nvidia,function = "sdio2";
+ };
+ dtb {
+ nvidia,pins = "dtb", "dtc", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "pwm";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dtb", "gma",
+ "gmb", "gmc", "gmd", "gme", "gpu7",
+ "gpv", "i2cp", "pta", "rm", "slxa",
+ "slxk", "spia", "spib", "uac";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spid", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+ "dtc", "dte", "dtf", "gpu", "sdio1",
+ "slxc", "slxd", "spdi", "spdo", "spig",
+ "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "dta", "dtd", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "sdc";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "owc", "sdb";
+ nvidia,tristate = <1>;
+ };
+ conf_irrx {
+ nvidia,pins = "irrx", "irtx", "sdd", "spic",
+ "spie", "spih", "uaa", "uab", "uad",
+ "uca", "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+ "lvs", "pmc";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ ldo0 {
+ regulator-name = "vdd_ldo0,vddio_pex_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5004400 {
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ sdhci@c8000200 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+ wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ bus-width = <8>;
+ };
+
+ kbc {
+ status = "okay";
+ nvidia,debounce-delay-ms = <2>;
+ nvidia,repeat-delay-ms = <160>;
+ nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+ linux,keymap = <0x00020011 /* KEY_W */
+ 0x0003001F /* KEY_S */
+ 0x0004001E /* KEY_A */
+ 0x0005002C /* KEY_Z */
+ 0x000701D0 /* KEY_FN */
+ 0x0107008B /* KEY_MENU */
+ 0x02060038 /* KEY_LEFTALT */
+ 0x02070064 /* KEY_RIGHTALT */
+ 0x03000006 /* KEY_5 */
+ 0x03010005 /* KEY_4 */
+ 0x03020013 /* KEY_R */
+ 0x03030012 /* KEY_E */
+ 0x03040021 /* KEY_F */
+ 0x03050020 /* KEY_D */
+ 0x0306002D /* KEY_X */
+ 0x04000008 /* KEY_7 */
+ 0x04010007 /* KEY_6 */
+ 0x04020014 /* KEY_T */
+ 0x04030023 /* KEY_H */
+ 0x04040022 /* KEY_G */
+ 0x0405002F /* KEY_V */
+ 0x0406002E /* KEY_C */
+ 0x04070039 /* KEY_SPACE */
+ 0x0500000A /* KEY_9 */
+ 0x05010009 /* KEY_8 */
+ 0x05020016 /* KEY_U */
+ 0x05030015 /* KEY_Y */
+ 0x05040024 /* KEY_J */
+ 0x05050031 /* KEY_N */
+ 0x05060030 /* KEY_B */
+ 0x0507002B /* KEY_BACKSLASH */
+ 0x0600000C /* KEY_MINUS */
+ 0x0601000B /* KEY_0 */
+ 0x06020018 /* KEY_O */
+ 0x06030017 /* KEY_I */
+ 0x06040026 /* KEY_L */
+ 0x06050025 /* KEY_K */
+ 0x06060033 /* KEY_COMMA */
+ 0x06070032 /* KEY_M */
+ 0x0701000D /* KEY_EQUAL */
+ 0x0702001B /* KEY_RIGHTBRACE */
+ 0x0703001C /* KEY_ENTER */
+ 0x0707008B /* KEY_MENU */
+ 0x0804002A /* KEY_LEFTSHIFT */
+ 0x08050036 /* KEY_RIGHTSHIFT */
+ 0x0905001D /* KEY_LEFTCTRL */
+ 0x09070061 /* KEY_RIGHTCTRL */
+ 0x0B00001A /* KEY_LEFTBRACE */
+ 0x0B010019 /* KEY_P */
+ 0x0B020028 /* KEY_APOSTROPHE */
+ 0x0B030027 /* KEY_SEMICOLON */
+ 0x0B040035 /* KEY_SLASH */
+ 0x0B050034 /* KEY_DOT */
+ 0x0C000044 /* KEY_F10 */
+ 0x0C010043 /* KEY_F9 */
+ 0x0C02000E /* KEY_BACKSPACE */
+ 0x0C030004 /* KEY_3 */
+ 0x0C040003 /* KEY_2 */
+ 0x0C050067 /* KEY_UP */
+ 0x0C0600D2 /* KEY_PRINT */
+ 0x0C070077 /* KEY_PAUSE */
+ 0x0D00006E /* KEY_INSERT */
+ 0x0D01006F /* KEY_DELETE */
+ 0x0D030068 /* KEY_PAGEUP */
+ 0x0D04006D /* KEY_PAGEDOWN */
+ 0x0D05006A /* KEY_RIGHT */
+ 0x0D06006C /* KEY_DOWN */
+ 0x0D070069 /* KEY_LEFT */
+ 0x0E000057 /* KEY_F11 */
+ 0x0E010058 /* KEY_F12 */
+ 0x0E020042 /* KEY_F8 */
+ 0x0E030010 /* KEY_Q */
+ 0x0E04003E /* KEY_F4 */
+ 0x0E05003D /* KEY_F3 */
+ 0x0E060002 /* KEY_1 */
+ 0x0E070041 /* KEY_F7 */
+ 0x0F000001 /* KEY_ESC */
+ 0x0F010029 /* KEY_GRAVE */
+ 0x0F02003F /* KEY_F5 */
+ 0x0F03000F /* KEY_TAB */
+ 0x0F04003B /* KEY_F1 */
+ 0x0F05003C /* KEY_F2 */
+ 0x0F06003A /* KEY_CAPSLOCK */
+ 0x0F070040 /* KEY_F6 */
+ 0x14000047 /* KEY_KP7 */
+ 0x15000049 /* KEY_KP9 */
+ 0x15010048 /* KEY_KP8 */
+ 0x1502004B /* KEY_KP4 */
+ 0x1504004F /* KEY_KP1 */
+ 0x1601004E /* KEY_KPSLASH */
+ 0x1602004D /* KEY_KP6 */
+ 0x1603004C /* KEY_KP5 */
+ 0x16040051 /* KEY_KP3 */
+ 0x16050050 /* KEY_KP2 */
+ 0x16070052 /* KEY_KP0 */
+ 0x1B010037 /* KEY_KPASTERISK */
+ 0x1B03004A /* KEY_KPMINUS */
+ 0x1B04004E /* KEY_KPPLUS */
+ 0x1B050053 /* KEY_KPDOT */
+ 0x1C050073 /* KEY_VOLUMEUP */
+ 0x1D030066 /* KEY_HOME */
+ 0x1D04006B /* KEY_END */
+ 0x1D0500E1 /* KEY_BRIGHTNESSUP */
+ 0x1D060072 /* KEY_VOLUMEDOWN */
+ 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
+ 0x1E000045 /* KEY_NUMLOCK */
+ 0x1E010046 /* KEY_SCROLLLOCK */
+ 0x1E020071 /* KEY_MUTE */
+ 0x1F0400D6>; /* KEY_QUESTION */
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_1v05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pmic 2 0>;
+ enable-active-high;
+ /* Hack until board-harmony-pcie.c is removed */
+ status = "disabled";
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 22 0>; /* gpio PC6 */
+ enable-active-high;
+ };
+
+ regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 176 0>; /* gpio PW0 */
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-harmony",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "NVIDIA Tegra Harmony";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
deleted file mode 100644
index 52f1103..0000000
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ /dev/null
@@ -1,89 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20-colibri-512.dtsi"
-
-/ {
- model = "Toradex Colibri T20 512MB on Iris";
- compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
-
- host1x {
- hdmi {
- status = "okay";
- };
- };
-
- pinmux {
- state_default: pinmux {
- hdint {
- nvidia,tristate = <0>;
- };
-
- i2cddc {
- nvidia,tristate = <0>;
- };
-
- sdio4 {
- nvidia,tristate = <0>;
- };
-
- uarta {
- nvidia,tristate = <0>;
- };
-
- uartd {
- nvidia,tristate = <0>;
- };
- };
- };
-
- usb@c5000000 {
- status = "okay";
- dr_mode = "otg";
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- serial@70006300 {
- status = "okay";
- };
-
- i2c_ddc: i2c@7000c400 {
- status = "okay";
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <4>;
- vmmc-supply = <&vcc_sd_reg>;
- vqmmc-supply = <&vcc_sd_reg>;
- };
-
- regulators {
- regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- gpio = <&gpio 178 0>;
- };
-
- vcc_sd_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dtsp b/arch/arm/boot/dts/tegra20-iris-512.dtsp
new file mode 100644
index 0000000..a0ba0b0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+#include "tegra20-colibri-512.dtsip"
+
+/ {
+ model = "Toradex Colibri T20 512MB on Iris";
+ compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+
+ host1x {
+ hdmi {
+ status = "okay";
+ };
+ };
+
+ pinmux {
+ state_default: pinmux {
+ hdint {
+ nvidia,tristate = <0>;
+ };
+
+ i2cddc {
+ nvidia,tristate = <0>;
+ };
+
+ sdio4 {
+ nvidia,tristate = <0>;
+ };
+
+ uarta {
+ nvidia,tristate = <0>;
+ };
+
+ uartd {
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ i2c_ddc: i2c@7000c400 {
+ status = "okay";
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ bus-width = <4>;
+ vmmc-supply = <&vcc_sd_reg>;
+ vqmmc-supply = <&vcc_sd_reg>;
+ };
+
+ regulators {
+ regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ gpio = <&gpio 178 0>;
+ };
+
+ vcc_sd_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
deleted file mode 100644
index a2d6d65..0000000
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ /dev/null
@@ -1,58 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20-tamonten.dtsi"
-
-/ {
- model = "Avionic Design Medcom-Wide board";
- compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
-
- i2c@7000c000 {
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff
- 0xffffffff
- 0
- 0xffffffff
- 0xffffffff>;
- };
- };
-
- backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm 0 5000000>;
-
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- };
-
- sound {
- compatible = "ad,tegra-audio-wm8903-medcom-wide",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "Avionic Design Medcom-Wide";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
new file mode 100644
index 0000000..6125604
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsip"
+
+/ {
+ model = "Avionic Design Medcom-Wide board";
+ compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+
+ i2c@7000c000 {
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-wm8903-medcom-wide",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design Medcom-Wide";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
deleted file mode 100644
index 54d6fce..0000000
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ /dev/null
@@ -1,505 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "Toshiba AC100 / Dynabook AZ";
- compatible = "compal,paz00", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata", "atc", "atd", "ate",
- "dap2", "gmb", "gmc", "gmd", "spia",
- "spib", "spic", "spid", "spie";
- nvidia,function = "gmi";
- };
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "pllc_out1";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
- nvidia,function = "rsvd1";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gpu {
- nvidia,pins = "gpu", "sdb", "sdd";
- nvidia,function = "pwm";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint", "pta";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uarta";
- };
- kbca {
- nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- kbcb {
- nvidia,pins = "kbcb", "kbcd";
- nvidia,function = "sdio2";
- };
- lcsn {
- nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
- "ld3", "ld4", "ld5", "ld6", "ld7",
- "ld8", "ld9", "ld10", "ld11", "ld12",
- "ld13", "ld14", "ld15", "ld16", "ld17",
- "ldc", "ldi", "lhp0", "lhp1", "lhp2",
- "lhs", "lm0", "lm1", "lpp", "lpw0",
- "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
- "lsda", "lsdi", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc";
- nvidia,function = "owr";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdc {
- nvidia,pins = "sdc";
- nvidia,function = "twc";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxc {
- nvidia,pins = "slxc", "slxd";
- nvidia,function = "spi4";
- };
- spdi {
- nvidia,pins = "spdi", "spdo";
- nvidia,function = "rsvd2";
- };
- spif {
- nvidia,pins = "spif", "uac";
- nvidia,function = "rsvd4";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "spdif";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "atd", "ate",
- "cdev1", "cdev2", "dap1", "dap2", "dtf",
- "gma", "gmb", "gmc", "gmd", "gme",
- "gpu", "gpu7", "gpv", "i2cp", "pta",
- "rm", "sdio1", "slxk", "spdo", "uac",
- "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_crtp {
- nvidia,pins = "crtp", "dap3", "dap4", "dtb",
- "dtc", "dte", "slxa", "slxc", "slxd",
- "spdi";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_csus {
- nvidia,pins = "csus", "spia", "spib", "spid",
- "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_ddc {
- nvidia,pins = "ddc", "irrx", "irtx", "kbca",
- "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
- "spic", "spig", "uaa", "uab";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_dta {
- nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
- "spie", "spih", "uad", "uca", "ucb";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "ld0", "ld1", "ld2",
- "ld3", "ld4", "ld5", "ld6", "ld7",
- "ld8", "ld9", "ld10", "ld11", "ld12",
- "ld13", "ld14", "ld15", "ld16", "ld17",
- "ldc", "ldi", "lhs", "lsc0", "lspi",
- "lvs", "pmc";
- nvidia,tristate = <0>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_lcsn {
- nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
- "lm0", "lm1", "lpp", "lpw0", "lpw1",
- "lpw2", "lsc1", "lsck", "lsda", "lsdi",
- "lvp0", "lvp1", "sdb";
- nvidia,tristate = <1>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- serial@70006200 {
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <400000>;
-
- alc5632: alc5632@1e {
- compatible = "realtek,alc5632";
- reg = <0x1e>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- nvec {
- compatible = "nvidia,nvec";
- reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <80000>;
- request-gpios = <&gpio 170 0>; /* gpio PV2 */
- slave-addr = <138>;
- clocks = <&tegra_car 67>, <&tegra_car 124>;
- clock-names = "div-clk", "fast-clk";
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <400000>;
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&p5valw_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- sys_reg: sys {
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- sm0 {
- regulator-name = "+1.2vs_sm0,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- sm1 {
- regulator-name = "+1.0vs_sm1,vdd_cpu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sm2_reg: sm2 {
- regulator-name = "+3.7vs_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- /* LDO0 is not connected to anything */
-
- ldo1 {
- regulator-name = "+1.1vs_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "+1.2vs_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3 {
- regulator-name = "+3.3vs_ldo3,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "+2.85vs_ldo5,vcore_mmc";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo6 {
- /*
- * Research indicates this should be
- * 1.8v; other boards that use this
- * rail for the same purpose need it
- * set to 1.8v. The schematic signal
- * name is incorrect; perhaps copied
- * from an incorrect NVIDIA reference.
- */
- regulator-name = "+2.85vs_ldo6,avdd_vdac";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- hdmi_vdd_reg: ldo7 {
- regulator-name = "+3.3vs_ldo7,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: ldo8 {
- regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo9 {
- regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo_rtc {
- regulator-name = "+3.3vs_rtc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- adt7461@4c {
- compatible = "adi,adt7461";
- reg = <0x4c>;
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- usb@c5000000 {
- status = "okay";
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- };
-
- sdhci@c8000000 {
- status = "okay";
- cd-gpios = <&gpio 173 0>; /* gpio PV5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 169 0>; /* gpio PV1 */
- bus-width = <4>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- label = "Power";
- gpios = <&gpio 79 1>; /* gpio PJ7, active low */
- linux,code = <116>; /* KEY_POWER */
- gpio-key,wakeup;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- wifi {
- label = "wifi-led";
- gpios = <&gpio 24 0>; /* gpio PD0 */
- linux,default-trigger = "rfkill0";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- p5valw_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+5valw";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-alc5632-paz00",
- "nvidia,tegra-audio-alc5632";
-
- nvidia,model = "Compal PAZ00";
-
- nvidia,audio-routing =
- "Int Spk", "SPKOUT",
- "Int Spk", "SPKOUTN",
- "Headset Mic", "MICBIAS1",
- "MIC1", "Headset Mic",
- "Headset Stereophone", "HPR",
- "Headset Stereophone", "HPL",
- "DMICDAT", "Digital Mic";
-
- nvidia,audio-codec = <&alc5632>;
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
new file mode 100644
index 0000000..e40d7ee
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -0,0 +1,505 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "Toshiba AC100 / Dynabook AZ";
+ compatible = "compal,paz00", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "dap2", "gmb", "gmc", "gmd", "spia",
+ "spib", "spic", "spid", "spie";
+ nvidia,function = "gmi";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "pllc_out1";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gpu {
+ nvidia,pins = "gpu", "sdb", "sdd";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ kbcb {
+ nvidia,pins = "kbcb", "kbcd";
+ nvidia,function = "sdio2";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc";
+ nvidia,function = "owr";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdc {
+ nvidia,pins = "sdc";
+ nvidia,function = "twc";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spi4";
+ };
+ spdi {
+ nvidia,pins = "spdi", "spdo";
+ nvidia,function = "rsvd2";
+ };
+ spif {
+ nvidia,pins = "spif", "uac";
+ nvidia,function = "rsvd4";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "spdif";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dap2", "dtf",
+ "gma", "gmb", "gmc", "gmd", "gme",
+ "gpu", "gpu7", "gpv", "i2cp", "pta",
+ "rm", "sdio1", "slxk", "spdo", "uac",
+ "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+ "dtc", "dte", "slxa", "slxc", "slxd",
+ "spdi";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spia", "spib", "spid",
+ "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "spic", "spig", "uaa", "uab";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+ "spie", "spih", "uad", "uca", "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhs", "lsc0", "lspi",
+ "lvs", "pmc";
+ nvidia,tristate = <0>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_lcsn {
+ nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+ "lm0", "lm1", "lpp", "lpw0", "lpw1",
+ "lpw2", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "lvp1", "sdb";
+ nvidia,tristate = <1>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ serial@70006200 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ alc5632: alc5632@1e {
+ compatible = "realtek,alc5632";
+ reg = <0x1e>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ nvec {
+ compatible = "nvidia,nvec";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <80000>;
+ request-gpios = <&gpio 170 0>; /* gpio PV2 */
+ slave-addr = <138>;
+ clocks = <&tegra_car 67>, <&tegra_car 124>;
+ clock-names = "div-clk", "fast-clk";
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&p5valw_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "+1.2vs_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "+1.0vs_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "+3.7vs_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "+1.1vs_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "+1.2vs_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "+3.3vs_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "+2.85vs_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ /*
+ * Research indicates this should be
+ * 1.8v; other boards that use this
+ * rail for the same purpose need it
+ * set to 1.8v. The schematic signal
+ * name is incorrect; perhaps copied
+ * from an incorrect NVIDIA reference.
+ */
+ regulator-name = "+2.85vs_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "+3.3vs_rtc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ adt7461@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5004400 {
+ nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ };
+
+ sdhci@c8000000 {
+ status = "okay";
+ cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 169 0>; /* gpio PV1 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+ linux,code = <116>; /* KEY_POWER */
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ wifi {
+ label = "wifi-led";
+ gpios = <&gpio 24 0>; /* gpio PD0 */
+ linux,default-trigger = "rfkill0";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ p5valw_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+5valw";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-alc5632-paz00",
+ "nvidia,tegra-audio-alc5632";
+
+ nvidia,model = "Compal PAZ00";
+
+ nvidia,audio-routing =
+ "Int Spk", "SPKOUT",
+ "Int Spk", "SPKOUTN",
+ "Headset Mic", "MICBIAS1",
+ "MIC1", "Headset Mic",
+ "Headset Stereophone", "HPR",
+ "Headset Stereophone", "HPL",
+ "DMICDAT", "Digital Mic";
+
+ nvidia,audio-codec = <&alc5632>;
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
deleted file mode 100644
index 2894800..0000000
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ /dev/null
@@ -1,56 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20-tamonten.dtsi"
-
-/ {
- model = "Avionic Design Plutux board";
- compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
-
- host1x {
- hdmi {
- status = "okay";
- };
- };
-
- i2c@7000c000 {
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff
- 0xffffffff
- 0
- 0xffffffff
- 0xffffffff>;
- };
- };
-
- sound {
- compatible = "ad,tegra-audio-plutux",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "Avionic Design Plutux";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
new file mode 100644
index 0000000..08401b9
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -0,0 +1,56 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsip"
+
+/ {
+ model = "Avionic Design Plutux board";
+ compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+
+ host1x {
+ hdmi {
+ status = "okay";
+ };
+ };
+
+ i2c@7000c000 {
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-plutux",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design Plutux";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
deleted file mode 100644
index 37b3a57..0000000
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ /dev/null
@@ -1,812 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "NVIDIA Seaboard";
- compatible = "nvidia,seaboard", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x40000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata";
- nvidia,function = "ide";
- };
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- };
- atc {
- nvidia,pins = "atc";
- nvidia,function = "nand";
- };
- atd {
- nvidia,pins = "atd", "ate", "gmb", "spia",
- "spib", "spic";
- nvidia,function = "gmi";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp", "lm1";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
- nvidia,function = "vi";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gmc {
- nvidia,pins = "gmc";
- nvidia,function = "uartd";
- };
- gmd {
- nvidia,pins = "gmd";
- nvidia,function = "sflash";
- };
- gpu {
- nvidia,pins = "gpu";
- nvidia,function = "pwm";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
- "lsck", "lsda";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uartb";
- };
- kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- lcsn {
- nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
- "lsdi", "lvp0";
- nvidia,function = "rsvd4";
- };
- ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lpp", "lsc0",
- "lspi", "lvp1", "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "spdi", "spdo", "uac";
- nvidia,function = "rsvd2";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd";
- nvidia,function = "sdio3";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxc {
- nvidia,pins = "slxc", "slxd";
- nvidia,function = "spdif";
- };
- spid {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "atd",
- "cdev1", "cdev2", "dap1", "dap2",
- "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
- "gme", "gpu", "gpu7", "i2cp", "irrx",
- "irtx", "pta", "rm", "sdc", "sdd",
- "slxd", "slxk", "spdi", "spdo", "uac",
- "uad", "uca", "ucb", "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ate {
- nvidia,pins = "ate", "csus", "dap3",
- "gpv", "owc", "slxc", "spib", "spid",
- "spie";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_crtp {
- nvidia,pins = "crtp", "gmb", "slxa", "spia",
- "spig", "spih";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- };
- conf_dte {
- nvidia,pins = "dte", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
- "lpw1", "lsc1", "lsck", "lsda", "lsdi",
- "lvp0";
- nvidia,tristate = <1>;
- };
- conf_kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf", "sdio1", "spic", "uaa",
- "uab";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lm0", "lpp",
- "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
- "lvs", "pmc", "sdb";
- nvidia,tristate = <0>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- drive_sdio1 {
- nvidia,pins = "drive_sdio1";
- nvidia,high-speed-mode = <0>;
- nvidia,schmitt = <0>;
- nvidia,low-power-mode = <3>;
- nvidia,pull-down-strength = <31>;
- nvidia,pull-up-strength = <31>;
- nvidia,slew-rate-rising = <3>;
- nvidia,slew-rate-falling = <3>;
- };
- };
-
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
-
- state_i2cmux_pta: pinmux_i2cmux_pta {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "i2c2";
- };
- };
-
- state_i2cmux_idle: pinmux_i2cmux_idle {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006300 {
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <400000>;
-
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
-
- /* ALS and proximity sensor */
- isl29018@44 {
- compatible = "isil,isl29018";
- reg = <0x44>;
- interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /* GPIO PZ2 */
- };
-
- gyrometer@68 {
- compatible = "invn,mpu3050";
- reg = <0x68>;
- interrupt-parent = <&gpio>;
- interrupts = <204 0x04>; /* gpio PZ4 */
- };
- };
-
- i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- smart-battery@b {
- compatible = "ti,bq20z75", "smart-battery-1.1";
- reg = <0xb>;
- ti,i2c-retry-count = <2>;
- ti,poll-retry-count = <10>;
- };
- };
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <400000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <400000>;
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&vdd_5v0_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- sys_reg: sys {
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- sm0 {
- regulator-name = "vdd_sm0,vdd_core";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- };
-
- sm1 {
- regulator-name = "vdd_sm1,vdd_cpu";
- regulator-min-microvolt = <1125000>;
- regulator-max-microvolt = <1125000>;
- regulator-always-on;
- };
-
- sm2_reg: sm2 {
- regulator-name = "vdd_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- /* LDO0 is not connected to anything */
-
- ldo1 {
- regulator-name = "vdd_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "vdd_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3 {
- regulator-name = "vdd_ldo3,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "vdd_ldo5,vcore_mmc";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo6 {
- regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- hdmi_vdd_reg: ldo7 {
- regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: ldo8 {
- regulator-name = "vdd_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo9 {
- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo_rtc {
- regulator-name = "vdd_rtc_out,vdd_cell";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
- };
-
- magnetometer@c {
- compatible = "ak,ak8975";
- reg = <0xc>;
- interrupt-parent = <&gpio>;
- interrupts = <109 0x04>; /* gpio PN5 */
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- memory-controller@7000f400 {
- emc-table@190000 {
- reg = <190000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <190000>;
- nvidia,emc-registers = <0x0000000c 0x00000026
- 0x00000009 0x00000003 0x00000004 0x00000004
- 0x00000002 0x0000000c 0x00000003 0x00000003
- 0x00000002 0x00000001 0x00000004 0x00000005
- 0x00000004 0x00000009 0x0000000d 0x0000059f
- 0x00000000 0x00000003 0x00000003 0x00000003
- 0x00000003 0x00000001 0x0000000b 0x000000c8
- 0x00000003 0x00000007 0x00000004 0x0000000f
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0xa06204ae
- 0x007dc010 0x00000000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
-
- emc-table@380000 {
- reg = <380000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <380000>;
- nvidia,emc-registers = <0x00000017 0x0000004b
- 0x00000012 0x00000006 0x00000004 0x00000005
- 0x00000003 0x0000000c 0x00000006 0x00000006
- 0x00000003 0x00000001 0x00000004 0x00000005
- 0x00000004 0x00000009 0x0000000d 0x00000b5f
- 0x00000000 0x00000003 0x00000003 0x00000006
- 0x00000006 0x00000001 0x00000011 0x000000c8
- 0x00000003 0x0000000e 0x00000007 0x0000000f
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0xe044048b
- 0x007d8010 0x00000000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- };
-
- usb@c5000000 {
- status = "okay";
- nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
- dr_mode = "otg";
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- sdhci@c8000000 {
- status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
- bus-width = <4>;
- };
-
- sdhci@c8000400 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
- bus-width = <4>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- label = "Power";
- gpios = <&gpio 170 1>; /* gpio PV2, active low */
- linux,code = <116>; /* KEY_POWER */
- gpio-key,wakeup;
- };
-
- lid {
- label = "Lid";
- gpios = <&gpio 23 0>; /* gpio PC7 */
- linux,input-type = <5>; /* EV_SW */
- linux,code = <0>; /* SW_LID */
- debounce-interval = <1>;
- gpio-key,wakeup;
- };
- };
-
- kbc {
- status = "okay";
- nvidia,debounce-delay-ms = <32>;
- nvidia,repeat-delay-ms = <160>;
- nvidia,ghost-filter;
- nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
- nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
- linux,keymap = <0x00020011 /* KEY_W */
- 0x0003001F /* KEY_S */
- 0x0004001E /* KEY_A */
- 0x0005002C /* KEY_Z */
- 0x000701d0 /* KEY_FN */
-
- 0x0107007D /* KEY_LEFTMETA */
- 0x02060064 /* KEY_RIGHTALT */
- 0x02070038 /* KEY_LEFTALT */
-
- 0x03000006 /* KEY_5 */
- 0x03010005 /* KEY_4 */
- 0x03020013 /* KEY_R */
- 0x03030012 /* KEY_E */
- 0x03040021 /* KEY_F */
- 0x03050020 /* KEY_D */
- 0x0306002D /* KEY_X */
-
- 0x04000008 /* KEY_7 */
- 0x04010007 /* KEY_6 */
- 0x04020014 /* KEY_T */
- 0x04030023 /* KEY_H */
- 0x04040022 /* KEY_G */
- 0x0405002F /* KEY_V */
- 0x0406002E /* KEY_C */
- 0x04070039 /* KEY_SPACE */
-
- 0x0500000A /* KEY_9 */
- 0x05010009 /* KEY_8 */
- 0x05020016 /* KEY_U */
- 0x05030015 /* KEY_Y */
- 0x05040024 /* KEY_J */
- 0x05050031 /* KEY_N */
- 0x05060030 /* KEY_B */
- 0x0507002B /* KEY_BACKSLASH */
-
- 0x0600000C /* KEY_MINUS */
- 0x0601000B /* KEY_0 */
- 0x06020018 /* KEY_O */
- 0x06030017 /* KEY_I */
- 0x06040026 /* KEY_L */
- 0x06050025 /* KEY_K */
- 0x06060033 /* KEY_COMMA */
- 0x06070032 /* KEY_M */
-
- 0x0701000D /* KEY_EQUAL */
- 0x0702001B /* KEY_RIGHTBRACE */
- 0x0703001C /* KEY_ENTER */
- 0x0707008B /* KEY_MENU */
-
- 0x08040036 /* KEY_RIGHTSHIFT */
- 0x0805002A /* KEY_LEFTSHIFT */
-
- 0x09050061 /* KEY_RIGHTCTRL */
- 0x0907001D /* KEY_LEFTCTRL */
-
- 0x0B00001A /* KEY_LEFTBRACE */
- 0x0B010019 /* KEY_P */
- 0x0B020028 /* KEY_APOSTROPHE */
- 0x0B030027 /* KEY_SEMICOLON */
- 0x0B040035 /* KEY_SLASH */
- 0x0B050034 /* KEY_DOT */
-
- 0x0C000044 /* KEY_F10 */
- 0x0C010043 /* KEY_F9 */
- 0x0C02000E /* KEY_BACKSPACE */
- 0x0C030004 /* KEY_3 */
- 0x0C040003 /* KEY_2 */
- 0x0C050067 /* KEY_UP */
- 0x0C0600D2 /* KEY_PRINT */
- 0x0C070077 /* KEY_PAUSE */
-
- 0x0D00006E /* KEY_INSERT */
- 0x0D01006F /* KEY_DELETE */
- 0x0D030068 /* KEY_PAGEUP */
- 0x0D04006D /* KEY_PAGEDOWN */
- 0x0D05006A /* KEY_RIGHT */
- 0x0D06006C /* KEY_DOWN */
- 0x0D070069 /* KEY_LEFT */
-
- 0x0E000057 /* KEY_F11 */
- 0x0E010058 /* KEY_F12 */
- 0x0E020042 /* KEY_F8 */
- 0x0E030010 /* KEY_Q */
- 0x0E04003E /* KEY_F4 */
- 0x0E05003D /* KEY_F3 */
- 0x0E060002 /* KEY_1 */
- 0x0E070041 /* KEY_F7 */
-
- 0x0F000001 /* KEY_ESC */
- 0x0F010029 /* KEY_GRAVE */
- 0x0F02003F /* KEY_F5 */
- 0x0F03000F /* KEY_TAB */
- 0x0F04003B /* KEY_F1 */
- 0x0F05003C /* KEY_F2 */
- 0x0F06003A /* KEY_CAPSLOCK */
- 0x0F070040 /* KEY_F6 */
-
- /* Software Handled Function Keys */
- 0x14000047 /* KEY_KP7 */
-
- 0x15000049 /* KEY_KP9 */
- 0x15010048 /* KEY_KP8 */
- 0x1502004B /* KEY_KP4 */
- 0x1504004F /* KEY_KP1 */
-
- 0x1601004E /* KEY_KPSLASH */
- 0x1602004D /* KEY_KP6 */
- 0x1603004C /* KEY_KP5 */
- 0x16040051 /* KEY_KP3 */
- 0x16050050 /* KEY_KP2 */
- 0x16070052 /* KEY_KP0 */
-
- 0x1B010037 /* KEY_KPASTERISK */
- 0x1B03004A /* KEY_KPMINUS */
- 0x1B04004E /* KEY_KPPLUS */
- 0x1B050053 /* KEY_KPDOT */
-
- 0x1C050073 /* KEY_VOLUMEUP */
-
- 0x1D030066 /* KEY_HOME */
- 0x1D04006B /* KEY_END */
- 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
- 0x1D060072 /* KEY_VOLUMEDOWN */
- 0x1D0700E1 /* KEY_BRIGHTNESSUP */
-
- 0x1E000045 /* KEY_NUMLOCK */
- 0x1E010046 /* KEY_SCROLLLOCK */
- 0x1E020071 /* KEY_MUTE */
-
- 0x1F04008A>; /* KEY_HELP */
- };
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 0>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 0>;
- enable-active-high;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-seaboard",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "NVIDIA Tegra Seaboard";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1R", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
new file mode 100644
index 0000000..6534a61
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -0,0 +1,812 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "NVIDIA Seaboard";
+ compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp", "lm1";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
+ "lsck", "lsda";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lsc0",
+ "lspi", "lvp1", "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "dap1", "dap2",
+ "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
+ "gme", "gpu", "gpu7", "i2cp", "irrx",
+ "irtx", "pta", "rm", "sdc", "sdd",
+ "slxd", "slxk", "spdi", "spdo", "uac",
+ "uad", "uca", "ucb", "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ate {
+ nvidia,pins = "ate", "csus", "dap3",
+ "gpv", "owc", "slxc", "spib", "spid",
+ "spie";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "gmb", "slxa", "spia",
+ "spig", "spih";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,pull = <1>;
+ nvidia,tristate = <0>;
+ };
+ conf_dte {
+ nvidia,pins = "dte", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0";
+ nvidia,tristate = <1>;
+ };
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "spic", "uaa",
+ "uab";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+ "lvs", "pmc", "sdb";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <0>;
+ nvidia,low-power-mode = <3>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <3>;
+ nvidia,slew-rate-falling = <3>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux_i2cmux_pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+
+ state_i2cmux_idle: pinmux_i2cmux_idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+
+ /* ALS and proximity sensor */
+ isl29018@44 {
+ compatible = "isil,isl29018";
+ reg = <0x44>;
+ interrupt-parent = <&gpio>;
+ interrupts = <202 0x04>; /* GPIO PZ2 */
+ };
+
+ gyrometer@68 {
+ compatible = "invn,mpu3050";
+ reg = <0x68>;
+ interrupt-parent = <&gpio>;
+ interrupts = <204 0x04>; /* gpio PZ4 */
+ };
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smart-battery@b {
+ compatible = "ti,bq20z75", "smart-battery-1.1";
+ reg = <0xb>;
+ ti,i2c-retry-count = <2>;
+ ti,poll-retry-count = <10>;
+ };
+ };
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1125000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ };
+
+ magnetometer@c {
+ compatible = "ak,ak8975";
+ reg = <0xc>;
+ interrupt-parent = <&gpio>;
+ interrupts = <109 0x04>; /* gpio PN5 */
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ memory-controller@7000f400 {
+ emc-table@190000 {
+ reg = <190000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <190000>;
+ nvidia,emc-registers = <0x0000000c 0x00000026
+ 0x00000009 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x0000059f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000b 0x000000c8
+ 0x00000003 0x00000007 0x00000004 0x0000000f
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xa06204ae
+ 0x007dc010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@380000 {
+ reg = <380000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <380000>;
+ nvidia,emc-registers = <0x00000017 0x0000004b
+ 0x00000012 0x00000006 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000b5f
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x0000000f
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe044048b
+ 0x007d8010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ dr_mode = "otg";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5004400 {
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ sdhci@c8000000 {
+ status = "okay";
+ power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000400 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio 170 1>; /* gpio PV2, active low */
+ linux,code = <116>; /* KEY_POWER */
+ gpio-key,wakeup;
+ };
+
+ lid {
+ label = "Lid";
+ gpios = <&gpio 23 0>; /* gpio PC7 */
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0>; /* SW_LID */
+ debounce-interval = <1>;
+ gpio-key,wakeup;
+ };
+ };
+
+ kbc {
+ status = "okay";
+ nvidia,debounce-delay-ms = <32>;
+ nvidia,repeat-delay-ms = <160>;
+ nvidia,ghost-filter;
+ nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+ linux,keymap = <0x00020011 /* KEY_W */
+ 0x0003001F /* KEY_S */
+ 0x0004001E /* KEY_A */
+ 0x0005002C /* KEY_Z */
+ 0x000701d0 /* KEY_FN */
+
+ 0x0107007D /* KEY_LEFTMETA */
+ 0x02060064 /* KEY_RIGHTALT */
+ 0x02070038 /* KEY_LEFTALT */
+
+ 0x03000006 /* KEY_5 */
+ 0x03010005 /* KEY_4 */
+ 0x03020013 /* KEY_R */
+ 0x03030012 /* KEY_E */
+ 0x03040021 /* KEY_F */
+ 0x03050020 /* KEY_D */
+ 0x0306002D /* KEY_X */
+
+ 0x04000008 /* KEY_7 */
+ 0x04010007 /* KEY_6 */
+ 0x04020014 /* KEY_T */
+ 0x04030023 /* KEY_H */
+ 0x04040022 /* KEY_G */
+ 0x0405002F /* KEY_V */
+ 0x0406002E /* KEY_C */
+ 0x04070039 /* KEY_SPACE */
+
+ 0x0500000A /* KEY_9 */
+ 0x05010009 /* KEY_8 */
+ 0x05020016 /* KEY_U */
+ 0x05030015 /* KEY_Y */
+ 0x05040024 /* KEY_J */
+ 0x05050031 /* KEY_N */
+ 0x05060030 /* KEY_B */
+ 0x0507002B /* KEY_BACKSLASH */
+
+ 0x0600000C /* KEY_MINUS */
+ 0x0601000B /* KEY_0 */
+ 0x06020018 /* KEY_O */
+ 0x06030017 /* KEY_I */
+ 0x06040026 /* KEY_L */
+ 0x06050025 /* KEY_K */
+ 0x06060033 /* KEY_COMMA */
+ 0x06070032 /* KEY_M */
+
+ 0x0701000D /* KEY_EQUAL */
+ 0x0702001B /* KEY_RIGHTBRACE */
+ 0x0703001C /* KEY_ENTER */
+ 0x0707008B /* KEY_MENU */
+
+ 0x08040036 /* KEY_RIGHTSHIFT */
+ 0x0805002A /* KEY_LEFTSHIFT */
+
+ 0x09050061 /* KEY_RIGHTCTRL */
+ 0x0907001D /* KEY_LEFTCTRL */
+
+ 0x0B00001A /* KEY_LEFTBRACE */
+ 0x0B010019 /* KEY_P */
+ 0x0B020028 /* KEY_APOSTROPHE */
+ 0x0B030027 /* KEY_SEMICOLON */
+ 0x0B040035 /* KEY_SLASH */
+ 0x0B050034 /* KEY_DOT */
+
+ 0x0C000044 /* KEY_F10 */
+ 0x0C010043 /* KEY_F9 */
+ 0x0C02000E /* KEY_BACKSPACE */
+ 0x0C030004 /* KEY_3 */
+ 0x0C040003 /* KEY_2 */
+ 0x0C050067 /* KEY_UP */
+ 0x0C0600D2 /* KEY_PRINT */
+ 0x0C070077 /* KEY_PAUSE */
+
+ 0x0D00006E /* KEY_INSERT */
+ 0x0D01006F /* KEY_DELETE */
+ 0x0D030068 /* KEY_PAGEUP */
+ 0x0D04006D /* KEY_PAGEDOWN */
+ 0x0D05006A /* KEY_RIGHT */
+ 0x0D06006C /* KEY_DOWN */
+ 0x0D070069 /* KEY_LEFT */
+
+ 0x0E000057 /* KEY_F11 */
+ 0x0E010058 /* KEY_F12 */
+ 0x0E020042 /* KEY_F8 */
+ 0x0E030010 /* KEY_Q */
+ 0x0E04003E /* KEY_F4 */
+ 0x0E05003D /* KEY_F3 */
+ 0x0E060002 /* KEY_1 */
+ 0x0E070041 /* KEY_F7 */
+
+ 0x0F000001 /* KEY_ESC */
+ 0x0F010029 /* KEY_GRAVE */
+ 0x0F02003F /* KEY_F5 */
+ 0x0F03000F /* KEY_TAB */
+ 0x0F04003B /* KEY_F1 */
+ 0x0F05003C /* KEY_F2 */
+ 0x0F06003A /* KEY_CAPSLOCK */
+ 0x0F070040 /* KEY_F6 */
+
+ /* Software Handled Function Keys */
+ 0x14000047 /* KEY_KP7 */
+
+ 0x15000049 /* KEY_KP9 */
+ 0x15010048 /* KEY_KP8 */
+ 0x1502004B /* KEY_KP4 */
+ 0x1504004F /* KEY_KP1 */
+
+ 0x1601004E /* KEY_KPSLASH */
+ 0x1602004D /* KEY_KP6 */
+ 0x1603004C /* KEY_KP5 */
+ 0x16040051 /* KEY_KP3 */
+ 0x16050050 /* KEY_KP2 */
+ 0x16070052 /* KEY_KP0 */
+
+ 0x1B010037 /* KEY_KPASTERISK */
+ 0x1B03004A /* KEY_KPMINUS */
+ 0x1B04004E /* KEY_KPPLUS */
+ 0x1B050053 /* KEY_KPDOT */
+
+ 0x1C050073 /* KEY_VOLUMEUP */
+
+ 0x1D030066 /* KEY_HOME */
+ 0x1D04006B /* KEY_END */
+ 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
+ 0x1D060072 /* KEY_VOLUMEDOWN */
+ 0x1D0700E1 /* KEY_BRIGHTNESSUP */
+
+ 0x1E000045 /* KEY_NUMLOCK */
+ 0x1E010046 /* KEY_SCROLLLOCK */
+ 0x1E020071 /* KEY_MUTE */
+
+ 0x1F04008A>; /* KEY_HELP */
+ };
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-seaboard",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "NVIDIA Tegra Seaboard";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1R", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
deleted file mode 100644
index 4766aba..0000000
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ /dev/null
@@ -1,489 +0,0 @@
-/include/ "tegra20.dtsi"
-
-/ {
- model = "Avionic Design Tamonten SOM";
- compatible = "ad,tamonten", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- host1x {
- hdmi {
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata";
- nvidia,function = "ide";
- };
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- };
- atc {
- nvidia,pins = "atc";
- nvidia,function = "nand";
- };
- atd {
- nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
- "spia", "spib", "spic";
- nvidia,function = "gmi";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- dta {
- nvidia,pins = "dta", "dtd";
- nvidia,function = "sdio2";
- };
- dtb {
- nvidia,pins = "dtb", "dtc", "dte";
- nvidia,function = "rsvd1";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gmc {
- nvidia,pins = "gmc";
- nvidia,function = "uartd";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uarta";
- };
- kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- lcsn {
- nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
- "ld3", "ld4", "ld5", "ld6", "ld7",
- "ld8", "ld9", "ld10", "ld11", "ld12",
- "ld13", "ld14", "ld15", "ld16", "ld17",
- "ldc", "ldi", "lhp0", "lhp1", "lhp2",
- "lhs", "lm0", "lm1", "lpp", "lpw0",
- "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
- "lsda", "lsdi", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "spdi", "spdo", "uac";
- nvidia,function = "rsvd2";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd";
- nvidia,function = "pwm";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxc {
- nvidia,pins = "slxc", "slxd";
- nvidia,function = "spdif";
- };
- spid {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "atd", "ate",
- "cdev1", "cdev2", "dap1", "dtb", "gma",
- "gmb", "gmc", "gmd", "gme", "gpu7",
- "gpv", "i2cp", "pta", "rm", "slxa",
- "slxk", "spia", "spib", "uac";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_csus {
- nvidia,pins = "csus", "spid", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_crtp {
- nvidia,pins = "crtp", "dap2", "dap3", "dap4",
- "dtc", "dte", "dtf", "gpu", "sdio1",
- "slxc", "slxd", "spdi", "spdo", "spig",
- "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_ddc {
- nvidia,pins = "ddc", "dta", "dtd", "kbca",
- "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
- "sdc";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
- "lpw1", "lsc1", "lsck", "lsda", "lsdi",
- "lvp0", "owc", "sdb";
- nvidia,tristate = <1>;
- };
- conf_irrx {
- nvidia,pins = "irrx", "irtx", "sdd", "spic",
- "spie", "spih", "uaa", "uab", "uad",
- "uca", "ucb";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lm0", "lpp",
- "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
- "lvs", "pmc";
- nvidia,tristate = <0>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- };
-
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
-
- state_i2cmux_pta: pinmux_i2cmux_pta {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "i2c2";
- };
- };
-
- state_i2cmux_idle: pinmux_i2cmux_idle {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006300 {
- status = "okay";
- };
-
- i2c@7000c000 {
- clock-frequency = <400000>;
- status = "okay";
- };
-
- i2c@7000c400 {
- clock-frequency = <100000>;
- status = "okay";
- };
-
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- i2c@7000d000 {
- clock-frequency = <400000>;
- status = "okay";
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&vdd_5v0_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- sys_reg: sys {
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- sm0 {
- regulator-name = "vdd_sys_sm0,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- sm1 {
- regulator-name = "vdd_sys_sm1,vdd_cpu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sm2_reg: sm2 {
- regulator-name = "vdd_sys_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- ldo0 {
- regulator-name = "vdd_ldo0,vddio_pex_clk";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo1 {
- regulator-name = "vdd_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "vdd_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3 {
- regulator-name = "vdd_ldo3,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "vdd_ldo5,vcore_mmc";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- ldo6 {
- regulator-name = "vdd_ldo6,avdd_vdac";
- /*
- * According to the Tegra 2 Automotive
- * DataSheet, a typical value for this
- * would be 2.8V, but the PMIC only
- * supports 2.85V.
- */
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- hdmi_vdd_reg: ldo7 {
- regulator-name = "vdd_ldo7,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: ldo8 {
- regulator-name = "vdd_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo9 {
- regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
- /*
- * According to the Tegra 2 Automotive
- * DataSheet, a typical value for this
- * would be 2.8V, but the PMIC only
- * supports 2.85V.
- */
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo_rtc {
- regulator-name = "vdd_rtc_out";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- sdhci@c8000600 {
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
- bus-width = <4>;
- status = "okay";
- };
-
- regulators {
- compatible = "simple-bus";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
new file mode 100644
index 0000000..089bbec
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -0,0 +1,489 @@
+#include "tegra20.dtsip"
+
+/ {
+ model = "Avionic Design Tamonten SOM";
+ compatible = "ad,tamonten", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ host1x {
+ hdmi {
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+ "spia", "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtd";
+ nvidia,function = "sdio2";
+ };
+ dtb {
+ nvidia,pins = "dtb", "dtc", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "pwm";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dtb", "gma",
+ "gmb", "gmc", "gmd", "gme", "gpu7",
+ "gpv", "i2cp", "pta", "rm", "slxa",
+ "slxk", "spia", "spib", "uac";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spid", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+ "dtc", "dte", "dtf", "gpu", "sdio1",
+ "slxc", "slxd", "spdi", "spdo", "spig",
+ "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "dta", "dtd", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "sdc";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "owc", "sdb";
+ nvidia,tristate = <1>;
+ };
+ conf_irrx {
+ nvidia,pins = "irrx", "irtx", "sdd", "spic",
+ "spie", "spih", "uaa", "uab", "uad",
+ "uca", "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+ "lvs", "pmc";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux_i2cmux_pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+
+ state_i2cmux_idle: pinmux_i2cmux_idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ status = "okay";
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <100000>;
+ status = "okay";
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "vdd_sys_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "vdd_sys_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sys_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ ldo0 {
+ regulator-name = "vdd_ldo0,vddio_pex_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ /*
+ * According to the Tegra 2 Automotive
+ * DataSheet, a typical value for this
+ * would be 2.8V, but the PMIC only
+ * supports 2.85V.
+ */
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+ /*
+ * According to the Tegra 2 Automotive
+ * DataSheet, a typical value for this
+ * would be 2.8V, but the PMIC only
+ * supports 2.85V.
+ */
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ sdhci@c8000600 {
+ cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+ wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ bus-width = <4>;
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
deleted file mode 100644
index 402b210..0000000
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ /dev/null
@@ -1,56 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20-tamonten.dtsi"
-
-/ {
- model = "Avionic Design Tamonten Evaluation Carrier";
- compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
-
- host1x {
- hdmi {
- status = "okay";
- };
- };
-
- i2c@7000c000 {
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff
- 0xffffffff
- 0
- 0xffffffff
- 0xffffffff>;
- };
- };
-
- sound {
- compatible = "ad,tegra-audio-wm8903-tec",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "Avionic Design TEC";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
new file mode 100644
index 0000000..331c81a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -0,0 +1,56 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsip"
+
+/ {
+ model = "Avionic Design Tamonten Evaluation Carrier";
+ compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+
+ host1x {
+ hdmi {
+ status = "okay";
+ };
+ };
+
+ i2c@7000c000 {
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-wm8903-tec",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design TEC";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
deleted file mode 100644
index 5d79e4f..0000000
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ /dev/null
@@ -1,367 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "Compulab TrimSlice board";
- compatible = "compulab,trimslice", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x40000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata";
- nvidia,function = "ide";
- };
- atb {
- nvidia,pins = "atb", "gma";
- nvidia,function = "sdio4";
- };
- atc {
- nvidia,pins = "atc", "gmb";
- nvidia,function = "nand";
- };
- atd {
- nvidia,pins = "atd", "ate", "gme", "pta";
- nvidia,function = "gmi";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
- nvidia,function = "vi";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gmc {
- nvidia,pins = "gmc", "gmd";
- nvidia,function = "sflash";
- };
- gpu {
- nvidia,pins = "gpu";
- nvidia,function = "uarta";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uartb";
- };
- kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- lcsn {
- nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
- "ld3", "ld4", "ld5", "ld6", "ld7",
- "ld8", "ld9", "ld10", "ld11", "ld12",
- "ld13", "ld14", "ld15", "ld16", "ld17",
- "ldc", "ldi", "lhp0", "lhp1", "lhp2",
- "lhs", "lm0", "lm1", "lpp", "lpw0",
- "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
- "lsda", "lsdi", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "uac";
- nvidia,function = "rsvd2";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd";
- nvidia,function = "pwm";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxc {
- nvidia,pins = "slxc", "slxd";
- nvidia,function = "sdio3";
- };
- spdi {
- nvidia,pins = "spdi", "spdo";
- nvidia,function = "spdif";
- };
- spia {
- nvidia,pins = "spia", "spib", "spic";
- nvidia,function = "spi2";
- };
- spid {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atc", "atd", "ate",
- "crtp", "dap2", "dap3", "dap4", "dta",
- "dtb", "dtc", "dtd", "dte", "gmb",
- "gme", "i2cp", "pta", "slxc", "slxd",
- "spdi", "spdo", "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_atb {
- nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
- "gma", "gmc", "gmd", "gpu", "gpu7",
- "gpv", "sdio1", "slxa", "slxk", "uac";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_csus {
- nvidia,pins = "csus", "spia", "spib",
- "spid", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_ddc {
- nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
- "lpw1", "lsc1", "lsck", "lsda", "lsdi",
- "lvp0", "pmc";
- nvidia,tristate = <1>;
- };
- conf_irrx {
- nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
- "kbcc", "kbcd", "kbce", "kbcf", "owc",
- "spic", "spie", "spig", "spih", "uaa",
- "uab", "uad", "uca", "ucb";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lm0", "lpp",
- "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
- "lvs", "sdb";
- nvidia,tristate = <0>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- conf_spif {
- nvidia,pins = "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- dvi_ddc: i2c@7000c000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- spi@7000c380 {
- status = "okay";
- spi-max-frequency = <48000000>;
- spi-flash@0 {
- compatible = "winbond,w25q80bl";
- reg = <0>;
- spi-max-frequency = <48000000>;
- };
- };
-
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <400000>;
-
- codec: codec@1a {
- compatible = "ti,tlv320aic23";
- reg = <0x1a>;
- };
-
- rtc@56 {
- compatible = "emmicro,em3027";
- reg = <0x56>;
- };
- };
-
- usb@c5000000 {
- status = "okay";
- nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- };
-
- sdhci@c8000000 {
- status = "okay";
- bus-width = <4>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- cd-gpios = <&gpio 121 0>; /* gpio PP1 */
- wp-gpios = <&gpio 122 0>; /* gpio PP2 */
- bus-width = <4>;
- };
-
- poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio 191 1>; /* gpio PX7, active low */
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi_vdd_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- hdmi_pll_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-trimslice";
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&codec>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dtsp b/arch/arm/boot/dts/tegra20-trimslice.dtsp
new file mode 100644
index 0000000..1f6cd20
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
@@ -0,0 +1,367 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "Compulab TrimSlice board";
+ compatible = "compulab,trimslice", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc", "gmb";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gme", "pta";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc", "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "uarta";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "pwm";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "sdio3";
+ };
+ spdi {
+ nvidia,pins = "spdi", "spdo";
+ nvidia,function = "spdif";
+ };
+ spia {
+ nvidia,pins = "spia", "spib", "spic";
+ nvidia,function = "spi2";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "crtp", "dap2", "dap3", "dap4", "dta",
+ "dtb", "dtc", "dtd", "dte", "gmb",
+ "gme", "i2cp", "pta", "slxc", "slxd",
+ "spdi", "spdo", "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_atb {
+ nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
+ "gma", "gmc", "gmd", "gpu", "gpu7",
+ "gpv", "sdio1", "slxa", "slxk", "uac";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spia", "spib",
+ "spid", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "pmc";
+ nvidia,tristate = <1>;
+ };
+ conf_irrx {
+ nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
+ "kbcc", "kbcd", "kbce", "kbcf", "owc",
+ "spic", "spie", "spig", "spih", "uaa",
+ "uab", "uad", "uca", "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+ "lvs", "sdb";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ conf_spif {
+ nvidia,pins = "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ dvi_ddc: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ spi@7000c380 {
+ status = "okay";
+ spi-max-frequency = <48000000>;
+ spi-flash@0 {
+ compatible = "winbond,w25q80bl";
+ reg = <0>;
+ spi-max-frequency = <48000000>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ codec: codec@1a {
+ compatible = "ti,tlv320aic23";
+ reg = <0x1a>;
+ };
+
+ rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5004400 {
+ nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ };
+
+ sdhci@c8000000 {
+ status = "okay";
+ bus-width = <4>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+ wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+ bus-width = <4>;
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 191 1>; /* gpio PX7, active low */
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_vdd_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ hdmi_pll_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-trimslice";
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&codec>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
deleted file mode 100644
index 425c890..0000000
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ /dev/null
@@ -1,611 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "NVIDIA Tegra20 Ventana evaluation board";
- compatible = "nvidia,ventana", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x40000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata";
- nvidia,function = "ide";
- };
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- };
- atc {
- nvidia,pins = "atc";
- nvidia,function = "nand";
- };
- atd {
- nvidia,pins = "atd", "ate", "gmb", "spia",
- "spib", "spic";
- nvidia,function = "gmi";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "pllp_out4";
- };
- crtp {
- nvidia,pins = "crtp", "lm1";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
- nvidia,function = "vi";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gmc {
- nvidia,pins = "gmc";
- nvidia,function = "uartd";
- };
- gmd {
- nvidia,pins = "gmd";
- nvidia,function = "sflash";
- };
- gpu {
- nvidia,pins = "gpu";
- nvidia,function = "pwm";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv", "slxa", "slxk";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uartb";
- };
- kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- lcsn {
- nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
- "lsdi", "lvp0";
- nvidia,function = "rsvd4";
- };
- ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lpp", "lpw0",
- "lpw2", "lsc0", "lsc1", "lsck", "lsda",
- "lspi", "lvp1", "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "spdi", "spdo", "uac";
- nvidia,function = "rsvd2";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd", "slxc";
- nvidia,function = "sdio3";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- slxd {
- nvidia,pins = "slxd";
- nvidia,function = "spdif";
- };
- spid {
- nvidia,pins = "spid", "spie", "spif";
- nvidia,function = "spi1";
- };
- spig {
- nvidia,pins = "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- uaa {
- nvidia,pins = "uaa", "uab", "uda";
- nvidia,function = "ulpi";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "atd",
- "cdev1", "cdev2", "dap1", "dap2",
- "dap4", "ddc", "dtf", "gma", "gmc",
- "gme", "gpu", "gpu7", "i2cp", "irrx",
- "irtx", "pta", "rm", "sdc", "sdd",
- "slxc", "slxd", "slxk", "spdi", "spdo",
- "uac", "uad", "uca", "ucb", "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_ate {
- nvidia,pins = "ate", "csus", "dap3", "gmd",
- "gpv", "owc", "spia", "spib", "spic",
- "spid", "spie", "spig";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
- "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
- nvidia,pull = <0>;
- };
- conf_crtp {
- nvidia,pins = "crtp", "gmb", "slxa", "spih";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- };
- conf_dte {
- nvidia,pins = "dte", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_hdint {
- nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
- "lpw1", "lsck", "lsda", "lsdi", "lvp0";
- nvidia,tristate = <1>;
- };
- conf_kbca {
- nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
- "kbce", "kbcf", "sdio1", "uaa", "uab";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_lc {
- nvidia,pins = "lc", "ls";
- nvidia,pull = <2>;
- };
- conf_ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldi", "lhp0",
- "lhp1", "lhp2", "lhs", "lm0", "lpp",
- "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
- "lvp1", "lvs", "pmc", "sdb";
- nvidia,tristate = <0>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- drive_sdio1 {
- nvidia,pins = "drive_sdio1";
- nvidia,high-speed-mode = <0>;
- nvidia,schmitt = <1>;
- nvidia,low-power-mode = <3>;
- nvidia,pull-down-strength = <31>;
- nvidia,pull-up-strength = <31>;
- nvidia,slew-rate-rising = <3>;
- nvidia,slew-rate-falling = <3>;
- };
- };
-
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
-
- state_i2cmux_pta: pinmux_i2cmux_pta {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "i2c2";
- };
- };
-
- state_i2cmux_idle: pinmux_i2cmux_idle {
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "rsvd4";
- };
- pta {
- nvidia,pins = "pta";
- nvidia,function = "rsvd4";
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006300 {
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <400000>;
-
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
-
- /* ALS and proximity sensor */
- isl29018@44 {
- compatible = "isil,isl29018";
- reg = <0x44>;
- interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /*gpio PZ2 */
- };
- };
-
- i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <400000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <400000>;
-
- pmic: tps6586x@34 {
- compatible = "ti,tps6586x";
- reg = <0x34>;
- interrupts = <0 86 0x4>;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- sys-supply = <&vdd_5v0_reg>;
- vin-sm0-supply = <&sys_reg>;
- vin-sm1-supply = <&sys_reg>;
- vin-sm2-supply = <&sys_reg>;
- vinldo01-supply = <&sm2_reg>;
- vinldo23-supply = <&sm2_reg>;
- vinldo4-supply = <&sm2_reg>;
- vinldo678-supply = <&sm2_reg>;
- vinldo9-supply = <&sm2_reg>;
-
- regulators {
- sys_reg: sys {
- regulator-name = "vdd_sys";
- regulator-always-on;
- };
-
- sm0 {
- regulator-name = "vdd_sm0,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- sm1 {
- regulator-name = "vdd_sm1,vdd_cpu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sm2_reg: sm2 {
- regulator-name = "vdd_sm2,vin_ldo*";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
- };
-
- /* LDO0 is not connected to anything */
-
- ldo1 {
- regulator-name = "vdd_ldo1,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "vdd_ldo2,vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3 {
- regulator-name = "vdd_ldo3,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "vdd_ldo5,vcore_mmc";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo6 {
- regulator-name = "vdd_ldo6,avdd_vdac";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- hdmi_vdd_reg: ldo7 {
- regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_pll_reg: ldo8 {
- regulator-name = "vdd_ldo8,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo9 {
- regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
-
- ldo_rtc {
- regulator-name = "vdd_rtc_out,vdd_cell";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- usb@c5000000 {
- status = "okay";
- };
-
- usb@c5004000 {
- status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
- };
-
- sdhci@c8000000 {
- status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
- bus-width = <4>;
- };
-
- sdhci@c8000400 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
- bus-width = <4>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 0>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 0>;
- enable-active-high;
- };
-
- regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_pnl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
- enable-active-high;
- };
-
- regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
- enable-active-high;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-ventana",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "NVIDIA Tegra Ventana";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
new file mode 100644
index 0000000..a5ae217
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -0,0 +1,611 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "NVIDIA Tegra20 Ventana evaluation board";
+ compatible = "nvidia,ventana", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp", "lm1";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lpw0",
+ "lpw2", "lsc0", "lsc1", "lsck", "lsda",
+ "lspi", "lvp1", "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxd {
+ nvidia,pins = "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "dap1", "dap2",
+ "dap4", "ddc", "dtf", "gma", "gmc",
+ "gme", "gpu", "gpu7", "i2cp", "irrx",
+ "irtx", "pta", "rm", "sdc", "sdd",
+ "slxc", "slxd", "slxk", "spdi", "spdo",
+ "uac", "uad", "uca", "ucb", "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ate {
+ nvidia,pins = "ate", "csus", "dap3", "gmd",
+ "gpv", "owc", "spia", "spib", "spic",
+ "spid", "spie", "spig";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "gmb", "slxa", "spih";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,pull = <1>;
+ nvidia,tristate = <0>;
+ };
+ conf_dte {
+ nvidia,pins = "dte", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsck", "lsda", "lsdi", "lvp0";
+ nvidia,tristate = <1>;
+ };
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "uaa", "uab";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+ "lvp1", "lvs", "pmc", "sdb";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <1>;
+ nvidia,low-power-mode = <3>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <3>;
+ nvidia,slew-rate-falling = <3>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux_i2cmux_pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+
+ state_i2cmux_idle: pinmux_i2cmux_idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+
+ /* ALS and proximity sensor */
+ isl29018@44 {
+ compatible = "isil,isl29018";
+ reg = <0x44>;
+ interrupt-parent = <&gpio>;
+ interrupts = <202 0x04>; /*gpio PZ2 */
+ };
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5004400 {
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ };
+
+ sdhci@c8000000 {
+ status = "okay";
+ power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000400 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ bus-width = <4>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 22 0>; /* gpio PC6 */
+ enable-active-high;
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 176 0>; /* gpio PW0 */
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-ventana",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "NVIDIA Tegra Ventana";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
+ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
deleted file mode 100644
index ea57c0f..0000000
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ /dev/null
@@ -1,563 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra20.dtsi"
-
-/ {
- model = "NVIDIA Tegra20 Whistler evaluation board";
- compatible = "nvidia,whistler", "nvidia,tegra20";
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- host1x {
- hdmi {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
- };
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
- "gmc", "gmd", "gpu";
- nvidia,function = "gmi";
- };
- atc {
- nvidia,pins = "atc", "atd";
- nvidia,function = "sdio4";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "osc";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd";
- nvidia,function = "vi";
- };
- dte {
- nvidia,pins = "dte";
- nvidia,function = "rsvd1";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gme {
- nvidia,pins = "gme";
- nvidia,function = "dap5";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint", "pta";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uartb";
- };
- kbca {
- nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- kbcb {
- nvidia,pins = "kbcb", "kbcd";
- nvidia,function = "sdio2";
- };
- lcsn {
- nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
- "spia", "spib", "spic";
- nvidia,function = "spi3";
- };
- ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldc", "ldi",
- "lhp0", "lhp1", "lhp2", "lhs", "lm0",
- "lm1", "lpp", "lpw0", "lpw1", "lpw2",
- "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "uac";
- nvidia,function = "owr";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd", "slxa",
- "slxc", "slxd", "slxk";
- nvidia,function = "sdio3";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- spdi {
- nvidia,pins = "spdi", "spdo";
- nvidia,function = "rsvd2";
- };
- spid {
- nvidia,pins = "spid", "spie", "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- spif {
- nvidia,pins = "spif";
- nvidia,function = "spi2";
- };
- uaa {
- nvidia,pins = "uaa", "uab";
- nvidia,function = "uarta";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- uda {
- nvidia,pins = "uda";
- nvidia,function = "spi1";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
- "gmb", "gmc", "gmd", "irrx", "irtx",
- "kbca", "kbcb", "kbcc", "kbcd", "kbce",
- "kbcf", "sdc", "sdd", "spie", "spig",
- "spih", "uaa", "uab", "uad", "uca",
- "ucb";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- conf_atd {
- nvidia,pins = "atd", "ate", "cdev1", "csus",
- "dap1", "dap2", "dap3", "dap4", "dte",
- "dtf", "gpu", "gpu7", "gpv", "i2cp",
- "rm", "sdio1", "slxa", "slxc", "slxd",
- "slxk", "spdi", "spdo", "uac", "uda";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- conf_cdev2 {
- nvidia,pins = "cdev2", "spia", "spib";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "lc", "pmca",
- "pmcb", "pmcc", "pmcd", "xm2c",
- "xm2d";
- nvidia,pull = <0>;
- };
- conf_crtp {
- nvidia,pins = "crtp";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- };
- conf_dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd",
- "spid", "spif";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- };
- conf_gme {
- nvidia,pins = "gme", "owc", "pta", "spic";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <1>;
- };
- conf_ls {
- nvidia,pins = "ls", "pmce";
- nvidia,pull = <2>;
- };
- drive_dap1 {
- nvidia,pins = "drive_dap1";
- nvidia,high-speed-mode = <0>;
- nvidia,schmitt = <1>;
- nvidia,low-power-mode = <0>;
- nvidia,pull-down-strength = <0>;
- nvidia,pull-up-strength = <0>;
- nvidia,slew-rate-rising = <0>;
- nvidia,slew-rate-falling = <0>;
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <100000>;
-
- codec: codec@1a {
- compatible = "wlf,wm8753";
- reg = <0x1a>;
- };
-
- tca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max8907@3c {
- compatible = "maxim,max8907";
- reg = <0x3c>;
- interrupts = <0 86 0x4>;
-
- maxim,system-power-controller;
-
- mbatt-supply = <&usb0_vbus_reg>;
- in-v1-supply = <&mbatt_reg>;
- in-v2-supply = <&mbatt_reg>;
- in-v3-supply = <&mbatt_reg>;
- in1-supply = <&mbatt_reg>;
- in2-supply = <&nvvdd_sv3_reg>;
- in3-supply = <&mbatt_reg>;
- in4-supply = <&mbatt_reg>;
- in5-supply = <&mbatt_reg>;
- in6-supply = <&mbatt_reg>;
- in7-supply = <&mbatt_reg>;
- in8-supply = <&mbatt_reg>;
- in9-supply = <&mbatt_reg>;
- in10-supply = <&mbatt_reg>;
- in11-supply = <&mbatt_reg>;
- in12-supply = <&mbatt_reg>;
- in13-supply = <&mbatt_reg>;
- in14-supply = <&mbatt_reg>;
- in15-supply = <&mbatt_reg>;
- in16-supply = <&mbatt_reg>;
- in17-supply = <&nvvdd_sv3_reg>;
- in18-supply = <&nvvdd_sv3_reg>;
- in19-supply = <&mbatt_reg>;
- in20-supply = <&mbatt_reg>;
-
- regulators {
- mbatt_reg: mbatt {
- regulator-name = "vbat_pmu";
- regulator-always-on;
- };
-
- sd1 {
- regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sd2 {
- regulator-name = "nvvdd_sv2,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- nvvdd_sv3_reg: sd3 {
- regulator-name = "nvvdd_sv3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo1 {
- regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "nvvdd_ldo2,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo3 {
- regulator-name = "nvvdd_ldo3,vcom_1v8b";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "nvvdd_ldo4,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- hdmi_pll_reg: ldo6 {
- regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo7 {
- regulator-name = "nvvdd_ldo7,avddio_audio";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo8 {
- regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo9 {
- regulator-name = "nvvdd_ldo9,avdd_cam*";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo10 {
- regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- hdmi_vdd_reg: ldo11 {
- regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo12 {
- regulator-name = "nvvdd_ldo12,vddio_sdio";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo13 {
- regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo14 {
- regulator-name = "nvvdd_ldo14,avdd_vdac";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo15 {
- regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo16 {
- regulator-name = "nvvdd_ldo16,vdd_dbrtr";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- ldo17 {
- regulator-name = "nvvdd_ldo17,vddio_mipi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo18 {
- regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo19 {
- regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo20 {
- regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- out5v {
- regulator-name = "usb0_vbus_reg";
- };
-
- out33v {
- regulator-name = "pmu_out3v3";
- };
-
- bbat {
- regulator-name = "pmu_bbat";
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <2400000>;
- regulator-always-on;
- };
-
- sdby {
- regulator-name = "vdd_aon";
- regulator-always-on;
- };
-
- vrtc {
- regulator-name = "vrtc,pmu_vccadc";
- regulator-always-on;
- };
- };
- };
- };
-
- pmc {
- nvidia,invert-interrupt;
- };
-
- usb@c5000000 {
- status = "okay";
- nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
- };
-
- usb@c5008000 {
- status = "okay";
- nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
- };
-
- sdhci@c8000400 {
- status = "okay";
- wp-gpios = <&gpio 173 0>; /* gpio PV5 */
- bus-width = <8>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- kbc {
- status = "okay";
- nvidia,debounce-delay-ms = <20>;
- nvidia,repeat-delay-ms = <160>;
- nvidia,kbc-row-pins = <0 1 2>;
- nvidia,kbc-col-pins = <16 17>;
- linux,keymap = <0x00000074 /* KEY_POWER */
- 0x01000066 /* KEY_HOME */
- 0x0101009E /* KEY_BACK */
- 0x0201008B>; /* KEY_MENU */
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb0_vbus_reg: regulator {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb0_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8753-whistler",
- "nvidia,tegra-audio-wm8753";
- nvidia,model = "NVIDIA Tegra Whistler";
-
- nvidia,audio-routing =
- "Headphone Jack", "LOUT1",
- "Headphone Jack", "ROUT1",
- "MIC2", "Mic Jack",
- "MIC2N", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&codec>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
new file mode 100644
index 0000000..ee24daa
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -0,0 +1,563 @@
+/dts-v1/;
+
+#include "tegra20.dtsip"
+
+/ {
+ model = "NVIDIA Tegra20 Whistler evaluation board";
+ compatible = "nvidia,whistler", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
+ "gmc", "gmd", "gpu";
+ nvidia,function = "gmi";
+ };
+ atc {
+ nvidia,pins = "atc", "atd";
+ nvidia,function = "sdio4";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "osc";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,function = "vi";
+ };
+ dte {
+ nvidia,pins = "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gme {
+ nvidia,pins = "gme";
+ nvidia,function = "dap5";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ kbcb {
+ nvidia,pins = "kbcb", "kbcd";
+ nvidia,function = "sdio2";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
+ "spia", "spib", "spic";
+ nvidia,function = "spi3";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldc", "ldi",
+ "lhp0", "lhp1", "lhp2", "lhs", "lm0",
+ "lm1", "lpp", "lpw0", "lpw1", "lpw2",
+ "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "uac";
+ nvidia,function = "owr";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxa",
+ "slxc", "slxd", "slxk";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ spdi {
+ nvidia,pins = "spdi", "spdo";
+ nvidia,function = "rsvd2";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ spif {
+ nvidia,pins = "spif";
+ nvidia,function = "spi2";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab";
+ nvidia,function = "uarta";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ uda {
+ nvidia,pins = "uda";
+ nvidia,function = "spi1";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
+ "gmb", "gmc", "gmd", "irrx", "irtx",
+ "kbca", "kbcb", "kbcc", "kbcd", "kbce",
+ "kbcf", "sdc", "sdd", "spie", "spig",
+ "spih", "uaa", "uab", "uad", "uca",
+ "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_atd {
+ nvidia,pins = "atd", "ate", "cdev1", "csus",
+ "dap1", "dap2", "dap3", "dap4", "dte",
+ "dtf", "gpu", "gpu7", "gpv", "i2cp",
+ "rm", "sdio1", "slxa", "slxc", "slxd",
+ "slxk", "spdi", "spdo", "uac", "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_cdev2 {
+ nvidia,pins = "cdev2", "spia", "spib";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "lc", "pmca",
+ "pmcb", "pmcc", "pmcd", "xm2c",
+ "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd",
+ "spid", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <0>;
+ };
+ conf_gme {
+ nvidia,pins = "gme", "owc", "pta", "spic";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ conf_ls {
+ nvidia,pins = "ls", "pmce";
+ nvidia,pull = <2>;
+ };
+ drive_dap1 {
+ nvidia,pins = "drive_dap1";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <1>;
+ nvidia,low-power-mode = <0>;
+ nvidia,pull-down-strength = <0>;
+ nvidia,pull-up-strength = <0>;
+ nvidia,slew-rate-rising = <0>;
+ nvidia,slew-rate-falling = <0>;
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ codec: codec@1a {
+ compatible = "wlf,wm8753";
+ reg = <0x1a>;
+ };
+
+ tca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max8907@3c {
+ compatible = "maxim,max8907";
+ reg = <0x3c>;
+ interrupts = <0 86 0x4>;
+
+ maxim,system-power-controller;
+
+ mbatt-supply = <&usb0_vbus_reg>;
+ in-v1-supply = <&mbatt_reg>;
+ in-v2-supply = <&mbatt_reg>;
+ in-v3-supply = <&mbatt_reg>;
+ in1-supply = <&mbatt_reg>;
+ in2-supply = <&nvvdd_sv3_reg>;
+ in3-supply = <&mbatt_reg>;
+ in4-supply = <&mbatt_reg>;
+ in5-supply = <&mbatt_reg>;
+ in6-supply = <&mbatt_reg>;
+ in7-supply = <&mbatt_reg>;
+ in8-supply = <&mbatt_reg>;
+ in9-supply = <&mbatt_reg>;
+ in10-supply = <&mbatt_reg>;
+ in11-supply = <&mbatt_reg>;
+ in12-supply = <&mbatt_reg>;
+ in13-supply = <&mbatt_reg>;
+ in14-supply = <&mbatt_reg>;
+ in15-supply = <&mbatt_reg>;
+ in16-supply = <&mbatt_reg>;
+ in17-supply = <&nvvdd_sv3_reg>;
+ in18-supply = <&nvvdd_sv3_reg>;
+ in19-supply = <&mbatt_reg>;
+ in20-supply = <&mbatt_reg>;
+
+ regulators {
+ mbatt_reg: mbatt {
+ regulator-name = "vbat_pmu";
+ regulator-always-on;
+ };
+
+ sd1 {
+ regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sd2 {
+ regulator-name = "nvvdd_sv2,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ nvvdd_sv3_reg: sd3 {
+ regulator-name = "nvvdd_sv3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1 {
+ regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "nvvdd_ldo2,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo3 {
+ regulator-name = "nvvdd_ldo3,vcom_1v8b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "nvvdd_ldo4,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ hdmi_pll_reg: ldo6 {
+ regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo7 {
+ regulator-name = "nvvdd_ldo7,avddio_audio";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo8 {
+ regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo9 {
+ regulator-name = "nvvdd_ldo9,avdd_cam*";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo10 {
+ regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ hdmi_vdd_reg: ldo11 {
+ regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo12 {
+ regulator-name = "nvvdd_ldo12,vddio_sdio";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo13 {
+ regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo14 {
+ regulator-name = "nvvdd_ldo14,avdd_vdac";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo15 {
+ regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo16 {
+ regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ ldo17 {
+ regulator-name = "nvvdd_ldo17,vddio_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo18 {
+ regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo19 {
+ regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo20 {
+ regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ out5v {
+ regulator-name = "usb0_vbus_reg";
+ };
+
+ out33v {
+ regulator-name = "pmu_out3v3";
+ };
+
+ bbat {
+ regulator-name = "pmu_bbat";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-always-on;
+ };
+
+ sdby {
+ regulator-name = "vdd_aon";
+ regulator-always-on;
+ };
+
+ vrtc {
+ regulator-name = "vrtc,pmu_vccadc";
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+ };
+
+ sdhci@c8000400 {
+ status = "okay";
+ wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+ bus-width = <8>;
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ kbc {
+ status = "okay";
+ nvidia,debounce-delay-ms = <20>;
+ nvidia,repeat-delay-ms = <160>;
+ nvidia,kbc-row-pins = <0 1 2>;
+ nvidia,kbc-col-pins = <16 17>;
+ linux,keymap = <0x00000074 /* KEY_POWER */
+ 0x01000066 /* KEY_HOME */
+ 0x0101009E /* KEY_BACK */
+ 0x0201008B>; /* KEY_MENU */
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb0_vbus_reg: regulator {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8753-whistler",
+ "nvidia,tegra-audio-wm8753";
+ nvidia,model = "NVIDIA Tegra Whistler";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "LOUT1",
+ "Headphone Jack", "ROUT1",
+ "MIC2", "Mic Jack",
+ "MIC2N", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&codec>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
deleted file mode 100644
index 5916c93..0000000
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ /dev/null
@@ -1,556 +0,0 @@
-/include/ "skeleton.dtsi"
-
-/ {
- compatible = "nvidia,tegra20";
- interrupt-parent = <&intc>;
-
- aliases {
- serial0 = &uarta;
- serial1 = &uartb;
- serial2 = &uartc;
- serial3 = &uartd;
- serial4 = &uarte;
- };
-
- host1x {
- compatible = "nvidia,tegra20-host1x", "simple-bus";
- reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
- clocks = <&tegra_car 28>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x04000000>;
-
- mpe {
- compatible = "nvidia,tegra20-mpe";
- reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
- clocks = <&tegra_car 60>;
- };
-
- vi {
- compatible = "nvidia,tegra20-vi";
- reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
- clocks = <&tegra_car 100>;
- };
-
- epp {
- compatible = "nvidia,tegra20-epp";
- reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
- clocks = <&tegra_car 19>;
- };
-
- isp {
- compatible = "nvidia,tegra20-isp";
- reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
- clocks = <&tegra_car 23>;
- };
-
- gr2d {
- compatible = "nvidia,tegra20-gr2d";
- reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
- clocks = <&tegra_car 21>;
- };
-
- gr3d {
- compatible = "nvidia,tegra20-gr3d";
- reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car 24>;
- };
-
- dc@54200000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
- clocks = <&tegra_car 27>, <&tegra_car 121>;
- clock-names = "disp1", "parent";
-
- rgb {
- status = "disabled";
- };
- };
-
- dc@54240000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
- clocks = <&tegra_car 26>, <&tegra_car 121>;
- clock-names = "disp2", "parent";
-
- rgb {
- status = "disabled";
- };
- };
-
- hdmi {
- compatible = "nvidia,tegra20-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
- clocks = <&tegra_car 51>, <&tegra_car 117>;
- clock-names = "hdmi", "parent";
- status = "disabled";
- };
-
- tvo {
- compatible = "nvidia,tegra20-tvo";
- reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
- clocks = <&tegra_car 102>;
- status = "disabled";
- };
-
- dsi {
- compatible = "nvidia,tegra20-dsi";
- reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car 48>;
- status = "disabled";
- };
- };
-
- timer@50004600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x50040600 0x20>;
- interrupts = <1 13 0x304>;
- };
-
- intc: interrupt-controller {
- compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000
- 0x50040100 0x0100>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0x50043000 0x1000>;
- arm,data-latency = <5 5 2>;
- arm,tag-latency = <4 4 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- timer@60005000 {
- compatible = "nvidia,tegra20-timer";
- reg = <0x60005000 0x60>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04>;
- };
-
- tegra_car: clock {
- compatible = "nvidia,tegra20-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- };
-
- apbdma: dma {
- compatible = "nvidia,tegra20-apbdma";
- reg = <0x6000a000 0x1200>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04>;
- clocks = <&tegra_car 34>;
- };
-
- ahb {
- compatible = "nvidia,tegra20-ahb";
- reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
- };
-
- gpio: gpio {
- compatible = "nvidia,tegra20-gpio";
- reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04>;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- pinmux: pinmux {
- compatible = "nvidia,tegra20-pinmux";
- reg = <0x70000014 0x10 /* Tri-state registers */
- 0x70000080 0x20 /* Mux registers */
- 0x700000a0 0x14 /* Pull-up/down registers */
- 0x70000868 0xa8>; /* Pad control registers */
- };
-
- das {
- compatible = "nvidia,tegra20-das";
- reg = <0x70000c00 0x80>;
- };
-
- tegra_ac97: ac97 {
- compatible = "nvidia,tegra20-ac97";
- reg = <0x70002000 0x200>;
- interrupts = <0 81 0x04>;
- nvidia,dma-request-selector = <&apbdma 12>;
- clocks = <&tegra_car 3>;
- status = "disabled";
- };
-
- tegra_i2s1: i2s@70002800 {
- compatible = "nvidia,tegra20-i2s";
- reg = <0x70002800 0x200>;
- interrupts = <0 13 0x04>;
- nvidia,dma-request-selector = <&apbdma 2>;
- clocks = <&tegra_car 11>;
- status = "disabled";
- };
-
- tegra_i2s2: i2s@70002a00 {
- compatible = "nvidia,tegra20-i2s";
- reg = <0x70002a00 0x200>;
- interrupts = <0 3 0x04>;
- nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 18>;
- status = "disabled";
- };
-
- /*
- * There are two serial driver i.e. 8250 based simple serial
- * driver and APB DMA based serial driver for higher baudrate
- * and performace. To enable the 8250 based driver, the compatible
- * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
- * driver, the comptible is "nvidia,tegra20-hsuart".
- */
- uarta: serial@70006000 {
- compatible = "nvidia,tegra20-uart";
- reg = <0x70006000 0x40>;
- reg-shift = <2>;
- interrupts = <0 36 0x04>;
- clock-frequency = <216000000>;
- nvidia,dma-request-selector = <&apbdma 8>;
- clocks = <&tegra_car 6>;
- status = "disabled";
- };
-
- uartb: serial@70006040 {
- compatible = "nvidia,tegra20-uart";
- reg = <0x70006040 0x40>;
- reg-shift = <2>;
- interrupts = <0 37 0x04>;
- clock-frequency = <216000000>;
- nvidia,dma-request-selector = <&apbdma 9>;
- clocks = <&tegra_car 96>;
- status = "disabled";
- };
-
- uartc: serial@70006200 {
- compatible = "nvidia,tegra20-uart";
- reg = <0x70006200 0x100>;
- reg-shift = <2>;
- interrupts = <0 46 0x04>;
- clock-frequency = <216000000>;
- nvidia,dma-request-selector = <&apbdma 10>;
- clocks = <&tegra_car 55>;
- status = "disabled";
- };
-
- uartd: serial@70006300 {
- compatible = "nvidia,tegra20-uart";
- reg = <0x70006300 0x100>;
- reg-shift = <2>;
- interrupts = <0 90 0x04>;
- clock-frequency = <216000000>;
- nvidia,dma-request-selector = <&apbdma 19>;
- clocks = <&tegra_car 65>;
- status = "disabled";
- };
-
- uarte: serial@70006400 {
- compatible = "nvidia,tegra20-uart";
- reg = <0x70006400 0x100>;
- reg-shift = <2>;
- interrupts = <0 91 0x04>;
- clock-frequency = <216000000>;
- nvidia,dma-request-selector = <&apbdma 20>;
- clocks = <&tegra_car 66>;
- status = "disabled";
- };
-
- pwm: pwm {
- compatible = "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
- clocks = <&tegra_car 17>;
- };
-
- rtc {
- compatible = "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
- };
-
- i2c@7000c000 {
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 12>, <&tegra_car 124>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- spi@7000c380 {
- compatible = "nvidia,tegra20-sflash";
- reg = <0x7000c380 0x80>;
- interrupts = <0 39 0x04>;
- nvidia,dma-request-selector = <&apbdma 11>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 43>;
- status = "disabled";
- };
-
- i2c@7000c400 {
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 54>, <&tegra_car 124>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000c500 {
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 67>, <&tegra_car 124>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000d000 {
- compatible = "nvidia,tegra20-i2c-dvc";
- reg = <0x7000d000 0x200>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>, <&tegra_car 124>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- spi@7000d400 {
- compatible = "nvidia,tegra20-slink";
- reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
- nvidia,dma-request-selector = <&apbdma 15>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 41>;
- status = "disabled";
- };
-
- spi@7000d600 {
- compatible = "nvidia,tegra20-slink";
- reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
- nvidia,dma-request-selector = <&apbdma 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 44>;
- status = "disabled";
- };
-
- spi@7000d800 {
- compatible = "nvidia,tegra20-slink";
- reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
- nvidia,dma-request-selector = <&apbdma 17>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 46>;
- status = "disabled";
- };
-
- spi@7000da00 {
- compatible = "nvidia,tegra20-slink";
- reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
- nvidia,dma-request-selector = <&apbdma 18>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 68>;
- status = "disabled";
- };
-
- kbc {
- compatible = "nvidia,tegra20-kbc";
- reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
- clocks = <&tegra_car 36>;
- status = "disabled";
- };
-
- pmc {
- compatible = "nvidia,tegra20-pmc";
- reg = <0x7000e400 0x400>;
- };
-
- memory-controller@7000f000 {
- compatible = "nvidia,tegra20-mc";
- reg = <0x7000f000 0x024
- 0x7000f03c 0x3c4>;
- interrupts = <0 77 0x04>;
- };
-
- iommu {
- compatible = "nvidia,tegra20-gart";
- reg = <0x7000f024 0x00000018 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
- };
-
- memory-controller@7000f400 {
- compatible = "nvidia,tegra20-emc";
- reg = <0x7000f400 0x200>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb@c5000000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
- reg = <0xc5000000 0x4000>;
- interrupts = <0 20 0x04>;
- phy_type = "utmi";
- nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>;
- nvidia,needs-double-reset;
- nvidia,phy = <&phy1>;
- status = "disabled";
- };
-
- phy1: usb-phy@c5000400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5000400 0x3c00>;
- phy_type = "utmi";
- nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- usb@c5004000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
- reg = <0xc5004000 0x4000>;
- interrupts = <0 21 0x04>;
- phy_type = "ulpi";
- clocks = <&tegra_car 58>;
- nvidia,phy = <&phy2>;
- status = "disabled";
- };
-
- phy2: usb-phy@c5004400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5004400 0x3c00>;
- phy_type = "ulpi";
- clocks = <&tegra_car 94>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- usb@c5008000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
- reg = <0xc5008000 0x4000>;
- interrupts = <0 97 0x04>;
- phy_type = "utmi";
- clocks = <&tegra_car 59>;
- nvidia,phy = <&phy3>;
- status = "disabled";
- };
-
- phy3: usb-phy@c5008400 {
- compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5008400 0x3c00>;
- phy_type = "utmi";
- clocks = <&tegra_car 22>, <&tegra_car 127>;
- clock-names = "phy", "pll_u";
- };
-
- sdhci@c8000000 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000000 0x200>;
- interrupts = <0 14 0x04>;
- clocks = <&tegra_car 14>;
- status = "disabled";
- };
-
- sdhci@c8000200 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000200 0x200>;
- interrupts = <0 15 0x04>;
- clocks = <&tegra_car 9>;
- status = "disabled";
- };
-
- sdhci@c8000400 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000400 0x200>;
- interrupts = <0 19 0x04>;
- clocks = <&tegra_car 69>;
- status = "disabled";
- };
-
- sdhci@c8000600 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000600 0x200>;
- interrupts = <0 31 0x04>;
- clocks = <&tegra_car 15>;
- status = "disabled";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 56 0x04
- 0 57 0x04>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
new file mode 100644
index 0000000..917edd4
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -0,0 +1,556 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra20";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &uarta;
+ serial1 = &uartb;
+ serial2 = &uartc;
+ serial3 = &uartd;
+ serial4 = &uarte;
+ };
+
+ host1x {
+ compatible = "nvidia,tegra20-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04>; /* mpcore general */
+ clocks = <&tegra_car 28>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ mpe {
+ compatible = "nvidia,tegra20-mpe";
+ reg = <0x54040000 0x00040000>;
+ interrupts = <0 68 0x04>;
+ clocks = <&tegra_car 60>;
+ };
+
+ vi {
+ compatible = "nvidia,tegra20-vi";
+ reg = <0x54080000 0x00040000>;
+ interrupts = <0 69 0x04>;
+ clocks = <&tegra_car 100>;
+ };
+
+ epp {
+ compatible = "nvidia,tegra20-epp";
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <0 70 0x04>;
+ clocks = <&tegra_car 19>;
+ };
+
+ isp {
+ compatible = "nvidia,tegra20-isp";
+ reg = <0x54100000 0x00040000>;
+ interrupts = <0 71 0x04>;
+ clocks = <&tegra_car 23>;
+ };
+
+ gr2d {
+ compatible = "nvidia,tegra20-gr2d";
+ reg = <0x54140000 0x00040000>;
+ interrupts = <0 72 0x04>;
+ clocks = <&tegra_car 21>;
+ };
+
+ gr3d {
+ compatible = "nvidia,tegra20-gr3d";
+ reg = <0x54180000 0x00040000>;
+ clocks = <&tegra_car 24>;
+ };
+
+ dc@54200000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <0 73 0x04>;
+ clocks = <&tegra_car 27>, <&tegra_car 121>;
+ clock-names = "disp1", "parent";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <0 74 0x04>;
+ clocks = <&tegra_car 26>, <&tegra_car 121>;
+ clock-names = "disp2", "parent";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ hdmi {
+ compatible = "nvidia,tegra20-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <0 75 0x04>;
+ clocks = <&tegra_car 51>, <&tegra_car 117>;
+ clock-names = "hdmi", "parent";
+ status = "disabled";
+ };
+
+ tvo {
+ compatible = "nvidia,tegra20-tvo";
+ reg = <0x542c0000 0x00040000>;
+ interrupts = <0 76 0x04>;
+ clocks = <&tegra_car 102>;
+ status = "disabled";
+ };
+
+ dsi {
+ compatible = "nvidia,tegra20-dsi";
+ reg = <0x54300000 0x00040000>;
+ clocks = <&tegra_car 48>;
+ status = "disabled";
+ };
+ };
+
+ timer@50004600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x50040600 0x20>;
+ interrupts = <1 13 0x304>;
+ };
+
+ intc: interrupt-controller {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x50041000 0x1000
+ 0x50040100 0x0100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <5 5 2>;
+ arm,tag-latency = <4 4 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra20-timer";
+ reg = <0x60005000 0x60>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04>;
+ };
+
+ tegra_car: clock {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apbdma: dma {
+ compatible = "nvidia,tegra20-apbdma";
+ reg = <0x6000a000 0x1200>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04>;
+ clocks = <&tegra_car 34>;
+ };
+
+ ahb {
+ compatible = "nvidia,tegra20-ahb";
+ reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
+ };
+
+ gpio: gpio {
+ compatible = "nvidia,tegra20-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ pinmux: pinmux {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = <0x70000014 0x10 /* Tri-state registers */
+ 0x70000080 0x20 /* Mux registers */
+ 0x700000a0 0x14 /* Pull-up/down registers */
+ 0x70000868 0xa8>; /* Pad control registers */
+ };
+
+ das {
+ compatible = "nvidia,tegra20-das";
+ reg = <0x70000c00 0x80>;
+ };
+
+ tegra_ac97: ac97 {
+ compatible = "nvidia,tegra20-ac97";
+ reg = <0x70002000 0x200>;
+ interrupts = <0 81 0x04>;
+ nvidia,dma-request-selector = <&apbdma 12>;
+ clocks = <&tegra_car 3>;
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@70002800 {
+ compatible = "nvidia,tegra20-i2s";
+ reg = <0x70002800 0x200>;
+ interrupts = <0 13 0x04>;
+ nvidia,dma-request-selector = <&apbdma 2>;
+ clocks = <&tegra_car 11>;
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@70002a00 {
+ compatible = "nvidia,tegra20-i2s";
+ reg = <0x70002a00 0x200>;
+ interrupts = <0 3 0x04>;
+ nvidia,dma-request-selector = <&apbdma 1>;
+ clocks = <&tegra_car 18>;
+ status = "disabled";
+ };
+
+ /*
+ * There are two serial driver i.e. 8250 based simple serial
+ * driver and APB DMA based serial driver for higher baudrate
+ * and performace. To enable the 8250 based driver, the compatible
+ * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
+ * driver, the comptible is "nvidia,tegra20-hsuart".
+ */
+ uarta: serial@70006000 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = <0 36 0x04>;
+ clock-frequency = <216000000>;
+ nvidia,dma-request-selector = <&apbdma 8>;
+ clocks = <&tegra_car 6>;
+ status = "disabled";
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006040 0x40>;
+ reg-shift = <2>;
+ interrupts = <0 37 0x04>;
+ clock-frequency = <216000000>;
+ nvidia,dma-request-selector = <&apbdma 9>;
+ clocks = <&tegra_car 96>;
+ status = "disabled";
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006200 0x100>;
+ reg-shift = <2>;
+ interrupts = <0 46 0x04>;
+ clock-frequency = <216000000>;
+ nvidia,dma-request-selector = <&apbdma 10>;
+ clocks = <&tegra_car 55>;
+ status = "disabled";
+ };
+
+ uartd: serial@70006300 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006300 0x100>;
+ reg-shift = <2>;
+ interrupts = <0 90 0x04>;
+ clock-frequency = <216000000>;
+ nvidia,dma-request-selector = <&apbdma 19>;
+ clocks = <&tegra_car 65>;
+ status = "disabled";
+ };
+
+ uarte: serial@70006400 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006400 0x100>;
+ reg-shift = <2>;
+ interrupts = <0 91 0x04>;
+ clock-frequency = <216000000>;
+ nvidia,dma-request-selector = <&apbdma 20>;
+ clocks = <&tegra_car 66>;
+ status = "disabled";
+ };
+
+ pwm: pwm {
+ compatible = "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car 17>;
+ };
+
+ rtc {
+ compatible = "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 12>, <&tegra_car 124>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ spi@7000c380 {
+ compatible = "nvidia,tegra20-sflash";
+ reg = <0x7000c380 0x80>;
+ interrupts = <0 39 0x04>;
+ nvidia,dma-request-selector = <&apbdma 11>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 43>;
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 54>, <&tegra_car 124>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 67>, <&tegra_car 124>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra20-i2c-dvc";
+ reg = <0x7000d000 0x200>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>, <&tegra_car 124>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ spi@7000d400 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 41>;
+ status = "disabled";
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 44>;
+ status = "disabled";
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 46>;
+ status = "disabled";
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 68>;
+ status = "disabled";
+ };
+
+ kbc {
+ compatible = "nvidia,tegra20-kbc";
+ reg = <0x7000e200 0x100>;
+ interrupts = <0 85 0x04>;
+ clocks = <&tegra_car 36>;
+ status = "disabled";
+ };
+
+ pmc {
+ compatible = "nvidia,tegra20-pmc";
+ reg = <0x7000e400 0x400>;
+ };
+
+ memory-controller@7000f000 {
+ compatible = "nvidia,tegra20-mc";
+ reg = <0x7000f000 0x024
+ 0x7000f03c 0x3c4>;
+ interrupts = <0 77 0x04>;
+ };
+
+ iommu {
+ compatible = "nvidia,tegra20-gart";
+ reg = <0x7000f024 0x00000018 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
+ };
+
+ memory-controller@7000f400 {
+ compatible = "nvidia,tegra20-emc";
+ reg = <0x7000f400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb@c5000000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5000000 0x4000>;
+ interrupts = <0 20 0x04>;
+ phy_type = "utmi";
+ nvidia,has-legacy-mode;
+ clocks = <&tegra_car 22>;
+ nvidia,needs-double-reset;
+ nvidia,phy = <&phy1>;
+ status = "disabled";
+ };
+
+ phy1: usb-phy@c5000400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5000400 0x3c00>;
+ phy_type = "utmi";
+ nvidia,has-legacy-mode;
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
+ usb@c5004000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5004000 0x4000>;
+ interrupts = <0 21 0x04>;
+ phy_type = "ulpi";
+ clocks = <&tegra_car 58>;
+ nvidia,phy = <&phy2>;
+ status = "disabled";
+ };
+
+ phy2: usb-phy@c5004400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5004400 0x3c00>;
+ phy_type = "ulpi";
+ clocks = <&tegra_car 94>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
+ usb@c5008000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5008000 0x4000>;
+ interrupts = <0 97 0x04>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>;
+ nvidia,phy = <&phy3>;
+ status = "disabled";
+ };
+
+ phy3: usb-phy@c5008400 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5008400 0x3c00>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clock-names = "phy", "pll_u";
+ };
+
+ sdhci@c8000000 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000000 0x200>;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
+ };
+
+ sdhci@c8000200 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000200 0x200>;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
+ };
+
+ sdhci@c8000400 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000400 0x200>;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
+ };
+
+ sdhci@c8000600 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000600 0x200>;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 56 0x04
+ 0 57 0x04>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
deleted file mode 100644
index 8ff2ff2..0000000
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ /dev/null
@@ -1,373 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30.dtsi"
-
-/ {
- model = "NVIDIA Tegra30 Beaver evaluation board";
- compatible = "nvidia,beaver", "nvidia,tegra30";
-
- memory {
- reg = <0x80000000 0x80000000>;
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- sdmmc1_clk_pz0 {
- nvidia,pins = "sdmmc1_clk_pz0";
- nvidia,function = "sdmmc1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc1_cmd_pz1 {
- nvidia,pins = "sdmmc1_cmd_pz1",
- "sdmmc1_dat0_py7",
- "sdmmc1_dat1_py6",
- "sdmmc1_dat2_py5",
- "sdmmc1_dat3_py4";
- nvidia,function = "sdmmc1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- sdmmc3_clk_pa6 {
- nvidia,pins = "sdmmc3_clk_pa6";
- nvidia,function = "sdmmc3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc3_cmd_pa7 {
- nvidia,pins = "sdmmc3_cmd_pa7",
- "sdmmc3_dat0_pb7",
- "sdmmc3_dat1_pb6",
- "sdmmc3_dat2_pb5",
- "sdmmc3_dat3_pb4";
- nvidia,function = "sdmmc3";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- "sdmmc4_rst_n_pcc3";
- nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- dap2_fs_pa2 {
- nvidia,pins = "dap2_fs_pa2",
- "dap2_sclk_pa3",
- "dap2_din_pa4",
- "dap2_dout_pa5";
- nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdio3 {
- nvidia,pins = "drive_sdio3";
- nvidia,high-speed-mode = <0>;
- nvidia,schmitt = <0>;
- nvidia,pull-down-strength = <46>;
- nvidia,pull-up-strength = <42>;
- nvidia,slew-rate-rising = <1>;
- nvidia,slew-rate-falling = <1>;
- };
- };
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c700 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <100000>;
-
- tps62361 {
- compatible = "ti,tps62361";
- reg = <0x60>;
-
- regulator-name = "tps62361-vout";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-always-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- };
-
- pmic: tps65911@2d {
- compatible = "ti,tps65911";
- reg = <0x2d>;
-
- interrupts = <0 86 0x4>;
- #interrupt-cells = <2>;
- interrupt-controller;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- vcc1-supply = <&vdd_5v_in_reg>;
- vcc2-supply = <&vdd_5v_in_reg>;
- vcc3-supply = <&vio_reg>;
- vcc4-supply = <&vdd_5v_in_reg>;
- vcc5-supply = <&vdd_5v_in_reg>;
- vcc6-supply = <&vdd2_reg>;
- vcc7-supply = <&vdd_5v_in_reg>;
- vccio-supply = <&vdd_5v_in_reg>;
-
- regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd1_reg: vdd1 {
- regulator-name = "vddio_ddr_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vdd2_reg: vdd2 {
- regulator-name = "vdd_1v5_gen";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
-
- vddctrl_reg: vddctrl {
- regulator-name = "vdd_cpu,vdd_sys";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- vio_reg: vio {
- regulator-name = "vdd_1v8_gen";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "vdd_pexa,vdd_pexb";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "vdd_sata,avdd_plle";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- /* LDO3 is not connected to anything */
-
- ldo4_reg: ldo4 {
- regulator-name = "vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- regulator-name = "vddio_sdmmc,avdd_vdac";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo6_reg: ldo6 {
- regulator-name = "avdd_dsi_csi,pwrdet_mipi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo7_reg: ldo7 {
- regulator-name = "vdd_pllm,x,u,a_p_c_s";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- ldo8_reg: ldo8 {
- regulator-name = "vdd_ddr_hs";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
- };
- };
- };
-
- spi@7000da00 {
- status = "okay";
- spi-max-frequency = <25000000>;
- spi-flash@1 {
- compatible = "winbond,w25q32";
- reg = <1>;
- spi-max-frequency = <20000000>;
- };
- };
-
- ahub {
- i2s@70080400 {
- status = "okay";
- };
- };
-
- pmc {
- status = "okay";
- nvidia,invert-interrupt;
- };
-
- sdhci@78000000 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
- bus-width = <4>;
- };
-
- sdhci@78000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v_in_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v_in";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- chargepump_5v_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "chargepump_5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
- };
-
- ddr_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
- vin-supply = <&vdd_5v_in_reg>;
- };
-
- vdd_5v_sata_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_5v_sata";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
- vin-supply = <&vdd_5v_in_reg>;
- };
-
- usb1_vbus_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
- gpio-open-drain;
- vin-supply = <&vdd_5v_in_reg>;
- };
-
- usb3_vbus_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
- gpio-open-drain;
- vin-supply = <&vdd_5v_in_reg>;
- };
-
- sys_3v3_reg: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "sys_3v3,vdd_3v3_alw";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
- vin-supply = <&vdd_5v_in_reg>;
- };
-
- sys_3v3_pexs_reg: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "sys_3v3_pexs";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
- vin-supply = <&sys_3v3_reg>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
new file mode 100644
index 0000000..af23c94
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -0,0 +1,373 @@
+/dts-v1/;
+
+#include "tegra30.dtsip"
+
+/ {
+ model = "NVIDIA Tegra30 Beaver evaluation board";
+ compatible = "nvidia,beaver", "nvidia,tegra30";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <0>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <1>;
+ nvidia,slew-rate-falling = <1>;
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ tps62361 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ };
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <0 86 0x4>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_5v_in_reg>;
+ vcc2-supply = <&vdd_5v_in_reg>;
+ vcc3-supply = <&vio_reg>;
+ vcc4-supply = <&vdd_5v_in_reg>;
+ vcc5-supply = <&vdd_5v_in_reg>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_5v_in_reg>;
+ vccio-supply = <&vdd_5v_in_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd1_reg: vdd1 {
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "vdd_1v5_gen";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vddctrl_reg: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vio_reg: vio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4_reg: ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ spi-flash@1 {
+ compatible = "winbond,w25q32";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+
+ ahub {
+ i2s@70080400 {
+ status = "okay";
+ };
+ };
+
+ pmc {
+ status = "okay";
+ nvidia,invert-interrupt;
+ };
+
+ sdhci@78000000 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+ power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ bus-width = <4>;
+ };
+
+ sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v_in_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v_in";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ chargepump_5v_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "chargepump_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+ };
+
+ ddr_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ vdd_5v_sata_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_5v_sata";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 30 0>; /* gpio PD6 */
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ usb1_vbus_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ usb3_vbus_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ sys_3v3_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "sys_3v3,vdd_3v3_alw";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ sys_3v3_pexs_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "sys_3v3_pexs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 95 0>; /* gpio PL7 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
deleted file mode 100644
index adc88aa..0000000
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30-cardhu.dtsi"
-
-/* This dts file support the cardhu A02 version of board */
-
-/ {
- model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
- compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddr_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 0>;
- };
-
- sys_3v3_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "sys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 0>;
- };
-
- usb1_vbus_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
-
- usb3_vbus_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
-
- vdd_5v0_reg: regulator@104 {
- compatible = "regulator-fixed";
- reg = <104>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&pmic 2 0>;
- };
-
- vdd_bl_reg: regulator@105 {
- compatible = "regulator-fixed";
- reg = <105>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 83 0>; /* GPIO PK3 */
- };
- };
-
- sdhci@78000400 {
- status = "okay";
- power-gpios = <&gpio 28 0>; /* gpio PD4 */
- bus-width = <4>;
- };
-};
-
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
new file mode 100644
index 0000000..64b7184
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
@@ -0,0 +1,93 @@
+/dts-v1/;
+
+#include "tegra30-cardhu.dtsip"
+
+/* This dts file support the cardhu A02 version of board */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
+ compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ reg = <100>;
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 0>;
+ };
+
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 0>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ reg = <102>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ reg = <103>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ reg = <104>;
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 2 0>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 83 0>; /* GPIO PK3 */
+ };
+ };
+
+ sdhci@78000400 {
+ status = "okay";
+ power-gpios = <&gpio 28 0>; /* gpio PD4 */
+ bus-width = <4>;
+ };
+};
+
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
deleted file mode 100644
index 08163e1..0000000
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ /dev/null
@@ -1,104 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30-cardhu.dtsi"
-
-/* This dts file support the cardhu A04 and later versions of board */
-
-/ {
- model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
- compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddr_reg: regulator@100 {
- compatible = "regulator-fixed";
- regulator-name = "ddr";
- reg = <100>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 0>;
- };
-
- sys_3v3_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "sys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 0>;
- };
-
- usb1_vbus_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 238 0>; /* GPIO PDD6 */
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
-
- usb3_vbus_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 236 0>; /* GPIO PDD4 */
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
-
- vdd_5v0_reg: regulator@104 {
- compatible = "regulator-fixed";
- reg = <104>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&pmic 8 0>;
- };
-
- vdd_bl_reg: regulator@105 {
- compatible = "regulator-fixed";
- reg = <105>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 234 0>; /* GPIO PDD2 */
- };
-
- vdd_bl2_reg: regulator@106 {
- compatible = "regulator-fixed";
- reg = <106>;
- regulator-name = "vdd_bl2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 232 0>; /* GPIO PDD0 */
- };
- };
-
- sdhci@78000400 {
- status = "okay";
- power-gpios = <&gpio 27 0>; /* gpio PD3 */
- bus-width = <4>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
new file mode 100644
index 0000000..fc0d771
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
@@ -0,0 +1,104 @@
+/dts-v1/;
+
+#include "tegra30-cardhu.dtsip"
+
+/* This dts file support the cardhu A04 and later versions of board */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
+ compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "ddr";
+ reg = <100>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 0>;
+ };
+
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 0>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ reg = <102>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 238 0>; /* GPIO PDD6 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ reg = <103>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 236 0>; /* GPIO PDD4 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ reg = <104>;
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 8 0>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 234 0>; /* GPIO PDD2 */
+ };
+
+ vdd_bl2_reg: regulator@106 {
+ compatible = "regulator-fixed";
+ reg = <106>;
+ regulator-name = "vdd_bl2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 232 0>; /* GPIO PDD0 */
+ };
+ };
+
+ sdhci@78000400 {
+ status = "okay";
+ power-gpios = <&gpio 27 0>; /* gpio PD3 */
+ bus-width = <4>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
deleted file mode 100644
index 1749927..0000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ /dev/null
@@ -1,500 +0,0 @@
-/include/ "tegra30.dtsi"
-
-/**
- * This file contains common DT entry for all fab version of Cardhu.
- * There is multiple fab version of Cardhu starting from A01 to A07.
- * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
- * A02 will have different sets of GPIOs for fixed regulator compare to
- * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
- * compatible with fab version A04. Based on Cardhu fab version, the
- * related dts file need to be chosen like for Cardhu fab version A02,
- * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
- * tegra30-cardhu-a04.dts.
- * The identification of board is done in two ways, by looking the sticker
- * on PCB and by reading board id eeprom.
- * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
- * number is the fab version like here it is 002 and hence fab version A02.
- * The (downstream internal) U-Boot of Cardhu display the board-id as
- * follows:
- * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
- * In this Fab version is 02 i.e. A02.
- * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
- * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
- * wide.
- */
-
-/ {
- model = "NVIDIA Tegra30 Cardhu evaluation board";
- compatible = "nvidia,cardhu", "nvidia,tegra30";
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- sdmmc1_clk_pz0 {
- nvidia,pins = "sdmmc1_clk_pz0";
- nvidia,function = "sdmmc1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc1_cmd_pz1 {
- nvidia,pins = "sdmmc1_cmd_pz1",
- "sdmmc1_dat0_py7",
- "sdmmc1_dat1_py6",
- "sdmmc1_dat2_py5",
- "sdmmc1_dat3_py4";
- nvidia,function = "sdmmc1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- sdmmc3_clk_pa6 {
- nvidia,pins = "sdmmc3_clk_pa6";
- nvidia,function = "sdmmc3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc3_cmd_pa7 {
- nvidia,pins = "sdmmc3_cmd_pa7",
- "sdmmc3_dat0_pb7",
- "sdmmc3_dat1_pb6",
- "sdmmc3_dat2_pb5",
- "sdmmc3_dat3_pb4";
- nvidia,function = "sdmmc3";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- "sdmmc4_rst_n_pcc3";
- nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- dap2_fs_pa2 {
- nvidia,pins = "dap2_fs_pa2",
- "dap2_sclk_pa3",
- "dap2_din_pa4",
- "dap2_dout_pa5";
- nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdio3 {
- nvidia,pins = "drive_sdio3";
- nvidia,high-speed-mode = <0>;
- nvidia,schmitt = <0>;
- nvidia,pull-down-strength = <46>;
- nvidia,pull-up-strength = <42>;
- nvidia,slew-rate-rising = <1>;
- nvidia,slew-rate-falling = <1>;
- };
- uart3_txd_pw6 {
- nvidia,pins = "uart3_txd_pw6",
- "uart3_cts_n_pa1",
- "uart3_rts_n_pc0",
- "uart3_rxd_pw7";
- nvidia,function = "uartc";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- serial@70006200 {
- compatible = "nvidia,tegra30-hsuart";
- status = "okay";
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <100000>;
-
- /* ALS and Proximity sensor */
- isl29028@44 {
- compatible = "isil,isl29028";
- reg = <0x44>;
- interrupt-parent = <&gpio>;
- interrupts = <88 0x04>; /*gpio PL0 */
- };
- };
-
- i2c@7000c700 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <100000>;
-
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <179 0x04>; /* gpio PW3 */
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
-
- tps62361 {
- compatible = "ti,tps62361";
- reg = <0x60>;
-
- regulator-name = "tps62361-vout";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-always-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- };
-
- pmic: tps65911@2d {
- compatible = "ti,tps65911";
- reg = <0x2d>;
-
- interrupts = <0 86 0x4>;
- #interrupt-cells = <2>;
- interrupt-controller;
-
- ti,system-power-controller;
-
- #gpio-cells = <2>;
- gpio-controller;
-
- vcc1-supply = <&vdd_ac_bat_reg>;
- vcc2-supply = <&vdd_ac_bat_reg>;
- vcc3-supply = <&vio_reg>;
- vcc4-supply = <&vdd_5v0_reg>;
- vcc5-supply = <&vdd_ac_bat_reg>;
- vcc6-supply = <&vdd2_reg>;
- vcc7-supply = <&vdd_ac_bat_reg>;
- vccio-supply = <&vdd_ac_bat_reg>;
-
- regulators {
- vdd1_reg: vdd1 {
- regulator-name = "vddio_ddr_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vdd2_reg: vdd2 {
- regulator-name = "vdd_1v5_gen";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
-
- vddctrl_reg: vddctrl {
- regulator-name = "vdd_cpu,vdd_sys";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- vio_reg: vio {
- regulator-name = "vdd_1v8_gen";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "vdd_pexa,vdd_pexb";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "vdd_sata,avdd_plle";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- /* LDO3 is not connected to anything */
-
- ldo4_reg: ldo4 {
- regulator-name = "vdd_rtc";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- regulator-name = "vddio_sdmmc,avdd_vdac";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo6_reg: ldo6 {
- regulator-name = "avdd_dsi_csi,pwrdet_mipi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo7_reg: ldo7 {
- regulator-name = "vdd_pllm,x,u,a_p_c_s";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- ldo8_reg: ldo8 {
- regulator-name = "vdd_ddr_hs";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
- };
- };
- };
-
- spi@7000da00 {
- status = "okay";
- spi-max-frequency = <25000000>;
- spi-flash@1 {
- compatible = "winbond,w25q32";
- reg = <1>;
- spi-max-frequency = <20000000>;
- };
- };
-
- ahub {
- i2s@70080400 {
- status = "okay";
- };
- };
-
- pmc {
- status = "okay";
- nvidia,invert-interrupt;
- };
-
- sdhci@78000000 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
- bus-width = <4>;
- };
-
- sdhci@78000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_ac_bat_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_ac_bat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- cam_1v8_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "cam_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- gpio = <&gpio 220 0>; /* gpio PBB4 */
- vin-supply = <&vio_reg>;
- };
-
- cp_5v_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "cp_5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
- };
-
- emmc_3v3_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "emmc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 25 0>; /* gpio PD1 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- modem_3v3_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "modem_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
- };
-
- pex_hvdd_3v3_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "pex_hvdd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_cam1_ldo_reg: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "vdd_cam1_ldo";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- enable-active-high;
- gpio = <&gpio 142 0>; /* gpio PR6 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_cam2_ldo_reg: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "vdd_cam2_ldo";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- enable-active-high;
- gpio = <&gpio 143 0>; /* gpio PR7 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_cam3_ldo_reg: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "vdd_cam3_ldo";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio 144 0>; /* gpio PS0 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_com_reg: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "vdd_com";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 24 0>; /* gpio PD0 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_fuse_3v3_reg: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "vdd_fuse_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio 94 0>; /* gpio PL6 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_pnl1_reg: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "vdd_pnl1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio 92 0>; /* gpio PL4 */
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_vid_reg: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "vddio_vid";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio 152 0>; /* GPIO PT0 */
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-cardhu",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "NVIDIA Tegra Cardhu";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
new file mode 100644
index 0000000..75ff544
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -0,0 +1,500 @@
+#include "tegra30.dtsip"
+
+/**
+ * This file contains common DT entry for all fab version of Cardhu.
+ * There is multiple fab version of Cardhu starting from A01 to A07.
+ * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
+ * A02 will have different sets of GPIOs for fixed regulator compare to
+ * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
+ * compatible with fab version A04. Based on Cardhu fab version, the
+ * related dts file need to be chosen like for Cardhu fab version A02,
+ * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
+ * tegra30-cardhu-a04.dts.
+ * The identification of board is done in two ways, by looking the sticker
+ * on PCB and by reading board id eeprom.
+ * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
+ * number is the fab version like here it is 002 and hence fab version A02.
+ * The (downstream internal) U-Boot of Cardhu display the board-id as
+ * follows:
+ * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
+ * In this Fab version is 02 i.e. A02.
+ * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
+ * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
+ * wide.
+ */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu evaluation board";
+ compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <0>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <1>;
+ nvidia,slew-rate-falling = <1>;
+ };
+ uart3_txd_pw6 {
+ nvidia,pins = "uart3_txd_pw6",
+ "uart3_cts_n_pa1",
+ "uart3_rts_n_pc0",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* ALS and Proximity sensor */
+ isl29028@44 {
+ compatible = "isil,isl29028";
+ reg = <0x44>;
+ interrupt-parent = <&gpio>;
+ interrupts = <88 0x04>; /*gpio PL0 */
+ };
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <179 0x04>; /* gpio PW3 */
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+
+ tps62361 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ };
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <0 86 0x4>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_ac_bat_reg>;
+ vcc2-supply = <&vdd_ac_bat_reg>;
+ vcc3-supply = <&vio_reg>;
+ vcc4-supply = <&vdd_5v0_reg>;
+ vcc5-supply = <&vdd_ac_bat_reg>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_ac_bat_reg>;
+ vccio-supply = <&vdd_ac_bat_reg>;
+
+ regulators {
+ vdd1_reg: vdd1 {
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "vdd_1v5_gen";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vddctrl_reg: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vio_reg: vio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4_reg: ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ spi-flash@1 {
+ compatible = "winbond,w25q32";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+
+ ahub {
+ i2s@70080400 {
+ status = "okay";
+ };
+ };
+
+ pmc {
+ status = "okay";
+ nvidia,invert-interrupt;
+ };
+
+ sdhci@78000000 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+ power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ bus-width = <4>;
+ };
+
+ sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_ac_bat_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ cam_1v8_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "cam_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&gpio 220 0>; /* gpio PBB4 */
+ vin-supply = <&vio_reg>;
+ };
+
+ cp_5v_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "cp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+ };
+
+ emmc_3v3_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "emmc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 25 0>; /* gpio PD1 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ modem_3v3_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "modem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 30 0>; /* gpio PD6 */
+ };
+
+ pex_hvdd_3v3_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "pex_hvdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 95 0>; /* gpio PL7 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam1_ldo_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "vdd_cam1_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio 142 0>; /* gpio PR6 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam2_ldo_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "vdd_cam2_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio 143 0>; /* gpio PR7 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam3_ldo_reg: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "vdd_cam3_ldo";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 144 0>; /* gpio PS0 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_com_reg: regulator@9 {
+ compatible = "regulator-fixed";
+ reg = <9>;
+ regulator-name = "vdd_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 24 0>; /* gpio PD0 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_fuse_3v3_reg: regulator@10 {
+ compatible = "regulator-fixed";
+ reg = <10>;
+ regulator-name = "vdd_fuse_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 94 0>; /* gpio PL6 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_pnl1_reg: regulator@11 {
+ compatible = "regulator-fixed";
+ reg = <11>;
+ regulator-name = "vdd_pnl1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 92 0>; /* gpio PL4 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_vid_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ reg = <12>;
+ regulator-name = "vddio_vid";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 152 0>; /* GPIO PT0 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-cardhu",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "NVIDIA Tegra Cardhu";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
deleted file mode 100644
index 572a45b..0000000
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ /dev/null
@@ -1,579 +0,0 @@
-/include/ "skeleton.dtsi"
-
-/ {
- compatible = "nvidia,tegra30";
- interrupt-parent = <&intc>;
-
- aliases {
- serial0 = &uarta;
- serial1 = &uartb;
- serial2 = &uartc;
- serial3 = &uartd;
- serial4 = &uarte;
- };
-
- host1x {
- compatible = "nvidia,tegra30-host1x", "simple-bus";
- reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
- clocks = <&tegra_car 28>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x04000000>;
-
- mpe {
- compatible = "nvidia,tegra30-mpe";
- reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
- clocks = <&tegra_car 60>;
- };
-
- vi {
- compatible = "nvidia,tegra30-vi";
- reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
- clocks = <&tegra_car 164>;
- };
-
- epp {
- compatible = "nvidia,tegra30-epp";
- reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
- clocks = <&tegra_car 19>;
- };
-
- isp {
- compatible = "nvidia,tegra30-isp";
- reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
- clocks = <&tegra_car 23>;
- };
-
- gr2d {
- compatible = "nvidia,tegra30-gr2d";
- reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
- clocks = <&tegra_car 21>;
- };
-
- gr3d {
- compatible = "nvidia,tegra30-gr3d";
- reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car 24 &tegra_car 98>;
- clock-names = "3d", "3d2";
- };
-
- dc@54200000 {
- compatible = "nvidia,tegra30-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
- clocks = <&tegra_car 27>, <&tegra_car 179>;
- clock-names = "disp1", "parent";
-
- rgb {
- status = "disabled";
- };
- };
-
- dc@54240000 {
- compatible = "nvidia,tegra30-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
- clocks = <&tegra_car 26>, <&tegra_car 179>;
- clock-names = "disp2", "parent";
-
- rgb {
- status = "disabled";
- };
- };
-
- hdmi {
- compatible = "nvidia,tegra30-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
- clocks = <&tegra_car 51>, <&tegra_car 189>;
- clock-names = "hdmi", "parent";
- status = "disabled";
- };
-
- tvo {
- compatible = "nvidia,tegra30-tvo";
- reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
- clocks = <&tegra_car 169>;
- status = "disabled";
- };
-
- dsi {
- compatible = "nvidia,tegra30-dsi";
- reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car 48>;
- status = "disabled";
- };
- };
-
- timer@50004600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x50040600 0x20>;
- interrupts = <1 13 0xf04>;
- };
-
- intc: interrupt-controller {
- compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000
- 0x50040100 0x0100>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0x50043000 0x1000>;
- arm,data-latency = <6 6 2>;
- arm,tag-latency = <5 5 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- timer@60005000 {
- compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
- reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
- };
-
- tegra_car: clock {
- compatible = "nvidia,tegra30-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- };
-
- apbdma: dma {
- compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
- reg = <0x6000a000 0x1400>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04
- 0 128 0x04
- 0 129 0x04
- 0 130 0x04
- 0 131 0x04
- 0 132 0x04
- 0 133 0x04
- 0 134 0x04
- 0 135 0x04
- 0 136 0x04
- 0 137 0x04
- 0 138 0x04
- 0 139 0x04
- 0 140 0x04
- 0 141 0x04
- 0 142 0x04
- 0 143 0x04>;
- clocks = <&tegra_car 34>;
- };
-
- ahb: ahb {
- compatible = "nvidia,tegra30-ahb";
- reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
- };
-
- gpio: gpio {
- compatible = "nvidia,tegra30-gpio";
- reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- pinmux: pinmux {
- compatible = "nvidia,tegra30-pinmux";
- reg = <0x70000868 0xd4 /* Pad control registers */
- 0x70003000 0x3e4>; /* Mux registers */
- };
-
- /*
- * There are two serial driver i.e. 8250 based simple serial
- * driver and APB DMA based serial driver for higher baudrate
- * and performace. To enable the 8250 based driver, the compatible
- * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
- * the APB DMA based serial driver, the comptible is
- * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
- */
- uarta: serial@70006000 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006000 0x40>;
- reg-shift = <2>;
- interrupts = <0 36 0x04>;
- clock-frequency = <408000000>;
- nvidia,dma-request-selector = <&apbdma 8>;
- clocks = <&tegra_car 6>;
- status = "disabled";
- };
-
- uartb: serial@70006040 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006040 0x40>;
- reg-shift = <2>;
- clock-frequency = <408000000>;
- interrupts = <0 37 0x04>;
- nvidia,dma-request-selector = <&apbdma 9>;
- clocks = <&tegra_car 160>;
- status = "disabled";
- };
-
- uartc: serial@70006200 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006200 0x100>;
- reg-shift = <2>;
- clock-frequency = <408000000>;
- interrupts = <0 46 0x04>;
- nvidia,dma-request-selector = <&apbdma 10>;
- clocks = <&tegra_car 55>;
- status = "disabled";
- };
-
- uartd: serial@70006300 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006300 0x100>;
- reg-shift = <2>;
- clock-frequency = <408000000>;
- interrupts = <0 90 0x04>;
- nvidia,dma-request-selector = <&apbdma 19>;
- clocks = <&tegra_car 65>;
- status = "disabled";
- };
-
- uarte: serial@70006400 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006400 0x100>;
- reg-shift = <2>;
- clock-frequency = <408000000>;
- interrupts = <0 91 0x04>;
- nvidia,dma-request-selector = <&apbdma 20>;
- clocks = <&tegra_car 66>;
- status = "disabled";
- };
-
- pwm: pwm {
- compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
- clocks = <&tegra_car 17>;
- };
-
- rtc {
- compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
- };
-
- i2c@7000c000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 12>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000c400 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 54>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000c500 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 67>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000c700 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c700 0x100>;
- interrupts = <0 120 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 103>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000d000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000d000 0x100>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- spi@7000d400 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
- nvidia,dma-request-selector = <&apbdma 15>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 41>;
- status = "disabled";
- };
-
- spi@7000d600 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
- nvidia,dma-request-selector = <&apbdma 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 44>;
- status = "disabled";
- };
-
- spi@7000d800 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
- nvidia,dma-request-selector = <&apbdma 17>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 46>;
- status = "disabled";
- };
-
- spi@7000da00 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
- nvidia,dma-request-selector = <&apbdma 18>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 68>;
- status = "disabled";
- };
-
- spi@7000dc00 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000dc00 0x200>;
- interrupts = <0 94 0x04>;
- nvidia,dma-request-selector = <&apbdma 27>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 104>;
- status = "disabled";
- };
-
- spi@7000de00 {
- compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000de00 0x200>;
- interrupts = <0 79 0x04>;
- nvidia,dma-request-selector = <&apbdma 28>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 105>;
- status = "disabled";
- };
-
- kbc {
- compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
- reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
- clocks = <&tegra_car 36>;
- status = "disabled";
- };
-
- pmc {
- compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
- reg = <0x7000e400 0x400>;
- };
-
- memory-controller {
- compatible = "nvidia,tegra30-mc";
- reg = <0x7000f000 0x010
- 0x7000f03c 0x1b4
- 0x7000f200 0x028
- 0x7000f284 0x17c>;
- interrupts = <0 77 0x04>;
- };
-
- iommu {
- compatible = "nvidia,tegra30-smmu";
- reg = <0x7000f010 0x02c
- 0x7000f1f0 0x010
- 0x7000f228 0x05c>;
- nvidia,#asids = <4>; /* # of ASIDs */
- dma-window = <0 0x40000000>; /* IOVA start & length */
- nvidia,ahb = <&ahb>;
- };
-
- ahub {
- compatible = "nvidia,tegra30-ahub";
- reg = <0x70080000 0x200
- 0x70080200 0x100>;
- interrupts = <0 103 0x04>;
- nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
- <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
- <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
- <&tegra_car 110>, <&tegra_car 162>;
- clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
- "i2s3", "i2s4", "dam0", "dam1", "dam2",
- "spdif_in";
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
-
- tegra_i2s0: i2s@70080300 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080300 0x100>;
- nvidia,ahub-cif-ids = <4 4>;
- clocks = <&tegra_car 30>;
- status = "disabled";
- };
-
- tegra_i2s1: i2s@70080400 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080400 0x100>;
- nvidia,ahub-cif-ids = <5 5>;
- clocks = <&tegra_car 11>;
- status = "disabled";
- };
-
- tegra_i2s2: i2s@70080500 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080500 0x100>;
- nvidia,ahub-cif-ids = <6 6>;
- clocks = <&tegra_car 18>;
- status = "disabled";
- };
-
- tegra_i2s3: i2s@70080600 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080600 0x100>;
- nvidia,ahub-cif-ids = <7 7>;
- clocks = <&tegra_car 101>;
- status = "disabled";
- };
-
- tegra_i2s4: i2s@70080700 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080700 0x100>;
- nvidia,ahub-cif-ids = <8 8>;
- clocks = <&tegra_car 102>;
- status = "disabled";
- };
- };
-
- sdhci@78000000 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
- reg = <0x78000000 0x200>;
- interrupts = <0 14 0x04>;
- clocks = <&tegra_car 14>;
- status = "disabled";
- };
-
- sdhci@78000200 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
- reg = <0x78000200 0x200>;
- interrupts = <0 15 0x04>;
- clocks = <&tegra_car 9>;
- status = "disabled";
- };
-
- sdhci@78000400 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
- reg = <0x78000400 0x200>;
- interrupts = <0 19 0x04>;
- clocks = <&tegra_car 69>;
- status = "disabled";
- };
-
- sdhci@78000600 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
- reg = <0x78000600 0x200>;
- interrupts = <0 31 0x04>;
- clocks = <&tegra_car 15>;
- status = "disabled";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 144 0x04
- 0 145 0x04
- 0 146 0x04
- 0 147 0x04>;
- };
-};
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
new file mode 100644
index 0000000..d25975e
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -0,0 +1,579 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra30";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &uarta;
+ serial1 = &uartb;
+ serial2 = &uartc;
+ serial3 = &uartd;
+ serial4 = &uarte;
+ };
+
+ host1x {
+ compatible = "nvidia,tegra30-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04>; /* mpcore general */
+ clocks = <&tegra_car 28>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ mpe {
+ compatible = "nvidia,tegra30-mpe";
+ reg = <0x54040000 0x00040000>;
+ interrupts = <0 68 0x04>;
+ clocks = <&tegra_car 60>;
+ };
+
+ vi {
+ compatible = "nvidia,tegra30-vi";
+ reg = <0x54080000 0x00040000>;
+ interrupts = <0 69 0x04>;
+ clocks = <&tegra_car 164>;
+ };
+
+ epp {
+ compatible = "nvidia,tegra30-epp";
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <0 70 0x04>;
+ clocks = <&tegra_car 19>;
+ };
+
+ isp {
+ compatible = "nvidia,tegra30-isp";
+ reg = <0x54100000 0x00040000>;
+ interrupts = <0 71 0x04>;
+ clocks = <&tegra_car 23>;
+ };
+
+ gr2d {
+ compatible = "nvidia,tegra30-gr2d";
+ reg = <0x54140000 0x00040000>;
+ interrupts = <0 72 0x04>;
+ clocks = <&tegra_car 21>;
+ };
+
+ gr3d {
+ compatible = "nvidia,tegra30-gr3d";
+ reg = <0x54180000 0x00040000>;
+ clocks = <&tegra_car 24 &tegra_car 98>;
+ clock-names = "3d", "3d2";
+ };
+
+ dc@54200000 {
+ compatible = "nvidia,tegra30-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <0 73 0x04>;
+ clocks = <&tegra_car 27>, <&tegra_car 179>;
+ clock-names = "disp1", "parent";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra30-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <0 74 0x04>;
+ clocks = <&tegra_car 26>, <&tegra_car 179>;
+ clock-names = "disp2", "parent";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ hdmi {
+ compatible = "nvidia,tegra30-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <0 75 0x04>;
+ clocks = <&tegra_car 51>, <&tegra_car 189>;
+ clock-names = "hdmi", "parent";
+ status = "disabled";
+ };
+
+ tvo {
+ compatible = "nvidia,tegra30-tvo";
+ reg = <0x542c0000 0x00040000>;
+ interrupts = <0 76 0x04>;
+ clocks = <&tegra_car 169>;
+ status = "disabled";
+ };
+
+ dsi {
+ compatible = "nvidia,tegra30-dsi";
+ reg = <0x54300000 0x00040000>;
+ clocks = <&tegra_car 48>;
+ status = "disabled";
+ };
+ };
+
+ timer@50004600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x50040600 0x20>;
+ interrupts = <1 13 0xf04>;
+ };
+
+ intc: interrupt-controller {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x50041000 0x1000
+ 0x50040100 0x0100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <6 6 2>;
+ arm,tag-latency = <5 5 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04
+ 0 121 0x04
+ 0 122 0x04>;
+ };
+
+ tegra_car: clock {
+ compatible = "nvidia,tegra30-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apbdma: dma {
+ compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+ reg = <0x6000a000 0x1400>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04>;
+ clocks = <&tegra_car 34>;
+ };
+
+ ahb: ahb {
+ compatible = "nvidia,tegra30-ahb";
+ reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
+ };
+
+ gpio: gpio {
+ compatible = "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ pinmux: pinmux {
+ compatible = "nvidia,tegra30-pinmux";
+ reg = <0x70000868 0xd4 /* Pad control registers */
+ 0x70003000 0x3e4>; /* Mux registers */
+ };
+
+ /*
+ * There are two serial driver i.e. 8250 based simple serial
+ * driver and APB DMA based serial driver for higher baudrate
+ * and performace. To enable the 8250 based driver, the compatible
+ * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
+ * the APB DMA based serial driver, the comptible is
+ * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+ */
+ uarta: serial@70006000 {
+ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = <0 36 0x04>;
+ clock-frequency = <408000000>;
+ nvidia,dma-request-selector = <&apbdma 8>;
+ clocks = <&tegra_car 6>;
+ status = "disabled";
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+ reg = <0x70006040 0x40>;
+ reg-shift = <2>;
+ clock-frequency = <408000000>;
+ interrupts = <0 37 0x04>;
+ nvidia,dma-request-selector = <&apbdma 9>;
+ clocks = <&tegra_car 160>;
+ status = "disabled";
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+ reg = <0x70006200 0x100>;
+ reg-shift = <2>;
+ clock-frequency = <408000000>;
+ interrupts = <0 46 0x04>;
+ nvidia,dma-request-selector = <&apbdma 10>;
+ clocks = <&tegra_car 55>;
+ status = "disabled";
+ };
+
+ uartd: serial@70006300 {
+ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+ reg = <0x70006300 0x100>;
+ reg-shift = <2>;
+ clock-frequency = <408000000>;
+ interrupts = <0 90 0x04>;
+ nvidia,dma-request-selector = <&apbdma 19>;
+ clocks = <&tegra_car 65>;
+ status = "disabled";
+ };
+
+ uarte: serial@70006400 {
+ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+ reg = <0x70006400 0x100>;
+ reg-shift = <2>;
+ clock-frequency = <408000000>;
+ interrupts = <0 91 0x04>;
+ nvidia,dma-request-selector = <&apbdma 20>;
+ clocks = <&tegra_car 66>;
+ status = "disabled";
+ };
+
+ pwm: pwm {
+ compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car 17>;
+ };
+
+ rtc {
+ compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 12>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 54>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 67>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <0 120 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 103>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
+ };
+
+ spi@7000d400 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 41>;
+ status = "disabled";
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 44>;
+ status = "disabled";
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 46>;
+ status = "disabled";
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 68>;
+ status = "disabled";
+ };
+
+ spi@7000dc00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-request-selector = <&apbdma 27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 104>;
+ status = "disabled";
+ };
+
+ spi@7000de00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-request-selector = <&apbdma 28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 105>;
+ status = "disabled";
+ };
+
+ kbc {
+ compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
+ reg = <0x7000e200 0x100>;
+ interrupts = <0 85 0x04>;
+ clocks = <&tegra_car 36>;
+ status = "disabled";
+ };
+
+ pmc {
+ compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+ reg = <0x7000e400 0x400>;
+ };
+
+ memory-controller {
+ compatible = "nvidia,tegra30-mc";
+ reg = <0x7000f000 0x010
+ 0x7000f03c 0x1b4
+ 0x7000f200 0x028
+ 0x7000f284 0x17c>;
+ interrupts = <0 77 0x04>;
+ };
+
+ iommu {
+ compatible = "nvidia,tegra30-smmu";
+ reg = <0x7000f010 0x02c
+ 0x7000f1f0 0x010
+ 0x7000f228 0x05c>;
+ nvidia,#asids = <4>; /* # of ASIDs */
+ dma-window = <0 0x40000000>; /* IOVA start & length */
+ nvidia,ahb = <&ahb>;
+ };
+
+ ahub {
+ compatible = "nvidia,tegra30-ahub";
+ reg = <0x70080000 0x200
+ 0x70080200 0x100>;
+ interrupts = <0 103 0x04>;
+ nvidia,dma-request-selector = <&apbdma 1>;
+ clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+ <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
+ <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
+ <&tegra_car 110>, <&tegra_car 162>;
+ clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+ "i2s3", "i2s4", "dam0", "dam1", "dam2",
+ "spdif_in";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tegra_i2s0: i2s@70080300 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080300 0x100>;
+ nvidia,ahub-cif-ids = <4 4>;
+ clocks = <&tegra_car 30>;
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@70080400 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080400 0x100>;
+ nvidia,ahub-cif-ids = <5 5>;
+ clocks = <&tegra_car 11>;
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@70080500 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080500 0x100>;
+ nvidia,ahub-cif-ids = <6 6>;
+ clocks = <&tegra_car 18>;
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@70080600 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080600 0x100>;
+ nvidia,ahub-cif-ids = <7 7>;
+ clocks = <&tegra_car 101>;
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@70080700 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080700 0x100>;
+ nvidia,ahub-cif-ids = <8 8>;
+ clocks = <&tegra_car 102>;
+ status = "disabled";
+ };
+ };
+
+ sdhci@78000000 {
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ reg = <0x78000000 0x200>;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
+ };
+
+ sdhci@78000200 {
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ reg = <0x78000200 0x200>;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
+ };
+
+ sdhci@78000400 {
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ reg = <0x78000400 0x200>;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
+ };
+
+ sdhci@78000600 {
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ reg = <0x78000600 0x200>;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 144 0x04
+ 0 145 0x04
+ 0 146 0x04
+ 0 147 0x04>;
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 7/9] ARM: tegra: create a DT header defining GPIO IDs
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
All Tegra GPIOs are named after the GPIO bank and GPIO number within
the bank. Define a macro to calculate the GPIO ID based on those
parameters. Make the macro available via all Tegra .dtsip files.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra-gpio.h | 45 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/tegra114.dtsip | 1 +
arch/arm/boot/dts/tegra20.dtsip | 1 +
arch/arm/boot/dts/tegra30.dtsip | 1 +
4 files changed, 48 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra-gpio.h
diff --git a/arch/arm/boot/dts/tegra-gpio.h b/arch/arm/boot/dts/tegra-gpio.h
new file mode 100644
index 0000000..aecc570
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-gpio.h
@@ -0,0 +1,45 @@
+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#include "gpio.h"
+
+#define TEGRA_GPIO_BANK_ID_A 0
+#define TEGRA_GPIO_BANK_ID_B 1
+#define TEGRA_GPIO_BANK_ID_C 2
+#define TEGRA_GPIO_BANK_ID_D 3
+#define TEGRA_GPIO_BANK_ID_E 4
+#define TEGRA_GPIO_BANK_ID_F 5
+#define TEGRA_GPIO_BANK_ID_G 6
+#define TEGRA_GPIO_BANK_ID_H 7
+#define TEGRA_GPIO_BANK_ID_I 8
+#define TEGRA_GPIO_BANK_ID_J 9
+#define TEGRA_GPIO_BANK_ID_K 10
+#define TEGRA_GPIO_BANK_ID_L 11
+#define TEGRA_GPIO_BANK_ID_M 12
+#define TEGRA_GPIO_BANK_ID_N 13
+#define TEGRA_GPIO_BANK_ID_O 14
+#define TEGRA_GPIO_BANK_ID_P 15
+#define TEGRA_GPIO_BANK_ID_Q 16
+#define TEGRA_GPIO_BANK_ID_R 17
+#define TEGRA_GPIO_BANK_ID_S 18
+#define TEGRA_GPIO_BANK_ID_T 19
+#define TEGRA_GPIO_BANK_ID_U 20
+#define TEGRA_GPIO_BANK_ID_V 21
+#define TEGRA_GPIO_BANK_ID_W 22
+#define TEGRA_GPIO_BANK_ID_X 23
+#define TEGRA_GPIO_BANK_ID_Y 24
+#define TEGRA_GPIO_BANK_ID_Z 25
+#define TEGRA_GPIO_BANK_ID_AA 26
+#define TEGRA_GPIO_BANK_ID_BB 27
+#define TEGRA_GPIO_BANK_ID_CC 28
+#define TEGRA_GPIO_BANK_ID_DD 29
+#define TEGRA_GPIO_BANK_ID_EE 30
+
+#define TEGRA_GPIO(bank, offset) \
+ ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
index d2150f0..356a8af 100644
--- a/arch/arm/boot/dts/tegra114.dtsip
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra114";
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 917edd4..1caece9 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra20";
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index d25975e..70b6ac7 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra30";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 7/9] ARM: tegra: create a DT header defining GPIO IDs
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
All Tegra GPIOs are named after the GPIO bank and GPIO number within
the bank. Define a macro to calculate the GPIO ID based on those
parameters. Make the macro available via all Tegra .dtsip files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra-gpio.h | 45 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/tegra114.dtsip | 1 +
arch/arm/boot/dts/tegra20.dtsip | 1 +
arch/arm/boot/dts/tegra30.dtsip | 1 +
4 files changed, 48 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra-gpio.h
diff --git a/arch/arm/boot/dts/tegra-gpio.h b/arch/arm/boot/dts/tegra-gpio.h
new file mode 100644
index 0000000..aecc570
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-gpio.h
@@ -0,0 +1,45 @@
+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#include "gpio.h"
+
+#define TEGRA_GPIO_BANK_ID_A 0
+#define TEGRA_GPIO_BANK_ID_B 1
+#define TEGRA_GPIO_BANK_ID_C 2
+#define TEGRA_GPIO_BANK_ID_D 3
+#define TEGRA_GPIO_BANK_ID_E 4
+#define TEGRA_GPIO_BANK_ID_F 5
+#define TEGRA_GPIO_BANK_ID_G 6
+#define TEGRA_GPIO_BANK_ID_H 7
+#define TEGRA_GPIO_BANK_ID_I 8
+#define TEGRA_GPIO_BANK_ID_J 9
+#define TEGRA_GPIO_BANK_ID_K 10
+#define TEGRA_GPIO_BANK_ID_L 11
+#define TEGRA_GPIO_BANK_ID_M 12
+#define TEGRA_GPIO_BANK_ID_N 13
+#define TEGRA_GPIO_BANK_ID_O 14
+#define TEGRA_GPIO_BANK_ID_P 15
+#define TEGRA_GPIO_BANK_ID_Q 16
+#define TEGRA_GPIO_BANK_ID_R 17
+#define TEGRA_GPIO_BANK_ID_S 18
+#define TEGRA_GPIO_BANK_ID_T 19
+#define TEGRA_GPIO_BANK_ID_U 20
+#define TEGRA_GPIO_BANK_ID_V 21
+#define TEGRA_GPIO_BANK_ID_W 22
+#define TEGRA_GPIO_BANK_ID_X 23
+#define TEGRA_GPIO_BANK_ID_Y 24
+#define TEGRA_GPIO_BANK_ID_Z 25
+#define TEGRA_GPIO_BANK_ID_AA 26
+#define TEGRA_GPIO_BANK_ID_BB 27
+#define TEGRA_GPIO_BANK_ID_CC 28
+#define TEGRA_GPIO_BANK_ID_DD 29
+#define TEGRA_GPIO_BANK_ID_EE 30
+
+#define TEGRA_GPIO(bank, offset) \
+ ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
index d2150f0..356a8af 100644
--- a/arch/arm/boot/dts/tegra114.dtsip
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra114";
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 917edd4..1caece9 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra20";
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index d25975e..70b6ac7 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,4 +1,5 @@
#include "skeleton.dtsi"
+#include "tegra-gpio.h"
/ {
compatible = "nvidia,tegra30";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 8/9] ARM: tegra: convert device tree files to use GPIO defines
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 16 +++++++-----
arch/arm/boot/dts/tegra20-harmony.dtsp | 36 ++++++++++++++++-----------
arch/arm/boot/dts/tegra20-iris-512.dtsp | 2 +-
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 4 +--
arch/arm/boot/dts/tegra20-paz00.dtsp | 24 ++++++++++--------
arch/arm/boot/dts/tegra20-plutux.dtsp | 4 +--
arch/arm/boot/dts/tegra20-seaboard.dtsp | 33 +++++++++++++-----------
arch/arm/boot/dts/tegra20-tamonten.dtsip | 7 +++---
arch/arm/boot/dts/tegra20-tec.dtsp | 5 ++--
arch/arm/boot/dts/tegra20-trimslice.dtsp | 17 +++++++------
arch/arm/boot/dts/tegra20-ventana.dtsp | 33 +++++++++++++-----------
arch/arm/boot/dts/tegra20-whistler.dtsp | 5 ++--
arch/arm/boot/dts/tegra30-beaver.dtsp | 14 +++++------
arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 8 +++---
arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 10 ++++----
arch/arm/boot/dts/tegra30-cardhu.dtsip | 35 +++++++++++++-------------
16 files changed, 141 insertions(+), 112 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
index bf8865b..b7d8e7a 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsip
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&i2c_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -434,17 +435,20 @@
ac97: ac97 {
status = "okay";
- nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+ nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000600 {
- cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
};
sound {
@@ -485,7 +489,7 @@
enable-active-high;
regulator-boot-on;
regulator-always-on;
- gpio = <&gpio 217 0>;
+ gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
};
};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
index 3fe66c1..c8de58b 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dtsp
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -262,7 +263,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -424,7 +425,8 @@
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
@@ -432,22 +434,23 @@
};
usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000200 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000600 {
status = "okay";
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@@ -619,7 +622,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -629,7 +632,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -653,8 +656,11 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dtsp b/arch/arm/boot/dts/tegra20-iris-512.dtsp
index a0ba0b0..239ef4d 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dtsp
+++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
@@ -73,7 +73,7 @@
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
- gpio = <&gpio 178 0>;
+ gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
vcc_sd_reg: regulator@1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index 6125604..66a5234 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -11,7 +11,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -53,6 +53,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index e40d7ee..cb9bf21 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -274,7 +275,7 @@
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <80000>;
- request-gpios = <&gpio 170 0>; /* gpio PV2 */
+ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
@@ -423,7 +424,8 @@
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
@@ -431,14 +433,15 @@
};
usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000000 {
status = "okay";
- cd-gpios = <&gpio 173 0>; /* gpio PV5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 169 0>; /* gpio PV1 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -452,7 +455,7 @@
power {
label = "Power";
- gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+ gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@@ -463,7 +466,7 @@
wifi {
label = "wifi-led";
- gpios = <&gpio 24 0>; /* gpio PD0 */
+ gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "rfkill0";
};
};
@@ -500,6 +503,7 @@
nvidia,audio-codec = <&alc5632>;
nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
index 08401b9..119c85a 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dtsp
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -51,6 +51,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
index 6534a61..a427c57 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dtsp
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -313,7 +314,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -328,14 +329,14 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /* GPIO PZ2 */
+ interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
};
gyrometer@68 {
compatible = "invn,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
- interrupts = <204 0x04>; /* gpio PZ4 */
+ interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
};
};
@@ -511,7 +512,7 @@
compatible = "ak,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
- interrupts = <109 0x04>; /* gpio PN5 */
+ interrupts = <TEGRA_GPIO(N, 5) 0x04>;
};
};
@@ -559,13 +560,14 @@
usb@c5000000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
@@ -573,20 +575,21 @@
};
usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000000 {
status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -600,14 +603,14 @@
power {
label = "Power";
- gpios = <&gpio 170 1>; /* gpio PV2, active low */
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
lid {
label = "Lid";
- gpios = <&gpio 23 0>; /* gpio PC7 */
+ gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
@@ -807,6 +810,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
index 089bbec..f1b44d8 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsip
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -465,8 +466,8 @@
};
sdhci@c8000600 {
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
index 331c81a..f655aca 100644
--- a/arch/arm/boot/dts/tegra20-tec.dtsp
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -51,6 +51,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dtsp b/arch/arm/boot/dts/tegra20-trimslice.dtsp
index 1f6cd20..a6713a5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dtsp
+++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -302,12 +303,13 @@
usb@c5000000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
@@ -315,7 +317,8 @@
};
usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000000 {
@@ -325,14 +328,14 @@
sdhci@c8000600 {
status = "okay";
- cd-gpios = <&gpio 121 0>; /* gpio PP1 */
- wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+ cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
poweroff {
compatible = "gpio-poweroff";
- gpios = <&gpio 191 1>; /* gpio PX7, active low */
+ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
regulators {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
index a5ae217..20a27f3 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dtsp
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -310,7 +311,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -325,7 +326,7 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /*gpio PZ2 */
+ interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
};
};
@@ -501,7 +502,8 @@
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
@@ -509,20 +511,21 @@
};
usb-phy@c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci@c8000000 {
status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -570,7 +573,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -580,7 +583,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -604,8 +607,10 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
index ee24daa..c8f2314 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dtsp
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -510,7 +511,7 @@
sdhci@c8000400 {
status = "okay";
- wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+ wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
index af23c94..6d815da 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dtsp
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -257,9 +257,9 @@
sdhci@78000000 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -316,7 +316,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -327,7 +327,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -339,7 +339,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -366,7 +366,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
index 64b7184..6ff21ea 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
@@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -80,13 +80,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 83 0>; /* GPIO PK3 */
+ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
- power-gpios = <&gpio 28 0>; /* gpio PD4 */
+ power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
index fc0d771..2957b69 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
@@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 238 0>; /* GPIO PDD6 */
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 236 0>; /* GPIO PDD4 */
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -80,7 +80,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 234 0>; /* GPIO PDD2 */
+ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
vdd_bl2_reg: regulator@106 {
@@ -92,13 +92,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 232 0>; /* GPIO PDD0 */
+ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
- power-gpios = <&gpio 27 0>; /* gpio PD3 */
+ power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
index 75ff544..4f99c5d 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsip
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -146,7 +146,7 @@
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <88 0x04>; /*gpio PL0 */
+ interrupts = <TEGRA_GPIO(L, 0) 0x04>;
};
};
@@ -163,7 +163,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <179 0x04>; /* gpio PW3 */
+ interrupts = <TEGRA_GPIO(W, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -311,9 +311,9 @@
sdhci@78000000 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -343,7 +343,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
- gpio = <&gpio 220 0>; /* gpio PBB4 */
+ gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&vio_reg>;
};
@@ -368,7 +368,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 25 0>; /* gpio PD1 */
+ gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -379,7 +379,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
};
pex_hvdd_3v3_reg: regulator@5 {
@@ -389,7 +389,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -400,7 +400,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
- gpio = <&gpio 142 0>; /* gpio PR6 */
+ gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -411,7 +411,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
- gpio = <&gpio 143 0>; /* gpio PR7 */
+ gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -422,7 +422,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 144 0>; /* gpio PS0 */
+ gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -435,7 +435,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 24 0>; /* gpio PD0 */
+ gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -446,7 +446,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 94 0>; /* gpio PL6 */
+ gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -459,7 +459,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 92 0>; /* gpio PL4 */
+ gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -470,7 +470,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 152 0>; /* GPIO PT0 */
+ gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -495,6 +495,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 8/9] ARM: tegra: convert device tree files to use GPIO defines
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 16 +++++++-----
arch/arm/boot/dts/tegra20-harmony.dtsp | 36 ++++++++++++++++-----------
arch/arm/boot/dts/tegra20-iris-512.dtsp | 2 +-
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 4 +--
arch/arm/boot/dts/tegra20-paz00.dtsp | 24 ++++++++++--------
arch/arm/boot/dts/tegra20-plutux.dtsp | 4 +--
arch/arm/boot/dts/tegra20-seaboard.dtsp | 33 +++++++++++++-----------
arch/arm/boot/dts/tegra20-tamonten.dtsip | 7 +++---
arch/arm/boot/dts/tegra20-tec.dtsp | 5 ++--
arch/arm/boot/dts/tegra20-trimslice.dtsp | 17 +++++++------
arch/arm/boot/dts/tegra20-ventana.dtsp | 33 +++++++++++++-----------
arch/arm/boot/dts/tegra20-whistler.dtsp | 5 ++--
arch/arm/boot/dts/tegra30-beaver.dtsp | 14 +++++------
arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 8 +++---
arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 10 ++++----
arch/arm/boot/dts/tegra30-cardhu.dtsip | 35 +++++++++++++-------------
16 files changed, 141 insertions(+), 112 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
index bf8865b..b7d8e7a 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsip
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&i2c_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -434,17 +435,20 @@
ac97: ac97 {
status = "okay";
- nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
- nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+ nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000600 {
- cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
};
sound {
@@ -485,7 +489,7 @@
enable-active-high;
regulator-boot-on;
regulator-always-on;
- gpio = <&gpio 217 0>;
+ gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
};
};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
index 3fe66c1..c8de58b 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dtsp
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -262,7 +263,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -424,7 +425,8 @@
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5008000 {
@@ -432,22 +434,23 @@
};
usb-phy at c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000200 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci at c8000600 {
status = "okay";
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@@ -619,7 +622,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -629,7 +632,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -653,8 +656,11 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dtsp b/arch/arm/boot/dts/tegra20-iris-512.dtsp
index a0ba0b0..239ef4d 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dtsp
+++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
@@ -73,7 +73,7 @@
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
- gpio = <&gpio 178 0>;
+ gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
vcc_sd_reg: regulator at 1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index 6125604..66a5234 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -11,7 +11,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -53,6 +53,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index e40d7ee..cb9bf21 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -274,7 +275,7 @@
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <80000>;
- request-gpios = <&gpio 170 0>; /* gpio PV2 */
+ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
@@ -423,7 +424,8 @@
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5008000 {
@@ -431,14 +433,15 @@
};
usb-phy at c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000000 {
status = "okay";
- cd-gpios = <&gpio 173 0>; /* gpio PV5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 169 0>; /* gpio PV1 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -452,7 +455,7 @@
power {
label = "Power";
- gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+ gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@@ -463,7 +466,7 @@
wifi {
label = "wifi-led";
- gpios = <&gpio 24 0>; /* gpio PD0 */
+ gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "rfkill0";
};
};
@@ -500,6 +503,7 @@
nvidia,audio-codec = <&alc5632>;
nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
index 08401b9..119c85a 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dtsp
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -51,6 +51,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
index 6534a61..a427c57 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dtsp
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -313,7 +314,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -328,14 +329,14 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /* GPIO PZ2 */
+ interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
};
gyrometer at 68 {
compatible = "invn,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
- interrupts = <204 0x04>; /* gpio PZ4 */
+ interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
};
};
@@ -511,7 +512,7 @@
compatible = "ak,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
- interrupts = <109 0x04>; /* gpio PN5 */
+ interrupts = <TEGRA_GPIO(N, 5) 0x04>;
};
};
@@ -559,13 +560,14 @@
usb at c5000000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5008000 {
@@ -573,20 +575,21 @@
};
usb-phy at c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000000 {
status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci at c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -600,14 +603,14 @@
power {
label = "Power";
- gpios = <&gpio 170 1>; /* gpio PV2, active low */
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
lid {
label = "Lid";
- gpios = <&gpio 23 0>; /* gpio PC7 */
+ gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
@@ -807,6 +810,6 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
index 089bbec..f1b44d8 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsip
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -465,8 +466,8 @@
};
sdhci at c8000600 {
- cd-gpios = <&gpio 58 0>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
index 331c81a..f655aca 100644
--- a/arch/arm/boot/dts/tegra20-tec.dtsp
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -51,6 +51,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dtsp b/arch/arm/boot/dts/tegra20-trimslice.dtsp
index 1f6cd20..a6713a5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dtsp
+++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -302,12 +303,13 @@
usb at c5000000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5008000 {
@@ -315,7 +317,8 @@
};
usb-phy at c5004400 {
- nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000000 {
@@ -325,14 +328,14 @@
sdhci at c8000600 {
status = "okay";
- cd-gpios = <&gpio 121 0>; /* gpio PP1 */
- wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+ cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
poweroff {
compatible = "gpio-poweroff";
- gpios = <&gpio 191 1>; /* gpio PX7, active low */
+ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
regulators {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
index a5ae217..20a27f3 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dtsp
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -310,7 +311,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <187 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -325,7 +326,7 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <202 0x04>; /*gpio PZ2 */
+ interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
};
};
@@ -501,7 +502,8 @@
usb at c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
usb at c5008000 {
@@ -509,20 +511,21 @@
};
usb-phy at c5004400 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_HIGH>;
};
sdhci at c8000000 {
status = "okay";
- power-gpios = <&gpio 86 0>; /* gpio PK6 */
+ power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci at c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -570,7 +573,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 22 0>; /* gpio PC6 */
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -580,7 +583,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- gpio = <&gpio 176 0>; /* gpio PW0 */
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -604,8 +607,10 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
- nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+ GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
index ee24daa..c8f2314 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dtsp
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -510,7 +511,7 @@
sdhci at c8000400 {
status = "okay";
- wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+ wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
index af23c94..6d815da 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dtsp
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -257,9 +257,9 @@
sdhci at 78000000 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -316,7 +316,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -327,7 +327,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -339,7 +339,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@@ -366,7 +366,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
index 64b7184..6ff21ea 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
@@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -80,13 +80,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 83 0>; /* GPIO PK3 */
+ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
};
};
sdhci at 78000400 {
status = "okay";
- power-gpios = <&gpio 28 0>; /* gpio PD4 */
+ power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
index fc0d771..2957b69 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
@@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 238 0>; /* GPIO PDD6 */
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 236 0>; /* GPIO PDD4 */
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -80,7 +80,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 234 0>; /* GPIO PDD2 */
+ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
vdd_bl2_reg: regulator at 106 {
@@ -92,13 +92,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 232 0>; /* GPIO PDD0 */
+ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
};
sdhci at 78000400 {
status = "okay";
- power-gpios = <&gpio 27 0>; /* gpio PD3 */
+ power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
index 75ff544..4f99c5d 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsip
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -146,7 +146,7 @@
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <88 0x04>; /*gpio PL0 */
+ interrupts = <TEGRA_GPIO(L, 0) 0x04>;
};
};
@@ -163,7 +163,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <179 0x04>; /* gpio PW3 */
+ interrupts = <TEGRA_GPIO(W, 3) 0x04>;
gpio-controller;
#gpio-cells = <2>;
@@ -311,9 +311,9 @@
sdhci at 78000000 {
status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -343,7 +343,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
- gpio = <&gpio 220 0>; /* gpio PBB4 */
+ gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&vio_reg>;
};
@@ -368,7 +368,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 25 0>; /* gpio PD1 */
+ gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -379,7 +379,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 30 0>; /* gpio PD6 */
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
};
pex_hvdd_3v3_reg: regulator at 5 {
@@ -389,7 +389,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 95 0>; /* gpio PL7 */
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -400,7 +400,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
- gpio = <&gpio 142 0>; /* gpio PR6 */
+ gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -411,7 +411,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
- gpio = <&gpio 143 0>; /* gpio PR7 */
+ gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -422,7 +422,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 144 0>; /* gpio PS0 */
+ gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -435,7 +435,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 24 0>; /* gpio PD0 */
+ gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -446,7 +446,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
- gpio = <&gpio 94 0>; /* gpio PL6 */
+ gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -459,7 +459,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
- gpio = <&gpio 92 0>; /* gpio PL4 */
+ gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@@ -470,7 +470,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio 152 0>; /* GPIO PT0 */
+ gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@@ -495,6 +495,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 9/9] ARM: tegra: convert device tree files to use IRQ defines
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 21:33 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Use the GIC and standard IRQ binding defines in all IRQ specifiers.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra114.dtsip | 55 +++++----
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 2 +-
arch/arm/boot/dts/tegra20-harmony.dtsp | 4 +-
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 2 +-
arch/arm/boot/dts/tegra20-paz00.dtsp | 4 +-
arch/arm/boot/dts/tegra20-plutux.dtsp | 2 +-
arch/arm/boot/dts/tegra20-seaboard.dtsp | 10 +-
arch/arm/boot/dts/tegra20-tamonten.dtsip | 2 +-
arch/arm/boot/dts/tegra20-tec.dtsp | 2 +-
arch/arm/boot/dts/tegra20-ventana.dtsp | 6 +-
arch/arm/boot/dts/tegra20-whistler.dtsp | 2 +-
arch/arm/boot/dts/tegra20.dtsip | 138 ++++++++++-----------
arch/arm/boot/dts/tegra30-beaver.dtsp | 2 +-
arch/arm/boot/dts/tegra30-cardhu.dtsip | 6 +-
arch/arm/boot/dts/tegra30.dtsip | 174 ++++++++++++++-------------
15 files changed, 211 insertions(+), 200 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
index 356a8af..52c0c03 100644
--- a/arch/arm/boot/dts/tegra114.dtsip
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra114";
@@ -13,18 +14,19 @@
<0x50042000 0x1000>,
<0x50044000 0x2000>,
<0x50046000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer@60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -41,14 +43,14 @@
gpio: gpio {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -65,7 +67,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -73,7 +75,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -81,7 +83,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -89,14 +91,14 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
pmc {
@@ -146,9 +148,14 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
index b7d8e7a..afdcd92 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsip
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -218,7 +218,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
index c8de58b..8513ad6 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dtsp
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -263,7 +263,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -291,7 +291,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index 66a5234..6837fc6 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -11,7 +11,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index cb9bf21..e63473b 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -271,7 +271,7 @@
nvec {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <80000>;
@@ -288,7 +288,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
index 119c85a..29b646c 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dtsp
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
index a427c57..f4da29e 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dtsp
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -314,7 +314,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -329,14 +329,14 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
gyrometer@68 {
compatible = "invn,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -389,7 +389,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@@ -512,7 +512,7 @@
compatible = "ak,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(N, 5) 0x04>;
+ interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
index f1b44d8..43c6048 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsip
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -322,7 +322,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
index f655aca..362b0da 100644
--- a/arch/arm/boot/dts/tegra20-tec.dtsp
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
index 20a27f3..eea712c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dtsp
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -311,7 +311,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -326,7 +326,7 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -372,7 +372,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
index c8f2314..2062780 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dtsp
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -282,7 +282,7 @@
max8907@3c {
compatible = "maxim,max8907";
reg = <0x3c>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
maxim,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 1caece9..7b05f53 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra20";
@@ -16,8 +17,8 @@
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>;
#address-cells = <1>;
@@ -28,35 +29,35 @@
mpe {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>;
};
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 100>;
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>;
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>;
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>;
};
@@ -69,7 +70,7 @@
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 121>;
clock-names = "disp1", "parent";
@@ -81,7 +82,7 @@
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 121>;
clock-names = "disp2", "parent";
@@ -93,7 +94,7 @@
hdmi {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 117>;
clock-names = "hdmi", "parent";
status = "disabled";
@@ -102,7 +103,7 @@
tvo {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 102>;
status = "disabled";
};
@@ -118,7 +119,8 @@
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
intc: interrupt-controller {
@@ -141,10 +143,10 @@
timer@60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -156,22 +158,22 @@
apbdma: dma {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>;
};
@@ -183,13 +185,13 @@
gpio: gpio {
compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -212,7 +214,7 @@
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
- interrupts = <0 81 0x04>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>;
status = "disabled";
@@ -221,7 +223,7 @@
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
- interrupts = <0 13 0x04>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>;
clocks = <&tegra_car 11>;
status = "disabled";
@@ -230,7 +232,7 @@
tegra_i2s2: i2s@70002a00 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>;
- interrupts = <0 3 0x04>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 18>;
status = "disabled";
@@ -247,7 +249,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
@@ -258,7 +260,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>;
@@ -269,7 +271,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
@@ -280,7 +282,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
@@ -291,7 +293,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
- interrupts = <0 91 0x04>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
@@ -308,13 +310,13 @@
rtc {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
@@ -325,7 +327,7 @@
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
- interrupts = <0 39 0x04>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>;
#size-cells = <0>;
@@ -336,7 +338,7 @@
i2c@7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 124>;
@@ -347,7 +349,7 @@
i2c@7000c500 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
@@ -358,7 +360,7 @@
i2c@7000d000 {
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>;
- interrupts = <0 53 0x04>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 124>;
@@ -369,7 +371,7 @@
spi@7000d400 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
@@ -380,7 +382,7 @@
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -391,7 +393,7 @@
spi@7000d800 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
@@ -402,7 +404,7 @@
spi@7000da00 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
@@ -413,7 +415,7 @@
kbc {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>;
status = "disabled";
};
@@ -427,7 +429,7 @@
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
- interrupts = <0 77 0x04>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@@ -446,7 +448,7 @@
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
- interrupts = <0 20 0x04>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>;
@@ -467,7 +469,7 @@
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
- interrupts = <0 21 0x04>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car 58>;
nvidia,phy = <&phy2>;
@@ -485,7 +487,7 @@
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
- interrupts = <0 97 0x04>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 59>;
nvidia,phy = <&phy3>;
@@ -503,7 +505,7 @@
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
- interrupts = <0 14 0x04>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>;
status = "disabled";
};
@@ -511,7 +513,7 @@
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
- interrupts = <0 15 0x04>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>;
status = "disabled";
};
@@ -519,7 +521,7 @@
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
- interrupts = <0 19 0x04>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>;
status = "disabled";
};
@@ -527,7 +529,7 @@
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
- interrupts = <0 31 0x04>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>;
status = "disabled";
};
@@ -551,7 +553,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 56 0x04
- 0 57 0x04>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
index 6d815da..cbac057 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dtsp
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -133,7 +133,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
index 4f99c5d..8079533 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsip
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -146,7 +146,7 @@
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(L, 0) 0x04>;
+ interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -163,7 +163,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -190,7 +190,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index 70b6ac7..0148459 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra30";
@@ -16,8 +17,8 @@
host1x {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>;
#address-cells = <1>;
@@ -28,35 +29,35 @@
mpe {
compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>;
};
vi {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 164>;
};
epp {
compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>;
};
isp {
compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>;
};
gr2d {
compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>;
};
@@ -70,7 +71,7 @@
dc@54200000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 179>;
clock-names = "disp1", "parent";
@@ -82,7 +83,7 @@
dc@54240000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 179>;
clock-names = "disp2", "parent";
@@ -94,7 +95,7 @@
hdmi {
compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 189>;
clock-names = "hdmi", "parent";
status = "disabled";
@@ -103,7 +104,7 @@
tvo {
compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 169>;
status = "disabled";
};
@@ -119,7 +120,8 @@
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
- interrupts = <1 13 0xf04>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
intc: interrupt-controller {
@@ -142,12 +144,12 @@
timer@60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -159,38 +161,38 @@
apbdma: dma {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04
- 0 128 0x04
- 0 129 0x04
- 0 130 0x04
- 0 131 0x04
- 0 132 0x04
- 0 133 0x04
- 0 134 0x04
- 0 135 0x04
- 0 136 0x04
- 0 137 0x04
- 0 138 0x04
- 0 139 0x04
- 0 140 0x04
- 0 141 0x04
- 0 142 0x04
- 0 143 0x04>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>;
};
@@ -202,14 +204,14 @@
gpio: gpio {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -234,7 +236,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <408000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
@@ -246,7 +248,7 @@
reg = <0x70006040 0x40>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
status = "disabled";
@@ -257,7 +259,7 @@
reg = <0x70006200 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
status = "disabled";
@@ -268,7 +270,7 @@
reg = <0x70006300 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
status = "disabled";
@@ -279,7 +281,7 @@
reg = <0x70006400 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 91 0x04>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
status = "disabled";
@@ -295,13 +297,13 @@
rtc {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 182>;
@@ -312,7 +314,7 @@
i2c@7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 182>;
@@ -323,7 +325,7 @@
i2c@7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 182>;
@@ -334,7 +336,7 @@
i2c@7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
- interrupts = <0 120 0x04>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>, <&tegra_car 182>;
@@ -345,7 +347,7 @@
i2c@7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>;
- interrupts = <0 53 0x04>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 182>;
@@ -356,7 +358,7 @@
spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
@@ -367,7 +369,7 @@
spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -378,7 +380,7 @@
spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
@@ -389,7 +391,7 @@
spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
@@ -400,7 +402,7 @@
spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>;
- interrupts = <0 94 0x04>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
@@ -411,7 +413,7 @@
spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>;
- interrupts = <0 79 0x04>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
@@ -422,7 +424,7 @@
kbc {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>;
status = "disabled";
};
@@ -438,7 +440,7 @@
0x7000f03c 0x1b4
0x7000f200 0x028
0x7000f284 0x17c>;
- interrupts = <0 77 0x04>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@@ -455,7 +457,7 @@
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
0x70080200 0x100>;
- interrupts = <0 103 0x04>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
@@ -512,7 +514,7 @@
sdhci@78000000 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
- interrupts = <0 14 0x04>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>;
status = "disabled";
};
@@ -520,7 +522,7 @@
sdhci@78000200 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
- interrupts = <0 15 0x04>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>;
status = "disabled";
};
@@ -528,7 +530,7 @@
sdhci@78000400 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
- interrupts = <0 19 0x04>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>;
status = "disabled";
};
@@ -536,7 +538,7 @@
sdhci@78000600 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
- interrupts = <0 31 0x04>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>;
status = "disabled";
};
@@ -572,9 +574,9 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 144 0x04
- 0 145 0x04
- 0 146 0x04
- 0 147 0x04>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 9/9] ARM: tegra: convert device tree files to use IRQ defines
@ 2013-02-13 21:33 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 21:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Use the GIC and standard IRQ binding defines in all IRQ specifiers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra114.dtsip | 55 +++++----
arch/arm/boot/dts/tegra20-colibri-512.dtsip | 2 +-
arch/arm/boot/dts/tegra20-harmony.dtsp | 4 +-
arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 2 +-
arch/arm/boot/dts/tegra20-paz00.dtsp | 4 +-
arch/arm/boot/dts/tegra20-plutux.dtsp | 2 +-
arch/arm/boot/dts/tegra20-seaboard.dtsp | 10 +-
arch/arm/boot/dts/tegra20-tamonten.dtsip | 2 +-
arch/arm/boot/dts/tegra20-tec.dtsp | 2 +-
arch/arm/boot/dts/tegra20-ventana.dtsp | 6 +-
arch/arm/boot/dts/tegra20-whistler.dtsp | 2 +-
arch/arm/boot/dts/tegra20.dtsip | 138 ++++++++++-----------
arch/arm/boot/dts/tegra30-beaver.dtsp | 2 +-
arch/arm/boot/dts/tegra30-cardhu.dtsip | 6 +-
arch/arm/boot/dts/tegra30.dtsip | 174 ++++++++++++++-------------
15 files changed, 211 insertions(+), 200 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
index 356a8af..52c0c03 100644
--- a/arch/arm/boot/dts/tegra114.dtsip
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra114";
@@ -13,18 +14,19 @@
<0x50042000 0x1000>,
<0x50044000 0x2000>,
<0x50046000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer at 60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -41,14 +43,14 @@
gpio: gpio {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -65,7 +67,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -73,7 +75,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -81,7 +83,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -89,14 +91,14 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
pmc {
@@ -146,9 +148,14 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
index b7d8e7a..afdcd92 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsip
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -218,7 +218,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
index c8de58b..8513ad6 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dtsp
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -263,7 +263,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -291,7 +291,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index 66a5234..6837fc6 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -11,7 +11,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index cb9bf21..e63473b 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -271,7 +271,7 @@
nvec {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <80000>;
@@ -288,7 +288,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
index 119c85a..29b646c 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dtsp
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
index a427c57..f4da29e 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dtsp
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -314,7 +314,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -329,14 +329,14 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
gyrometer at 68 {
compatible = "invn,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 4) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -389,7 +389,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@@ -512,7 +512,7 @@
compatible = "ak,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(N, 5) 0x04>;
+ interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
index f1b44d8..43c6048 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsip
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -322,7 +322,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
index f655aca..362b0da 100644
--- a/arch/arm/boot/dts/tegra20-tec.dtsp
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
index 20a27f3..eea712c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dtsp
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -311,7 +311,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -326,7 +326,7 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Z, 2) 0x04>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -372,7 +372,7 @@
pmic: tps6586x at 34 {
compatible = "ti,tps6586x";
reg = <0x34>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
index c8f2314..2062780 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dtsp
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -282,7 +282,7 @@
max8907 at 3c {
compatible = "maxim,max8907";
reg = <0x3c>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
maxim,system-power-controller;
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 1caece9..7b05f53 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra20";
@@ -16,8 +17,8 @@
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>;
#address-cells = <1>;
@@ -28,35 +29,35 @@
mpe {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>;
};
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 100>;
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>;
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>;
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>;
};
@@ -69,7 +70,7 @@
dc at 54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 121>;
clock-names = "disp1", "parent";
@@ -81,7 +82,7 @@
dc at 54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 121>;
clock-names = "disp2", "parent";
@@ -93,7 +94,7 @@
hdmi {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 117>;
clock-names = "hdmi", "parent";
status = "disabled";
@@ -102,7 +103,7 @@
tvo {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 102>;
status = "disabled";
};
@@ -118,7 +119,8 @@
timer at 50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
intc: interrupt-controller {
@@ -141,10 +143,10 @@
timer at 60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -156,22 +158,22 @@
apbdma: dma {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>;
};
@@ -183,13 +185,13 @@
gpio: gpio {
compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -212,7 +214,7 @@
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
- interrupts = <0 81 0x04>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>;
status = "disabled";
@@ -221,7 +223,7 @@
tegra_i2s1: i2s at 70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
- interrupts = <0 13 0x04>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>;
clocks = <&tegra_car 11>;
status = "disabled";
@@ -230,7 +232,7 @@
tegra_i2s2: i2s at 70002a00 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>;
- interrupts = <0 3 0x04>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 18>;
status = "disabled";
@@ -247,7 +249,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
@@ -258,7 +260,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>;
@@ -269,7 +271,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
@@ -280,7 +282,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
@@ -291,7 +293,7 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
- interrupts = <0 91 0x04>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
@@ -308,13 +310,13 @@
rtc {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
i2c at 7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
@@ -325,7 +327,7 @@
spi at 7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
- interrupts = <0 39 0x04>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>;
#size-cells = <0>;
@@ -336,7 +338,7 @@
i2c at 7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 124>;
@@ -347,7 +349,7 @@
i2c at 7000c500 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
@@ -358,7 +360,7 @@
i2c at 7000d000 {
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>;
- interrupts = <0 53 0x04>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 124>;
@@ -369,7 +371,7 @@
spi at 7000d400 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
@@ -380,7 +382,7 @@
spi at 7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -391,7 +393,7 @@
spi at 7000d800 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
@@ -402,7 +404,7 @@
spi at 7000da00 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
@@ -413,7 +415,7 @@
kbc {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>;
status = "disabled";
};
@@ -427,7 +429,7 @@
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
- interrupts = <0 77 0x04>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@@ -446,7 +448,7 @@
usb at c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
- interrupts = <0 20 0x04>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>;
@@ -467,7 +469,7 @@
usb at c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
- interrupts = <0 21 0x04>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car 58>;
nvidia,phy = <&phy2>;
@@ -485,7 +487,7 @@
usb at c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
- interrupts = <0 97 0x04>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 59>;
nvidia,phy = <&phy3>;
@@ -503,7 +505,7 @@
sdhci at c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
- interrupts = <0 14 0x04>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>;
status = "disabled";
};
@@ -511,7 +513,7 @@
sdhci at c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
- interrupts = <0 15 0x04>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>;
status = "disabled";
};
@@ -519,7 +521,7 @@
sdhci at c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
- interrupts = <0 19 0x04>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>;
status = "disabled";
};
@@ -527,7 +529,7 @@
sdhci at c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
- interrupts = <0 31 0x04>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>;
status = "disabled";
};
@@ -551,7 +553,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 56 0x04
- 0 57 0x04>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
index 6d815da..cbac057 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dtsp
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -133,7 +133,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
index 4f99c5d..8079533 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsip
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -146,7 +146,7 @@
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(L, 0) 0x04>;
+ interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -163,7 +163,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) 0x04>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@@ -190,7 +190,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
- interrupts = <0 86 0x4>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index 70b6ac7..0148459 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
+#include "arm-gic.h"
/ {
compatible = "nvidia,tegra30";
@@ -16,8 +17,8 @@
host1x {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>;
#address-cells = <1>;
@@ -28,35 +29,35 @@
mpe {
compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>;
};
vi {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 164>;
};
epp {
compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>;
};
isp {
compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>;
};
gr2d {
compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>;
};
@@ -70,7 +71,7 @@
dc at 54200000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 179>;
clock-names = "disp1", "parent";
@@ -82,7 +83,7 @@
dc at 54240000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 179>;
clock-names = "disp2", "parent";
@@ -94,7 +95,7 @@
hdmi {
compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 189>;
clock-names = "hdmi", "parent";
status = "disabled";
@@ -103,7 +104,7 @@
tvo {
compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 169>;
status = "disabled";
};
@@ -119,7 +120,8 @@
timer at 50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
- interrupts = <1 13 0xf04>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
intc: interrupt-controller {
@@ -142,12 +144,12 @@
timer at 60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
- interrupts = <0 0 0x04
- 0 1 0x04
- 0 41 0x04
- 0 42 0x04
- 0 121 0x04
- 0 122 0x04>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
};
tegra_car: clock {
@@ -159,38 +161,38 @@
apbdma: dma {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04
- 0 128 0x04
- 0 129 0x04
- 0 130 0x04
- 0 131 0x04
- 0 132 0x04
- 0 133 0x04
- 0 134 0x04
- 0 135 0x04
- 0 136 0x04
- 0 137 0x04
- 0 138 0x04
- 0 139 0x04
- 0 140 0x04
- 0 141 0x04
- 0 142 0x04
- 0 143 0x04>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>;
};
@@ -202,14 +204,14 @@
gpio: gpio {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@@ -234,7 +236,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
- interrupts = <0 36 0x04>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <408000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
@@ -246,7 +248,7 @@
reg = <0x70006040 0x40>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 37 0x04>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
status = "disabled";
@@ -257,7 +259,7 @@
reg = <0x70006200 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 46 0x04>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
status = "disabled";
@@ -268,7 +270,7 @@
reg = <0x70006300 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 90 0x04>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
status = "disabled";
@@ -279,7 +281,7 @@
reg = <0x70006400 0x100>;
reg-shift = <2>;
clock-frequency = <408000000>;
- interrupts = <0 91 0x04>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
status = "disabled";
@@ -295,13 +297,13 @@
rtc {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
i2c at 7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 182>;
@@ -312,7 +314,7 @@
i2c at 7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 182>;
@@ -323,7 +325,7 @@
i2c at 7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 182>;
@@ -334,7 +336,7 @@
i2c at 7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
- interrupts = <0 120 0x04>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>, <&tegra_car 182>;
@@ -345,7 +347,7 @@
i2c at 7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>;
- interrupts = <0 53 0x04>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 182>;
@@ -356,7 +358,7 @@
spi at 7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
@@ -367,7 +369,7 @@
spi at 7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -378,7 +380,7 @@
spi at 7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
@@ -389,7 +391,7 @@
spi at 7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
@@ -400,7 +402,7 @@
spi at 7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>;
- interrupts = <0 94 0x04>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
@@ -411,7 +413,7 @@
spi at 7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>;
- interrupts = <0 79 0x04>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
@@ -422,7 +424,7 @@
kbc {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
- interrupts = <0 85 0x04>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>;
status = "disabled";
};
@@ -438,7 +440,7 @@
0x7000f03c 0x1b4
0x7000f200 0x028
0x7000f284 0x17c>;
- interrupts = <0 77 0x04>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@@ -455,7 +457,7 @@
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
0x70080200 0x100>;
- interrupts = <0 103 0x04>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
@@ -512,7 +514,7 @@
sdhci at 78000000 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
- interrupts = <0 14 0x04>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>;
status = "disabled";
};
@@ -520,7 +522,7 @@
sdhci at 78000200 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
- interrupts = <0 15 0x04>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>;
status = "disabled";
};
@@ -528,7 +530,7 @@
sdhci at 78000400 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
- interrupts = <0 19 0x04>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>;
status = "disabled";
};
@@ -536,7 +538,7 @@
sdhci at 78000600 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
- interrupts = <0 31 0x04>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>;
status = "disabled";
};
@@ -572,9 +574,9 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 144 0x04
- 0 145 0x04
- 0 146 0x04
- 0 147 0x04>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-13 22:21 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 22:21 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This enables a C pre-processor pass on all Tegra device trees. This
allows future use of #defines and header files in order to define names
for various constants, such as the IDs and flags in GPIO specifiers.
Use of those features will increase the readability of the device tree
files.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/{tegra114-dalmore.dts => tegra114-dalmore.dtsp} | 2 +-
arch/arm/boot/dts/{tegra114-pluto.dts => tegra114-pluto.dtsp} | 2 +-
arch/arm/boot/dts/{tegra114.dtsi => tegra114.dtsip} | 2 +-
.../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri-512.dtsip} | 2 +-
arch/arm/boot/dts/{tegra20-harmony.dts => tegra20-harmony.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-iris-512.dts => tegra20-iris-512.dtsp} | 2 +-
.../boot/dts/{tegra20-medcom-wide.dts => tegra20-medcom-wide.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-paz00.dts => tegra20-paz00.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-plutux.dts => tegra20-plutux.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-seaboard.dts => tegra20-seaboard.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-tamonten.dtsi => tegra20-tamonten.dtsip} | 2 +-
arch/arm/boot/dts/{tegra20-tec.dts => tegra20-tec.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-trimslice.dts => tegra20-trimslice.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-ventana.dts => tegra20-ventana.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-whistler.dts => tegra20-whistler.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20.dtsi => tegra20.dtsip} | 2 +-
arch/arm/boot/dts/{tegra30-beaver.dts => tegra30-beaver.dtsp} | 2 +-
.../arm/boot/dts/{tegra30-cardhu-a02.dts => tegra30-cardhu-a02.dtsp} | 2 +-
.../arm/boot/dts/{tegra30-cardhu-a04.dts => tegra30-cardhu-a04.dtsp} | 2 +-
arch/arm/boot/dts/{tegra30-cardhu.dtsi => tegra30-cardhu.dtsip} | 2 +-
arch/arm/boot/dts/{tegra30.dtsi => tegra30.dtsip} | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
rename arch/arm/boot/dts/{tegra114-dalmore.dts => tegra114-dalmore.dtsp} (91%)
rename arch/arm/boot/dts/{tegra114-pluto.dts => tegra114-pluto.dtsp} (91%)
rename arch/arm/boot/dts/{tegra114.dtsi => tegra114.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri-512.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-harmony.dts => tegra20-harmony.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-iris-512.dts => tegra20-iris-512.dtsp} (97%)
rename arch/arm/boot/dts/{tegra20-medcom-wide.dts => tegra20-medcom-wide.dtsp} (97%)
rename arch/arm/boot/dts/{tegra20-paz00.dts => tegra20-paz00.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-plutux.dts => tegra20-plutux.dtsp} (96%)
rename arch/arm/boot/dts/{tegra20-seaboard.dts => tegra20-seaboard.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-tamonten.dtsi => tegra20-tamonten.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-tec.dts => tegra20-tec.dtsp} (96%)
rename arch/arm/boot/dts/{tegra20-trimslice.dts => tegra20-trimslice.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-ventana.dts => tegra20-ventana.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-whistler.dts => tegra20-whistler.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20.dtsi => tegra20.dtsip} (99%)
rename arch/arm/boot/dts/{tegra30-beaver.dts => tegra30-beaver.dtsp} (99%)
rename arch/arm/boot/dts/{tegra30-cardhu-a02.dts => tegra30-cardhu-a02.dtsp} (98%)
rename arch/arm/boot/dts/{tegra30-cardhu-a04.dts => tegra30-cardhu-a04.dtsp} (98%)
rename arch/arm/boot/dts/{tegra30-cardhu.dtsi => tegra30-cardhu.dtsip} (99%)
rename arch/arm/boot/dts/{tegra30.dtsi => tegra30.dtsip} (99%)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dtsp
similarity index 91%
rename from arch/arm/boot/dts/tegra114-dalmore.dts
rename to arch/arm/boot/dts/tegra114-dalmore.dtsp
index a30aca6..51f67cd 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsip"
/ {
model = "NVIDIA Tegra114 Dalmore evaluation board";
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dtsp
similarity index 91%
rename from arch/arm/boot/dts/tegra114-pluto.dts
rename to arch/arm/boot/dts/tegra114-pluto.dtsp
index 9bea8f5..40a88d1 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsip"
/ {
model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra114.dtsi
rename to arch/arm/boot/dts/tegra114.dtsip
index 1dfaf28..d2150f0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
rename to arch/arm/boot/dts/tegra20-colibri-512.dtsip
index 4441620..bf8865b 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Toradex Colibri T20 512MB";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-harmony.dts
rename to arch/arm/boot/dts/tegra20-harmony.dtsp
index 61d027f..3fe66c1 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Harmony evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dtsp
similarity index 97%
rename from arch/arm/boot/dts/tegra20-iris-512.dts
rename to arch/arm/boot/dts/tegra20-iris-512.dtsp
index 52f1103..a0ba0b0 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsip"
/ {
model = "Toradex Colibri T20 512MB on Iris";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
similarity index 97%
rename from arch/arm/boot/dts/tegra20-medcom-wide.dts
rename to arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index a2d6d65..6125604 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Medcom-Wide board";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-paz00.dts
rename to arch/arm/boot/dts/tegra20-paz00.dtsp
index 54d6fce..e40d7ee 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Toshiba AC100 / Dynabook AZ";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dtsp
similarity index 96%
rename from arch/arm/boot/dts/tegra20-plutux.dts
rename to arch/arm/boot/dts/tegra20-plutux.dtsp
index 2894800..08401b9 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Plutux board";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-seaboard.dts
rename to arch/arm/boot/dts/tegra20-seaboard.dtsp
index 37b3a57..6534a61 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Seaboard";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20-tamonten.dtsi
rename to arch/arm/boot/dts/tegra20-tamonten.dtsip
index 4766aba..089bbec 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Avionic Design Tamonten SOM";
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dtsp
similarity index 96%
rename from arch/arm/boot/dts/tegra20-tec.dts
rename to arch/arm/boot/dts/tegra20-tec.dtsp
index 402b210..331c81a 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Tamonten Evaluation Carrier";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-trimslice.dts
rename to arch/arm/boot/dts/tegra20-trimslice.dtsp
index 5d79e4f..1f6cd20 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Compulab TrimSlice board";
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-ventana.dts
rename to arch/arm/boot/dts/tegra20-ventana.dtsp
index 425c890..a5ae217 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-whistler.dts
rename to arch/arm/boot/dts/tegra20-whistler.dtsp
index ea57c0f..ee24daa 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Whistler evaluation board";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20.dtsi
rename to arch/arm/boot/dts/tegra20.dtsip
index 5916c93..917edd4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra30-beaver.dts
rename to arch/arm/boot/dts/tegra30-beaver.dtsp
index 8ff2ff2..af23c94 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsip"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
similarity index 98%
rename from arch/arm/boot/dts/tegra30-cardhu-a02.dts
rename to arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
index adc88aa..64b7184 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsip"
/* This dts file support the cardhu A02 version of board */
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
similarity index 98%
rename from arch/arm/boot/dts/tegra30-cardhu-a04.dts
rename to arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
index 08163e1..fc0d771 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsip"
/* This dts file support the cardhu A04 and later versions of board */
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra30-cardhu.dtsi
rename to arch/arm/boot/dts/tegra30-cardhu.dtsip
index 1749927..75ff544 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsip"
/**
* This file contains common DT entry for all fab version of Cardhu.
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra30.dtsi
rename to arch/arm/boot/dts/tegra30.dtsip
index 572a45b..d25975e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
@ 2013-02-13 22:21 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-13 22:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
This enables a C pre-processor pass on all Tegra device trees. This
allows future use of #defines and header files in order to define names
for various constants, such as the IDs and flags in GPIO specifiers.
Use of those features will increase the readability of the device tree
files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/{tegra114-dalmore.dts => tegra114-dalmore.dtsp} | 2 +-
arch/arm/boot/dts/{tegra114-pluto.dts => tegra114-pluto.dtsp} | 2 +-
arch/arm/boot/dts/{tegra114.dtsi => tegra114.dtsip} | 2 +-
.../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri-512.dtsip} | 2 +-
arch/arm/boot/dts/{tegra20-harmony.dts => tegra20-harmony.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-iris-512.dts => tegra20-iris-512.dtsp} | 2 +-
.../boot/dts/{tegra20-medcom-wide.dts => tegra20-medcom-wide.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-paz00.dts => tegra20-paz00.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-plutux.dts => tegra20-plutux.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-seaboard.dts => tegra20-seaboard.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-tamonten.dtsi => tegra20-tamonten.dtsip} | 2 +-
arch/arm/boot/dts/{tegra20-tec.dts => tegra20-tec.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-trimslice.dts => tegra20-trimslice.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-ventana.dts => tegra20-ventana.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20-whistler.dts => tegra20-whistler.dtsp} | 2 +-
arch/arm/boot/dts/{tegra20.dtsi => tegra20.dtsip} | 2 +-
arch/arm/boot/dts/{tegra30-beaver.dts => tegra30-beaver.dtsp} | 2 +-
.../arm/boot/dts/{tegra30-cardhu-a02.dts => tegra30-cardhu-a02.dtsp} | 2 +-
.../arm/boot/dts/{tegra30-cardhu-a04.dts => tegra30-cardhu-a04.dtsp} | 2 +-
arch/arm/boot/dts/{tegra30-cardhu.dtsi => tegra30-cardhu.dtsip} | 2 +-
arch/arm/boot/dts/{tegra30.dtsi => tegra30.dtsip} | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
rename arch/arm/boot/dts/{tegra114-dalmore.dts => tegra114-dalmore.dtsp} (91%)
rename arch/arm/boot/dts/{tegra114-pluto.dts => tegra114-pluto.dtsp} (91%)
rename arch/arm/boot/dts/{tegra114.dtsi => tegra114.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri-512.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-harmony.dts => tegra20-harmony.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-iris-512.dts => tegra20-iris-512.dtsp} (97%)
rename arch/arm/boot/dts/{tegra20-medcom-wide.dts => tegra20-medcom-wide.dtsp} (97%)
rename arch/arm/boot/dts/{tegra20-paz00.dts => tegra20-paz00.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-plutux.dts => tegra20-plutux.dtsp} (96%)
rename arch/arm/boot/dts/{tegra20-seaboard.dts => tegra20-seaboard.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-tamonten.dtsi => tegra20-tamonten.dtsip} (99%)
rename arch/arm/boot/dts/{tegra20-tec.dts => tegra20-tec.dtsp} (96%)
rename arch/arm/boot/dts/{tegra20-trimslice.dts => tegra20-trimslice.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-ventana.dts => tegra20-ventana.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20-whistler.dts => tegra20-whistler.dtsp} (99%)
rename arch/arm/boot/dts/{tegra20.dtsi => tegra20.dtsip} (99%)
rename arch/arm/boot/dts/{tegra30-beaver.dts => tegra30-beaver.dtsp} (99%)
rename arch/arm/boot/dts/{tegra30-cardhu-a02.dts => tegra30-cardhu-a02.dtsp} (98%)
rename arch/arm/boot/dts/{tegra30-cardhu-a04.dts => tegra30-cardhu-a04.dtsp} (98%)
rename arch/arm/boot/dts/{tegra30-cardhu.dtsi => tegra30-cardhu.dtsip} (99%)
rename arch/arm/boot/dts/{tegra30.dtsi => tegra30.dtsip} (99%)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dtsp
similarity index 91%
rename from arch/arm/boot/dts/tegra114-dalmore.dts
rename to arch/arm/boot/dts/tegra114-dalmore.dtsp
index a30aca6..51f67cd 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsip"
/ {
model = "NVIDIA Tegra114 Dalmore evaluation board";
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dtsp
similarity index 91%
rename from arch/arm/boot/dts/tegra114-pluto.dts
rename to arch/arm/boot/dts/tegra114-pluto.dtsp
index 9bea8f5..40a88d1 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsip"
/ {
model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra114.dtsi
rename to arch/arm/boot/dts/tegra114.dtsip
index 1dfaf28..d2150f0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
rename to arch/arm/boot/dts/tegra20-colibri-512.dtsip
index 4441620..bf8865b 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Toradex Colibri T20 512MB";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-harmony.dts
rename to arch/arm/boot/dts/tegra20-harmony.dtsp
index 61d027f..3fe66c1 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Harmony evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dtsp
similarity index 97%
rename from arch/arm/boot/dts/tegra20-iris-512.dts
rename to arch/arm/boot/dts/tegra20-iris-512.dtsp
index 52f1103..a0ba0b0 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsip"
/ {
model = "Toradex Colibri T20 512MB on Iris";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
similarity index 97%
rename from arch/arm/boot/dts/tegra20-medcom-wide.dts
rename to arch/arm/boot/dts/tegra20-medcom-wide.dtsp
index a2d6d65..6125604 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Medcom-Wide board";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-paz00.dts
rename to arch/arm/boot/dts/tegra20-paz00.dtsp
index 54d6fce..e40d7ee 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Toshiba AC100 / Dynabook AZ";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dtsp
similarity index 96%
rename from arch/arm/boot/dts/tegra20-plutux.dts
rename to arch/arm/boot/dts/tegra20-plutux.dtsp
index 2894800..08401b9 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Plutux board";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-seaboard.dts
rename to arch/arm/boot/dts/tegra20-seaboard.dtsp
index 37b3a57..6534a61 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Seaboard";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20-tamonten.dtsi
rename to arch/arm/boot/dts/tegra20-tamonten.dtsip
index 4766aba..089bbec 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Avionic Design Tamonten SOM";
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dtsp
similarity index 96%
rename from arch/arm/boot/dts/tegra20-tec.dts
rename to arch/arm/boot/dts/tegra20-tec.dtsp
index 402b210..331c81a 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsip"
/ {
model = "Avionic Design Tamonten Evaluation Carrier";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-trimslice.dts
rename to arch/arm/boot/dts/tegra20-trimslice.dtsp
index 5d79e4f..1f6cd20 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "Compulab TrimSlice board";
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-ventana.dts
rename to arch/arm/boot/dts/tegra20-ventana.dtsp
index 425c890..a5ae217 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra20-whistler.dts
rename to arch/arm/boot/dts/tegra20-whistler.dtsp
index ea57c0f..ee24daa 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsip"
/ {
model = "NVIDIA Tegra20 Whistler evaluation board";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra20.dtsi
rename to arch/arm/boot/dts/tegra20.dtsip
index 5916c93..917edd4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dtsp
similarity index 99%
rename from arch/arm/boot/dts/tegra30-beaver.dts
rename to arch/arm/boot/dts/tegra30-beaver.dtsp
index 8ff2ff2..af23c94 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsip"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
similarity index 98%
rename from arch/arm/boot/dts/tegra30-cardhu-a02.dts
rename to arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
index adc88aa..64b7184 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsip"
/* This dts file support the cardhu A02 version of board */
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
similarity index 98%
rename from arch/arm/boot/dts/tegra30-cardhu-a04.dts
rename to arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
index 08163e1..fc0d771 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsip"
/* This dts file support the cardhu A04 and later versions of board */
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra30-cardhu.dtsi
rename to arch/arm/boot/dts/tegra30-cardhu.dtsip
index 1749927..75ff544 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsip"
/**
* This file contains common DT entry for all fab version of Cardhu.
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsip
similarity index 99%
rename from arch/arm/boot/dts/tegra30.dtsi
rename to arch/arm/boot/dts/tegra30.dtsip
index 572a45b..d25975e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-13 21:33 ` Stephen Warren
(?)
@ 2013-02-14 6:38 ` Hiroshi Doyu
-1 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 6:38 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Hiroshi Doyu,
Stephen Warren, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
To replace magic number in "clocks = <&tegra_car 28>;"
Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch depends on:
[PATCH 0/9] ARM: tegra: use new dtc+cpp feature
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html
This patch is the experiment for Tegra20. The same replacement can be
done for Tegra{30,114}.
Usage:
Modified arch/arm/boot/dts/tegra20.dtsip
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 7b05f53..6edd397 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,6 +1,7 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
#include "arm-gic.h"
+#include "tegra20-car.h"
/ {
compatible = "nvidia,tegra20";
@@ -19,7 +20,7 @@
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra20-car.h | 126 +++++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra20-car.h
diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
new file mode 100644
index 0000000..6426320
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-car.h
@@ -0,0 +1,126 @@
+#define CLK_CPU 0
+/* UNUSED 1 */
+/* UNUSED 2 */
+#define CLK_AC97 3
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+/* UNUSED 7 */
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+/* UNUSED 10 */
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_TWC 16
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+/* UNUSED 20 */
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_IDE 25
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+/* UNUSED 30 */
+#define CLK_CACHE2 31
+#define CLK_MEM 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+/* UNUSED 35 */
+#define CLK_KBC 36
+#define CLK_STAT_MON 37
+#define CLK_PMC 38
+#define CLK_FUSE 39
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SPI 43
+#define CLK_SBC2 44
+#define CLK_XIO 45
+#define CLK_SBC3 46
+#define CLK_DVC 47
+#define CLK_DSI 48
+/* UNUSED 49 */
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+/* UNUSED 56 */
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PEX 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIE_XCLK 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+/* UNUSED 77-83 */
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 89
+#define CLK_CLK_D 90
+/* UNUSED 91 */
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+/* UNUSED 95 */
+#define CLK_UARTB 96
+#define CLK_VFIR 97
+#define CLK_SPDIF_IN 98
+#define CLK_SPDIF_OUT 99
+#define CLK_VI 100
+#define CLK_VI_SENSOR 101
+#define CLK_TVO 102
+#define CLK_CVE 103
+#define CLK_OSC 104
+#define CLK_CLK_32K 105
+#define CLK_CLK_M 106
+#define CLK_SCLK 107
+#define CLK_CCLK 108
+#define CLK_HCLK 109
+#define CLK_PCLK 110
+#define CLK_BLINK 111
+#define CLK_PLL_A 112
+#define CLK_PLL_A_OUT0 113
+#define CLK_PLL_C 114
+#define CLK_PLL_C_OUT1 115
+#define CLK_PLL_D 116
+#define CLK_PLL_D_OUT0 117
+#define CLK_PLL_E 118
+#define CLK_PLL_M 119
+#define CLK_PLL_M_OUT1 120
+#define CLK_PLL_P 121
+#define CLK_PLL_P_OUT1 122
+#define CLK_PLL_P_OUT2 123
+#define CLK_PLL_P_OUT3 124
+#define CLK_PLL_P_OUT4 125
+#define CLK_PLL_U 126
+#define CLK_PLL_X 127
+#define CLK_AUDIO 128
+#define CLK_PLL_REF 129
+#define CLK_TWD 130
+#define CLK_MAX 131
--
1.7.9.5
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 6:38 ` Hiroshi Doyu
0 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 6:38 UTC (permalink / raw)
To: linux-tegra
Cc: devicetree-discuss, Hiroshi Doyu, Stephen Warren, Russell King,
linux-arm-kernel, linux-kernel
To replace magic number in "clocks = <&tegra_car 28>;"
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
This patch depends on:
[PATCH 0/9] ARM: tegra: use new dtc+cpp feature
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html
This patch is the experiment for Tegra20. The same replacement can be
done for Tegra{30,114}.
Usage:
Modified arch/arm/boot/dts/tegra20.dtsip
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 7b05f53..6edd397 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,6 +1,7 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
#include "arm-gic.h"
+#include "tegra20-car.h"
/ {
compatible = "nvidia,tegra20";
@@ -19,7 +20,7 @@
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/boot/dts/tegra20-car.h | 126 +++++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra20-car.h
diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
new file mode 100644
index 0000000..6426320
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-car.h
@@ -0,0 +1,126 @@
+#define CLK_CPU 0
+/* UNUSED 1 */
+/* UNUSED 2 */
+#define CLK_AC97 3
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+/* UNUSED 7 */
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+/* UNUSED 10 */
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_TWC 16
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+/* UNUSED 20 */
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_IDE 25
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+/* UNUSED 30 */
+#define CLK_CACHE2 31
+#define CLK_MEM 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+/* UNUSED 35 */
+#define CLK_KBC 36
+#define CLK_STAT_MON 37
+#define CLK_PMC 38
+#define CLK_FUSE 39
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SPI 43
+#define CLK_SBC2 44
+#define CLK_XIO 45
+#define CLK_SBC3 46
+#define CLK_DVC 47
+#define CLK_DSI 48
+/* UNUSED 49 */
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+/* UNUSED 56 */
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PEX 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIE_XCLK 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+/* UNUSED 77-83 */
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 89
+#define CLK_CLK_D 90
+/* UNUSED 91 */
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+/* UNUSED 95 */
+#define CLK_UARTB 96
+#define CLK_VFIR 97
+#define CLK_SPDIF_IN 98
+#define CLK_SPDIF_OUT 99
+#define CLK_VI 100
+#define CLK_VI_SENSOR 101
+#define CLK_TVO 102
+#define CLK_CVE 103
+#define CLK_OSC 104
+#define CLK_CLK_32K 105
+#define CLK_CLK_M 106
+#define CLK_SCLK 107
+#define CLK_CCLK 108
+#define CLK_HCLK 109
+#define CLK_PCLK 110
+#define CLK_BLINK 111
+#define CLK_PLL_A 112
+#define CLK_PLL_A_OUT0 113
+#define CLK_PLL_C 114
+#define CLK_PLL_C_OUT1 115
+#define CLK_PLL_D 116
+#define CLK_PLL_D_OUT0 117
+#define CLK_PLL_E 118
+#define CLK_PLL_M 119
+#define CLK_PLL_M_OUT1 120
+#define CLK_PLL_P 121
+#define CLK_PLL_P_OUT1 122
+#define CLK_PLL_P_OUT2 123
+#define CLK_PLL_P_OUT3 124
+#define CLK_PLL_P_OUT4 125
+#define CLK_PLL_U 126
+#define CLK_PLL_X 127
+#define CLK_AUDIO 128
+#define CLK_PLL_REF 129
+#define CLK_TWD 130
+#define CLK_MAX 131
--
1.7.9.5
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 6:38 ` Hiroshi Doyu
0 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 6:38 UTC (permalink / raw)
To: linux-arm-kernel
To replace magic number in "clocks = <&tegra_car 28>;"
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
This patch depends on:
[PATCH 0/9] ARM: tegra: use new dtc+cpp feature
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html
This patch is the experiment for Tegra20. The same replacement can be
done for Tegra{30,114}.
Usage:
Modified arch/arm/boot/dts/tegra20.dtsip
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 7b05f53..6edd397 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,6 +1,7 @@
#include "skeleton.dtsi"
#include "tegra-gpio.h"
#include "arm-gic.h"
+#include "tegra20-car.h"
/ {
compatible = "nvidia,tegra20";
@@ -19,7 +20,7 @@
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/boot/dts/tegra20-car.h | 126 +++++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra20-car.h
diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
new file mode 100644
index 0000000..6426320
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-car.h
@@ -0,0 +1,126 @@
+#define CLK_CPU 0
+/* UNUSED 1 */
+/* UNUSED 2 */
+#define CLK_AC97 3
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+/* UNUSED 7 */
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+/* UNUSED 10 */
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_TWC 16
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+/* UNUSED 20 */
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_IDE 25
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+/* UNUSED 30 */
+#define CLK_CACHE2 31
+#define CLK_MEM 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+/* UNUSED 35 */
+#define CLK_KBC 36
+#define CLK_STAT_MON 37
+#define CLK_PMC 38
+#define CLK_FUSE 39
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SPI 43
+#define CLK_SBC2 44
+#define CLK_XIO 45
+#define CLK_SBC3 46
+#define CLK_DVC 47
+#define CLK_DSI 48
+/* UNUSED 49 */
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+/* UNUSED 56 */
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PEX 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIE_XCLK 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+/* UNUSED 77-83 */
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 89
+#define CLK_CLK_D 90
+/* UNUSED 91 */
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+/* UNUSED 95 */
+#define CLK_UARTB 96
+#define CLK_VFIR 97
+#define CLK_SPDIF_IN 98
+#define CLK_SPDIF_OUT 99
+#define CLK_VI 100
+#define CLK_VI_SENSOR 101
+#define CLK_TVO 102
+#define CLK_CVE 103
+#define CLK_OSC 104
+#define CLK_CLK_32K 105
+#define CLK_CLK_M 106
+#define CLK_SCLK 107
+#define CLK_CCLK 108
+#define CLK_HCLK 109
+#define CLK_PCLK 110
+#define CLK_BLINK 111
+#define CLK_PLL_A 112
+#define CLK_PLL_A_OUT0 113
+#define CLK_PLL_C 114
+#define CLK_PLL_C_OUT1 115
+#define CLK_PLL_D 116
+#define CLK_PLL_D_OUT0 117
+#define CLK_PLL_E 118
+#define CLK_PLL_M 119
+#define CLK_PLL_M_OUT1 120
+#define CLK_PLL_P 121
+#define CLK_PLL_P_OUT1 122
+#define CLK_PLL_P_OUT2 123
+#define CLK_PLL_P_OUT3 124
+#define CLK_PLL_P_OUT4 125
+#define CLK_PLL_U 126
+#define CLK_PLL_X 127
+#define CLK_AUDIO 128
+#define CLK_PLL_REF 129
+#define CLK_TWD 130
+#define CLK_MAX 131
--
1.7.9.5
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-14 6:38 ` Hiroshi Doyu
(?)
@ 2013-02-14 10:12 ` Peter De Schrijver
-1 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 10:12 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
>
But then we should probably also remove the enum tegra20_clk and replace it
with this header file. We should also consider removing the list of IDs from
the documentation and refer to the header file instead. Otherwise we will have
3 places which define the same IDs and we need to be sure they stay in sync...
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 10:12 ` Peter De Schrijver
0 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 10:12 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra, Russell King, devicetree-discuss, linux-kernel,
linux-arm-kernel
On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
>
But then we should probably also remove the enum tegra20_clk and replace it
with this header file. We should also consider removing the list of IDs from
the documentation and refer to the header file instead. Otherwise we will have
3 places which define the same IDs and we need to be sure they stay in sync...
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 10:12 ` Peter De Schrijver
0 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 10:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
>
But then we should probably also remove the enum tegra20_clk and replace it
with this header file. We should also consider removing the list of IDs from
the documentation and refer to the header file instead. Otherwise we will have
3 places which define the same IDs and we need to be sure they stay in sync...
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-14 10:12 ` Peter De Schrijver
(?)
@ 2013-02-14 13:42 ` Hiroshi Doyu
-1 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 13:42 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote @ Thu, 14 Feb 2013 11:12:20 +0100:
> On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
> >
>
> But then we should probably also remove the enum tegra20_clk and replace it
> with this header file. We should also consider removing the list of IDs from
> the documentation and refer to the header file instead. Otherwise we will have
> 3 places which define the same IDs and we need to be sure they stay in sync...
Actually I generate "arch/arm/boot/dts/tegra{20,30}-car.h" by parsing
"enum tegra{20,30}_clk {..};" with a python script.
There could be the same kind of requirement from others that both
"dtsip" and "C-source" want to share the same header file. If we
consider that DT is the exact H/W description, C-source should be able
to include a DT header file.
For example, a C-header file for "enum tegra{20,30}_clk" should be
generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
"arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 13:42 ` Hiroshi Doyu
0 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 13:42 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-tegra, linux, devicetree-discuss, linux-kernel, linux-arm-kernel
Peter De Schrijver <pdeschrijver@nvidia.com> wrote @ Thu, 14 Feb 2013 11:12:20 +0100:
> On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
> >
>
> But then we should probably also remove the enum tegra20_clk and replace it
> with this header file. We should also consider removing the list of IDs from
> the documentation and refer to the header file instead. Otherwise we will have
> 3 places which define the same IDs and we need to be sure they stay in sync...
Actually I generate "arch/arm/boot/dts/tegra{20,30}-car.h" by parsing
"enum tegra{20,30}_clk {..};" with a python script.
There could be the same kind of requirement from others that both
"dtsip" and "C-source" want to share the same header file. If we
consider that DT is the exact H/W description, C-source should be able
to include a DT header file.
For example, a C-header file for "enum tegra{20,30}_clk" should be
generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
"arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 13:42 ` Hiroshi Doyu
0 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 13:42 UTC (permalink / raw)
To: linux-arm-kernel
Peter De Schrijver <pdeschrijver@nvidia.com> wrote @ Thu, 14 Feb 2013 11:12:20 +0100:
> On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
> >
>
> But then we should probably also remove the enum tegra20_clk and replace it
> with this header file. We should also consider removing the list of IDs from
> the documentation and refer to the header file instead. Otherwise we will have
> 3 places which define the same IDs and we need to be sure they stay in sync...
Actually I generate "arch/arm/boot/dts/tegra{20,30}-car.h" by parsing
"enum tegra{20,30}_clk {..};" with a python script.
There could be the same kind of requirement from others that both
"dtsip" and "C-source" want to share the same header file. If we
consider that DT is the exact H/W description, C-source should be able
to include a DT header file.
For example, a C-header file for "enum tegra{20,30}_clk" should be
generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
"arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-14 13:42 ` Hiroshi Doyu
(?)
@ 2013-02-14 14:58 ` Peter De Schrijver
-1 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 14:58 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
> There could be the same kind of requirement from others that both
> "dtsip" and "C-source" want to share the same header file. If we
> consider that DT is the exact H/W description, C-source should be able
> to include a DT header file.
>
> For example, a C-header file for "enum tegra{20,30}_clk" should be
> generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
> alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
> "arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
Including arch/arm/boot/dts/tegra{20,30}-car.h seems to make much more sense
to me than generating a enum based on #defines... :)
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 14:58 ` Peter De Schrijver
0 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 14:58 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra, linux, devicetree-discuss, linux-kernel, linux-arm-kernel
> There could be the same kind of requirement from others that both
> "dtsip" and "C-source" want to share the same header file. If we
> consider that DT is the exact H/W description, C-source should be able
> to include a DT header file.
>
> For example, a C-header file for "enum tegra{20,30}_clk" should be
> generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
> alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
> "arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
Including arch/arm/boot/dts/tegra{20,30}-car.h seems to make much more sense
to me than generating a enum based on #defines... :)
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 14:58 ` Peter De Schrijver
0 siblings, 0 replies; 59+ messages in thread
From: Peter De Schrijver @ 2013-02-14 14:58 UTC (permalink / raw)
To: linux-arm-kernel
> There could be the same kind of requirement from others that both
> "dtsip" and "C-source" want to share the same header file. If we
> consider that DT is the exact H/W description, C-source should be able
> to include a DT header file.
>
> For example, a C-header file for "enum tegra{20,30}_clk" should be
> generated from "arch/arm/boot/dts/tegra{20,30}-car.h" at runtime, or
> alternatively just "drivers/clk/tegra/clk-tegra{20,30}.c" can include
> "arch/arm/boot/dts/tegra{20,30}-car.h"? The latter may be easier.
Including arch/arm/boot/dts/tegra{20,30}-car.h seems to make much more sense
to me than generating a enum based on #defines... :)
Cheers,
Peter.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-14 17:03 ` Tony Lindgren
-1 siblings, 0 replies; 59+ messages in thread
From: Tony Lindgren @ 2013-02-14 17:03 UTC (permalink / raw)
To: Stephen Warren
Cc: Grant Likely, Rob Herring, Olof Johansson, Arnd Bergmann,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
* Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> [130213 13:37]:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> This series converts the Tegra device tree files to use the new feature
> of running cpp over .dts files before compiling them with dtc. This
> allows GPIOs and other GPIO/IRQ specifier cells to be named for example.
>
> As far as merging goes, I'd anticipate the first 3 patches being useful
> to any other ARM sub-arch that wants to convert; perhaps they could go
> through some arm-soc common branch. The next 2 patches are Tegra-specific
> cleanup that I'd anticipate applying to Tegra's for-3.10/cleanup. The
> rest of the patches depend on those 5 previous patches, so would need to
> go into a Tegra branch that merges in the previous patches; I'd anticipate
> calling it for-3.10/dtc-cpp say.
Great! This will help a lot with making the .dts* files readable.
> One issue this raises: The first 2 patches aren't ARM-specific. I put the
> files they create into arch/arm/boot/dts, but I wonder if they wouldn't be
> better in some arch-agnostic include directory, or even right with the
> binding documentation in Documentation/devicetree/bindings. Moving the
> files would require adjusting the cpp include path.
I'd assume this will be used by many architectures, so it would probably
be a good idea to make them common to start with.
Regards,
Tony
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
@ 2013-02-14 17:03 ` Tony Lindgren
0 siblings, 0 replies; 59+ messages in thread
From: Tony Lindgren @ 2013-02-14 17:03 UTC (permalink / raw)
To: linux-arm-kernel
* Stephen Warren <swarren@wwwdotorg.org> [130213 13:37]:
> From: Stephen Warren <swarren@nvidia.com>
>
> This series converts the Tegra device tree files to use the new feature
> of running cpp over .dts files before compiling them with dtc. This
> allows GPIOs and other GPIO/IRQ specifier cells to be named for example.
>
> As far as merging goes, I'd anticipate the first 3 patches being useful
> to any other ARM sub-arch that wants to convert; perhaps they could go
> through some arm-soc common branch. The next 2 patches are Tegra-specific
> cleanup that I'd anticipate applying to Tegra's for-3.10/cleanup. The
> rest of the patches depend on those 5 previous patches, so would need to
> go into a Tegra branch that merges in the previous patches; I'd anticipate
> calling it for-3.10/dtc-cpp say.
Great! This will help a lot with making the .dts* files readable.
> One issue this raises: The first 2 patches aren't ARM-specific. I put the
> files they create into arch/arm/boot/dts, but I wonder if they wouldn't be
> better in some arch-agnostic include directory, or even right with the
> binding documentation in Documentation/devicetree/bindings. Moving the
> files would require adjusting the cpp include path.
I'd assume this will be used by many architectures, so it would probably
be a good idea to make them common to start with.
Regards,
Tony
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
[not found] ` <1360791198-29462-7-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
@ 2013-02-14 17:41 ` Rob Herring
[not found] ` <511D21E7.5090307-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-03-04 8:44 ` Grant Likely
1 sibling, 1 reply; 59+ messages in thread
From: Rob Herring @ 2013-02-14 17:41 UTC (permalink / raw)
To: Stephen Warren
Cc: Grant Likely, Olof Johansson, Arnd Bergmann,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On 02/13/2013 03:33 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> This enables a C pre-processor pass on all Tegra device trees. This
> allows future use of #defines and header files in order to define names
> for various constants, such as the IDs and flags in GPIO specifiers.
> Use of those features will increase the readability of the device tree
> files.
>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
> arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
> arch/arm/boot/dts/tegra114-pluto.dts | 21 -
> arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
> arch/arm/boot/dts/tegra114.dtsi | 153 -----
> arch/arm/boot/dts/tegra114.dtsip | 153 +++++
> arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
> arch/arm/boot/dts/tegra20-colibri-512.dtsip | 491 ++++++++++++++++
> arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
> arch/arm/boot/dts/tegra20-harmony.dtsp | 660 ++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
> arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
> arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
> arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
> arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
> arch/arm/boot/dts/tegra20-paz00.dtsp | 505 +++++++++++++++++
> arch/arm/boot/dts/tegra20-plutux.dts | 56 --
> arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-seaboard.dts | 812 ---------------------------
> arch/arm/boot/dts/tegra20-seaboard.dtsp | 812 +++++++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
> arch/arm/boot/dts/tegra20-tamonten.dtsip | 489 ++++++++++++++++
> arch/arm/boot/dts/tegra20-tec.dts | 56 --
> arch/arm/boot/dts/tegra20-tec.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
> arch/arm/boot/dts/tegra20-trimslice.dtsp | 367 ++++++++++++
> arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
> arch/arm/boot/dts/tegra20-ventana.dtsp | 611 ++++++++++++++++++++
> arch/arm/boot/dts/tegra20-whistler.dts | 563 -------------------
> arch/arm/boot/dts/tegra20-whistler.dtsp | 563 +++++++++++++++++++
> arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
> arch/arm/boot/dts/tegra20.dtsip | 556 ++++++++++++++++++
> arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
> arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
> arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
> arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
> arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
> arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 -----------------
> arch/arm/boot/dts/tegra30-cardhu.dtsip | 500 +++++++++++++++++
> arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
> arch/arm/boot/dts/tegra30.dtsip | 579 +++++++++++++++++++
> 42 files changed, 7157 insertions(+), 7157 deletions(-)
> delete mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
> create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
> create mode 100644 arch/arm/boot/dts/tegra114-pluto.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra114.dtsi
> create mode 100644 arch/arm/boot/dts/tegra114.dtsip
> delete mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi
> create mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsip
> delete mode 100644 arch/arm/boot/dts/tegra20-harmony.dts
> create mode 100644 arch/arm/boot/dts/tegra20-harmony.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts
> create mode 100644 arch/arm/boot/dts/tegra20-iris-512.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts
> create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-paz00.dts
> create mode 100644 arch/arm/boot/dts/tegra20-paz00.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-plutux.dts
> create mode 100644 arch/arm/boot/dts/tegra20-plutux.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-seaboard.dts
> create mode 100644 arch/arm/boot/dts/tegra20-seaboard.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi
> create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsip
> delete mode 100644 arch/arm/boot/dts/tegra20-tec.dts
> create mode 100644 arch/arm/boot/dts/tegra20-tec.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-trimslice.dts
> create mode 100644 arch/arm/boot/dts/tegra20-trimslice.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-ventana.dts
> create mode 100644 arch/arm/boot/dts/tegra20-ventana.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20-whistler.dts
> create mode 100644 arch/arm/boot/dts/tegra20-whistler.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra20.dtsi
> create mode 100644 arch/arm/boot/dts/tegra20.dtsip
> delete mode 100644 arch/arm/boot/dts/tegra30-beaver.dts
> create mode 100644 arch/arm/boot/dts/tegra30-beaver.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dts
> create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dts
> create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
> delete mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsi
> create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsip
> delete mode 100644 arch/arm/boot/dts/tegra30.dtsi
> create mode 100644 arch/arm/boot/dts/tegra30.dtsip
Just a reminder to use -M for git format-patch. Why -M for format-patch
is not the default I wonder.
Rob
>
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
> deleted file mode 100644
> index a30aca6..0000000
> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra114.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra114 Dalmore evaluation board";
> - compatible = "nvidia,dalmore", "nvidia,tegra114";
> -
> - memory {
> - reg = <0x80000000 0x40000000>;
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - clock-frequency = <408000000>;
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dtsp b/arch/arm/boot/dts/tegra114-dalmore.dtsp
> new file mode 100644
> index 0000000..51f67cd
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra114-dalmore.dtsp
> @@ -0,0 +1,21 @@
> +/dts-v1/;
> +
> +#include "tegra114.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra114 Dalmore evaluation board";
> + compatible = "nvidia,dalmore", "nvidia,tegra114";
> +
> + memory {
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + clock-frequency = <408000000>;
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
> deleted file mode 100644
> index 9bea8f5..0000000
> --- a/arch/arm/boot/dts/tegra114-pluto.dts
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra114.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra114 Pluto evaluation board";
> - compatible = "nvidia,pluto", "nvidia,tegra114";
> -
> - memory {
> - reg = <0x80000000 0x40000000>;
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - clock-frequency = <408000000>;
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra114-pluto.dtsp b/arch/arm/boot/dts/tegra114-pluto.dtsp
> new file mode 100644
> index 0000000..40a88d1
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra114-pluto.dtsp
> @@ -0,0 +1,21 @@
> +/dts-v1/;
> +
> +#include "tegra114.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra114 Pluto evaluation board";
> + compatible = "nvidia,pluto", "nvidia,tegra114";
> +
> + memory {
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + clock-frequency = <408000000>;
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> deleted file mode 100644
> index 1dfaf28..0000000
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ /dev/null
> @@ -1,153 +0,0 @@
> -/include/ "skeleton.dtsi"
> -
> -/ {
> - compatible = "nvidia,tegra114";
> - interrupt-parent = <&gic>;
> -
> - gic: interrupt-controller {
> - compatible = "arm,cortex-a15-gic";
> - #interrupt-cells = <3>;
> - interrupt-controller;
> - reg = <0x50041000 0x1000>,
> - <0x50042000 0x1000>,
> - <0x50044000 0x2000>,
> - <0x50046000 0x2000>;
> - interrupts = <1 9 0xf04>;
> - };
> -
> - timer@60005000 {
> - compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> - reg = <0x60005000 0x400>;
> - interrupts = <0 0 0x04
> - 0 1 0x04
> - 0 41 0x04
> - 0 42 0x04
> - 0 121 0x04
> - 0 122 0x04>;
> - };
> -
> - tegra_car: clock {
> - compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
> - reg = <0x60006000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - ahb: ahb {
> - compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
> - reg = <0x6000c004 0x14c>;
> - };
> -
> - gpio: gpio {
> - compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
> - reg = <0x6000d000 0x1000>;
> - interrupts = <0 32 0x04
> - 0 33 0x04
> - 0 34 0x04
> - 0 35 0x04
> - 0 55 0x04
> - 0 87 0x04
> - 0 89 0x04
> - 0 125 0x04>;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - pinmux: pinmux {
> - compatible = "nvidia,tegra114-pinmux";
> - reg = <0x70000868 0x148 /* Pad control registers */
> - 0x70003000 0x40c>; /* Mux registers */
> - };
> -
> - serial@70006000 {
> - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> - reg = <0x70006000 0x40>;
> - reg-shift = <2>;
> - interrupts = <0 36 0x04>;
> - status = "disabled";
> - };
> -
> - serial@70006040 {
> - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> - reg = <0x70006040 0x40>;
> - reg-shift = <2>;
> - interrupts = <0 37 0x04>;
> - status = "disabled";
> - };
> -
> - serial@70006200 {
> - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> - reg = <0x70006200 0x100>;
> - reg-shift = <2>;
> - interrupts = <0 46 0x04>;
> - status = "disabled";
> - };
> -
> - serial@70006300 {
> - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> - reg = <0x70006300 0x100>;
> - reg-shift = <2>;
> - interrupts = <0 90 0x04>;
> - status = "disabled";
> - };
> -
> - rtc {
> - compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
> - reg = <0x7000e000 0x100>;
> - interrupts = <0 2 0x04>;
> - };
> -
> - pmc {
> - compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
> - reg = <0x7000e400 0x400>;
> - };
> -
> - iommu {
> - compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
> - reg = <0x7000f010 0x02c
> - 0x7000f1f0 0x010
> - 0x7000f228 0x074>;
> - nvidia,#asids = <4>;
> - dma-window = <0 0x40000000>;
> - nvidia,swgroups = <0x18659fe>;
> - nvidia,ahb = <&ahb>;
> - };
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - cpu@0 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a15";
> - reg = <0>;
> - };
> -
> - cpu@1 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a15";
> - reg = <1>;
> - };
> -
> - cpu@2 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a15";
> - reg = <2>;
> - };
> -
> - cpu@3 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a15";
> - reg = <3>;
> - };
> - };
> -
> - timer {
> - compatible = "arm,armv7-timer";
> - interrupts = <1 13 0xf08>,
> - <1 14 0xf08>,
> - <1 11 0xf08>,
> - <1 10 0xf08>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip
> new file mode 100644
> index 0000000..d2150f0
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra114.dtsip
> @@ -0,0 +1,153 @@
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "nvidia,tegra114";
> + interrupt-parent = <&gic>;
> +
> + gic: interrupt-controller {
> + compatible = "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x50041000 0x1000>,
> + <0x50042000 0x1000>,
> + <0x50044000 0x2000>,
> + <0x50046000 0x2000>;
> + interrupts = <1 9 0xf04>;
> + };
> +
> + timer@60005000 {
> + compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> + reg = <0x60005000 0x400>;
> + interrupts = <0 0 0x04
> + 0 1 0x04
> + 0 41 0x04
> + 0 42 0x04
> + 0 121 0x04
> + 0 122 0x04>;
> + };
> +
> + tegra_car: clock {
> + compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
> + reg = <0x60006000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + ahb: ahb {
> + compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
> + reg = <0x6000c004 0x14c>;
> + };
> +
> + gpio: gpio {
> + compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
> + reg = <0x6000d000 0x1000>;
> + interrupts = <0 32 0x04
> + 0 33 0x04
> + 0 34 0x04
> + 0 35 0x04
> + 0 55 0x04
> + 0 87 0x04
> + 0 89 0x04
> + 0 125 0x04>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + };
> +
> + pinmux: pinmux {
> + compatible = "nvidia,tegra114-pinmux";
> + reg = <0x70000868 0x148 /* Pad control registers */
> + 0x70003000 0x40c>; /* Mux registers */
> + };
> +
> + serial@70006000 {
> + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> + reg = <0x70006000 0x40>;
> + reg-shift = <2>;
> + interrupts = <0 36 0x04>;
> + status = "disabled";
> + };
> +
> + serial@70006040 {
> + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> + reg = <0x70006040 0x40>;
> + reg-shift = <2>;
> + interrupts = <0 37 0x04>;
> + status = "disabled";
> + };
> +
> + serial@70006200 {
> + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> + reg = <0x70006200 0x100>;
> + reg-shift = <2>;
> + interrupts = <0 46 0x04>;
> + status = "disabled";
> + };
> +
> + serial@70006300 {
> + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> + reg = <0x70006300 0x100>;
> + reg-shift = <2>;
> + interrupts = <0 90 0x04>;
> + status = "disabled";
> + };
> +
> + rtc {
> + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
> + reg = <0x7000e000 0x100>;
> + interrupts = <0 2 0x04>;
> + };
> +
> + pmc {
> + compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
> + reg = <0x7000e400 0x400>;
> + };
> +
> + iommu {
> + compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
> + reg = <0x7000f010 0x02c
> + 0x7000f1f0 0x010
> + 0x7000f228 0x074>;
> + nvidia,#asids = <4>;
> + dma-window = <0 0x40000000>;
> + nvidia,swgroups = <0x18659fe>;
> + nvidia,ahb = <&ahb>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <3>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <1 13 0xf08>,
> + <1 14 0xf08>,
> + <1 11 0xf08>,
> + <1 10 0xf08>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> deleted file mode 100644
> index 4441620..0000000
> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> +++ /dev/null
> @@ -1,491 +0,0 @@
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "Toradex Colibri T20 512MB";
> - compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x20000000>;
> - };
> -
> - host1x {
> - hdmi {
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&i2c_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - audio_refclk {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - crt {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - displaya {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3",
> - "ld4", "ld5", "ld6", "ld7", "ld8",
> - "ld9", "ld10", "ld11", "ld12", "ld13",
> - "ld14", "ld15", "ld16", "ld17",
> - "lhs", "lpw0", "lpw2", "lsc0",
> - "lsc1", "lsck", "lsda", "lspi", "lvs";
> - nvidia,function = "displaya";
> - nvidia,tristate = <1>;
> - };
> - gpio_dte {
> - nvidia,pins = "dte";
> - nvidia,function = "rsvd1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - gpio_gmi {
> - nvidia,pins = "ata", "atc", "atd", "ate",
> - "dap1", "dap2", "dap4", "gpu", "irrx",
> - "irtx", "spia", "spib", "spic";
> - nvidia,function = "gmi";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - gpio_pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - gpio_uac {
> - nvidia,pins = "uac";
> - nvidia,function = "rsvd2";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - hdint {
> - nvidia,pins = "hdint";
> - nvidia,function = "hdmi";
> - nvidia,tristate = <1>;
> - };
> - i2c1 {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - i2c3 {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - i2cddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - irda {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - nand {
> - nvidia,pins = "kbca", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "nand";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - owc {
> - nvidia,pins = "owc";
> - nvidia,function = "owr";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - nvidia,tristate = <0>;
> - };
> - pwm {
> - nvidia,pins = "sdb", "sdc", "sdd";
> - nvidia,function = "pwm";
> - nvidia,tristate = <1>;
> - };
> - sdio4 {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - spi1 {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - spi4 {
> - nvidia,pins = "slxa", "slxc", "slxd", "slxk";
> - nvidia,function = "spi4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - uarta {
> - nvidia,pins = "sdio1";
> - nvidia,function = "uarta";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - uartd {
> - nvidia,pins = "gmc";
> - nvidia,function = "uartd";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - ulpi {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - ulpi_refclk {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - usb_gpio {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - vi {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd";
> - nvidia,function = "vi";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - vi_sc {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - };
> - };
> -
> - i2c@7000c000 {
> - clock-frequency = <400000>;
> - };
> -
> - i2c_ddc: i2c@7000c400 {
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c500 {
> - clock-frequency = <400000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&vdd_5v0_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - sys_reg: regulator@0 {
> - reg = <0>;
> - regulator-compatible = "sys";
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - regulator@1 {
> - reg = <1>;
> - regulator-compatible = "sm0";
> - regulator-name = "vdd_sm0,vdd_core";
> - regulator-min-microvolt = <1275000>;
> - regulator-max-microvolt = <1275000>;
> - regulator-always-on;
> - };
> -
> - regulator@2 {
> - reg = <2>;
> - regulator-compatible = "sm1";
> - regulator-name = "vdd_sm1,vdd_cpu";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: regulator@3 {
> - reg = <3>;
> - regulator-compatible = "sm2";
> - regulator-name = "vdd_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - /* LDO0 is not connected to anything */
> -
> - regulator@5 {
> - reg = <5>;
> - regulator-compatible = "ldo1";
> - regulator-name = "vdd_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - regulator@6 {
> - reg = <6>;
> - regulator-compatible = "ldo2";
> - regulator-name = "vdd_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - /* LDO3 is not connected to anything */
> -
> - regulator@8 {
> - reg = <8>;
> - regulator-compatible = "ldo4";
> - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5_reg: regulator@9 {
> - reg = <9>;
> - regulator-compatible = "ldo5";
> - regulator-name = "vdd_ldo5,vdd_fuse";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - regulator@10 {
> - reg = <10>;
> - regulator-compatible = "ldo6";
> - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - hdmi_vdd_reg: regulator@11 {
> - reg = <11>;
> - regulator-compatible = "ldo7";
> - regulator-name = "vdd_ldo7,avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: regulator@12 {
> - reg = <12>;
> - regulator-compatible = "ldo8";
> - regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - regulator@13 {
> - reg = <13>;
> - regulator-compatible = "ldo9";
> - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - regulator@14 {
> - reg = <14>;
> - regulator-compatible = "ldo_rtc";
> - regulator-name = "vdd_rtc_out,vdd_cell";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - temperature-sensor@4c {
> - compatible = "national,lm95245";
> - reg = <0x4c>;
> - };
> - };
> -
> - memory-controller@7000f400 {
> - emc-table@83250 {
> - reg = <83250>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <83250>;
> - nvidia,emc-registers = <0x00000005 0x00000011
> - 0x00000004 0x00000002 0x00000004 0x00000004
> - 0x00000001 0x0000000a 0x00000002 0x00000002
> - 0x00000001 0x00000001 0x00000003 0x00000004
> - 0x00000003 0x00000009 0x0000000c 0x0000025f
> - 0x00000000 0x00000003 0x00000003 0x00000002
> - 0x00000002 0x00000001 0x00000008 0x000000c8
> - 0x00000003 0x00000005 0x00000003 0x0000000c
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0x00520006
> - 0x00000010 0x00000008 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> - emc-table@133200 {
> - reg = <133200>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <133200>;
> - nvidia,emc-registers = <0x00000008 0x00000019
> - 0x00000006 0x00000002 0x00000004 0x00000004
> - 0x00000001 0x0000000a 0x00000002 0x00000002
> - 0x00000002 0x00000001 0x00000003 0x00000004
> - 0x00000003 0x00000009 0x0000000c 0x0000039f
> - 0x00000000 0x00000003 0x00000003 0x00000002
> - 0x00000002 0x00000001 0x00000008 0x000000c8
> - 0x00000003 0x00000007 0x00000003 0x0000000c
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0x00510006
> - 0x00000010 0x00000008 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> - emc-table@166500 {
> - reg = <166500>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <166500>;
> - nvidia,emc-registers = <0x0000000a 0x00000021
> - 0x00000008 0x00000003 0x00000004 0x00000004
> - 0x00000002 0x0000000a 0x00000003 0x00000003
> - 0x00000002 0x00000001 0x00000003 0x00000004
> - 0x00000003 0x00000009 0x0000000c 0x000004df
> - 0x00000000 0x00000003 0x00000003 0x00000003
> - 0x00000003 0x00000001 0x00000009 0x000000c8
> - 0x00000003 0x00000009 0x00000004 0x0000000c
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0x004f0006
> - 0x00000010 0x00000008 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> - emc-table@333000 {
> - reg = <333000>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <333000>;
> - nvidia,emc-registers = <0x00000014 0x00000041
> - 0x0000000f 0x00000005 0x00000004 0x00000005
> - 0x00000003 0x0000000a 0x00000005 0x00000005
> - 0x00000004 0x00000001 0x00000003 0x00000004
> - 0x00000003 0x00000009 0x0000000c 0x000009ff
> - 0x00000000 0x00000003 0x00000003 0x00000005
> - 0x00000005 0x00000001 0x0000000e 0x000000c8
> - 0x00000003 0x00000011 0x00000006 0x0000000c
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0x00380006
> - 0x00000010 0x00000008 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> - };
> -
> - ac97: ac97 {
> - status = "okay";
> - nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> - nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - sdhci@c8000600 {
> - cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
> - "nvidia,tegra-audio-wm9712";
> - nvidia,model = "Colibri T20 AC97 Audio";
> -
> - nvidia,audio-routing =
> - "Headphone", "HPOUTL",
> - "Headphone", "HPOUTR",
> - "LineIn", "LINEINL",
> - "LineIn", "LINEINR",
> - "Mic", "MIC1";
> -
> - nvidia,ac97-controller = <&ac97>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v0_reg: regulator@100 {
> - compatible = "regulator-fixed";
> - reg = <100>;
> - regulator-name = "vdd_5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - regulator@101 {
> - compatible = "regulator-fixed";
> - reg = <101>;
> - regulator-name = "internal_usb";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - regulator-boot-on;
> - regulator-always-on;
> - gpio = <&gpio 217 0>;
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsip b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
> new file mode 100644
> index 0000000..bf8865b
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsip
> @@ -0,0 +1,491 @@
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "Toradex Colibri T20 512MB";
> + compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + host1x {
> + hdmi {
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&i2c_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + audio_refclk {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + crt {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + displaya {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3",
> + "ld4", "ld5", "ld6", "ld7", "ld8",
> + "ld9", "ld10", "ld11", "ld12", "ld13",
> + "ld14", "ld15", "ld16", "ld17",
> + "lhs", "lpw0", "lpw2", "lsc0",
> + "lsc1", "lsck", "lsda", "lspi", "lvs";
> + nvidia,function = "displaya";
> + nvidia,tristate = <1>;
> + };
> + gpio_dte {
> + nvidia,pins = "dte";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + gpio_gmi {
> + nvidia,pins = "ata", "atc", "atd", "ate",
> + "dap1", "dap2", "dap4", "gpu", "irrx",
> + "irtx", "spia", "spib", "spic";
> + nvidia,function = "gmi";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + gpio_pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + gpio_uac {
> + nvidia,pins = "uac";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + hdint {
> + nvidia,pins = "hdint";
> + nvidia,function = "hdmi";
> + nvidia,tristate = <1>;
> + };
> + i2c1 {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + i2c3 {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + i2cddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + irda {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + nand {
> + nvidia,pins = "kbca", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "nand";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + owc {
> + nvidia,pins = "owc";
> + nvidia,function = "owr";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + nvidia,tristate = <0>;
> + };
> + pwm {
> + nvidia,pins = "sdb", "sdc", "sdd";
> + nvidia,function = "pwm";
> + nvidia,tristate = <1>;
> + };
> + sdio4 {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + spi1 {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + spi4 {
> + nvidia,pins = "slxa", "slxc", "slxd", "slxk";
> + nvidia,function = "spi4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + uarta {
> + nvidia,pins = "sdio1";
> + nvidia,function = "uarta";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + uartd {
> + nvidia,pins = "gmc";
> + nvidia,function = "uartd";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + ulpi {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + ulpi_refclk {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + usb_gpio {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + vi {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd";
> + nvidia,function = "vi";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + vi_sc {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + };
> + };
> +
> + i2c@7000c000 {
> + clock-frequency = <400000>;
> + };
> +
> + i2c_ddc: i2c@7000c400 {
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c500 {
> + clock-frequency = <400000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&vdd_5v0_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sys_reg: regulator@0 {
> + reg = <0>;
> + regulator-compatible = "sys";
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + regulator@1 {
> + reg = <1>;
> + regulator-compatible = "sm0";
> + regulator-name = "vdd_sm0,vdd_core";
> + regulator-min-microvolt = <1275000>;
> + regulator-max-microvolt = <1275000>;
> + regulator-always-on;
> + };
> +
> + regulator@2 {
> + reg = <2>;
> + regulator-compatible = "sm1";
> + regulator-name = "vdd_sm1,vdd_cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: regulator@3 {
> + reg = <3>;
> + regulator-compatible = "sm2";
> + regulator-name = "vdd_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + /* LDO0 is not connected to anything */
> +
> + regulator@5 {
> + reg = <5>;
> + regulator-compatible = "ldo1";
> + regulator-name = "vdd_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + regulator@6 {
> + reg = <6>;
> + regulator-compatible = "ldo2";
> + regulator-name = "vdd_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + /* LDO3 is not connected to anything */
> +
> + regulator@8 {
> + reg = <8>;
> + regulator-compatible = "ldo4";
> + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: regulator@9 {
> + reg = <9>;
> + regulator-compatible = "ldo5";
> + regulator-name = "vdd_ldo5,vdd_fuse";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + regulator@10 {
> + reg = <10>;
> + regulator-compatible = "ldo6";
> + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + hdmi_vdd_reg: regulator@11 {
> + reg = <11>;
> + regulator-compatible = "ldo7";
> + regulator-name = "vdd_ldo7,avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: regulator@12 {
> + reg = <12>;
> + regulator-compatible = "ldo8";
> + regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + regulator@13 {
> + reg = <13>;
> + regulator-compatible = "ldo9";
> + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + regulator@14 {
> + reg = <14>;
> + regulator-compatible = "ldo_rtc";
> + regulator-name = "vdd_rtc_out,vdd_cell";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + temperature-sensor@4c {
> + compatible = "national,lm95245";
> + reg = <0x4c>;
> + };
> + };
> +
> + memory-controller@7000f400 {
> + emc-table@83250 {
> + reg = <83250>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <83250>;
> + nvidia,emc-registers = <0x00000005 0x00000011
> + 0x00000004 0x00000002 0x00000004 0x00000004
> + 0x00000001 0x0000000a 0x00000002 0x00000002
> + 0x00000001 0x00000001 0x00000003 0x00000004
> + 0x00000003 0x00000009 0x0000000c 0x0000025f
> + 0x00000000 0x00000003 0x00000003 0x00000002
> + 0x00000002 0x00000001 0x00000008 0x000000c8
> + 0x00000003 0x00000005 0x00000003 0x0000000c
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0x00520006
> + 0x00000010 0x00000008 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> + emc-table@133200 {
> + reg = <133200>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <133200>;
> + nvidia,emc-registers = <0x00000008 0x00000019
> + 0x00000006 0x00000002 0x00000004 0x00000004
> + 0x00000001 0x0000000a 0x00000002 0x00000002
> + 0x00000002 0x00000001 0x00000003 0x00000004
> + 0x00000003 0x00000009 0x0000000c 0x0000039f
> + 0x00000000 0x00000003 0x00000003 0x00000002
> + 0x00000002 0x00000001 0x00000008 0x000000c8
> + 0x00000003 0x00000007 0x00000003 0x0000000c
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0x00510006
> + 0x00000010 0x00000008 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> + emc-table@166500 {
> + reg = <166500>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <166500>;
> + nvidia,emc-registers = <0x0000000a 0x00000021
> + 0x00000008 0x00000003 0x00000004 0x00000004
> + 0x00000002 0x0000000a 0x00000003 0x00000003
> + 0x00000002 0x00000001 0x00000003 0x00000004
> + 0x00000003 0x00000009 0x0000000c 0x000004df
> + 0x00000000 0x00000003 0x00000003 0x00000003
> + 0x00000003 0x00000001 0x00000009 0x000000c8
> + 0x00000003 0x00000009 0x00000004 0x0000000c
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0x004f0006
> + 0x00000010 0x00000008 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> + emc-table@333000 {
> + reg = <333000>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <333000>;
> + nvidia,emc-registers = <0x00000014 0x00000041
> + 0x0000000f 0x00000005 0x00000004 0x00000005
> + 0x00000003 0x0000000a 0x00000005 0x00000005
> + 0x00000004 0x00000001 0x00000003 0x00000004
> + 0x00000003 0x00000009 0x0000000c 0x000009ff
> + 0x00000000 0x00000003 0x00000003 0x00000005
> + 0x00000005 0x00000001 0x0000000e 0x000000c8
> + 0x00000003 0x00000011 0x00000006 0x0000000c
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0x00380006
> + 0x00000010 0x00000008 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> + };
> +
> + ac97: ac97 {
> + status = "okay";
> + nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> + nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + sdhci@c8000600 {
> + cd-gpios = <&gpio 23 0>; /* gpio PC7 */
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
> + "nvidia,tegra-audio-wm9712";
> + nvidia,model = "Colibri T20 AC97 Audio";
> +
> + nvidia,audio-routing =
> + "Headphone", "HPOUTL",
> + "Headphone", "HPOUTR",
> + "LineIn", "LINEINL",
> + "LineIn", "LINEINR",
> + "Mic", "MIC1";
> +
> + nvidia,ac97-controller = <&ac97>;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v0_reg: regulator@100 {
> + compatible = "regulator-fixed";
> + reg = <100>;
> + regulator-name = "vdd_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + regulator@101 {
> + compatible = "regulator-fixed";
> + reg = <101>;
> + regulator-name = "internal_usb";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + gpio = <&gpio 217 0>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
> deleted file mode 100644
> index 61d027f..0000000
> --- a/arch/arm/boot/dts/tegra20-harmony.dts
> +++ /dev/null
> @@ -1,660 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra20 Harmony evaluation board";
> - compatible = "nvidia,harmony", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x40000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata";
> - nvidia,function = "ide";
> - };
> - atb {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - };
> - atc {
> - nvidia,pins = "atc";
> - nvidia,function = "nand";
> - };
> - atd {
> - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
> - "spia", "spib", "spic";
> - nvidia,function = "gmi";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - dta {
> - nvidia,pins = "dta", "dtd";
> - nvidia,function = "sdio2";
> - };
> - dtb {
> - nvidia,pins = "dtb", "dtc", "dte";
> - nvidia,function = "rsvd1";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gmc {
> - nvidia,pins = "gmc";
> - nvidia,function = "uartd";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint", "pta";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uarta";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> - "ld3", "ld4", "ld5", "ld6", "ld7",
> - "ld8", "ld9", "ld10", "ld11", "ld12",
> - "ld13", "ld14", "ld15", "ld16", "ld17",
> - "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> - "lhs", "lm0", "lm1", "lpp", "lpw0",
> - "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> - "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> - "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "spdi", "spdo", "uac";
> - nvidia,function = "rsvd2";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd";
> - nvidia,function = "pwm";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxc {
> - nvidia,pins = "slxc", "slxd";
> - nvidia,function = "spdif";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> - "cdev1", "cdev2", "dap1", "dtb", "gma",
> - "gmb", "gmc", "gmd", "gme", "gpu7",
> - "gpv", "i2cp", "pta", "rm", "slxa",
> - "slxk", "spia", "spib", "uac";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_csus {
> - nvidia,pins = "csus", "spid", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp", "dap2", "dap3", "dap4",
> - "dtc", "dte", "dtf", "gpu", "sdio1",
> - "slxc", "slxd", "spdi", "spdo", "spig",
> - "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_ddc {
> - nvidia,pins = "ddc", "dta", "dtd", "kbca",
> - "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> - "sdc";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> - "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> - "lvp0", "owc", "sdb";
> - nvidia,tristate = <1>;
> - };
> - conf_irrx {
> - nvidia,pins = "irrx", "irtx", "sdd", "spic",
> - "spie", "spih", "uaa", "uab", "uad",
> - "uca", "ucb";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lm0", "lpp",
> - "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> - "lvs", "pmc";
> - nvidia,tristate = <0>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> - };
> - };
> -
> - hdmi_ddc: i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <400000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&vdd_5v0_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - sys_reg: sys {
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - sm0 {
> - regulator-name = "vdd_sm0,vdd_core";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - sm1 {
> - regulator-name = "vdd_sm1,vdd_cpu";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: sm2 {
> - regulator-name = "vdd_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - ldo0 {
> - regulator-name = "vdd_ldo0,vddio_pex_clk";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo1 {
> - regulator-name = "vdd_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "vdd_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo3 {
> - regulator-name = "vdd_ldo3,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "vdd_ldo5,vcore_mmc";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo6 {
> - regulator-name = "vdd_ldo6,avdd_vdac";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - hdmi_vdd_reg: ldo7 {
> - regulator-name = "vdd_ldo7,avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: ldo8 {
> - regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo9 {
> - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo_rtc {
> - regulator-name = "vdd_rtc_out,vdd_cell";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - temperature-sensor@4c {
> - compatible = "adi,adt7461";
> - reg = <0x4c>;
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - usb-phy@c5004400 {
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - sdhci@c8000200 {
> - status = "okay";
> - cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> - wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> - power-gpios = <&gpio 155 0>; /* gpio PT3 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - cd-gpios = <&gpio 58 0>; /* gpio PH2 */
> - wp-gpios = <&gpio 59 0>; /* gpio PH3 */
> - power-gpios = <&gpio 70 0>; /* gpio PI6 */
> - bus-width = <8>;
> - };
> -
> - kbc {
> - status = "okay";
> - nvidia,debounce-delay-ms = <2>;
> - nvidia,repeat-delay-ms = <160>;
> - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
> - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
> - linux,keymap = <0x00020011 /* KEY_W */
> - 0x0003001F /* KEY_S */
> - 0x0004001E /* KEY_A */
> - 0x0005002C /* KEY_Z */
> - 0x000701D0 /* KEY_FN */
> - 0x0107008B /* KEY_MENU */
> - 0x02060038 /* KEY_LEFTALT */
> - 0x02070064 /* KEY_RIGHTALT */
> - 0x03000006 /* KEY_5 */
> - 0x03010005 /* KEY_4 */
> - 0x03020013 /* KEY_R */
> - 0x03030012 /* KEY_E */
> - 0x03040021 /* KEY_F */
> - 0x03050020 /* KEY_D */
> - 0x0306002D /* KEY_X */
> - 0x04000008 /* KEY_7 */
> - 0x04010007 /* KEY_6 */
> - 0x04020014 /* KEY_T */
> - 0x04030023 /* KEY_H */
> - 0x04040022 /* KEY_G */
> - 0x0405002F /* KEY_V */
> - 0x0406002E /* KEY_C */
> - 0x04070039 /* KEY_SPACE */
> - 0x0500000A /* KEY_9 */
> - 0x05010009 /* KEY_8 */
> - 0x05020016 /* KEY_U */
> - 0x05030015 /* KEY_Y */
> - 0x05040024 /* KEY_J */
> - 0x05050031 /* KEY_N */
> - 0x05060030 /* KEY_B */
> - 0x0507002B /* KEY_BACKSLASH */
> - 0x0600000C /* KEY_MINUS */
> - 0x0601000B /* KEY_0 */
> - 0x06020018 /* KEY_O */
> - 0x06030017 /* KEY_I */
> - 0x06040026 /* KEY_L */
> - 0x06050025 /* KEY_K */
> - 0x06060033 /* KEY_COMMA */
> - 0x06070032 /* KEY_M */
> - 0x0701000D /* KEY_EQUAL */
> - 0x0702001B /* KEY_RIGHTBRACE */
> - 0x0703001C /* KEY_ENTER */
> - 0x0707008B /* KEY_MENU */
> - 0x0804002A /* KEY_LEFTSHIFT */
> - 0x08050036 /* KEY_RIGHTSHIFT */
> - 0x0905001D /* KEY_LEFTCTRL */
> - 0x09070061 /* KEY_RIGHTCTRL */
> - 0x0B00001A /* KEY_LEFTBRACE */
> - 0x0B010019 /* KEY_P */
> - 0x0B020028 /* KEY_APOSTROPHE */
> - 0x0B030027 /* KEY_SEMICOLON */
> - 0x0B040035 /* KEY_SLASH */
> - 0x0B050034 /* KEY_DOT */
> - 0x0C000044 /* KEY_F10 */
> - 0x0C010043 /* KEY_F9 */
> - 0x0C02000E /* KEY_BACKSPACE */
> - 0x0C030004 /* KEY_3 */
> - 0x0C040003 /* KEY_2 */
> - 0x0C050067 /* KEY_UP */
> - 0x0C0600D2 /* KEY_PRINT */
> - 0x0C070077 /* KEY_PAUSE */
> - 0x0D00006E /* KEY_INSERT */
> - 0x0D01006F /* KEY_DELETE */
> - 0x0D030068 /* KEY_PAGEUP */
> - 0x0D04006D /* KEY_PAGEDOWN */
> - 0x0D05006A /* KEY_RIGHT */
> - 0x0D06006C /* KEY_DOWN */
> - 0x0D070069 /* KEY_LEFT */
> - 0x0E000057 /* KEY_F11 */
> - 0x0E010058 /* KEY_F12 */
> - 0x0E020042 /* KEY_F8 */
> - 0x0E030010 /* KEY_Q */
> - 0x0E04003E /* KEY_F4 */
> - 0x0E05003D /* KEY_F3 */
> - 0x0E060002 /* KEY_1 */
> - 0x0E070041 /* KEY_F7 */
> - 0x0F000001 /* KEY_ESC */
> - 0x0F010029 /* KEY_GRAVE */
> - 0x0F02003F /* KEY_F5 */
> - 0x0F03000F /* KEY_TAB */
> - 0x0F04003B /* KEY_F1 */
> - 0x0F05003C /* KEY_F2 */
> - 0x0F06003A /* KEY_CAPSLOCK */
> - 0x0F070040 /* KEY_F6 */
> - 0x14000047 /* KEY_KP7 */
> - 0x15000049 /* KEY_KP9 */
> - 0x15010048 /* KEY_KP8 */
> - 0x1502004B /* KEY_KP4 */
> - 0x1504004F /* KEY_KP1 */
> - 0x1601004E /* KEY_KPSLASH */
> - 0x1602004D /* KEY_KP6 */
> - 0x1603004C /* KEY_KP5 */
> - 0x16040051 /* KEY_KP3 */
> - 0x16050050 /* KEY_KP2 */
> - 0x16070052 /* KEY_KP0 */
> - 0x1B010037 /* KEY_KPASTERISK */
> - 0x1B03004A /* KEY_KPMINUS */
> - 0x1B04004E /* KEY_KPPLUS */
> - 0x1B050053 /* KEY_KPDOT */
> - 0x1C050073 /* KEY_VOLUMEUP */
> - 0x1D030066 /* KEY_HOME */
> - 0x1D04006B /* KEY_END */
> - 0x1D0500E1 /* KEY_BRIGHTNESSUP */
> - 0x1D060072 /* KEY_VOLUMEDOWN */
> - 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
> - 0x1E000045 /* KEY_NUMLOCK */
> - 0x1E010046 /* KEY_SCROLLLOCK */
> - 0x1E020071 /* KEY_MUTE */
> - 0x1F0400D6>; /* KEY_QUESTION */
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v0_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "vdd_1v5";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - gpio = <&pmic 0 0>;
> - };
> -
> - regulator@2 {
> - compatible = "regulator-fixed";
> - reg = <2>;
> - regulator-name = "vdd_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - gpio = <&pmic 1 0>;
> - enable-active-high;
> - };
> -
> - regulator@3 {
> - compatible = "regulator-fixed";
> - reg = <3>;
> - regulator-name = "vdd_1v05";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - gpio = <&pmic 2 0>;
> - enable-active-high;
> - /* Hack until board-harmony-pcie.c is removed */
> - status = "disabled";
> - };
> -
> - regulator@4 {
> - compatible = "regulator-fixed";
> - reg = <4>;
> - regulator-name = "vdd_pnl";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - gpio = <&gpio 22 0>; /* gpio PC6 */
> - enable-active-high;
> - };
> -
> - regulator@5 {
> - compatible = "regulator-fixed";
> - reg = <5>;
> - regulator-name = "vdd_bl";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - gpio = <&gpio 176 0>; /* gpio PW0 */
> - enable-active-high;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm8903-harmony",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "NVIDIA Tegra Harmony";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
> - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-harmony.dtsp b/arch/arm/boot/dts/tegra20-harmony.dtsp
> new file mode 100644
> index 0000000..3fe66c1
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-harmony.dtsp
> @@ -0,0 +1,660 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra20 Harmony evaluation board";
> + compatible = "nvidia,harmony", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x40000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata";
> + nvidia,function = "ide";
> + };
> + atb {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + };
> + atc {
> + nvidia,pins = "atc";
> + nvidia,function = "nand";
> + };
> + atd {
> + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
> + "spia", "spib", "spic";
> + nvidia,function = "gmi";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + dta {
> + nvidia,pins = "dta", "dtd";
> + nvidia,function = "sdio2";
> + };
> + dtb {
> + nvidia,pins = "dtb", "dtc", "dte";
> + nvidia,function = "rsvd1";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gmc {
> + nvidia,pins = "gmc";
> + nvidia,function = "uartd";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint", "pta";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uarta";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> + "ld3", "ld4", "ld5", "ld6", "ld7",
> + "ld8", "ld9", "ld10", "ld11", "ld12",
> + "ld13", "ld14", "ld15", "ld16", "ld17",
> + "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> + "lhs", "lm0", "lm1", "lpp", "lpw0",
> + "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> + "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> + "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "spdi", "spdo", "uac";
> + nvidia,function = "rsvd2";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd";
> + nvidia,function = "pwm";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxc {
> + nvidia,pins = "slxc", "slxd";
> + nvidia,function = "spdif";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> + "cdev1", "cdev2", "dap1", "dtb", "gma",
> + "gmb", "gmc", "gmd", "gme", "gpu7",
> + "gpv", "i2cp", "pta", "rm", "slxa",
> + "slxk", "spia", "spib", "uac";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_csus {
> + nvidia,pins = "csus", "spid", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp", "dap2", "dap3", "dap4",
> + "dtc", "dte", "dtf", "gpu", "sdio1",
> + "slxc", "slxd", "spdi", "spdo", "spig",
> + "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_ddc {
> + nvidia,pins = "ddc", "dta", "dtd", "kbca",
> + "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> + "sdc";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> + "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> + "lvp0", "owc", "sdb";
> + nvidia,tristate = <1>;
> + };
> + conf_irrx {
> + nvidia,pins = "irrx", "irtx", "sdd", "spic",
> + "spie", "spih", "uaa", "uab", "uad",
> + "uca", "ucb";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lm0", "lpp",
> + "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> + "lvs", "pmc";
> + nvidia,tristate = <0>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> + };
> + };
> +
> + hdmi_ddc: i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&vdd_5v0_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + sys_reg: sys {
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + sm0 {
> + regulator-name = "vdd_sm0,vdd_core";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + sm1 {
> + regulator-name = "vdd_sm1,vdd_cpu";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: sm2 {
> + regulator-name = "vdd_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + ldo0 {
> + regulator-name = "vdd_ldo0,vddio_pex_clk";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo1 {
> + regulator-name = "vdd_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "vdd_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo3 {
> + regulator-name = "vdd_ldo3,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "vdd_ldo5,vcore_mmc";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo6 {
> + regulator-name = "vdd_ldo6,avdd_vdac";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + hdmi_vdd_reg: ldo7 {
> + regulator-name = "vdd_ldo7,avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: ldo8 {
> + regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo9 {
> + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo_rtc {
> + regulator-name = "vdd_rtc_out,vdd_cell";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + temperature-sensor@4c {
> + compatible = "adi,adt7461";
> + reg = <0x4c>;
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + usb-phy@c5004400 {
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + sdhci@c8000200 {
> + status = "okay";
> + cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> + wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> + power-gpios = <&gpio 155 0>; /* gpio PT3 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + cd-gpios = <&gpio 58 0>; /* gpio PH2 */
> + wp-gpios = <&gpio 59 0>; /* gpio PH3 */
> + power-gpios = <&gpio 70 0>; /* gpio PI6 */
> + bus-width = <8>;
> + };
> +
> + kbc {
> + status = "okay";
> + nvidia,debounce-delay-ms = <2>;
> + nvidia,repeat-delay-ms = <160>;
> + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
> + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
> + linux,keymap = <0x00020011 /* KEY_W */
> + 0x0003001F /* KEY_S */
> + 0x0004001E /* KEY_A */
> + 0x0005002C /* KEY_Z */
> + 0x000701D0 /* KEY_FN */
> + 0x0107008B /* KEY_MENU */
> + 0x02060038 /* KEY_LEFTALT */
> + 0x02070064 /* KEY_RIGHTALT */
> + 0x03000006 /* KEY_5 */
> + 0x03010005 /* KEY_4 */
> + 0x03020013 /* KEY_R */
> + 0x03030012 /* KEY_E */
> + 0x03040021 /* KEY_F */
> + 0x03050020 /* KEY_D */
> + 0x0306002D /* KEY_X */
> + 0x04000008 /* KEY_7 */
> + 0x04010007 /* KEY_6 */
> + 0x04020014 /* KEY_T */
> + 0x04030023 /* KEY_H */
> + 0x04040022 /* KEY_G */
> + 0x0405002F /* KEY_V */
> + 0x0406002E /* KEY_C */
> + 0x04070039 /* KEY_SPACE */
> + 0x0500000A /* KEY_9 */
> + 0x05010009 /* KEY_8 */
> + 0x05020016 /* KEY_U */
> + 0x05030015 /* KEY_Y */
> + 0x05040024 /* KEY_J */
> + 0x05050031 /* KEY_N */
> + 0x05060030 /* KEY_B */
> + 0x0507002B /* KEY_BACKSLASH */
> + 0x0600000C /* KEY_MINUS */
> + 0x0601000B /* KEY_0 */
> + 0x06020018 /* KEY_O */
> + 0x06030017 /* KEY_I */
> + 0x06040026 /* KEY_L */
> + 0x06050025 /* KEY_K */
> + 0x06060033 /* KEY_COMMA */
> + 0x06070032 /* KEY_M */
> + 0x0701000D /* KEY_EQUAL */
> + 0x0702001B /* KEY_RIGHTBRACE */
> + 0x0703001C /* KEY_ENTER */
> + 0x0707008B /* KEY_MENU */
> + 0x0804002A /* KEY_LEFTSHIFT */
> + 0x08050036 /* KEY_RIGHTSHIFT */
> + 0x0905001D /* KEY_LEFTCTRL */
> + 0x09070061 /* KEY_RIGHTCTRL */
> + 0x0B00001A /* KEY_LEFTBRACE */
> + 0x0B010019 /* KEY_P */
> + 0x0B020028 /* KEY_APOSTROPHE */
> + 0x0B030027 /* KEY_SEMICOLON */
> + 0x0B040035 /* KEY_SLASH */
> + 0x0B050034 /* KEY_DOT */
> + 0x0C000044 /* KEY_F10 */
> + 0x0C010043 /* KEY_F9 */
> + 0x0C02000E /* KEY_BACKSPACE */
> + 0x0C030004 /* KEY_3 */
> + 0x0C040003 /* KEY_2 */
> + 0x0C050067 /* KEY_UP */
> + 0x0C0600D2 /* KEY_PRINT */
> + 0x0C070077 /* KEY_PAUSE */
> + 0x0D00006E /* KEY_INSERT */
> + 0x0D01006F /* KEY_DELETE */
> + 0x0D030068 /* KEY_PAGEUP */
> + 0x0D04006D /* KEY_PAGEDOWN */
> + 0x0D05006A /* KEY_RIGHT */
> + 0x0D06006C /* KEY_DOWN */
> + 0x0D070069 /* KEY_LEFT */
> + 0x0E000057 /* KEY_F11 */
> + 0x0E010058 /* KEY_F12 */
> + 0x0E020042 /* KEY_F8 */
> + 0x0E030010 /* KEY_Q */
> + 0x0E04003E /* KEY_F4 */
> + 0x0E05003D /* KEY_F3 */
> + 0x0E060002 /* KEY_1 */
> + 0x0E070041 /* KEY_F7 */
> + 0x0F000001 /* KEY_ESC */
> + 0x0F010029 /* KEY_GRAVE */
> + 0x0F02003F /* KEY_F5 */
> + 0x0F03000F /* KEY_TAB */
> + 0x0F04003B /* KEY_F1 */
> + 0x0F05003C /* KEY_F2 */
> + 0x0F06003A /* KEY_CAPSLOCK */
> + 0x0F070040 /* KEY_F6 */
> + 0x14000047 /* KEY_KP7 */
> + 0x15000049 /* KEY_KP9 */
> + 0x15010048 /* KEY_KP8 */
> + 0x1502004B /* KEY_KP4 */
> + 0x1504004F /* KEY_KP1 */
> + 0x1601004E /* KEY_KPSLASH */
> + 0x1602004D /* KEY_KP6 */
> + 0x1603004C /* KEY_KP5 */
> + 0x16040051 /* KEY_KP3 */
> + 0x16050050 /* KEY_KP2 */
> + 0x16070052 /* KEY_KP0 */
> + 0x1B010037 /* KEY_KPASTERISK */
> + 0x1B03004A /* KEY_KPMINUS */
> + 0x1B04004E /* KEY_KPPLUS */
> + 0x1B050053 /* KEY_KPDOT */
> + 0x1C050073 /* KEY_VOLUMEUP */
> + 0x1D030066 /* KEY_HOME */
> + 0x1D04006B /* KEY_END */
> + 0x1D0500E1 /* KEY_BRIGHTNESSUP */
> + 0x1D060072 /* KEY_VOLUMEDOWN */
> + 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
> + 0x1E000045 /* KEY_NUMLOCK */
> + 0x1E010046 /* KEY_SCROLLLOCK */
> + 0x1E020071 /* KEY_MUTE */
> + 0x1F0400D6>; /* KEY_QUESTION */
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v0_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "vdd_1v5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&pmic 0 0>;
> + };
> +
> + regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "vdd_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&pmic 1 0>;
> + enable-active-high;
> + };
> +
> + regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "vdd_1v05";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + gpio = <&pmic 2 0>;
> + enable-active-high;
> + /* Hack until board-harmony-pcie.c is removed */
> + status = "disabled";
> + };
> +
> + regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "vdd_pnl";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + gpio = <&gpio 22 0>; /* gpio PC6 */
> + enable-active-high;
> + };
> +
> + regulator@5 {
> + compatible = "regulator-fixed";
> + reg = <5>;
> + regulator-name = "vdd_bl";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + gpio = <&gpio 176 0>; /* gpio PW0 */
> + enable-active-high;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm8903-harmony",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "NVIDIA Tegra Harmony";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
> + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
> deleted file mode 100644
> index 52f1103..0000000
> --- a/arch/arm/boot/dts/tegra20-iris-512.dts
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20-colibri-512.dtsi"
> -
> -/ {
> - model = "Toradex Colibri T20 512MB on Iris";
> - compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
> -
> - host1x {
> - hdmi {
> - status = "okay";
> - };
> - };
> -
> - pinmux {
> - state_default: pinmux {
> - hdint {
> - nvidia,tristate = <0>;
> - };
> -
> - i2cddc {
> - nvidia,tristate = <0>;
> - };
> -
> - sdio4 {
> - nvidia,tristate = <0>;
> - };
> -
> - uarta {
> - nvidia,tristate = <0>;
> - };
> -
> - uartd {
> - nvidia,tristate = <0>;
> - };
> - };
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - dr_mode = "otg";
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - };
> -
> - i2c_ddc: i2c@7000c400 {
> - status = "okay";
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - bus-width = <4>;
> - vmmc-supply = <&vcc_sd_reg>;
> - vqmmc-supply = <&vcc_sd_reg>;
> - };
> -
> - regulators {
> - regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "usb_host_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-boot-on;
> - regulator-always-on;
> - gpio = <&gpio 178 0>;
> - };
> -
> - vcc_sd_reg: regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "vcc_sd";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
> - regulator-always-on;
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dtsp b/arch/arm/boot/dts/tegra20-iris-512.dtsp
> new file mode 100644
> index 0000000..a0ba0b0
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-iris-512.dtsp
> @@ -0,0 +1,89 @@
> +/dts-v1/;
> +
> +#include "tegra20-colibri-512.dtsip"
> +
> +/ {
> + model = "Toradex Colibri T20 512MB on Iris";
> + compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
> +
> + host1x {
> + hdmi {
> + status = "okay";
> + };
> + };
> +
> + pinmux {
> + state_default: pinmux {
> + hdint {
> + nvidia,tristate = <0>;
> + };
> +
> + i2cddc {
> + nvidia,tristate = <0>;
> + };
> +
> + sdio4 {
> + nvidia,tristate = <0>;
> + };
> +
> + uarta {
> + nvidia,tristate = <0>;
> + };
> +
> + uartd {
> + nvidia,tristate = <0>;
> + };
> + };
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + dr_mode = "otg";
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + };
> +
> + i2c_ddc: i2c@7000c400 {
> + status = "okay";
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + bus-width = <4>;
> + vmmc-supply = <&vcc_sd_reg>;
> + vqmmc-supply = <&vcc_sd_reg>;
> + };
> +
> + regulators {
> + regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "usb_host_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + gpio = <&gpio 178 0>;
> + };
> +
> + vcc_sd_reg: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "vcc_sd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
> deleted file mode 100644
> index a2d6d65..0000000
> --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
> +++ /dev/null
> @@ -1,58 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20-tamonten.dtsi"
> -
> -/ {
> - model = "Avionic Design Medcom-Wide board";
> - compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
> -
> - i2c@7000c000 {
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff
> - 0xffffffff
> - 0
> - 0xffffffff
> - 0xffffffff>;
> - };
> - };
> -
> - backlight {
> - compatible = "pwm-backlight";
> - pwms = <&pwm 0 5000000>;
> -
> - brightness-levels = <0 4 8 16 32 64 128 255>;
> - default-brightness-level = <6>;
> - };
> -
> - sound {
> - compatible = "ad,tegra-audio-wm8903-medcom-wide",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "Avionic Design Medcom-Wide";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dtsp b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
> new file mode 100644
> index 0000000..6125604
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dtsp
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +
> +#include "tegra20-tamonten.dtsip"
> +
> +/ {
> + model = "Avionic Design Medcom-Wide board";
> + compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
> +
> + i2c@7000c000 {
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff
> + 0xffffffff
> + 0
> + 0xffffffff
> + 0xffffffff>;
> + };
> + };
> +
> + backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm 0 5000000>;
> +
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + };
> +
> + sound {
> + compatible = "ad,tegra-audio-wm8903-medcom-wide",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "Avionic Design Medcom-Wide";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
> deleted file mode 100644
> index 54d6fce..0000000
> --- a/arch/arm/boot/dts/tegra20-paz00.dts
> +++ /dev/null
> @@ -1,505 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "Toshiba AC100 / Dynabook AZ";
> - compatible = "compal,paz00", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x20000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata", "atc", "atd", "ate",
> - "dap2", "gmb", "gmc", "gmd", "spia",
> - "spib", "spic", "spid", "spie";
> - nvidia,function = "gmi";
> - };
> - atb {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "pllc_out1";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> - nvidia,function = "rsvd1";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gpu {
> - nvidia,pins = "gpu", "sdb", "sdd";
> - nvidia,function = "pwm";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint", "pta";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uarta";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - kbcb {
> - nvidia,pins = "kbcb", "kbcd";
> - nvidia,function = "sdio2";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> - "ld3", "ld4", "ld5", "ld6", "ld7",
> - "ld8", "ld9", "ld10", "ld11", "ld12",
> - "ld13", "ld14", "ld15", "ld16", "ld17",
> - "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> - "lhs", "lm0", "lm1", "lpp", "lpw0",
> - "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> - "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> - "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc";
> - nvidia,function = "owr";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdc {
> - nvidia,pins = "sdc";
> - nvidia,function = "twc";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxc {
> - nvidia,pins = "slxc", "slxd";
> - nvidia,function = "spi4";
> - };
> - spdi {
> - nvidia,pins = "spdi", "spdo";
> - nvidia,function = "rsvd2";
> - };
> - spif {
> - nvidia,pins = "spif", "uac";
> - nvidia,function = "rsvd4";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "spdif";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> - "cdev1", "cdev2", "dap1", "dap2", "dtf",
> - "gma", "gmb", "gmc", "gmd", "gme",
> - "gpu", "gpu7", "gpv", "i2cp", "pta",
> - "rm", "sdio1", "slxk", "spdo", "uac",
> - "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp", "dap3", "dap4", "dtb",
> - "dtc", "dte", "slxa", "slxc", "slxd",
> - "spdi";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_csus {
> - nvidia,pins = "csus", "spia", "spib", "spid",
> - "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_ddc {
> - nvidia,pins = "ddc", "irrx", "irtx", "kbca",
> - "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> - "spic", "spig", "uaa", "uab";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_dta {
> - nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
> - "spie", "spih", "uad", "uca", "ucb";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "ld0", "ld1", "ld2",
> - "ld3", "ld4", "ld5", "ld6", "ld7",
> - "ld8", "ld9", "ld10", "ld11", "ld12",
> - "ld13", "ld14", "ld15", "ld16", "ld17",
> - "ldc", "ldi", "lhs", "lsc0", "lspi",
> - "lvs", "pmc";
> - nvidia,tristate = <0>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_lcsn {
> - nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
> - "lm0", "lm1", "lpp", "lpw0", "lpw1",
> - "lpw2", "lsc1", "lsck", "lsda", "lsdi",
> - "lvp0", "lvp1", "sdb";
> - nvidia,tristate = <1>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - serial@70006200 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - alc5632: alc5632@1e {
> - compatible = "realtek,alc5632";
> - reg = <0x1e>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> - };
> -
> - hdmi_ddc: i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - nvec {
> - compatible = "nvidia,nvec";
> - reg = <0x7000c500 0x100>;
> - interrupts = <0 92 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clock-frequency = <80000>;
> - request-gpios = <&gpio 170 0>; /* gpio PV2 */
> - slave-addr = <138>;
> - clocks = <&tegra_car 67>, <&tegra_car 124>;
> - clock-names = "div-clk", "fast-clk";
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&p5valw_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - sys_reg: sys {
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - sm0 {
> - regulator-name = "+1.2vs_sm0,vdd_core";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - sm1 {
> - regulator-name = "+1.0vs_sm1,vdd_cpu";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: sm2 {
> - regulator-name = "+3.7vs_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - /* LDO0 is not connected to anything */
> -
> - ldo1 {
> - regulator-name = "+1.1vs_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "+1.2vs_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo3 {
> - regulator-name = "+3.3vs_ldo3,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "+2.85vs_ldo5,vcore_mmc";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo6 {
> - /*
> - * Research indicates this should be
> - * 1.8v; other boards that use this
> - * rail for the same purpose need it
> - * set to 1.8v. The schematic signal
> - * name is incorrect; perhaps copied
> - * from an incorrect NVIDIA reference.
> - */
> - regulator-name = "+2.85vs_ldo6,avdd_vdac";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - hdmi_vdd_reg: ldo7 {
> - regulator-name = "+3.3vs_ldo7,avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: ldo8 {
> - regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo9 {
> - regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo_rtc {
> - regulator-name = "+3.3vs_rtc";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - adt7461@4c {
> - compatible = "adi,adt7461";
> - reg = <0x4c>;
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - usb-phy@c5004400 {
> - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> - };
> -
> - sdhci@c8000000 {
> - status = "okay";
> - cd-gpios = <&gpio 173 0>; /* gpio PV5 */
> - wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> - power-gpios = <&gpio 169 0>; /* gpio PV1 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> -
> - power {
> - label = "Power";
> - gpios = <&gpio 79 1>; /* gpio PJ7, active low */
> - linux,code = <116>; /* KEY_POWER */
> - gpio-key,wakeup;
> - };
> - };
> -
> - gpio-leds {
> - compatible = "gpio-leds";
> -
> - wifi {
> - label = "wifi-led";
> - gpios = <&gpio 24 0>; /* gpio PD0 */
> - linux,default-trigger = "rfkill0";
> - };
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - p5valw_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "+5valw";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-alc5632-paz00",
> - "nvidia,tegra-audio-alc5632";
> -
> - nvidia,model = "Compal PAZ00";
> -
> - nvidia,audio-routing =
> - "Int Spk", "SPKOUT",
> - "Int Spk", "SPKOUTN",
> - "Headset Mic", "MICBIAS1",
> - "MIC1", "Headset Mic",
> - "Headset Stereophone", "HPR",
> - "Headset Stereophone", "HPL",
> - "DMICDAT", "Digital Mic";
> -
> - nvidia,audio-codec = <&alc5632>;
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
> new file mode 100644
> index 0000000..e40d7ee
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
> @@ -0,0 +1,505 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "Toshiba AC100 / Dynabook AZ";
> + compatible = "compal,paz00", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata", "atc", "atd", "ate",
> + "dap2", "gmb", "gmc", "gmd", "spia",
> + "spib", "spic", "spid", "spie";
> + nvidia,function = "gmi";
> + };
> + atb {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "pllc_out1";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> + nvidia,function = "rsvd1";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gpu {
> + nvidia,pins = "gpu", "sdb", "sdd";
> + nvidia,function = "pwm";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint", "pta";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uarta";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + kbcb {
> + nvidia,pins = "kbcb", "kbcd";
> + nvidia,function = "sdio2";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> + "ld3", "ld4", "ld5", "ld6", "ld7",
> + "ld8", "ld9", "ld10", "ld11", "ld12",
> + "ld13", "ld14", "ld15", "ld16", "ld17",
> + "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> + "lhs", "lm0", "lm1", "lpp", "lpw0",
> + "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> + "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> + "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc";
> + nvidia,function = "owr";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdc {
> + nvidia,pins = "sdc";
> + nvidia,function = "twc";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxc {
> + nvidia,pins = "slxc", "slxd";
> + nvidia,function = "spi4";
> + };
> + spdi {
> + nvidia,pins = "spdi", "spdo";
> + nvidia,function = "rsvd2";
> + };
> + spif {
> + nvidia,pins = "spif", "uac";
> + nvidia,function = "rsvd4";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "spdif";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> + "cdev1", "cdev2", "dap1", "dap2", "dtf",
> + "gma", "gmb", "gmc", "gmd", "gme",
> + "gpu", "gpu7", "gpv", "i2cp", "pta",
> + "rm", "sdio1", "slxk", "spdo", "uac",
> + "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp", "dap3", "dap4", "dtb",
> + "dtc", "dte", "slxa", "slxc", "slxd",
> + "spdi";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_csus {
> + nvidia,pins = "csus", "spia", "spib", "spid",
> + "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_ddc {
> + nvidia,pins = "ddc", "irrx", "irtx", "kbca",
> + "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> + "spic", "spig", "uaa", "uab";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_dta {
> + nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
> + "spie", "spih", "uad", "uca", "ucb";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "ld0", "ld1", "ld2",
> + "ld3", "ld4", "ld5", "ld6", "ld7",
> + "ld8", "ld9", "ld10", "ld11", "ld12",
> + "ld13", "ld14", "ld15", "ld16", "ld17",
> + "ldc", "ldi", "lhs", "lsc0", "lspi",
> + "lvs", "pmc";
> + nvidia,tristate = <0>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_lcsn {
> + nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
> + "lm0", "lm1", "lpp", "lpw0", "lpw1",
> + "lpw2", "lsc1", "lsck", "lsda", "lsdi",
> + "lvp0", "lvp1", "sdb";
> + nvidia,tristate = <1>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + serial@70006200 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + alc5632: alc5632@1e {
> + compatible = "realtek,alc5632";
> + reg = <0x1e>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> + };
> +
> + hdmi_ddc: i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + nvec {
> + compatible = "nvidia,nvec";
> + reg = <0x7000c500 0x100>;
> + interrupts = <0 92 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <80000>;
> + request-gpios = <&gpio 170 0>; /* gpio PV2 */
> + slave-addr = <138>;
> + clocks = <&tegra_car 67>, <&tegra_car 124>;
> + clock-names = "div-clk", "fast-clk";
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&p5valw_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + sys_reg: sys {
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + sm0 {
> + regulator-name = "+1.2vs_sm0,vdd_core";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + sm1 {
> + regulator-name = "+1.0vs_sm1,vdd_cpu";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: sm2 {
> + regulator-name = "+3.7vs_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + /* LDO0 is not connected to anything */
> +
> + ldo1 {
> + regulator-name = "+1.1vs_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "+1.2vs_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo3 {
> + regulator-name = "+3.3vs_ldo3,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "+2.85vs_ldo5,vcore_mmc";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo6 {
> + /*
> + * Research indicates this should be
> + * 1.8v; other boards that use this
> + * rail for the same purpose need it
> + * set to 1.8v. The schematic signal
> + * name is incorrect; perhaps copied
> + * from an incorrect NVIDIA reference.
> + */
> + regulator-name = "+2.85vs_ldo6,avdd_vdac";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + hdmi_vdd_reg: ldo7 {
> + regulator-name = "+3.3vs_ldo7,avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: ldo8 {
> + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo9 {
> + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo_rtc {
> + regulator-name = "+3.3vs_rtc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + adt7461@4c {
> + compatible = "adi,adt7461";
> + reg = <0x4c>;
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + usb-phy@c5004400 {
> + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> + };
> +
> + sdhci@c8000000 {
> + status = "okay";
> + cd-gpios = <&gpio 173 0>; /* gpio PV5 */
> + wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> + power-gpios = <&gpio 169 0>; /* gpio PV1 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power {
> + label = "Power";
> + gpios = <&gpio 79 1>; /* gpio PJ7, active low */
> + linux,code = <116>; /* KEY_POWER */
> + gpio-key,wakeup;
> + };
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> +
> + wifi {
> + label = "wifi-led";
> + gpios = <&gpio 24 0>; /* gpio PD0 */
> + linux,default-trigger = "rfkill0";
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + p5valw_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "+5valw";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-alc5632-paz00",
> + "nvidia,tegra-audio-alc5632";
> +
> + nvidia,model = "Compal PAZ00";
> +
> + nvidia,audio-routing =
> + "Int Spk", "SPKOUT",
> + "Int Spk", "SPKOUTN",
> + "Headset Mic", "MICBIAS1",
> + "MIC1", "Headset Mic",
> + "Headset Stereophone", "HPR",
> + "Headset Stereophone", "HPL",
> + "DMICDAT", "Digital Mic";
> +
> + nvidia,audio-codec = <&alc5632>;
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
> deleted file mode 100644
> index 2894800..0000000
> --- a/arch/arm/boot/dts/tegra20-plutux.dts
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20-tamonten.dtsi"
> -
> -/ {
> - model = "Avionic Design Plutux board";
> - compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
> -
> - host1x {
> - hdmi {
> - status = "okay";
> - };
> - };
> -
> - i2c@7000c000 {
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff
> - 0xffffffff
> - 0
> - 0xffffffff
> - 0xffffffff>;
> - };
> - };
> -
> - sound {
> - compatible = "ad,tegra-audio-plutux",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "Avionic Design Plutux";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-plutux.dtsp b/arch/arm/boot/dts/tegra20-plutux.dtsp
> new file mode 100644
> index 0000000..08401b9
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-plutux.dtsp
> @@ -0,0 +1,56 @@
> +/dts-v1/;
> +
> +#include "tegra20-tamonten.dtsip"
> +
> +/ {
> + model = "Avionic Design Plutux board";
> + compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
> +
> + host1x {
> + hdmi {
> + status = "okay";
> + };
> + };
> +
> + i2c@7000c000 {
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff
> + 0xffffffff
> + 0
> + 0xffffffff
> + 0xffffffff>;
> + };
> + };
> +
> + sound {
> + compatible = "ad,tegra-audio-plutux",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "Avionic Design Plutux";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
> deleted file mode 100644
> index 37b3a57..0000000
> --- a/arch/arm/boot/dts/tegra20-seaboard.dts
> +++ /dev/null
> @@ -1,812 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "NVIDIA Seaboard";
> - compatible = "nvidia,seaboard", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x40000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata";
> - nvidia,function = "ide";
> - };
> - atb {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - };
> - atc {
> - nvidia,pins = "atc";
> - nvidia,function = "nand";
> - };
> - atd {
> - nvidia,pins = "atd", "ate", "gmb", "spia",
> - "spib", "spic";
> - nvidia,function = "gmi";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp", "lm1";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> - nvidia,function = "vi";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gmc {
> - nvidia,pins = "gmc";
> - nvidia,function = "uartd";
> - };
> - gmd {
> - nvidia,pins = "gmd";
> - nvidia,function = "sflash";
> - };
> - gpu {
> - nvidia,pins = "gpu";
> - nvidia,function = "pwm";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
> - "lsck", "lsda";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uartb";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
> - "lsdi", "lvp0";
> - nvidia,function = "rsvd4";
> - };
> - ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lpp", "lsc0",
> - "lspi", "lvp1", "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "spdi", "spdo", "uac";
> - nvidia,function = "rsvd2";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd";
> - nvidia,function = "sdio3";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxc {
> - nvidia,pins = "slxc", "slxd";
> - nvidia,function = "spdif";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "atd",
> - "cdev1", "cdev2", "dap1", "dap2",
> - "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
> - "gme", "gpu", "gpu7", "i2cp", "irrx",
> - "irtx", "pta", "rm", "sdc", "sdd",
> - "slxd", "slxk", "spdi", "spdo", "uac",
> - "uad", "uca", "ucb", "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ate {
> - nvidia,pins = "ate", "csus", "dap3",
> - "gpv", "owc", "slxc", "spib", "spid",
> - "spie";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp", "gmb", "slxa", "spia",
> - "spig", "spih";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd";
> - nvidia,pull = <1>;
> - nvidia,tristate = <0>;
> - };
> - conf_dte {
> - nvidia,pins = "dte", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> - "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> - "lvp0";
> - nvidia,tristate = <1>;
> - };
> - conf_kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf", "sdio1", "spic", "uaa",
> - "uab";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lm0", "lpp",
> - "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> - "lvs", "pmc", "sdb";
> - nvidia,tristate = <0>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - drive_sdio1 {
> - nvidia,pins = "drive_sdio1";
> - nvidia,high-speed-mode = <0>;
> - nvidia,schmitt = <0>;
> - nvidia,low-power-mode = <3>;
> - nvidia,pull-down-strength = <31>;
> - nvidia,pull-up-strength = <31>;
> - nvidia,slew-rate-rising = <3>;
> - nvidia,slew-rate-falling = <3>;
> - };
> - };
> -
> - state_i2cmux_ddc: pinmux_i2cmux_ddc {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> -
> - state_i2cmux_pta: pinmux_i2cmux_pta {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "i2c2";
> - };
> - };
> -
> - state_i2cmux_idle: pinmux_i2cmux_idle {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> - };
> -
> - /* ALS and proximity sensor */
> - isl29018@44 {
> - compatible = "isil,isl29018";
> - reg = <0x44>;
> - interrupt-parent = <&gpio>;
> - interrupts = <202 0x04>; /* GPIO PZ2 */
> - };
> -
> - gyrometer@68 {
> - compatible = "invn,mpu3050";
> - reg = <0x68>;
> - interrupt-parent = <&gpio>;
> - interrupts = <204 0x04>; /* gpio PZ4 */
> - };
> - };
> -
> - i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2cmux {
> - compatible = "i2c-mux-pinctrl";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - i2c-parent = <&{/i2c@7000c400}>;
> -
> - pinctrl-names = "ddc", "pta", "idle";
> - pinctrl-0 = <&state_i2cmux_ddc>;
> - pinctrl-1 = <&state_i2cmux_pta>;
> - pinctrl-2 = <&state_i2cmux_idle>;
> -
> - hdmi_ddc: i2c@0 {
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c@1 {
> - reg = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - smart-battery@b {
> - compatible = "ti,bq20z75", "smart-battery-1.1";
> - reg = <0xb>;
> - ti,i2c-retry-count = <2>;
> - ti,poll-retry-count = <10>;
> - };
> - };
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <400000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&vdd_5v0_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - sys_reg: sys {
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - sm0 {
> - regulator-name = "vdd_sm0,vdd_core";
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - };
> -
> - sm1 {
> - regulator-name = "vdd_sm1,vdd_cpu";
> - regulator-min-microvolt = <1125000>;
> - regulator-max-microvolt = <1125000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: sm2 {
> - regulator-name = "vdd_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - /* LDO0 is not connected to anything */
> -
> - ldo1 {
> - regulator-name = "vdd_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "vdd_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo3 {
> - regulator-name = "vdd_ldo3,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "vdd_ldo5,vcore_mmc";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo6 {
> - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - hdmi_vdd_reg: ldo7 {
> - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: ldo8 {
> - regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo9 {
> - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo_rtc {
> - regulator-name = "vdd_rtc_out,vdd_cell";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - temperature-sensor@4c {
> - compatible = "onnn,nct1008";
> - reg = <0x4c>;
> - };
> -
> - magnetometer@c {
> - compatible = "ak,ak8975";
> - reg = <0xc>;
> - interrupt-parent = <&gpio>;
> - interrupts = <109 0x04>; /* gpio PN5 */
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - memory-controller@7000f400 {
> - emc-table@190000 {
> - reg = <190000>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <190000>;
> - nvidia,emc-registers = <0x0000000c 0x00000026
> - 0x00000009 0x00000003 0x00000004 0x00000004
> - 0x00000002 0x0000000c 0x00000003 0x00000003
> - 0x00000002 0x00000001 0x00000004 0x00000005
> - 0x00000004 0x00000009 0x0000000d 0x0000059f
> - 0x00000000 0x00000003 0x00000003 0x00000003
> - 0x00000003 0x00000001 0x0000000b 0x000000c8
> - 0x00000003 0x00000007 0x00000004 0x0000000f
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0xa06204ae
> - 0x007dc010 0x00000000 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> -
> - emc-table@380000 {
> - reg = <380000>;
> - compatible = "nvidia,tegra20-emc-table";
> - clock-frequency = <380000>;
> - nvidia,emc-registers = <0x00000017 0x0000004b
> - 0x00000012 0x00000006 0x00000004 0x00000005
> - 0x00000003 0x0000000c 0x00000006 0x00000006
> - 0x00000003 0x00000001 0x00000004 0x00000005
> - 0x00000004 0x00000009 0x0000000d 0x00000b5f
> - 0x00000000 0x00000003 0x00000003 0x00000006
> - 0x00000006 0x00000001 0x00000011 0x000000c8
> - 0x00000003 0x0000000e 0x00000007 0x0000000f
> - 0x00000002 0x00000000 0x00000000 0x00000002
> - 0x00000000 0x00000000 0x00000083 0xe044048b
> - 0x007d8010 0x00000000 0x00000000 0x00000000
> - 0x00000000 0x00000000 0x00000000 0x00000000>;
> - };
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
> - dr_mode = "otg";
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - usb-phy@c5004400 {
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - sdhci@c8000000 {
> - status = "okay";
> - power-gpios = <&gpio 86 0>; /* gpio PK6 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000400 {
> - status = "okay";
> - cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> - wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> - power-gpios = <&gpio 70 0>; /* gpio PI6 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> -
> - power {
> - label = "Power";
> - gpios = <&gpio 170 1>; /* gpio PV2, active low */
> - linux,code = <116>; /* KEY_POWER */
> - gpio-key,wakeup;
> - };
> -
> - lid {
> - label = "Lid";
> - gpios = <&gpio 23 0>; /* gpio PC7 */
> - linux,input-type = <5>; /* EV_SW */
> - linux,code = <0>; /* SW_LID */
> - debounce-interval = <1>;
> - gpio-key,wakeup;
> - };
> - };
> -
> - kbc {
> - status = "okay";
> - nvidia,debounce-delay-ms = <32>;
> - nvidia,repeat-delay-ms = <160>;
> - nvidia,ghost-filter;
> - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
> - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
> - linux,keymap = <0x00020011 /* KEY_W */
> - 0x0003001F /* KEY_S */
> - 0x0004001E /* KEY_A */
> - 0x0005002C /* KEY_Z */
> - 0x000701d0 /* KEY_FN */
> -
> - 0x0107007D /* KEY_LEFTMETA */
> - 0x02060064 /* KEY_RIGHTALT */
> - 0x02070038 /* KEY_LEFTALT */
> -
> - 0x03000006 /* KEY_5 */
> - 0x03010005 /* KEY_4 */
> - 0x03020013 /* KEY_R */
> - 0x03030012 /* KEY_E */
> - 0x03040021 /* KEY_F */
> - 0x03050020 /* KEY_D */
> - 0x0306002D /* KEY_X */
> -
> - 0x04000008 /* KEY_7 */
> - 0x04010007 /* KEY_6 */
> - 0x04020014 /* KEY_T */
> - 0x04030023 /* KEY_H */
> - 0x04040022 /* KEY_G */
> - 0x0405002F /* KEY_V */
> - 0x0406002E /* KEY_C */
> - 0x04070039 /* KEY_SPACE */
> -
> - 0x0500000A /* KEY_9 */
> - 0x05010009 /* KEY_8 */
> - 0x05020016 /* KEY_U */
> - 0x05030015 /* KEY_Y */
> - 0x05040024 /* KEY_J */
> - 0x05050031 /* KEY_N */
> - 0x05060030 /* KEY_B */
> - 0x0507002B /* KEY_BACKSLASH */
> -
> - 0x0600000C /* KEY_MINUS */
> - 0x0601000B /* KEY_0 */
> - 0x06020018 /* KEY_O */
> - 0x06030017 /* KEY_I */
> - 0x06040026 /* KEY_L */
> - 0x06050025 /* KEY_K */
> - 0x06060033 /* KEY_COMMA */
> - 0x06070032 /* KEY_M */
> -
> - 0x0701000D /* KEY_EQUAL */
> - 0x0702001B /* KEY_RIGHTBRACE */
> - 0x0703001C /* KEY_ENTER */
> - 0x0707008B /* KEY_MENU */
> -
> - 0x08040036 /* KEY_RIGHTSHIFT */
> - 0x0805002A /* KEY_LEFTSHIFT */
> -
> - 0x09050061 /* KEY_RIGHTCTRL */
> - 0x0907001D /* KEY_LEFTCTRL */
> -
> - 0x0B00001A /* KEY_LEFTBRACE */
> - 0x0B010019 /* KEY_P */
> - 0x0B020028 /* KEY_APOSTROPHE */
> - 0x0B030027 /* KEY_SEMICOLON */
> - 0x0B040035 /* KEY_SLASH */
> - 0x0B050034 /* KEY_DOT */
> -
> - 0x0C000044 /* KEY_F10 */
> - 0x0C010043 /* KEY_F9 */
> - 0x0C02000E /* KEY_BACKSPACE */
> - 0x0C030004 /* KEY_3 */
> - 0x0C040003 /* KEY_2 */
> - 0x0C050067 /* KEY_UP */
> - 0x0C0600D2 /* KEY_PRINT */
> - 0x0C070077 /* KEY_PAUSE */
> -
> - 0x0D00006E /* KEY_INSERT */
> - 0x0D01006F /* KEY_DELETE */
> - 0x0D030068 /* KEY_PAGEUP */
> - 0x0D04006D /* KEY_PAGEDOWN */
> - 0x0D05006A /* KEY_RIGHT */
> - 0x0D06006C /* KEY_DOWN */
> - 0x0D070069 /* KEY_LEFT */
> -
> - 0x0E000057 /* KEY_F11 */
> - 0x0E010058 /* KEY_F12 */
> - 0x0E020042 /* KEY_F8 */
> - 0x0E030010 /* KEY_Q */
> - 0x0E04003E /* KEY_F4 */
> - 0x0E05003D /* KEY_F3 */
> - 0x0E060002 /* KEY_1 */
> - 0x0E070041 /* KEY_F7 */
> -
> - 0x0F000001 /* KEY_ESC */
> - 0x0F010029 /* KEY_GRAVE */
> - 0x0F02003F /* KEY_F5 */
> - 0x0F03000F /* KEY_TAB */
> - 0x0F04003B /* KEY_F1 */
> - 0x0F05003C /* KEY_F2 */
> - 0x0F06003A /* KEY_CAPSLOCK */
> - 0x0F070040 /* KEY_F6 */
> -
> - /* Software Handled Function Keys */
> - 0x14000047 /* KEY_KP7 */
> -
> - 0x15000049 /* KEY_KP9 */
> - 0x15010048 /* KEY_KP8 */
> - 0x1502004B /* KEY_KP4 */
> - 0x1504004F /* KEY_KP1 */
> -
> - 0x1601004E /* KEY_KPSLASH */
> - 0x1602004D /* KEY_KP6 */
> - 0x1603004C /* KEY_KP5 */
> - 0x16040051 /* KEY_KP3 */
> - 0x16050050 /* KEY_KP2 */
> - 0x16070052 /* KEY_KP0 */
> -
> - 0x1B010037 /* KEY_KPASTERISK */
> - 0x1B03004A /* KEY_KPMINUS */
> - 0x1B04004E /* KEY_KPPLUS */
> - 0x1B050053 /* KEY_KPDOT */
> -
> - 0x1C050073 /* KEY_VOLUMEUP */
> -
> - 0x1D030066 /* KEY_HOME */
> - 0x1D04006B /* KEY_END */
> - 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
> - 0x1D060072 /* KEY_VOLUMEDOWN */
> - 0x1D0700E1 /* KEY_BRIGHTNESSUP */
> -
> - 0x1E000045 /* KEY_NUMLOCK */
> - 0x1E010046 /* KEY_SCROLLLOCK */
> - 0x1E020071 /* KEY_MUTE */
> -
> - 0x1F04008A>; /* KEY_HELP */
> - };
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v0_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "vdd_1v5";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - gpio = <&pmic 0 0>;
> - };
> -
> - regulator@2 {
> - compatible = "regulator-fixed";
> - reg = <2>;
> - regulator-name = "vdd_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - gpio = <&pmic 1 0>;
> - enable-active-high;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm8903-seaboard",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "NVIDIA Tegra Seaboard";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1R", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-seaboard.dtsp b/arch/arm/boot/dts/tegra20-seaboard.dtsp
> new file mode 100644
> index 0000000..6534a61
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-seaboard.dtsp
> @@ -0,0 +1,812 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "NVIDIA Seaboard";
> + compatible = "nvidia,seaboard", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x40000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata";
> + nvidia,function = "ide";
> + };
> + atb {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + };
> + atc {
> + nvidia,pins = "atc";
> + nvidia,function = "nand";
> + };
> + atd {
> + nvidia,pins = "atd", "ate", "gmb", "spia",
> + "spib", "spic";
> + nvidia,function = "gmi";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp", "lm1";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> + nvidia,function = "vi";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gmc {
> + nvidia,pins = "gmc";
> + nvidia,function = "uartd";
> + };
> + gmd {
> + nvidia,pins = "gmd";
> + nvidia,function = "sflash";
> + };
> + gpu {
> + nvidia,pins = "gpu";
> + nvidia,function = "pwm";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
> + "lsck", "lsda";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uartb";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
> + "lsdi", "lvp0";
> + nvidia,function = "rsvd4";
> + };
> + ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lpp", "lsc0",
> + "lspi", "lvp1", "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "spdi", "spdo", "uac";
> + nvidia,function = "rsvd2";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd";
> + nvidia,function = "sdio3";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxc {
> + nvidia,pins = "slxc", "slxd";
> + nvidia,function = "spdif";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "atd",
> + "cdev1", "cdev2", "dap1", "dap2",
> + "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
> + "gme", "gpu", "gpu7", "i2cp", "irrx",
> + "irtx", "pta", "rm", "sdc", "sdd",
> + "slxd", "slxk", "spdi", "spdo", "uac",
> + "uad", "uca", "ucb", "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ate {
> + nvidia,pins = "ate", "csus", "dap3",
> + "gpv", "owc", "slxc", "spib", "spid",
> + "spie";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp", "gmb", "slxa", "spia",
> + "spig", "spih";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd";
> + nvidia,pull = <1>;
> + nvidia,tristate = <0>;
> + };
> + conf_dte {
> + nvidia,pins = "dte", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> + "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> + "lvp0";
> + nvidia,tristate = <1>;
> + };
> + conf_kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf", "sdio1", "spic", "uaa",
> + "uab";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lm0", "lpp",
> + "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> + "lvs", "pmc", "sdb";
> + nvidia,tristate = <0>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + drive_sdio1 {
> + nvidia,pins = "drive_sdio1";
> + nvidia,high-speed-mode = <0>;
> + nvidia,schmitt = <0>;
> + nvidia,low-power-mode = <3>;
> + nvidia,pull-down-strength = <31>;
> + nvidia,pull-up-strength = <31>;
> + nvidia,slew-rate-rising = <3>;
> + nvidia,slew-rate-falling = <3>;
> + };
> + };
> +
> + state_i2cmux_ddc: pinmux_i2cmux_ddc {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> +
> + state_i2cmux_pta: pinmux_i2cmux_pta {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "i2c2";
> + };
> + };
> +
> + state_i2cmux_idle: pinmux_i2cmux_idle {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> + };
> +
> + /* ALS and proximity sensor */
> + isl29018@44 {
> + compatible = "isil,isl29018";
> + reg = <0x44>;
> + interrupt-parent = <&gpio>;
> + interrupts = <202 0x04>; /* GPIO PZ2 */
> + };
> +
> + gyrometer@68 {
> + compatible = "invn,mpu3050";
> + reg = <0x68>;
> + interrupt-parent = <&gpio>;
> + interrupts = <204 0x04>; /* gpio PZ4 */
> + };
> + };
> +
> + i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2cmux {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c-parent = <&{/i2c@7000c400}>;
> +
> + pinctrl-names = "ddc", "pta", "idle";
> + pinctrl-0 = <&state_i2cmux_ddc>;
> + pinctrl-1 = <&state_i2cmux_pta>;
> + pinctrl-2 = <&state_i2cmux_idle>;
> +
> + hdmi_ddc: i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + smart-battery@b {
> + compatible = "ti,bq20z75", "smart-battery-1.1";
> + reg = <0xb>;
> + ti,i2c-retry-count = <2>;
> + ti,poll-retry-count = <10>;
> + };
> + };
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&vdd_5v0_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + sys_reg: sys {
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + sm0 {
> + regulator-name = "vdd_sm0,vdd_core";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + };
> +
> + sm1 {
> + regulator-name = "vdd_sm1,vdd_cpu";
> + regulator-min-microvolt = <1125000>;
> + regulator-max-microvolt = <1125000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: sm2 {
> + regulator-name = "vdd_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + /* LDO0 is not connected to anything */
> +
> + ldo1 {
> + regulator-name = "vdd_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "vdd_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo3 {
> + regulator-name = "vdd_ldo3,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "vdd_ldo5,vcore_mmc";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo6 {
> + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + hdmi_vdd_reg: ldo7 {
> + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: ldo8 {
> + regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo9 {
> + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo_rtc {
> + regulator-name = "vdd_rtc_out,vdd_cell";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + temperature-sensor@4c {
> + compatible = "onnn,nct1008";
> + reg = <0x4c>;
> + };
> +
> + magnetometer@c {
> + compatible = "ak,ak8975";
> + reg = <0xc>;
> + interrupt-parent = <&gpio>;
> + interrupts = <109 0x04>; /* gpio PN5 */
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + memory-controller@7000f400 {
> + emc-table@190000 {
> + reg = <190000>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <190000>;
> + nvidia,emc-registers = <0x0000000c 0x00000026
> + 0x00000009 0x00000003 0x00000004 0x00000004
> + 0x00000002 0x0000000c 0x00000003 0x00000003
> + 0x00000002 0x00000001 0x00000004 0x00000005
> + 0x00000004 0x00000009 0x0000000d 0x0000059f
> + 0x00000000 0x00000003 0x00000003 0x00000003
> + 0x00000003 0x00000001 0x0000000b 0x000000c8
> + 0x00000003 0x00000007 0x00000004 0x0000000f
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0xa06204ae
> + 0x007dc010 0x00000000 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> +
> + emc-table@380000 {
> + reg = <380000>;
> + compatible = "nvidia,tegra20-emc-table";
> + clock-frequency = <380000>;
> + nvidia,emc-registers = <0x00000017 0x0000004b
> + 0x00000012 0x00000006 0x00000004 0x00000005
> + 0x00000003 0x0000000c 0x00000006 0x00000006
> + 0x00000003 0x00000001 0x00000004 0x00000005
> + 0x00000004 0x00000009 0x0000000d 0x00000b5f
> + 0x00000000 0x00000003 0x00000003 0x00000006
> + 0x00000006 0x00000001 0x00000011 0x000000c8
> + 0x00000003 0x0000000e 0x00000007 0x0000000f
> + 0x00000002 0x00000000 0x00000000 0x00000002
> + 0x00000000 0x00000000 0x00000083 0xe044048b
> + 0x007d8010 0x00000000 0x00000000 0x00000000
> + 0x00000000 0x00000000 0x00000000 0x00000000>;
> + };
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
> + dr_mode = "otg";
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + usb-phy@c5004400 {
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + sdhci@c8000000 {
> + status = "okay";
> + power-gpios = <&gpio 86 0>; /* gpio PK6 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000400 {
> + status = "okay";
> + cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> + wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> + power-gpios = <&gpio 70 0>; /* gpio PI6 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power {
> + label = "Power";
> + gpios = <&gpio 170 1>; /* gpio PV2, active low */
> + linux,code = <116>; /* KEY_POWER */
> + gpio-key,wakeup;
> + };
> +
> + lid {
> + label = "Lid";
> + gpios = <&gpio 23 0>; /* gpio PC7 */
> + linux,input-type = <5>; /* EV_SW */
> + linux,code = <0>; /* SW_LID */
> + debounce-interval = <1>;
> + gpio-key,wakeup;
> + };
> + };
> +
> + kbc {
> + status = "okay";
> + nvidia,debounce-delay-ms = <32>;
> + nvidia,repeat-delay-ms = <160>;
> + nvidia,ghost-filter;
> + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
> + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
> + linux,keymap = <0x00020011 /* KEY_W */
> + 0x0003001F /* KEY_S */
> + 0x0004001E /* KEY_A */
> + 0x0005002C /* KEY_Z */
> + 0x000701d0 /* KEY_FN */
> +
> + 0x0107007D /* KEY_LEFTMETA */
> + 0x02060064 /* KEY_RIGHTALT */
> + 0x02070038 /* KEY_LEFTALT */
> +
> + 0x03000006 /* KEY_5 */
> + 0x03010005 /* KEY_4 */
> + 0x03020013 /* KEY_R */
> + 0x03030012 /* KEY_E */
> + 0x03040021 /* KEY_F */
> + 0x03050020 /* KEY_D */
> + 0x0306002D /* KEY_X */
> +
> + 0x04000008 /* KEY_7 */
> + 0x04010007 /* KEY_6 */
> + 0x04020014 /* KEY_T */
> + 0x04030023 /* KEY_H */
> + 0x04040022 /* KEY_G */
> + 0x0405002F /* KEY_V */
> + 0x0406002E /* KEY_C */
> + 0x04070039 /* KEY_SPACE */
> +
> + 0x0500000A /* KEY_9 */
> + 0x05010009 /* KEY_8 */
> + 0x05020016 /* KEY_U */
> + 0x05030015 /* KEY_Y */
> + 0x05040024 /* KEY_J */
> + 0x05050031 /* KEY_N */
> + 0x05060030 /* KEY_B */
> + 0x0507002B /* KEY_BACKSLASH */
> +
> + 0x0600000C /* KEY_MINUS */
> + 0x0601000B /* KEY_0 */
> + 0x06020018 /* KEY_O */
> + 0x06030017 /* KEY_I */
> + 0x06040026 /* KEY_L */
> + 0x06050025 /* KEY_K */
> + 0x06060033 /* KEY_COMMA */
> + 0x06070032 /* KEY_M */
> +
> + 0x0701000D /* KEY_EQUAL */
> + 0x0702001B /* KEY_RIGHTBRACE */
> + 0x0703001C /* KEY_ENTER */
> + 0x0707008B /* KEY_MENU */
> +
> + 0x08040036 /* KEY_RIGHTSHIFT */
> + 0x0805002A /* KEY_LEFTSHIFT */
> +
> + 0x09050061 /* KEY_RIGHTCTRL */
> + 0x0907001D /* KEY_LEFTCTRL */
> +
> + 0x0B00001A /* KEY_LEFTBRACE */
> + 0x0B010019 /* KEY_P */
> + 0x0B020028 /* KEY_APOSTROPHE */
> + 0x0B030027 /* KEY_SEMICOLON */
> + 0x0B040035 /* KEY_SLASH */
> + 0x0B050034 /* KEY_DOT */
> +
> + 0x0C000044 /* KEY_F10 */
> + 0x0C010043 /* KEY_F9 */
> + 0x0C02000E /* KEY_BACKSPACE */
> + 0x0C030004 /* KEY_3 */
> + 0x0C040003 /* KEY_2 */
> + 0x0C050067 /* KEY_UP */
> + 0x0C0600D2 /* KEY_PRINT */
> + 0x0C070077 /* KEY_PAUSE */
> +
> + 0x0D00006E /* KEY_INSERT */
> + 0x0D01006F /* KEY_DELETE */
> + 0x0D030068 /* KEY_PAGEUP */
> + 0x0D04006D /* KEY_PAGEDOWN */
> + 0x0D05006A /* KEY_RIGHT */
> + 0x0D06006C /* KEY_DOWN */
> + 0x0D070069 /* KEY_LEFT */
> +
> + 0x0E000057 /* KEY_F11 */
> + 0x0E010058 /* KEY_F12 */
> + 0x0E020042 /* KEY_F8 */
> + 0x0E030010 /* KEY_Q */
> + 0x0E04003E /* KEY_F4 */
> + 0x0E05003D /* KEY_F3 */
> + 0x0E060002 /* KEY_1 */
> + 0x0E070041 /* KEY_F7 */
> +
> + 0x0F000001 /* KEY_ESC */
> + 0x0F010029 /* KEY_GRAVE */
> + 0x0F02003F /* KEY_F5 */
> + 0x0F03000F /* KEY_TAB */
> + 0x0F04003B /* KEY_F1 */
> + 0x0F05003C /* KEY_F2 */
> + 0x0F06003A /* KEY_CAPSLOCK */
> + 0x0F070040 /* KEY_F6 */
> +
> + /* Software Handled Function Keys */
> + 0x14000047 /* KEY_KP7 */
> +
> + 0x15000049 /* KEY_KP9 */
> + 0x15010048 /* KEY_KP8 */
> + 0x1502004B /* KEY_KP4 */
> + 0x1504004F /* KEY_KP1 */
> +
> + 0x1601004E /* KEY_KPSLASH */
> + 0x1602004D /* KEY_KP6 */
> + 0x1603004C /* KEY_KP5 */
> + 0x16040051 /* KEY_KP3 */
> + 0x16050050 /* KEY_KP2 */
> + 0x16070052 /* KEY_KP0 */
> +
> + 0x1B010037 /* KEY_KPASTERISK */
> + 0x1B03004A /* KEY_KPMINUS */
> + 0x1B04004E /* KEY_KPPLUS */
> + 0x1B050053 /* KEY_KPDOT */
> +
> + 0x1C050073 /* KEY_VOLUMEUP */
> +
> + 0x1D030066 /* KEY_HOME */
> + 0x1D04006B /* KEY_END */
> + 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
> + 0x1D060072 /* KEY_VOLUMEDOWN */
> + 0x1D0700E1 /* KEY_BRIGHTNESSUP */
> +
> + 0x1E000045 /* KEY_NUMLOCK */
> + 0x1E010046 /* KEY_SCROLLLOCK */
> + 0x1E020071 /* KEY_MUTE */
> +
> + 0x1F04008A>; /* KEY_HELP */
> + };
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v0_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "vdd_1v5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&pmic 0 0>;
> + };
> +
> + regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "vdd_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&pmic 1 0>;
> + enable-active-high;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm8903-seaboard",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "NVIDIA Tegra Seaboard";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1R", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
> deleted file mode 100644
> index 4766aba..0000000
> --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
> +++ /dev/null
> @@ -1,489 +0,0 @@
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "Avionic Design Tamonten SOM";
> - compatible = "ad,tamonten", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x20000000>;
> - };
> -
> - host1x {
> - hdmi {
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata";
> - nvidia,function = "ide";
> - };
> - atb {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - };
> - atc {
> - nvidia,pins = "atc";
> - nvidia,function = "nand";
> - };
> - atd {
> - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
> - "spia", "spib", "spic";
> - nvidia,function = "gmi";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - dta {
> - nvidia,pins = "dta", "dtd";
> - nvidia,function = "sdio2";
> - };
> - dtb {
> - nvidia,pins = "dtb", "dtc", "dte";
> - nvidia,function = "rsvd1";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gmc {
> - nvidia,pins = "gmc";
> - nvidia,function = "uartd";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uarta";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> - "ld3", "ld4", "ld5", "ld6", "ld7",
> - "ld8", "ld9", "ld10", "ld11", "ld12",
> - "ld13", "ld14", "ld15", "ld16", "ld17",
> - "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> - "lhs", "lm0", "lm1", "lpp", "lpw0",
> - "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> - "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> - "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "spdi", "spdo", "uac";
> - nvidia,function = "rsvd2";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd";
> - nvidia,function = "pwm";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxc {
> - nvidia,pins = "slxc", "slxd";
> - nvidia,function = "spdif";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> - "cdev1", "cdev2", "dap1", "dtb", "gma",
> - "gmb", "gmc", "gmd", "gme", "gpu7",
> - "gpv", "i2cp", "pta", "rm", "slxa",
> - "slxk", "spia", "spib", "uac";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_csus {
> - nvidia,pins = "csus", "spid", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp", "dap2", "dap3", "dap4",
> - "dtc", "dte", "dtf", "gpu", "sdio1",
> - "slxc", "slxd", "spdi", "spdo", "spig",
> - "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_ddc {
> - nvidia,pins = "ddc", "dta", "dtd", "kbca",
> - "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> - "sdc";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> - "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> - "lvp0", "owc", "sdb";
> - nvidia,tristate = <1>;
> - };
> - conf_irrx {
> - nvidia,pins = "irrx", "irtx", "sdd", "spic",
> - "spie", "spih", "uaa", "uab", "uad",
> - "uca", "ucb";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lm0", "lpp",
> - "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> - "lvs", "pmc";
> - nvidia,tristate = <0>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - };
> -
> - state_i2cmux_ddc: pinmux_i2cmux_ddc {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> -
> - state_i2cmux_pta: pinmux_i2cmux_pta {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "i2c2";
> - };
> - };
> -
> - state_i2cmux_idle: pinmux_i2cmux_idle {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - clock-frequency = <400000>;
> - status = "okay";
> - };
> -
> - i2c@7000c400 {
> - clock-frequency = <100000>;
> - status = "okay";
> - };
> -
> - i2cmux {
> - compatible = "i2c-mux-pinctrl";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - i2c-parent = <&{/i2c@7000c400}>;
> -
> - pinctrl-names = "ddc", "pta", "idle";
> - pinctrl-0 = <&state_i2cmux_ddc>;
> - pinctrl-1 = <&state_i2cmux_pta>;
> - pinctrl-2 = <&state_i2cmux_idle>;
> -
> - hdmi_ddc: i2c@0 {
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c@1 {
> - reg = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> - };
> -
> - i2c@7000d000 {
> - clock-frequency = <400000>;
> - status = "okay";
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&vdd_5v0_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - sys_reg: sys {
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - sm0 {
> - regulator-name = "vdd_sys_sm0,vdd_core";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - sm1 {
> - regulator-name = "vdd_sys_sm1,vdd_cpu";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: sm2 {
> - regulator-name = "vdd_sys_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - ldo0 {
> - regulator-name = "vdd_ldo0,vddio_pex_clk";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo1 {
> - regulator-name = "vdd_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "vdd_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo3 {
> - regulator-name = "vdd_ldo3,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "vdd_ldo5,vcore_mmc";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - };
> -
> - ldo6 {
> - regulator-name = "vdd_ldo6,avdd_vdac";
> - /*
> - * According to the Tegra 2 Automotive
> - * DataSheet, a typical value for this
> - * would be 2.8V, but the PMIC only
> - * supports 2.85V.
> - */
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - };
> -
> - hdmi_vdd_reg: ldo7 {
> - regulator-name = "vdd_ldo7,avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: ldo8 {
> - regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo9 {
> - regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
> - /*
> - * According to the Tegra 2 Automotive
> - * DataSheet, a typical value for this
> - * would be 2.8V, but the PMIC only
> - * supports 2.85V.
> - */
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo_rtc {
> - regulator-name = "vdd_rtc_out";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - temperature-sensor@4c {
> - compatible = "onnn,nct1008";
> - reg = <0x4c>;
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - sdhci@c8000600 {
> - cd-gpios = <&gpio 58 0>; /* gpio PH2 */
> - wp-gpios = <&gpio 59 0>; /* gpio PH3 */
> - bus-width = <4>;
> - status = "okay";
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> -
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v0_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsip b/arch/arm/boot/dts/tegra20-tamonten.dtsip
> new file mode 100644
> index 0000000..089bbec
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsip
> @@ -0,0 +1,489 @@
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "Avionic Design Tamonten SOM";
> + compatible = "ad,tamonten", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + host1x {
> + hdmi {
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata";
> + nvidia,function = "ide";
> + };
> + atb {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + };
> + atc {
> + nvidia,pins = "atc";
> + nvidia,function = "nand";
> + };
> + atd {
> + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
> + "spia", "spib", "spic";
> + nvidia,function = "gmi";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + dta {
> + nvidia,pins = "dta", "dtd";
> + nvidia,function = "sdio2";
> + };
> + dtb {
> + nvidia,pins = "dtb", "dtc", "dte";
> + nvidia,function = "rsvd1";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gmc {
> + nvidia,pins = "gmc";
> + nvidia,function = "uartd";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uarta";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> + "ld3", "ld4", "ld5", "ld6", "ld7",
> + "ld8", "ld9", "ld10", "ld11", "ld12",
> + "ld13", "ld14", "ld15", "ld16", "ld17",
> + "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> + "lhs", "lm0", "lm1", "lpp", "lpw0",
> + "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> + "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> + "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "spdi", "spdo", "uac";
> + nvidia,function = "rsvd2";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd";
> + nvidia,function = "pwm";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxc {
> + nvidia,pins = "slxc", "slxd";
> + nvidia,function = "spdif";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "atd", "ate",
> + "cdev1", "cdev2", "dap1", "dtb", "gma",
> + "gmb", "gmc", "gmd", "gme", "gpu7",
> + "gpv", "i2cp", "pta", "rm", "slxa",
> + "slxk", "spia", "spib", "uac";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_csus {
> + nvidia,pins = "csus", "spid", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp", "dap2", "dap3", "dap4",
> + "dtc", "dte", "dtf", "gpu", "sdio1",
> + "slxc", "slxd", "spdi", "spdo", "spig",
> + "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_ddc {
> + nvidia,pins = "ddc", "dta", "dtd", "kbca",
> + "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
> + "sdc";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> + "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> + "lvp0", "owc", "sdb";
> + nvidia,tristate = <1>;
> + };
> + conf_irrx {
> + nvidia,pins = "irrx", "irtx", "sdd", "spic",
> + "spie", "spih", "uaa", "uab", "uad",
> + "uca", "ucb";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lm0", "lpp",
> + "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> + "lvs", "pmc";
> + nvidia,tristate = <0>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + };
> +
> + state_i2cmux_ddc: pinmux_i2cmux_ddc {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> +
> + state_i2cmux_pta: pinmux_i2cmux_pta {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "i2c2";
> + };
> + };
> +
> + state_i2cmux_idle: pinmux_i2cmux_idle {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + clock-frequency = <400000>;
> + status = "okay";
> + };
> +
> + i2c@7000c400 {
> + clock-frequency = <100000>;
> + status = "okay";
> + };
> +
> + i2cmux {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c-parent = <&{/i2c@7000c400}>;
> +
> + pinctrl-names = "ddc", "pta", "idle";
> + pinctrl-0 = <&state_i2cmux_ddc>;
> + pinctrl-1 = <&state_i2cmux_pta>;
> + pinctrl-2 = <&state_i2cmux_idle>;
> +
> + hdmi_ddc: i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + i2c@7000d000 {
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&vdd_5v0_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + sys_reg: sys {
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + sm0 {
> + regulator-name = "vdd_sys_sm0,vdd_core";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + sm1 {
> + regulator-name = "vdd_sys_sm1,vdd_cpu";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: sm2 {
> + regulator-name = "vdd_sys_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + ldo0 {
> + regulator-name = "vdd_ldo0,vddio_pex_clk";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo1 {
> + regulator-name = "vdd_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "vdd_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo3 {
> + regulator-name = "vdd_ldo3,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "vdd_ldo5,vcore_mmc";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + };
> +
> + ldo6 {
> + regulator-name = "vdd_ldo6,avdd_vdac";
> + /*
> + * According to the Tegra 2 Automotive
> + * DataSheet, a typical value for this
> + * would be 2.8V, but the PMIC only
> + * supports 2.85V.
> + */
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + };
> +
> + hdmi_vdd_reg: ldo7 {
> + regulator-name = "vdd_ldo7,avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: ldo8 {
> + regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo9 {
> + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
> + /*
> + * According to the Tegra 2 Automotive
> + * DataSheet, a typical value for this
> + * would be 2.8V, but the PMIC only
> + * supports 2.85V.
> + */
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo_rtc {
> + regulator-name = "vdd_rtc_out";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + temperature-sensor@4c {
> + compatible = "onnn,nct1008";
> + reg = <0x4c>;
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + sdhci@c8000600 {
> + cd-gpios = <&gpio 58 0>; /* gpio PH2 */
> + wp-gpios = <&gpio 59 0>; /* gpio PH3 */
> + bus-width = <4>;
> + status = "okay";
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v0_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
> deleted file mode 100644
> index 402b210..0000000
> --- a/arch/arm/boot/dts/tegra20-tec.dts
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20-tamonten.dtsi"
> -
> -/ {
> - model = "Avionic Design Tamonten Evaluation Carrier";
> - compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
> -
> - host1x {
> - hdmi {
> - status = "okay";
> - };
> - };
> -
> - i2c@7000c000 {
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff
> - 0xffffffff
> - 0
> - 0xffffffff
> - 0xffffffff>;
> - };
> - };
> -
> - sound {
> - compatible = "ad,tegra-audio-wm8903-tec",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "Avionic Design TEC";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-tec.dtsp b/arch/arm/boot/dts/tegra20-tec.dtsp
> new file mode 100644
> index 0000000..331c81a
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-tec.dtsp
> @@ -0,0 +1,56 @@
> +/dts-v1/;
> +
> +#include "tegra20-tamonten.dtsip"
> +
> +/ {
> + model = "Avionic Design Tamonten Evaluation Carrier";
> + compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
> +
> + host1x {
> + hdmi {
> + status = "okay";
> + };
> + };
> +
> + i2c@7000c000 {
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff
> + 0xffffffff
> + 0
> + 0xffffffff
> + 0xffffffff>;
> + };
> + };
> +
> + sound {
> + compatible = "ad,tegra-audio-wm8903-tec",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "Avionic Design TEC";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
> deleted file mode 100644
> index 5d79e4f..0000000
> --- a/arch/arm/boot/dts/tegra20-trimslice.dts
> +++ /dev/null
> @@ -1,367 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "Compulab TrimSlice board";
> - compatible = "compulab,trimslice", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x40000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata";
> - nvidia,function = "ide";
> - };
> - atb {
> - nvidia,pins = "atb", "gma";
> - nvidia,function = "sdio4";
> - };
> - atc {
> - nvidia,pins = "atc", "gmb";
> - nvidia,function = "nand";
> - };
> - atd {
> - nvidia,pins = "atd", "ate", "gme", "pta";
> - nvidia,function = "gmi";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> - nvidia,function = "vi";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gmc {
> - nvidia,pins = "gmc", "gmd";
> - nvidia,function = "sflash";
> - };
> - gpu {
> - nvidia,pins = "gpu";
> - nvidia,function = "uarta";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uartb";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> - "ld3", "ld4", "ld5", "ld6", "ld7",
> - "ld8", "ld9", "ld10", "ld11", "ld12",
> - "ld13", "ld14", "ld15", "ld16", "ld17",
> - "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> - "lhs", "lm0", "lm1", "lpp", "lpw0",
> - "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> - "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> - "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "uac";
> - nvidia,function = "rsvd2";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd";
> - nvidia,function = "pwm";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxc {
> - nvidia,pins = "slxc", "slxd";
> - nvidia,function = "sdio3";
> - };
> - spdi {
> - nvidia,pins = "spdi", "spdo";
> - nvidia,function = "spdif";
> - };
> - spia {
> - nvidia,pins = "spia", "spib", "spic";
> - nvidia,function = "spi2";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atc", "atd", "ate",
> - "crtp", "dap2", "dap3", "dap4", "dta",
> - "dtb", "dtc", "dtd", "dte", "gmb",
> - "gme", "i2cp", "pta", "slxc", "slxd",
> - "spdi", "spdo", "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_atb {
> - nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
> - "gma", "gmc", "gmd", "gpu", "gpu7",
> - "gpv", "sdio1", "slxa", "slxk", "uac";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_csus {
> - nvidia,pins = "csus", "spia", "spib",
> - "spid", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_ddc {
> - nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> - "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> - "lvp0", "pmc";
> - nvidia,tristate = <1>;
> - };
> - conf_irrx {
> - nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
> - "kbcc", "kbcd", "kbce", "kbcf", "owc",
> - "spic", "spie", "spig", "spih", "uaa",
> - "uab", "uad", "uca", "ucb";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lm0", "lpp",
> - "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> - "lvs", "sdb";
> - nvidia,tristate = <0>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - conf_spif {
> - nvidia,pins = "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <0>;
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - dvi_ddc: i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - spi@7000c380 {
> - status = "okay";
> - spi-max-frequency = <48000000>;
> - spi-flash@0 {
> - compatible = "winbond,w25q80bl";
> - reg = <0>;
> - spi-max-frequency = <48000000>;
> - };
> - };
> -
> - hdmi_ddc: i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - codec: codec@1a {
> - compatible = "ti,tlv320aic23";
> - reg = <0x1a>;
> - };
> -
> - rtc@56 {
> - compatible = "emmicro,em3027";
> - reg = <0x56>;
> - };
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - usb-phy@c5004400 {
> - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> - };
> -
> - sdhci@c8000000 {
> - status = "okay";
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - cd-gpios = <&gpio 121 0>; /* gpio PP1 */
> - wp-gpios = <&gpio 122 0>; /* gpio PP2 */
> - bus-width = <4>;
> - };
> -
> - poweroff {
> - compatible = "gpio-poweroff";
> - gpios = <&gpio 191 1>; /* gpio PX7, active low */
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - hdmi_vdd_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - hdmi_pll_reg: regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-trimslice";
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&codec>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-trimslice.dtsp b/arch/arm/boot/dts/tegra20-trimslice.dtsp
> new file mode 100644
> index 0000000..1f6cd20
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-trimslice.dtsp
> @@ -0,0 +1,367 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "Compulab TrimSlice board";
> + compatible = "compulab,trimslice", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x40000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata";
> + nvidia,function = "ide";
> + };
> + atb {
> + nvidia,pins = "atb", "gma";
> + nvidia,function = "sdio4";
> + };
> + atc {
> + nvidia,pins = "atc", "gmb";
> + nvidia,function = "nand";
> + };
> + atd {
> + nvidia,pins = "atd", "ate", "gme", "pta";
> + nvidia,function = "gmi";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> + nvidia,function = "vi";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gmc {
> + nvidia,pins = "gmc", "gmd";
> + nvidia,function = "sflash";
> + };
> + gpu {
> + nvidia,pins = "gpu";
> + nvidia,function = "uarta";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uartb";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
> + "ld3", "ld4", "ld5", "ld6", "ld7",
> + "ld8", "ld9", "ld10", "ld11", "ld12",
> + "ld13", "ld14", "ld15", "ld16", "ld17",
> + "ldc", "ldi", "lhp0", "lhp1", "lhp2",
> + "lhs", "lm0", "lm1", "lpp", "lpw0",
> + "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
> + "lsda", "lsdi", "lspi", "lvp0", "lvp1",
> + "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "uac";
> + nvidia,function = "rsvd2";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd";
> + nvidia,function = "pwm";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxc {
> + nvidia,pins = "slxc", "slxd";
> + nvidia,function = "sdio3";
> + };
> + spdi {
> + nvidia,pins = "spdi", "spdo";
> + nvidia,function = "spdif";
> + };
> + spia {
> + nvidia,pins = "spia", "spib", "spic";
> + nvidia,function = "spi2";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atc", "atd", "ate",
> + "crtp", "dap2", "dap3", "dap4", "dta",
> + "dtb", "dtc", "dtd", "dte", "gmb",
> + "gme", "i2cp", "pta", "slxc", "slxd",
> + "spdi", "spdo", "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_atb {
> + nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
> + "gma", "gmc", "gmd", "gpu", "gpu7",
> + "gpv", "sdio1", "slxa", "slxk", "uac";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_csus {
> + nvidia,pins = "csus", "spia", "spib",
> + "spid", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_ddc {
> + nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> + "lpw1", "lsc1", "lsck", "lsda", "lsdi",
> + "lvp0", "pmc";
> + nvidia,tristate = <1>;
> + };
> + conf_irrx {
> + nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
> + "kbcc", "kbcd", "kbce", "kbcf", "owc",
> + "spic", "spie", "spig", "spih", "uaa",
> + "uab", "uad", "uca", "ucb";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lm0", "lpp",
> + "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
> + "lvs", "sdb";
> + nvidia,tristate = <0>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + conf_spif {
> + nvidia,pins = "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <0>;
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + dvi_ddc: i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + spi@7000c380 {
> + status = "okay";
> + spi-max-frequency = <48000000>;
> + spi-flash@0 {
> + compatible = "winbond,w25q80bl";
> + reg = <0>;
> + spi-max-frequency = <48000000>;
> + };
> + };
> +
> + hdmi_ddc: i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + codec: codec@1a {
> + compatible = "ti,tlv320aic23";
> + reg = <0x1a>;
> + };
> +
> + rtc@56 {
> + compatible = "emmicro,em3027";
> + reg = <0x56>;
> + };
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + usb-phy@c5004400 {
> + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
> + };
> +
> + sdhci@c8000000 {
> + status = "okay";
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + cd-gpios = <&gpio 121 0>; /* gpio PP1 */
> + wp-gpios = <&gpio 122 0>; /* gpio PP2 */
> + bus-width = <4>;
> + };
> +
> + poweroff {
> + compatible = "gpio-poweroff";
> + gpios = <&gpio 191 1>; /* gpio PX7, active low */
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi_vdd_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + hdmi_pll_reg: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-trimslice";
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&codec>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
> deleted file mode 100644
> index 425c890..0000000
> --- a/arch/arm/boot/dts/tegra20-ventana.dts
> +++ /dev/null
> @@ -1,611 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra20 Ventana evaluation board";
> - compatible = "nvidia,ventana", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x40000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata";
> - nvidia,function = "ide";
> - };
> - atb {
> - nvidia,pins = "atb", "gma", "gme";
> - nvidia,function = "sdio4";
> - };
> - atc {
> - nvidia,pins = "atc";
> - nvidia,function = "nand";
> - };
> - atd {
> - nvidia,pins = "atd", "ate", "gmb", "spia",
> - "spib", "spic";
> - nvidia,function = "gmi";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "pllp_out4";
> - };
> - crtp {
> - nvidia,pins = "crtp", "lm1";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> - nvidia,function = "vi";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gmc {
> - nvidia,pins = "gmc";
> - nvidia,function = "uartd";
> - };
> - gmd {
> - nvidia,pins = "gmd";
> - nvidia,function = "sflash";
> - };
> - gpu {
> - nvidia,pins = "gpu";
> - nvidia,function = "pwm";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv", "slxa", "slxk";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uartb";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
> - "lsdi", "lvp0";
> - nvidia,function = "rsvd4";
> - };
> - ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lpp", "lpw0",
> - "lpw2", "lsc0", "lsc1", "lsck", "lsda",
> - "lspi", "lvp1", "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "spdi", "spdo", "uac";
> - nvidia,function = "rsvd2";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd", "slxc";
> - nvidia,function = "sdio3";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - slxd {
> - nvidia,pins = "slxd";
> - nvidia,function = "spdif";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spif";
> - nvidia,function = "spi1";
> - };
> - spig {
> - nvidia,pins = "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab", "uda";
> - nvidia,function = "ulpi";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "atd",
> - "cdev1", "cdev2", "dap1", "dap2",
> - "dap4", "ddc", "dtf", "gma", "gmc",
> - "gme", "gpu", "gpu7", "i2cp", "irrx",
> - "irtx", "pta", "rm", "sdc", "sdd",
> - "slxc", "slxd", "slxk", "spdi", "spdo",
> - "uac", "uad", "uca", "ucb", "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_ate {
> - nvidia,pins = "ate", "csus", "dap3", "gmd",
> - "gpv", "owc", "spia", "spib", "spic",
> - "spid", "spie", "spig";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> - "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp", "gmb", "slxa", "spih";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd";
> - nvidia,pull = <1>;
> - nvidia,tristate = <0>;
> - };
> - conf_dte {
> - nvidia,pins = "dte", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_hdint {
> - nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> - "lpw1", "lsck", "lsda", "lsdi", "lvp0";
> - nvidia,tristate = <1>;
> - };
> - conf_kbca {
> - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> - "kbce", "kbcf", "sdio1", "uaa", "uab";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_lc {
> - nvidia,pins = "lc", "ls";
> - nvidia,pull = <2>;
> - };
> - conf_ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldi", "lhp0",
> - "lhp1", "lhp2", "lhs", "lm0", "lpp",
> - "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
> - "lvp1", "lvs", "pmc", "sdb";
> - nvidia,tristate = <0>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - drive_sdio1 {
> - nvidia,pins = "drive_sdio1";
> - nvidia,high-speed-mode = <0>;
> - nvidia,schmitt = <1>;
> - nvidia,low-power-mode = <3>;
> - nvidia,pull-down-strength = <31>;
> - nvidia,pull-up-strength = <31>;
> - nvidia,slew-rate-rising = <3>;
> - nvidia,slew-rate-falling = <3>;
> - };
> - };
> -
> - state_i2cmux_ddc: pinmux_i2cmux_ddc {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> -
> - state_i2cmux_pta: pinmux_i2cmux_pta {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "i2c2";
> - };
> - };
> -
> - state_i2cmux_idle: pinmux_i2cmux_idle {
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "rsvd4";
> - };
> - pta {
> - nvidia,pins = "pta";
> - nvidia,function = "rsvd4";
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006300 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <187 0x04>;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> - };
> -
> - /* ALS and proximity sensor */
> - isl29018@44 {
> - compatible = "isil,isl29018";
> - reg = <0x44>;
> - interrupt-parent = <&gpio>;
> - interrupts = <202 0x04>; /*gpio PZ2 */
> - };
> - };
> -
> - i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2cmux {
> - compatible = "i2c-mux-pinctrl";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - i2c-parent = <&{/i2c@7000c400}>;
> -
> - pinctrl-names = "ddc", "pta", "idle";
> - pinctrl-0 = <&state_i2cmux_ddc>;
> - pinctrl-1 = <&state_i2cmux_pta>;
> - pinctrl-2 = <&state_i2cmux_idle>;
> -
> - hdmi_ddc: i2c@0 {
> - reg = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c@1 {
> - reg = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <400000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <400000>;
> -
> - pmic: tps6586x@34 {
> - compatible = "ti,tps6586x";
> - reg = <0x34>;
> - interrupts = <0 86 0x4>;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - sys-supply = <&vdd_5v0_reg>;
> - vin-sm0-supply = <&sys_reg>;
> - vin-sm1-supply = <&sys_reg>;
> - vin-sm2-supply = <&sys_reg>;
> - vinldo01-supply = <&sm2_reg>;
> - vinldo23-supply = <&sm2_reg>;
> - vinldo4-supply = <&sm2_reg>;
> - vinldo678-supply = <&sm2_reg>;
> - vinldo9-supply = <&sm2_reg>;
> -
> - regulators {
> - sys_reg: sys {
> - regulator-name = "vdd_sys";
> - regulator-always-on;
> - };
> -
> - sm0 {
> - regulator-name = "vdd_sm0,vdd_core";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - sm1 {
> - regulator-name = "vdd_sm1,vdd_cpu";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - sm2_reg: sm2 {
> - regulator-name = "vdd_sm2,vin_ldo*";
> - regulator-min-microvolt = <3700000>;
> - regulator-max-microvolt = <3700000>;
> - regulator-always-on;
> - };
> -
> - /* LDO0 is not connected to anything */
> -
> - ldo1 {
> - regulator-name = "vdd_ldo1,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "vdd_ldo2,vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo3 {
> - regulator-name = "vdd_ldo3,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "vdd_ldo5,vcore_mmc";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo6 {
> - regulator-name = "vdd_ldo6,avdd_vdac";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - hdmi_vdd_reg: ldo7 {
> - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - hdmi_pll_reg: ldo8 {
> - regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo9 {
> - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> - regulator-min-microvolt = <2850000>;
> - regulator-max-microvolt = <2850000>;
> - regulator-always-on;
> - };
> -
> - ldo_rtc {
> - regulator-name = "vdd_rtc_out,vdd_cell";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> - };
> - };
> -
> - temperature-sensor@4c {
> - compatible = "onnn,nct1008";
> - reg = <0x4c>;
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - };
> -
> - usb@c5004000 {
> - status = "okay";
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - };
> -
> - usb-phy@c5004400 {
> - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> - };
> -
> - sdhci@c8000000 {
> - status = "okay";
> - power-gpios = <&gpio 86 0>; /* gpio PK6 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000400 {
> - status = "okay";
> - cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> - wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> - power-gpios = <&gpio 70 0>; /* gpio PI6 */
> - bus-width = <4>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v0_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "vdd_1v5";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - gpio = <&pmic 0 0>;
> - };
> -
> - regulator@2 {
> - compatible = "regulator-fixed";
> - reg = <2>;
> - regulator-name = "vdd_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - gpio = <&pmic 1 0>;
> - enable-active-high;
> - };
> -
> - regulator@3 {
> - compatible = "regulator-fixed";
> - reg = <3>;
> - regulator-name = "vdd_pnl";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - gpio = <&gpio 22 0>; /* gpio PC6 */
> - enable-active-high;
> - };
> -
> - regulator@4 {
> - compatible = "regulator-fixed";
> - reg = <4>;
> - regulator-name = "vdd_bl";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - gpio = <&gpio 176 0>; /* gpio PW0 */
> - enable-active-high;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm8903-ventana",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "NVIDIA Tegra Ventana";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
> - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-ventana.dtsp b/arch/arm/boot/dts/tegra20-ventana.dtsp
> new file mode 100644
> index 0000000..a5ae217
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-ventana.dtsp
> @@ -0,0 +1,611 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra20 Ventana evaluation board";
> + compatible = "nvidia,ventana", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x40000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata";
> + nvidia,function = "ide";
> + };
> + atb {
> + nvidia,pins = "atb", "gma", "gme";
> + nvidia,function = "sdio4";
> + };
> + atc {
> + nvidia,pins = "atc";
> + nvidia,function = "nand";
> + };
> + atd {
> + nvidia,pins = "atd", "ate", "gmb", "spia",
> + "spib", "spic";
> + nvidia,function = "gmi";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "pllp_out4";
> + };
> + crtp {
> + nvidia,pins = "crtp", "lm1";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
> + nvidia,function = "vi";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gmc {
> + nvidia,pins = "gmc";
> + nvidia,function = "uartd";
> + };
> + gmd {
> + nvidia,pins = "gmd";
> + nvidia,function = "sflash";
> + };
> + gpu {
> + nvidia,pins = "gpu";
> + nvidia,function = "pwm";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv", "slxa", "slxk";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uartb";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
> + "lsdi", "lvp0";
> + nvidia,function = "rsvd4";
> + };
> + ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lpp", "lpw0",
> + "lpw2", "lsc0", "lsc1", "lsck", "lsda",
> + "lspi", "lvp1", "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "spdi", "spdo", "uac";
> + nvidia,function = "rsvd2";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd", "slxc";
> + nvidia,function = "sdio3";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + slxd {
> + nvidia,pins = "slxd";
> + nvidia,function = "spdif";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spif";
> + nvidia,function = "spi1";
> + };
> + spig {
> + nvidia,pins = "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab", "uda";
> + nvidia,function = "ulpi";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "atd",
> + "cdev1", "cdev2", "dap1", "dap2",
> + "dap4", "ddc", "dtf", "gma", "gmc",
> + "gme", "gpu", "gpu7", "i2cp", "irrx",
> + "irtx", "pta", "rm", "sdc", "sdd",
> + "slxc", "slxd", "slxk", "spdi", "spdo",
> + "uac", "uad", "uca", "ucb", "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_ate {
> + nvidia,pins = "ate", "csus", "dap3", "gmd",
> + "gpv", "owc", "spia", "spib", "spic",
> + "spid", "spie", "spig";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
> + "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp", "gmb", "slxa", "spih";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd";
> + nvidia,pull = <1>;
> + nvidia,tristate = <0>;
> + };
> + conf_dte {
> + nvidia,pins = "dte", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_hdint {
> + nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
> + "lpw1", "lsck", "lsda", "lsdi", "lvp0";
> + nvidia,tristate = <1>;
> + };
> + conf_kbca {
> + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
> + "kbce", "kbcf", "sdio1", "uaa", "uab";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_lc {
> + nvidia,pins = "lc", "ls";
> + nvidia,pull = <2>;
> + };
> + conf_ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldi", "lhp0",
> + "lhp1", "lhp2", "lhs", "lm0", "lpp",
> + "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
> + "lvp1", "lvs", "pmc", "sdb";
> + nvidia,tristate = <0>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + drive_sdio1 {
> + nvidia,pins = "drive_sdio1";
> + nvidia,high-speed-mode = <0>;
> + nvidia,schmitt = <1>;
> + nvidia,low-power-mode = <3>;
> + nvidia,pull-down-strength = <31>;
> + nvidia,pull-up-strength = <31>;
> + nvidia,slew-rate-rising = <3>;
> + nvidia,slew-rate-falling = <3>;
> + };
> + };
> +
> + state_i2cmux_ddc: pinmux_i2cmux_ddc {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> +
> + state_i2cmux_pta: pinmux_i2cmux_pta {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "i2c2";
> + };
> + };
> +
> + state_i2cmux_idle: pinmux_i2cmux_idle {
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "rsvd4";
> + };
> + pta {
> + nvidia,pins = "pta";
> + nvidia,function = "rsvd4";
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006300 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <187 0x04>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> + };
> +
> + /* ALS and proximity sensor */
> + isl29018@44 {
> + compatible = "isil,isl29018";
> + reg = <0x44>;
> + interrupt-parent = <&gpio>;
> + interrupts = <202 0x04>; /*gpio PZ2 */
> + };
> + };
> +
> + i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2cmux {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c-parent = <&{/i2c@7000c400}>;
> +
> + pinctrl-names = "ddc", "pta", "idle";
> + pinctrl-0 = <&state_i2cmux_ddc>;
> + pinctrl-1 = <&state_i2cmux_pta>;
> + pinctrl-2 = <&state_i2cmux_idle>;
> +
> + hdmi_ddc: i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: tps6586x@34 {
> + compatible = "ti,tps6586x";
> + reg = <0x34>;
> + interrupts = <0 86 0x4>;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + sys-supply = <&vdd_5v0_reg>;
> + vin-sm0-supply = <&sys_reg>;
> + vin-sm1-supply = <&sys_reg>;
> + vin-sm2-supply = <&sys_reg>;
> + vinldo01-supply = <&sm2_reg>;
> + vinldo23-supply = <&sm2_reg>;
> + vinldo4-supply = <&sm2_reg>;
> + vinldo678-supply = <&sm2_reg>;
> + vinldo9-supply = <&sm2_reg>;
> +
> + regulators {
> + sys_reg: sys {
> + regulator-name = "vdd_sys";
> + regulator-always-on;
> + };
> +
> + sm0 {
> + regulator-name = "vdd_sm0,vdd_core";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + sm1 {
> + regulator-name = "vdd_sm1,vdd_cpu";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + sm2_reg: sm2 {
> + regulator-name = "vdd_sm2,vin_ldo*";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + regulator-always-on;
> + };
> +
> + /* LDO0 is not connected to anything */
> +
> + ldo1 {
> + regulator-name = "vdd_ldo1,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "vdd_ldo2,vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo3 {
> + regulator-name = "vdd_ldo3,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "vdd_ldo5,vcore_mmc";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo6 {
> + regulator-name = "vdd_ldo6,avdd_vdac";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + hdmi_vdd_reg: ldo7 {
> + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + hdmi_pll_reg: ldo8 {
> + regulator-name = "vdd_ldo8,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo9 {
> + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + regulator-always-on;
> + };
> +
> + ldo_rtc {
> + regulator-name = "vdd_rtc_out,vdd_cell";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + temperature-sensor@4c {
> + compatible = "onnn,nct1008";
> + reg = <0x4c>;
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + };
> +
> + usb@c5004000 {
> + status = "okay";
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + };
> +
> + usb-phy@c5004400 {
> + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
> + };
> +
> + sdhci@c8000000 {
> + status = "okay";
> + power-gpios = <&gpio 86 0>; /* gpio PK6 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000400 {
> + status = "okay";
> + cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> + wp-gpios = <&gpio 57 0>; /* gpio PH1 */
> + power-gpios = <&gpio 70 0>; /* gpio PI6 */
> + bus-width = <4>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v0_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "vdd_1v5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&pmic 0 0>;
> + };
> +
> + regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "vdd_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&pmic 1 0>;
> + enable-active-high;
> + };
> +
> + regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "vdd_pnl";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + gpio = <&gpio 22 0>; /* gpio PC6 */
> + enable-active-high;
> + };
> +
> + regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "vdd_bl";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + gpio = <&gpio 176 0>; /* gpio PW0 */
> + enable-active-high;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm8903-ventana",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "NVIDIA Tegra Ventana";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
> + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
> deleted file mode 100644
> index ea57c0f..0000000
> --- a/arch/arm/boot/dts/tegra20-whistler.dts
> +++ /dev/null
> @@ -1,563 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra20.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra20 Whistler evaluation board";
> - compatible = "nvidia,whistler", "nvidia,tegra20";
> -
> - memory {
> - reg = <0x00000000 0x20000000>;
> - };
> -
> - host1x {
> - hdmi {
> - status = "okay";
> -
> - vdd-supply = <&hdmi_vdd_reg>;
> - pll-supply = <&hdmi_pll_reg>;
> -
> - nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> - };
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - ata {
> - nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
> - "gmc", "gmd", "gpu";
> - nvidia,function = "gmi";
> - };
> - atc {
> - nvidia,pins = "atc", "atd";
> - nvidia,function = "sdio4";
> - };
> - cdev1 {
> - nvidia,pins = "cdev1";
> - nvidia,function = "plla_out";
> - };
> - cdev2 {
> - nvidia,pins = "cdev2";
> - nvidia,function = "osc";
> - };
> - crtp {
> - nvidia,pins = "crtp";
> - nvidia,function = "crt";
> - };
> - csus {
> - nvidia,pins = "csus";
> - nvidia,function = "vi_sensor_clk";
> - };
> - dap1 {
> - nvidia,pins = "dap1";
> - nvidia,function = "dap1";
> - };
> - dap2 {
> - nvidia,pins = "dap2";
> - nvidia,function = "dap2";
> - };
> - dap3 {
> - nvidia,pins = "dap3";
> - nvidia,function = "dap3";
> - };
> - dap4 {
> - nvidia,pins = "dap4";
> - nvidia,function = "dap4";
> - };
> - ddc {
> - nvidia,pins = "ddc";
> - nvidia,function = "i2c2";
> - };
> - dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd";
> - nvidia,function = "vi";
> - };
> - dte {
> - nvidia,pins = "dte";
> - nvidia,function = "rsvd1";
> - };
> - dtf {
> - nvidia,pins = "dtf";
> - nvidia,function = "i2c3";
> - };
> - gme {
> - nvidia,pins = "gme";
> - nvidia,function = "dap5";
> - };
> - gpu7 {
> - nvidia,pins = "gpu7";
> - nvidia,function = "rtck";
> - };
> - gpv {
> - nvidia,pins = "gpv";
> - nvidia,function = "pcie";
> - };
> - hdint {
> - nvidia,pins = "hdint", "pta";
> - nvidia,function = "hdmi";
> - };
> - i2cp {
> - nvidia,pins = "i2cp";
> - nvidia,function = "i2cp";
> - };
> - irrx {
> - nvidia,pins = "irrx", "irtx";
> - nvidia,function = "uartb";
> - };
> - kbca {
> - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
> - nvidia,function = "kbc";
> - };
> - kbcb {
> - nvidia,pins = "kbcb", "kbcd";
> - nvidia,function = "sdio2";
> - };
> - lcsn {
> - nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
> - "spia", "spib", "spic";
> - nvidia,function = "spi3";
> - };
> - ld0 {
> - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> - "ld5", "ld6", "ld7", "ld8", "ld9",
> - "ld10", "ld11", "ld12", "ld13", "ld14",
> - "ld15", "ld16", "ld17", "ldc", "ldi",
> - "lhp0", "lhp1", "lhp2", "lhs", "lm0",
> - "lm1", "lpp", "lpw0", "lpw1", "lpw2",
> - "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
> - "lvs";
> - nvidia,function = "displaya";
> - };
> - owc {
> - nvidia,pins = "owc", "uac";
> - nvidia,function = "owr";
> - };
> - pmc {
> - nvidia,pins = "pmc";
> - nvidia,function = "pwr_on";
> - };
> - rm {
> - nvidia,pins = "rm";
> - nvidia,function = "i2c1";
> - };
> - sdb {
> - nvidia,pins = "sdb", "sdc", "sdd", "slxa",
> - "slxc", "slxd", "slxk";
> - nvidia,function = "sdio3";
> - };
> - sdio1 {
> - nvidia,pins = "sdio1";
> - nvidia,function = "sdio1";
> - };
> - spdi {
> - nvidia,pins = "spdi", "spdo";
> - nvidia,function = "rsvd2";
> - };
> - spid {
> - nvidia,pins = "spid", "spie", "spig", "spih";
> - nvidia,function = "spi2_alt";
> - };
> - spif {
> - nvidia,pins = "spif";
> - nvidia,function = "spi2";
> - };
> - uaa {
> - nvidia,pins = "uaa", "uab";
> - nvidia,function = "uarta";
> - };
> - uad {
> - nvidia,pins = "uad";
> - nvidia,function = "irda";
> - };
> - uca {
> - nvidia,pins = "uca", "ucb";
> - nvidia,function = "uartc";
> - };
> - uda {
> - nvidia,pins = "uda";
> - nvidia,function = "spi1";
> - };
> - conf_ata {
> - nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
> - "gmb", "gmc", "gmd", "irrx", "irtx",
> - "kbca", "kbcb", "kbcc", "kbcd", "kbce",
> - "kbcf", "sdc", "sdd", "spie", "spig",
> - "spih", "uaa", "uab", "uad", "uca",
> - "ucb";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - conf_atd {
> - nvidia,pins = "atd", "ate", "cdev1", "csus",
> - "dap1", "dap2", "dap3", "dap4", "dte",
> - "dtf", "gpu", "gpu7", "gpv", "i2cp",
> - "rm", "sdio1", "slxa", "slxc", "slxd",
> - "slxk", "spdi", "spdo", "uac", "uda";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - conf_cdev2 {
> - nvidia,pins = "cdev2", "spia", "spib";
> - nvidia,pull = <1>;
> - nvidia,tristate = <1>;
> - };
> - conf_ck32 {
> - nvidia,pins = "ck32", "ddrc", "lc", "pmca",
> - "pmcb", "pmcc", "pmcd", "xm2c",
> - "xm2d";
> - nvidia,pull = <0>;
> - };
> - conf_crtp {
> - nvidia,pins = "crtp";
> - nvidia,pull = <0>;
> - nvidia,tristate = <1>;
> - };
> - conf_dta {
> - nvidia,pins = "dta", "dtb", "dtc", "dtd",
> - "spid", "spif";
> - nvidia,pull = <1>;
> - nvidia,tristate = <0>;
> - };
> - conf_gme {
> - nvidia,pins = "gme", "owc", "pta", "spic";
> - nvidia,pull = <2>;
> - nvidia,tristate = <1>;
> - };
> - conf_ld17_0 {
> - nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> - "ld23_22";
> - nvidia,pull = <1>;
> - };
> - conf_ls {
> - nvidia,pins = "ls", "pmce";
> - nvidia,pull = <2>;
> - };
> - drive_dap1 {
> - nvidia,pins = "drive_dap1";
> - nvidia,high-speed-mode = <0>;
> - nvidia,schmitt = <1>;
> - nvidia,low-power-mode = <0>;
> - nvidia,pull-down-strength = <0>;
> - nvidia,pull-up-strength = <0>;
> - nvidia,slew-rate-rising = <0>;
> - nvidia,slew-rate-falling = <0>;
> - };
> - };
> - };
> -
> - i2s@70002800 {
> - status = "okay";
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - hdmi_ddc: i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <100000>;
> -
> - codec: codec@1a {
> - compatible = "wlf,wm8753";
> - reg = <0x1a>;
> - };
> -
> - tca6416: gpio@20 {
> - compatible = "ti,tca6416";
> - reg = <0x20>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - max8907@3c {
> - compatible = "maxim,max8907";
> - reg = <0x3c>;
> - interrupts = <0 86 0x4>;
> -
> - maxim,system-power-controller;
> -
> - mbatt-supply = <&usb0_vbus_reg>;
> - in-v1-supply = <&mbatt_reg>;
> - in-v2-supply = <&mbatt_reg>;
> - in-v3-supply = <&mbatt_reg>;
> - in1-supply = <&mbatt_reg>;
> - in2-supply = <&nvvdd_sv3_reg>;
> - in3-supply = <&mbatt_reg>;
> - in4-supply = <&mbatt_reg>;
> - in5-supply = <&mbatt_reg>;
> - in6-supply = <&mbatt_reg>;
> - in7-supply = <&mbatt_reg>;
> - in8-supply = <&mbatt_reg>;
> - in9-supply = <&mbatt_reg>;
> - in10-supply = <&mbatt_reg>;
> - in11-supply = <&mbatt_reg>;
> - in12-supply = <&mbatt_reg>;
> - in13-supply = <&mbatt_reg>;
> - in14-supply = <&mbatt_reg>;
> - in15-supply = <&mbatt_reg>;
> - in16-supply = <&mbatt_reg>;
> - in17-supply = <&nvvdd_sv3_reg>;
> - in18-supply = <&nvvdd_sv3_reg>;
> - in19-supply = <&mbatt_reg>;
> - in20-supply = <&mbatt_reg>;
> -
> - regulators {
> - mbatt_reg: mbatt {
> - regulator-name = "vbat_pmu";
> - regulator-always-on;
> - };
> -
> - sd1 {
> - regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - sd2 {
> - regulator-name = "nvvdd_sv2,vdd_core";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - nvvdd_sv3_reg: sd3 {
> - regulator-name = "nvvdd_sv3";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo1 {
> - regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo2 {
> - regulator-name = "nvvdd_ldo2,avdd_pll*";
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1100000>;
> - regulator-always-on;
> - };
> -
> - ldo3 {
> - regulator-name = "nvvdd_ldo3,vcom_1v8b";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo4 {
> - regulator-name = "nvvdd_ldo4,avdd_usb*";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo5 {
> - regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - hdmi_pll_reg: ldo6 {
> - regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo7 {
> - regulator-name = "nvvdd_ldo7,avddio_audio";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - ldo8 {
> - regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo9 {
> - regulator-name = "nvvdd_ldo9,avdd_cam*";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo10 {
> - regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-always-on;
> - };
> -
> - hdmi_vdd_reg: ldo11 {
> - regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo12 {
> - regulator-name = "nvvdd_ldo12,vddio_sdio";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - ldo13 {
> - regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo14 {
> - regulator-name = "nvvdd_ldo14,avdd_vdac";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo15 {
> - regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo16 {
> - regulator-name = "nvvdd_ldo16,vdd_dbrtr";
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1300000>;
> - };
> -
> - ldo17 {
> - regulator-name = "nvvdd_ldo17,vddio_mipi";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo18 {
> - regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo19 {
> - regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo20 {
> - regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - out5v {
> - regulator-name = "usb0_vbus_reg";
> - };
> -
> - out33v {
> - regulator-name = "pmu_out3v3";
> - };
> -
> - bbat {
> - regulator-name = "pmu_bbat";
> - regulator-min-microvolt = <2400000>;
> - regulator-max-microvolt = <2400000>;
> - regulator-always-on;
> - };
> -
> - sdby {
> - regulator-name = "vdd_aon";
> - regulator-always-on;
> - };
> -
> - vrtc {
> - regulator-name = "vrtc,pmu_vccadc";
> - regulator-always-on;
> - };
> - };
> - };
> - };
> -
> - pmc {
> - nvidia,invert-interrupt;
> - };
> -
> - usb@c5000000 {
> - status = "okay";
> - nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
> - };
> -
> - usb@c5008000 {
> - status = "okay";
> - nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
> - };
> -
> - sdhci@c8000400 {
> - status = "okay";
> - wp-gpios = <&gpio 173 0>; /* gpio PV5 */
> - bus-width = <8>;
> - };
> -
> - sdhci@c8000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - kbc {
> - status = "okay";
> - nvidia,debounce-delay-ms = <20>;
> - nvidia,repeat-delay-ms = <160>;
> - nvidia,kbc-row-pins = <0 1 2>;
> - nvidia,kbc-col-pins = <16 17>;
> - linux,keymap = <0x00000074 /* KEY_POWER */
> - 0x01000066 /* KEY_HOME */
> - 0x0101009E /* KEY_BACK */
> - 0x0201008B>; /* KEY_MENU */
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - usb0_vbus_reg: regulator {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "usb0_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm8753-whistler",
> - "nvidia,tegra-audio-wm8753";
> - nvidia,model = "NVIDIA Tegra Whistler";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "LOUT1",
> - "Headphone Jack", "ROUT1",
> - "MIC2", "Mic Jack",
> - "MIC2N", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&codec>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20-whistler.dtsp b/arch/arm/boot/dts/tegra20-whistler.dtsp
> new file mode 100644
> index 0000000..ee24daa
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20-whistler.dtsp
> @@ -0,0 +1,563 @@
> +/dts-v1/;
> +
> +#include "tegra20.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra20 Whistler evaluation board";
> + compatible = "nvidia,whistler", "nvidia,tegra20";
> +
> + memory {
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + host1x {
> + hdmi {
> + status = "okay";
> +
> + vdd-supply = <&hdmi_vdd_reg>;
> + pll-supply = <&hdmi_pll_reg>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
> + };
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + ata {
> + nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
> + "gmc", "gmd", "gpu";
> + nvidia,function = "gmi";
> + };
> + atc {
> + nvidia,pins = "atc", "atd";
> + nvidia,function = "sdio4";
> + };
> + cdev1 {
> + nvidia,pins = "cdev1";
> + nvidia,function = "plla_out";
> + };
> + cdev2 {
> + nvidia,pins = "cdev2";
> + nvidia,function = "osc";
> + };
> + crtp {
> + nvidia,pins = "crtp";
> + nvidia,function = "crt";
> + };
> + csus {
> + nvidia,pins = "csus";
> + nvidia,function = "vi_sensor_clk";
> + };
> + dap1 {
> + nvidia,pins = "dap1";
> + nvidia,function = "dap1";
> + };
> + dap2 {
> + nvidia,pins = "dap2";
> + nvidia,function = "dap2";
> + };
> + dap3 {
> + nvidia,pins = "dap3";
> + nvidia,function = "dap3";
> + };
> + dap4 {
> + nvidia,pins = "dap4";
> + nvidia,function = "dap4";
> + };
> + ddc {
> + nvidia,pins = "ddc";
> + nvidia,function = "i2c2";
> + };
> + dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd";
> + nvidia,function = "vi";
> + };
> + dte {
> + nvidia,pins = "dte";
> + nvidia,function = "rsvd1";
> + };
> + dtf {
> + nvidia,pins = "dtf";
> + nvidia,function = "i2c3";
> + };
> + gme {
> + nvidia,pins = "gme";
> + nvidia,function = "dap5";
> + };
> + gpu7 {
> + nvidia,pins = "gpu7";
> + nvidia,function = "rtck";
> + };
> + gpv {
> + nvidia,pins = "gpv";
> + nvidia,function = "pcie";
> + };
> + hdint {
> + nvidia,pins = "hdint", "pta";
> + nvidia,function = "hdmi";
> + };
> + i2cp {
> + nvidia,pins = "i2cp";
> + nvidia,function = "i2cp";
> + };
> + irrx {
> + nvidia,pins = "irrx", "irtx";
> + nvidia,function = "uartb";
> + };
> + kbca {
> + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
> + nvidia,function = "kbc";
> + };
> + kbcb {
> + nvidia,pins = "kbcb", "kbcd";
> + nvidia,function = "sdio2";
> + };
> + lcsn {
> + nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
> + "spia", "spib", "spic";
> + nvidia,function = "spi3";
> + };
> + ld0 {
> + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
> + "ld5", "ld6", "ld7", "ld8", "ld9",
> + "ld10", "ld11", "ld12", "ld13", "ld14",
> + "ld15", "ld16", "ld17", "ldc", "ldi",
> + "lhp0", "lhp1", "lhp2", "lhs", "lm0",
> + "lm1", "lpp", "lpw0", "lpw1", "lpw2",
> + "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
> + "lvs";
> + nvidia,function = "displaya";
> + };
> + owc {
> + nvidia,pins = "owc", "uac";
> + nvidia,function = "owr";
> + };
> + pmc {
> + nvidia,pins = "pmc";
> + nvidia,function = "pwr_on";
> + };
> + rm {
> + nvidia,pins = "rm";
> + nvidia,function = "i2c1";
> + };
> + sdb {
> + nvidia,pins = "sdb", "sdc", "sdd", "slxa",
> + "slxc", "slxd", "slxk";
> + nvidia,function = "sdio3";
> + };
> + sdio1 {
> + nvidia,pins = "sdio1";
> + nvidia,function = "sdio1";
> + };
> + spdi {
> + nvidia,pins = "spdi", "spdo";
> + nvidia,function = "rsvd2";
> + };
> + spid {
> + nvidia,pins = "spid", "spie", "spig", "spih";
> + nvidia,function = "spi2_alt";
> + };
> + spif {
> + nvidia,pins = "spif";
> + nvidia,function = "spi2";
> + };
> + uaa {
> + nvidia,pins = "uaa", "uab";
> + nvidia,function = "uarta";
> + };
> + uad {
> + nvidia,pins = "uad";
> + nvidia,function = "irda";
> + };
> + uca {
> + nvidia,pins = "uca", "ucb";
> + nvidia,function = "uartc";
> + };
> + uda {
> + nvidia,pins = "uda";
> + nvidia,function = "spi1";
> + };
> + conf_ata {
> + nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
> + "gmb", "gmc", "gmd", "irrx", "irtx",
> + "kbca", "kbcb", "kbcc", "kbcd", "kbce",
> + "kbcf", "sdc", "sdd", "spie", "spig",
> + "spih", "uaa", "uab", "uad", "uca",
> + "ucb";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + conf_atd {
> + nvidia,pins = "atd", "ate", "cdev1", "csus",
> + "dap1", "dap2", "dap3", "dap4", "dte",
> + "dtf", "gpu", "gpu7", "gpv", "i2cp",
> + "rm", "sdio1", "slxa", "slxc", "slxd",
> + "slxk", "spdi", "spdo", "uac", "uda";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + conf_cdev2 {
> + nvidia,pins = "cdev2", "spia", "spib";
> + nvidia,pull = <1>;
> + nvidia,tristate = <1>;
> + };
> + conf_ck32 {
> + nvidia,pins = "ck32", "ddrc", "lc", "pmca",
> + "pmcb", "pmcc", "pmcd", "xm2c",
> + "xm2d";
> + nvidia,pull = <0>;
> + };
> + conf_crtp {
> + nvidia,pins = "crtp";
> + nvidia,pull = <0>;
> + nvidia,tristate = <1>;
> + };
> + conf_dta {
> + nvidia,pins = "dta", "dtb", "dtc", "dtd",
> + "spid", "spif";
> + nvidia,pull = <1>;
> + nvidia,tristate = <0>;
> + };
> + conf_gme {
> + nvidia,pins = "gme", "owc", "pta", "spic";
> + nvidia,pull = <2>;
> + nvidia,tristate = <1>;
> + };
> + conf_ld17_0 {
> + nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
> + "ld23_22";
> + nvidia,pull = <1>;
> + };
> + conf_ls {
> + nvidia,pins = "ls", "pmce";
> + nvidia,pull = <2>;
> + };
> + drive_dap1 {
> + nvidia,pins = "drive_dap1";
> + nvidia,high-speed-mode = <0>;
> + nvidia,schmitt = <1>;
> + nvidia,low-power-mode = <0>;
> + nvidia,pull-down-strength = <0>;
> + nvidia,pull-up-strength = <0>;
> + nvidia,slew-rate-rising = <0>;
> + nvidia,slew-rate-falling = <0>;
> + };
> + };
> + };
> +
> + i2s@70002800 {
> + status = "okay";
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + hdmi_ddc: i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + codec: codec@1a {
> + compatible = "wlf,wm8753";
> + reg = <0x1a>;
> + };
> +
> + tca6416: gpio@20 {
> + compatible = "ti,tca6416";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + max8907@3c {
> + compatible = "maxim,max8907";
> + reg = <0x3c>;
> + interrupts = <0 86 0x4>;
> +
> + maxim,system-power-controller;
> +
> + mbatt-supply = <&usb0_vbus_reg>;
> + in-v1-supply = <&mbatt_reg>;
> + in-v2-supply = <&mbatt_reg>;
> + in-v3-supply = <&mbatt_reg>;
> + in1-supply = <&mbatt_reg>;
> + in2-supply = <&nvvdd_sv3_reg>;
> + in3-supply = <&mbatt_reg>;
> + in4-supply = <&mbatt_reg>;
> + in5-supply = <&mbatt_reg>;
> + in6-supply = <&mbatt_reg>;
> + in7-supply = <&mbatt_reg>;
> + in8-supply = <&mbatt_reg>;
> + in9-supply = <&mbatt_reg>;
> + in10-supply = <&mbatt_reg>;
> + in11-supply = <&mbatt_reg>;
> + in12-supply = <&mbatt_reg>;
> + in13-supply = <&mbatt_reg>;
> + in14-supply = <&mbatt_reg>;
> + in15-supply = <&mbatt_reg>;
> + in16-supply = <&mbatt_reg>;
> + in17-supply = <&nvvdd_sv3_reg>;
> + in18-supply = <&nvvdd_sv3_reg>;
> + in19-supply = <&mbatt_reg>;
> + in20-supply = <&mbatt_reg>;
> +
> + regulators {
> + mbatt_reg: mbatt {
> + regulator-name = "vbat_pmu";
> + regulator-always-on;
> + };
> +
> + sd1 {
> + regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + sd2 {
> + regulator-name = "nvvdd_sv2,vdd_core";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + nvvdd_sv3_reg: sd3 {
> + regulator-name = "nvvdd_sv3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo1 {
> + regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo2 {
> + regulator-name = "nvvdd_ldo2,avdd_pll*";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +
> + ldo3 {
> + regulator-name = "nvvdd_ldo3,vcom_1v8b";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4 {
> + regulator-name = "nvvdd_ldo4,avdd_usb*";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo5 {
> + regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + hdmi_pll_reg: ldo6 {
> + regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo7 {
> + regulator-name = "nvvdd_ldo7,avddio_audio";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo8 {
> + regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo9 {
> + regulator-name = "nvvdd_ldo9,avdd_cam*";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo10 {
> + regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + hdmi_vdd_reg: ldo11 {
> + regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo12 {
> + regulator-name = "nvvdd_ldo12,vddio_sdio";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo13 {
> + regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo14 {
> + regulator-name = "nvvdd_ldo14,avdd_vdac";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo15 {
> + regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo16 {
> + regulator-name = "nvvdd_ldo16,vdd_dbrtr";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + };
> +
> + ldo17 {
> + regulator-name = "nvvdd_ldo17,vddio_mipi";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo18 {
> + regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19 {
> + regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo20 {
> + regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + out5v {
> + regulator-name = "usb0_vbus_reg";
> + };
> +
> + out33v {
> + regulator-name = "pmu_out3v3";
> + };
> +
> + bbat {
> + regulator-name = "pmu_bbat";
> + regulator-min-microvolt = <2400000>;
> + regulator-max-microvolt = <2400000>;
> + regulator-always-on;
> + };
> +
> + sdby {
> + regulator-name = "vdd_aon";
> + regulator-always-on;
> + };
> +
> + vrtc {
> + regulator-name = "vrtc,pmu_vccadc";
> + regulator-always-on;
> + };
> + };
> + };
> + };
> +
> + pmc {
> + nvidia,invert-interrupt;
> + };
> +
> + usb@c5000000 {
> + status = "okay";
> + nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
> + };
> +
> + usb@c5008000 {
> + status = "okay";
> + nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
> + };
> +
> + sdhci@c8000400 {
> + status = "okay";
> + wp-gpios = <&gpio 173 0>; /* gpio PV5 */
> + bus-width = <8>;
> + };
> +
> + sdhci@c8000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + kbc {
> + status = "okay";
> + nvidia,debounce-delay-ms = <20>;
> + nvidia,repeat-delay-ms = <160>;
> + nvidia,kbc-row-pins = <0 1 2>;
> + nvidia,kbc-col-pins = <16 17>;
> + linux,keymap = <0x00000074 /* KEY_POWER */
> + 0x01000066 /* KEY_HOME */
> + 0x0101009E /* KEY_BACK */
> + 0x0201008B>; /* KEY_MENU */
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + usb0_vbus_reg: regulator {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "usb0_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm8753-whistler",
> + "nvidia,tegra-audio-wm8753";
> + nvidia,model = "NVIDIA Tegra Whistler";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "LOUT1",
> + "Headphone Jack", "ROUT1",
> + "MIC2", "Mic Jack",
> + "MIC2N", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&codec>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> deleted file mode 100644
> index 5916c93..0000000
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ /dev/null
> @@ -1,556 +0,0 @@
> -/include/ "skeleton.dtsi"
> -
> -/ {
> - compatible = "nvidia,tegra20";
> - interrupt-parent = <&intc>;
> -
> - aliases {
> - serial0 = &uarta;
> - serial1 = &uartb;
> - serial2 = &uartc;
> - serial3 = &uartd;
> - serial4 = &uarte;
> - };
> -
> - host1x {
> - compatible = "nvidia,tegra20-host1x", "simple-bus";
> - reg = <0x50000000 0x00024000>;
> - interrupts = <0 65 0x04 /* mpcore syncpt */
> - 0 67 0x04>; /* mpcore general */
> - clocks = <&tegra_car 28>;
> -
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - ranges = <0x54000000 0x54000000 0x04000000>;
> -
> - mpe {
> - compatible = "nvidia,tegra20-mpe";
> - reg = <0x54040000 0x00040000>;
> - interrupts = <0 68 0x04>;
> - clocks = <&tegra_car 60>;
> - };
> -
> - vi {
> - compatible = "nvidia,tegra20-vi";
> - reg = <0x54080000 0x00040000>;
> - interrupts = <0 69 0x04>;
> - clocks = <&tegra_car 100>;
> - };
> -
> - epp {
> - compatible = "nvidia,tegra20-epp";
> - reg = <0x540c0000 0x00040000>;
> - interrupts = <0 70 0x04>;
> - clocks = <&tegra_car 19>;
> - };
> -
> - isp {
> - compatible = "nvidia,tegra20-isp";
> - reg = <0x54100000 0x00040000>;
> - interrupts = <0 71 0x04>;
> - clocks = <&tegra_car 23>;
> - };
> -
> - gr2d {
> - compatible = "nvidia,tegra20-gr2d";
> - reg = <0x54140000 0x00040000>;
> - interrupts = <0 72 0x04>;
> - clocks = <&tegra_car 21>;
> - };
> -
> - gr3d {
> - compatible = "nvidia,tegra20-gr3d";
> - reg = <0x54180000 0x00040000>;
> - clocks = <&tegra_car 24>;
> - };
> -
> - dc@54200000 {
> - compatible = "nvidia,tegra20-dc";
> - reg = <0x54200000 0x00040000>;
> - interrupts = <0 73 0x04>;
> - clocks = <&tegra_car 27>, <&tegra_car 121>;
> - clock-names = "disp1", "parent";
> -
> - rgb {
> - status = "disabled";
> - };
> - };
> -
> - dc@54240000 {
> - compatible = "nvidia,tegra20-dc";
> - reg = <0x54240000 0x00040000>;
> - interrupts = <0 74 0x04>;
> - clocks = <&tegra_car 26>, <&tegra_car 121>;
> - clock-names = "disp2", "parent";
> -
> - rgb {
> - status = "disabled";
> - };
> - };
> -
> - hdmi {
> - compatible = "nvidia,tegra20-hdmi";
> - reg = <0x54280000 0x00040000>;
> - interrupts = <0 75 0x04>;
> - clocks = <&tegra_car 51>, <&tegra_car 117>;
> - clock-names = "hdmi", "parent";
> - status = "disabled";
> - };
> -
> - tvo {
> - compatible = "nvidia,tegra20-tvo";
> - reg = <0x542c0000 0x00040000>;
> - interrupts = <0 76 0x04>;
> - clocks = <&tegra_car 102>;
> - status = "disabled";
> - };
> -
> - dsi {
> - compatible = "nvidia,tegra20-dsi";
> - reg = <0x54300000 0x00040000>;
> - clocks = <&tegra_car 48>;
> - status = "disabled";
> - };
> - };
> -
> - timer@50004600 {
> - compatible = "arm,cortex-a9-twd-timer";
> - reg = <0x50040600 0x20>;
> - interrupts = <1 13 0x304>;
> - };
> -
> - intc: interrupt-controller {
> - compatible = "arm,cortex-a9-gic";
> - reg = <0x50041000 0x1000
> - 0x50040100 0x0100>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - };
> -
> - cache-controller {
> - compatible = "arm,pl310-cache";
> - reg = <0x50043000 0x1000>;
> - arm,data-latency = <5 5 2>;
> - arm,tag-latency = <4 4 2>;
> - cache-unified;
> - cache-level = <2>;
> - };
> -
> - timer@60005000 {
> - compatible = "nvidia,tegra20-timer";
> - reg = <0x60005000 0x60>;
> - interrupts = <0 0 0x04
> - 0 1 0x04
> - 0 41 0x04
> - 0 42 0x04>;
> - };
> -
> - tegra_car: clock {
> - compatible = "nvidia,tegra20-car";
> - reg = <0x60006000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - apbdma: dma {
> - compatible = "nvidia,tegra20-apbdma";
> - reg = <0x6000a000 0x1200>;
> - interrupts = <0 104 0x04
> - 0 105 0x04
> - 0 106 0x04
> - 0 107 0x04
> - 0 108 0x04
> - 0 109 0x04
> - 0 110 0x04
> - 0 111 0x04
> - 0 112 0x04
> - 0 113 0x04
> - 0 114 0x04
> - 0 115 0x04
> - 0 116 0x04
> - 0 117 0x04
> - 0 118 0x04
> - 0 119 0x04>;
> - clocks = <&tegra_car 34>;
> - };
> -
> - ahb {
> - compatible = "nvidia,tegra20-ahb";
> - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
> - };
> -
> - gpio: gpio {
> - compatible = "nvidia,tegra20-gpio";
> - reg = <0x6000d000 0x1000>;
> - interrupts = <0 32 0x04
> - 0 33 0x04
> - 0 34 0x04
> - 0 35 0x04
> - 0 55 0x04
> - 0 87 0x04
> - 0 89 0x04>;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - pinmux: pinmux {
> - compatible = "nvidia,tegra20-pinmux";
> - reg = <0x70000014 0x10 /* Tri-state registers */
> - 0x70000080 0x20 /* Mux registers */
> - 0x700000a0 0x14 /* Pull-up/down registers */
> - 0x70000868 0xa8>; /* Pad control registers */
> - };
> -
> - das {
> - compatible = "nvidia,tegra20-das";
> - reg = <0x70000c00 0x80>;
> - };
> -
> - tegra_ac97: ac97 {
> - compatible = "nvidia,tegra20-ac97";
> - reg = <0x70002000 0x200>;
> - interrupts = <0 81 0x04>;
> - nvidia,dma-request-selector = <&apbdma 12>;
> - clocks = <&tegra_car 3>;
> - status = "disabled";
> - };
> -
> - tegra_i2s1: i2s@70002800 {
> - compatible = "nvidia,tegra20-i2s";
> - reg = <0x70002800 0x200>;
> - interrupts = <0 13 0x04>;
> - nvidia,dma-request-selector = <&apbdma 2>;
> - clocks = <&tegra_car 11>;
> - status = "disabled";
> - };
> -
> - tegra_i2s2: i2s@70002a00 {
> - compatible = "nvidia,tegra20-i2s";
> - reg = <0x70002a00 0x200>;
> - interrupts = <0 3 0x04>;
> - nvidia,dma-request-selector = <&apbdma 1>;
> - clocks = <&tegra_car 18>;
> - status = "disabled";
> - };
> -
> - /*
> - * There are two serial driver i.e. 8250 based simple serial
> - * driver and APB DMA based serial driver for higher baudrate
> - * and performace. To enable the 8250 based driver, the compatible
> - * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
> - * driver, the comptible is "nvidia,tegra20-hsuart".
> - */
> - uarta: serial@70006000 {
> - compatible = "nvidia,tegra20-uart";
> - reg = <0x70006000 0x40>;
> - reg-shift = <2>;
> - interrupts = <0 36 0x04>;
> - clock-frequency = <216000000>;
> - nvidia,dma-request-selector = <&apbdma 8>;
> - clocks = <&tegra_car 6>;
> - status = "disabled";
> - };
> -
> - uartb: serial@70006040 {
> - compatible = "nvidia,tegra20-uart";
> - reg = <0x70006040 0x40>;
> - reg-shift = <2>;
> - interrupts = <0 37 0x04>;
> - clock-frequency = <216000000>;
> - nvidia,dma-request-selector = <&apbdma 9>;
> - clocks = <&tegra_car 96>;
> - status = "disabled";
> - };
> -
> - uartc: serial@70006200 {
> - compatible = "nvidia,tegra20-uart";
> - reg = <0x70006200 0x100>;
> - reg-shift = <2>;
> - interrupts = <0 46 0x04>;
> - clock-frequency = <216000000>;
> - nvidia,dma-request-selector = <&apbdma 10>;
> - clocks = <&tegra_car 55>;
> - status = "disabled";
> - };
> -
> - uartd: serial@70006300 {
> - compatible = "nvidia,tegra20-uart";
> - reg = <0x70006300 0x100>;
> - reg-shift = <2>;
> - interrupts = <0 90 0x04>;
> - clock-frequency = <216000000>;
> - nvidia,dma-request-selector = <&apbdma 19>;
> - clocks = <&tegra_car 65>;
> - status = "disabled";
> - };
> -
> - uarte: serial@70006400 {
> - compatible = "nvidia,tegra20-uart";
> - reg = <0x70006400 0x100>;
> - reg-shift = <2>;
> - interrupts = <0 91 0x04>;
> - clock-frequency = <216000000>;
> - nvidia,dma-request-selector = <&apbdma 20>;
> - clocks = <&tegra_car 66>;
> - status = "disabled";
> - };
> -
> - pwm: pwm {
> - compatible = "nvidia,tegra20-pwm";
> - reg = <0x7000a000 0x100>;
> - #pwm-cells = <2>;
> - clocks = <&tegra_car 17>;
> - };
> -
> - rtc {
> - compatible = "nvidia,tegra20-rtc";
> - reg = <0x7000e000 0x100>;
> - interrupts = <0 2 0x04>;
> - };
> -
> - i2c@7000c000 {
> - compatible = "nvidia,tegra20-i2c";
> - reg = <0x7000c000 0x100>;
> - interrupts = <0 38 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 12>, <&tegra_car 124>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - spi@7000c380 {
> - compatible = "nvidia,tegra20-sflash";
> - reg = <0x7000c380 0x80>;
> - interrupts = <0 39 0x04>;
> - nvidia,dma-request-selector = <&apbdma 11>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 43>;
> - status = "disabled";
> - };
> -
> - i2c@7000c400 {
> - compatible = "nvidia,tegra20-i2c";
> - reg = <0x7000c400 0x100>;
> - interrupts = <0 84 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 54>, <&tegra_car 124>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000c500 {
> - compatible = "nvidia,tegra20-i2c";
> - reg = <0x7000c500 0x100>;
> - interrupts = <0 92 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 67>, <&tegra_car 124>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000d000 {
> - compatible = "nvidia,tegra20-i2c-dvc";
> - reg = <0x7000d000 0x200>;
> - interrupts = <0 53 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 47>, <&tegra_car 124>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - spi@7000d400 {
> - compatible = "nvidia,tegra20-slink";
> - reg = <0x7000d400 0x200>;
> - interrupts = <0 59 0x04>;
> - nvidia,dma-request-selector = <&apbdma 15>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 41>;
> - status = "disabled";
> - };
> -
> - spi@7000d600 {
> - compatible = "nvidia,tegra20-slink";
> - reg = <0x7000d600 0x200>;
> - interrupts = <0 82 0x04>;
> - nvidia,dma-request-selector = <&apbdma 16>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 44>;
> - status = "disabled";
> - };
> -
> - spi@7000d800 {
> - compatible = "nvidia,tegra20-slink";
> - reg = <0x7000d480 0x200>;
> - interrupts = <0 83 0x04>;
> - nvidia,dma-request-selector = <&apbdma 17>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 46>;
> - status = "disabled";
> - };
> -
> - spi@7000da00 {
> - compatible = "nvidia,tegra20-slink";
> - reg = <0x7000da00 0x200>;
> - interrupts = <0 93 0x04>;
> - nvidia,dma-request-selector = <&apbdma 18>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 68>;
> - status = "disabled";
> - };
> -
> - kbc {
> - compatible = "nvidia,tegra20-kbc";
> - reg = <0x7000e200 0x100>;
> - interrupts = <0 85 0x04>;
> - clocks = <&tegra_car 36>;
> - status = "disabled";
> - };
> -
> - pmc {
> - compatible = "nvidia,tegra20-pmc";
> - reg = <0x7000e400 0x400>;
> - };
> -
> - memory-controller@7000f000 {
> - compatible = "nvidia,tegra20-mc";
> - reg = <0x7000f000 0x024
> - 0x7000f03c 0x3c4>;
> - interrupts = <0 77 0x04>;
> - };
> -
> - iommu {
> - compatible = "nvidia,tegra20-gart";
> - reg = <0x7000f024 0x00000018 /* controller registers */
> - 0x58000000 0x02000000>; /* GART aperture */
> - };
> -
> - memory-controller@7000f400 {
> - compatible = "nvidia,tegra20-emc";
> - reg = <0x7000f400 0x200>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - usb@c5000000 {
> - compatible = "nvidia,tegra20-ehci", "usb-ehci";
> - reg = <0xc5000000 0x4000>;
> - interrupts = <0 20 0x04>;
> - phy_type = "utmi";
> - nvidia,has-legacy-mode;
> - clocks = <&tegra_car 22>;
> - nvidia,needs-double-reset;
> - nvidia,phy = <&phy1>;
> - status = "disabled";
> - };
> -
> - phy1: usb-phy@c5000400 {
> - compatible = "nvidia,tegra20-usb-phy";
> - reg = <0xc5000400 0x3c00>;
> - phy_type = "utmi";
> - nvidia,has-legacy-mode;
> - clocks = <&tegra_car 22>, <&tegra_car 127>;
> - clock-names = "phy", "pll_u";
> - };
> -
> - usb@c5004000 {
> - compatible = "nvidia,tegra20-ehci", "usb-ehci";
> - reg = <0xc5004000 0x4000>;
> - interrupts = <0 21 0x04>;
> - phy_type = "ulpi";
> - clocks = <&tegra_car 58>;
> - nvidia,phy = <&phy2>;
> - status = "disabled";
> - };
> -
> - phy2: usb-phy@c5004400 {
> - compatible = "nvidia,tegra20-usb-phy";
> - reg = <0xc5004400 0x3c00>;
> - phy_type = "ulpi";
> - clocks = <&tegra_car 94>, <&tegra_car 127>;
> - clock-names = "phy", "pll_u";
> - };
> -
> - usb@c5008000 {
> - compatible = "nvidia,tegra20-ehci", "usb-ehci";
> - reg = <0xc5008000 0x4000>;
> - interrupts = <0 97 0x04>;
> - phy_type = "utmi";
> - clocks = <&tegra_car 59>;
> - nvidia,phy = <&phy3>;
> - status = "disabled";
> - };
> -
> - phy3: usb-phy@c5008400 {
> - compatible = "nvidia,tegra20-usb-phy";
> - reg = <0xc5008400 0x3c00>;
> - phy_type = "utmi";
> - clocks = <&tegra_car 22>, <&tegra_car 127>;
> - clock-names = "phy", "pll_u";
> - };
> -
> - sdhci@c8000000 {
> - compatible = "nvidia,tegra20-sdhci";
> - reg = <0xc8000000 0x200>;
> - interrupts = <0 14 0x04>;
> - clocks = <&tegra_car 14>;
> - status = "disabled";
> - };
> -
> - sdhci@c8000200 {
> - compatible = "nvidia,tegra20-sdhci";
> - reg = <0xc8000200 0x200>;
> - interrupts = <0 15 0x04>;
> - clocks = <&tegra_car 9>;
> - status = "disabled";
> - };
> -
> - sdhci@c8000400 {
> - compatible = "nvidia,tegra20-sdhci";
> - reg = <0xc8000400 0x200>;
> - interrupts = <0 19 0x04>;
> - clocks = <&tegra_car 69>;
> - status = "disabled";
> - };
> -
> - sdhci@c8000600 {
> - compatible = "nvidia,tegra20-sdhci";
> - reg = <0xc8000600 0x200>;
> - interrupts = <0 31 0x04>;
> - clocks = <&tegra_car 15>;
> - status = "disabled";
> - };
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - cpu@0 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <0>;
> - };
> -
> - cpu@1 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <1>;
> - };
> - };
> -
> - pmu {
> - compatible = "arm,cortex-a9-pmu";
> - interrupts = <0 56 0x04
> - 0 57 0x04>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
> new file mode 100644
> index 0000000..917edd4
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra20.dtsip
> @@ -0,0 +1,556 @@
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "nvidia,tegra20";
> + interrupt-parent = <&intc>;
> +
> + aliases {
> + serial0 = &uarta;
> + serial1 = &uartb;
> + serial2 = &uartc;
> + serial3 = &uartd;
> + serial4 = &uarte;
> + };
> +
> + host1x {
> + compatible = "nvidia,tegra20-host1x", "simple-bus";
> + reg = <0x50000000 0x00024000>;
> + interrupts = <0 65 0x04 /* mpcore syncpt */
> + 0 67 0x04>; /* mpcore general */
> + clocks = <&tegra_car 28>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0x54000000 0x54000000 0x04000000>;
> +
> + mpe {
> + compatible = "nvidia,tegra20-mpe";
> + reg = <0x54040000 0x00040000>;
> + interrupts = <0 68 0x04>;
> + clocks = <&tegra_car 60>;
> + };
> +
> + vi {
> + compatible = "nvidia,tegra20-vi";
> + reg = <0x54080000 0x00040000>;
> + interrupts = <0 69 0x04>;
> + clocks = <&tegra_car 100>;
> + };
> +
> + epp {
> + compatible = "nvidia,tegra20-epp";
> + reg = <0x540c0000 0x00040000>;
> + interrupts = <0 70 0x04>;
> + clocks = <&tegra_car 19>;
> + };
> +
> + isp {
> + compatible = "nvidia,tegra20-isp";
> + reg = <0x54100000 0x00040000>;
> + interrupts = <0 71 0x04>;
> + clocks = <&tegra_car 23>;
> + };
> +
> + gr2d {
> + compatible = "nvidia,tegra20-gr2d";
> + reg = <0x54140000 0x00040000>;
> + interrupts = <0 72 0x04>;
> + clocks = <&tegra_car 21>;
> + };
> +
> + gr3d {
> + compatible = "nvidia,tegra20-gr3d";
> + reg = <0x54180000 0x00040000>;
> + clocks = <&tegra_car 24>;
> + };
> +
> + dc@54200000 {
> + compatible = "nvidia,tegra20-dc";
> + reg = <0x54200000 0x00040000>;
> + interrupts = <0 73 0x04>;
> + clocks = <&tegra_car 27>, <&tegra_car 121>;
> + clock-names = "disp1", "parent";
> +
> + rgb {
> + status = "disabled";
> + };
> + };
> +
> + dc@54240000 {
> + compatible = "nvidia,tegra20-dc";
> + reg = <0x54240000 0x00040000>;
> + interrupts = <0 74 0x04>;
> + clocks = <&tegra_car 26>, <&tegra_car 121>;
> + clock-names = "disp2", "parent";
> +
> + rgb {
> + status = "disabled";
> + };
> + };
> +
> + hdmi {
> + compatible = "nvidia,tegra20-hdmi";
> + reg = <0x54280000 0x00040000>;
> + interrupts = <0 75 0x04>;
> + clocks = <&tegra_car 51>, <&tegra_car 117>;
> + clock-names = "hdmi", "parent";
> + status = "disabled";
> + };
> +
> + tvo {
> + compatible = "nvidia,tegra20-tvo";
> + reg = <0x542c0000 0x00040000>;
> + interrupts = <0 76 0x04>;
> + clocks = <&tegra_car 102>;
> + status = "disabled";
> + };
> +
> + dsi {
> + compatible = "nvidia,tegra20-dsi";
> + reg = <0x54300000 0x00040000>;
> + clocks = <&tegra_car 48>;
> + status = "disabled";
> + };
> + };
> +
> + timer@50004600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0x50040600 0x20>;
> + interrupts = <1 13 0x304>;
> + };
> +
> + intc: interrupt-controller {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0x50041000 0x1000
> + 0x50040100 0x0100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + cache-controller {
> + compatible = "arm,pl310-cache";
> + reg = <0x50043000 0x1000>;
> + arm,data-latency = <5 5 2>;
> + arm,tag-latency = <4 4 2>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + timer@60005000 {
> + compatible = "nvidia,tegra20-timer";
> + reg = <0x60005000 0x60>;
> + interrupts = <0 0 0x04
> + 0 1 0x04
> + 0 41 0x04
> + 0 42 0x04>;
> + };
> +
> + tegra_car: clock {
> + compatible = "nvidia,tegra20-car";
> + reg = <0x60006000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apbdma: dma {
> + compatible = "nvidia,tegra20-apbdma";
> + reg = <0x6000a000 0x1200>;
> + interrupts = <0 104 0x04
> + 0 105 0x04
> + 0 106 0x04
> + 0 107 0x04
> + 0 108 0x04
> + 0 109 0x04
> + 0 110 0x04
> + 0 111 0x04
> + 0 112 0x04
> + 0 113 0x04
> + 0 114 0x04
> + 0 115 0x04
> + 0 116 0x04
> + 0 117 0x04
> + 0 118 0x04
> + 0 119 0x04>;
> + clocks = <&tegra_car 34>;
> + };
> +
> + ahb {
> + compatible = "nvidia,tegra20-ahb";
> + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
> + };
> +
> + gpio: gpio {
> + compatible = "nvidia,tegra20-gpio";
> + reg = <0x6000d000 0x1000>;
> + interrupts = <0 32 0x04
> + 0 33 0x04
> + 0 34 0x04
> + 0 35 0x04
> + 0 55 0x04
> + 0 87 0x04
> + 0 89 0x04>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + };
> +
> + pinmux: pinmux {
> + compatible = "nvidia,tegra20-pinmux";
> + reg = <0x70000014 0x10 /* Tri-state registers */
> + 0x70000080 0x20 /* Mux registers */
> + 0x700000a0 0x14 /* Pull-up/down registers */
> + 0x70000868 0xa8>; /* Pad control registers */
> + };
> +
> + das {
> + compatible = "nvidia,tegra20-das";
> + reg = <0x70000c00 0x80>;
> + };
> +
> + tegra_ac97: ac97 {
> + compatible = "nvidia,tegra20-ac97";
> + reg = <0x70002000 0x200>;
> + interrupts = <0 81 0x04>;
> + nvidia,dma-request-selector = <&apbdma 12>;
> + clocks = <&tegra_car 3>;
> + status = "disabled";
> + };
> +
> + tegra_i2s1: i2s@70002800 {
> + compatible = "nvidia,tegra20-i2s";
> + reg = <0x70002800 0x200>;
> + interrupts = <0 13 0x04>;
> + nvidia,dma-request-selector = <&apbdma 2>;
> + clocks = <&tegra_car 11>;
> + status = "disabled";
> + };
> +
> + tegra_i2s2: i2s@70002a00 {
> + compatible = "nvidia,tegra20-i2s";
> + reg = <0x70002a00 0x200>;
> + interrupts = <0 3 0x04>;
> + nvidia,dma-request-selector = <&apbdma 1>;
> + clocks = <&tegra_car 18>;
> + status = "disabled";
> + };
> +
> + /*
> + * There are two serial driver i.e. 8250 based simple serial
> + * driver and APB DMA based serial driver for higher baudrate
> + * and performace. To enable the 8250 based driver, the compatible
> + * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
> + * driver, the comptible is "nvidia,tegra20-hsuart".
> + */
> + uarta: serial@70006000 {
> + compatible = "nvidia,tegra20-uart";
> + reg = <0x70006000 0x40>;
> + reg-shift = <2>;
> + interrupts = <0 36 0x04>;
> + clock-frequency = <216000000>;
> + nvidia,dma-request-selector = <&apbdma 8>;
> + clocks = <&tegra_car 6>;
> + status = "disabled";
> + };
> +
> + uartb: serial@70006040 {
> + compatible = "nvidia,tegra20-uart";
> + reg = <0x70006040 0x40>;
> + reg-shift = <2>;
> + interrupts = <0 37 0x04>;
> + clock-frequency = <216000000>;
> + nvidia,dma-request-selector = <&apbdma 9>;
> + clocks = <&tegra_car 96>;
> + status = "disabled";
> + };
> +
> + uartc: serial@70006200 {
> + compatible = "nvidia,tegra20-uart";
> + reg = <0x70006200 0x100>;
> + reg-shift = <2>;
> + interrupts = <0 46 0x04>;
> + clock-frequency = <216000000>;
> + nvidia,dma-request-selector = <&apbdma 10>;
> + clocks = <&tegra_car 55>;
> + status = "disabled";
> + };
> +
> + uartd: serial@70006300 {
> + compatible = "nvidia,tegra20-uart";
> + reg = <0x70006300 0x100>;
> + reg-shift = <2>;
> + interrupts = <0 90 0x04>;
> + clock-frequency = <216000000>;
> + nvidia,dma-request-selector = <&apbdma 19>;
> + clocks = <&tegra_car 65>;
> + status = "disabled";
> + };
> +
> + uarte: serial@70006400 {
> + compatible = "nvidia,tegra20-uart";
> + reg = <0x70006400 0x100>;
> + reg-shift = <2>;
> + interrupts = <0 91 0x04>;
> + clock-frequency = <216000000>;
> + nvidia,dma-request-selector = <&apbdma 20>;
> + clocks = <&tegra_car 66>;
> + status = "disabled";
> + };
> +
> + pwm: pwm {
> + compatible = "nvidia,tegra20-pwm";
> + reg = <0x7000a000 0x100>;
> + #pwm-cells = <2>;
> + clocks = <&tegra_car 17>;
> + };
> +
> + rtc {
> + compatible = "nvidia,tegra20-rtc";
> + reg = <0x7000e000 0x100>;
> + interrupts = <0 2 0x04>;
> + };
> +
> + i2c@7000c000 {
> + compatible = "nvidia,tegra20-i2c";
> + reg = <0x7000c000 0x100>;
> + interrupts = <0 38 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 12>, <&tegra_car 124>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + spi@7000c380 {
> + compatible = "nvidia,tegra20-sflash";
> + reg = <0x7000c380 0x80>;
> + interrupts = <0 39 0x04>;
> + nvidia,dma-request-selector = <&apbdma 11>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 43>;
> + status = "disabled";
> + };
> +
> + i2c@7000c400 {
> + compatible = "nvidia,tegra20-i2c";
> + reg = <0x7000c400 0x100>;
> + interrupts = <0 84 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 54>, <&tegra_car 124>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000c500 {
> + compatible = "nvidia,tegra20-i2c";
> + reg = <0x7000c500 0x100>;
> + interrupts = <0 92 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 67>, <&tegra_car 124>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000d000 {
> + compatible = "nvidia,tegra20-i2c-dvc";
> + reg = <0x7000d000 0x200>;
> + interrupts = <0 53 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 47>, <&tegra_car 124>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + spi@7000d400 {
> + compatible = "nvidia,tegra20-slink";
> + reg = <0x7000d400 0x200>;
> + interrupts = <0 59 0x04>;
> + nvidia,dma-request-selector = <&apbdma 15>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 41>;
> + status = "disabled";
> + };
> +
> + spi@7000d600 {
> + compatible = "nvidia,tegra20-slink";
> + reg = <0x7000d600 0x200>;
> + interrupts = <0 82 0x04>;
> + nvidia,dma-request-selector = <&apbdma 16>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 44>;
> + status = "disabled";
> + };
> +
> + spi@7000d800 {
> + compatible = "nvidia,tegra20-slink";
> + reg = <0x7000d480 0x200>;
> + interrupts = <0 83 0x04>;
> + nvidia,dma-request-selector = <&apbdma 17>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 46>;
> + status = "disabled";
> + };
> +
> + spi@7000da00 {
> + compatible = "nvidia,tegra20-slink";
> + reg = <0x7000da00 0x200>;
> + interrupts = <0 93 0x04>;
> + nvidia,dma-request-selector = <&apbdma 18>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 68>;
> + status = "disabled";
> + };
> +
> + kbc {
> + compatible = "nvidia,tegra20-kbc";
> + reg = <0x7000e200 0x100>;
> + interrupts = <0 85 0x04>;
> + clocks = <&tegra_car 36>;
> + status = "disabled";
> + };
> +
> + pmc {
> + compatible = "nvidia,tegra20-pmc";
> + reg = <0x7000e400 0x400>;
> + };
> +
> + memory-controller@7000f000 {
> + compatible = "nvidia,tegra20-mc";
> + reg = <0x7000f000 0x024
> + 0x7000f03c 0x3c4>;
> + interrupts = <0 77 0x04>;
> + };
> +
> + iommu {
> + compatible = "nvidia,tegra20-gart";
> + reg = <0x7000f024 0x00000018 /* controller registers */
> + 0x58000000 0x02000000>; /* GART aperture */
> + };
> +
> + memory-controller@7000f400 {
> + compatible = "nvidia,tegra20-emc";
> + reg = <0x7000f400 0x200>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + usb@c5000000 {
> + compatible = "nvidia,tegra20-ehci", "usb-ehci";
> + reg = <0xc5000000 0x4000>;
> + interrupts = <0 20 0x04>;
> + phy_type = "utmi";
> + nvidia,has-legacy-mode;
> + clocks = <&tegra_car 22>;
> + nvidia,needs-double-reset;
> + nvidia,phy = <&phy1>;
> + status = "disabled";
> + };
> +
> + phy1: usb-phy@c5000400 {
> + compatible = "nvidia,tegra20-usb-phy";
> + reg = <0xc5000400 0x3c00>;
> + phy_type = "utmi";
> + nvidia,has-legacy-mode;
> + clocks = <&tegra_car 22>, <&tegra_car 127>;
> + clock-names = "phy", "pll_u";
> + };
> +
> + usb@c5004000 {
> + compatible = "nvidia,tegra20-ehci", "usb-ehci";
> + reg = <0xc5004000 0x4000>;
> + interrupts = <0 21 0x04>;
> + phy_type = "ulpi";
> + clocks = <&tegra_car 58>;
> + nvidia,phy = <&phy2>;
> + status = "disabled";
> + };
> +
> + phy2: usb-phy@c5004400 {
> + compatible = "nvidia,tegra20-usb-phy";
> + reg = <0xc5004400 0x3c00>;
> + phy_type = "ulpi";
> + clocks = <&tegra_car 94>, <&tegra_car 127>;
> + clock-names = "phy", "pll_u";
> + };
> +
> + usb@c5008000 {
> + compatible = "nvidia,tegra20-ehci", "usb-ehci";
> + reg = <0xc5008000 0x4000>;
> + interrupts = <0 97 0x04>;
> + phy_type = "utmi";
> + clocks = <&tegra_car 59>;
> + nvidia,phy = <&phy3>;
> + status = "disabled";
> + };
> +
> + phy3: usb-phy@c5008400 {
> + compatible = "nvidia,tegra20-usb-phy";
> + reg = <0xc5008400 0x3c00>;
> + phy_type = "utmi";
> + clocks = <&tegra_car 22>, <&tegra_car 127>;
> + clock-names = "phy", "pll_u";
> + };
> +
> + sdhci@c8000000 {
> + compatible = "nvidia,tegra20-sdhci";
> + reg = <0xc8000000 0x200>;
> + interrupts = <0 14 0x04>;
> + clocks = <&tegra_car 14>;
> + status = "disabled";
> + };
> +
> + sdhci@c8000200 {
> + compatible = "nvidia,tegra20-sdhci";
> + reg = <0xc8000200 0x200>;
> + interrupts = <0 15 0x04>;
> + clocks = <&tegra_car 9>;
> + status = "disabled";
> + };
> +
> + sdhci@c8000400 {
> + compatible = "nvidia,tegra20-sdhci";
> + reg = <0xc8000400 0x200>;
> + interrupts = <0 19 0x04>;
> + clocks = <&tegra_car 69>;
> + status = "disabled";
> + };
> +
> + sdhci@c8000600 {
> + compatible = "nvidia,tegra20-sdhci";
> + reg = <0xc8000600 0x200>;
> + interrupts = <0 31 0x04>;
> + clocks = <&tegra_car 15>;
> + status = "disabled";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <1>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 56 0x04
> + 0 57 0x04>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
> deleted file mode 100644
> index 8ff2ff2..0000000
> --- a/arch/arm/boot/dts/tegra30-beaver.dts
> +++ /dev/null
> @@ -1,373 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra30.dtsi"
> -
> -/ {
> - model = "NVIDIA Tegra30 Beaver evaluation board";
> - compatible = "nvidia,beaver", "nvidia,tegra30";
> -
> - memory {
> - reg = <0x80000000 0x80000000>;
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - sdmmc1_clk_pz0 {
> - nvidia,pins = "sdmmc1_clk_pz0";
> - nvidia,function = "sdmmc1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc1_cmd_pz1 {
> - nvidia,pins = "sdmmc1_cmd_pz1",
> - "sdmmc1_dat0_py7",
> - "sdmmc1_dat1_py6",
> - "sdmmc1_dat2_py5",
> - "sdmmc1_dat3_py4";
> - nvidia,function = "sdmmc1";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc3_clk_pa6 {
> - nvidia,pins = "sdmmc3_clk_pa6";
> - nvidia,function = "sdmmc3";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc3_cmd_pa7 {
> - nvidia,pins = "sdmmc3_cmd_pa7",
> - "sdmmc3_dat0_pb7",
> - "sdmmc3_dat1_pb6",
> - "sdmmc3_dat2_pb5",
> - "sdmmc3_dat3_pb4";
> - nvidia,function = "sdmmc3";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc4_clk_pcc4 {
> - nvidia,pins = "sdmmc4_clk_pcc4",
> - "sdmmc4_rst_n_pcc3";
> - nvidia,function = "sdmmc4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc4_dat0_paa0 {
> - nvidia,pins = "sdmmc4_dat0_paa0",
> - "sdmmc4_dat1_paa1",
> - "sdmmc4_dat2_paa2",
> - "sdmmc4_dat3_paa3",
> - "sdmmc4_dat4_paa4",
> - "sdmmc4_dat5_paa5",
> - "sdmmc4_dat6_paa6",
> - "sdmmc4_dat7_paa7";
> - nvidia,function = "sdmmc4";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - dap2_fs_pa2 {
> - nvidia,pins = "dap2_fs_pa2",
> - "dap2_sclk_pa3",
> - "dap2_din_pa4",
> - "dap2_dout_pa5";
> - nvidia,function = "i2s1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdio3 {
> - nvidia,pins = "drive_sdio3";
> - nvidia,high-speed-mode = <0>;
> - nvidia,schmitt = <0>;
> - nvidia,pull-down-strength = <46>;
> - nvidia,pull-up-strength = <42>;
> - nvidia,slew-rate-rising = <1>;
> - nvidia,slew-rate-falling = <1>;
> - };
> - };
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c700 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <100000>;
> -
> - tps62361 {
> - compatible = "ti,tps62361";
> - reg = <0x60>;
> -
> - regulator-name = "tps62361-vout";
> - regulator-min-microvolt = <500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-boot-on;
> - regulator-always-on;
> - ti,vsel0-state-high;
> - ti,vsel1-state-high;
> - };
> -
> - pmic: tps65911@2d {
> - compatible = "ti,tps65911";
> - reg = <0x2d>;
> -
> - interrupts = <0 86 0x4>;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - vcc1-supply = <&vdd_5v_in_reg>;
> - vcc2-supply = <&vdd_5v_in_reg>;
> - vcc3-supply = <&vio_reg>;
> - vcc4-supply = <&vdd_5v_in_reg>;
> - vcc5-supply = <&vdd_5v_in_reg>;
> - vcc6-supply = <&vdd2_reg>;
> - vcc7-supply = <&vdd_5v_in_reg>;
> - vccio-supply = <&vdd_5v_in_reg>;
> -
> - regulators {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd1_reg: vdd1 {
> - regulator-name = "vddio_ddr_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - vdd2_reg: vdd2 {
> - regulator-name = "vdd_1v5_gen";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - };
> -
> - vddctrl_reg: vddctrl {
> - regulator-name = "vdd_cpu,vdd_sys";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - vio_reg: vio {
> - regulator-name = "vdd_1v8_gen";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo1_reg: ldo1 {
> - regulator-name = "vdd_pexa,vdd_pexb";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - ldo2_reg: ldo2 {
> - regulator-name = "vdd_sata,avdd_plle";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - /* LDO3 is not connected to anything */
> -
> - ldo4_reg: ldo4 {
> - regulator-name = "vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - ldo5_reg: ldo5 {
> - regulator-name = "vddio_sdmmc,avdd_vdac";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo6_reg: ldo6 {
> - regulator-name = "avdd_dsi_csi,pwrdet_mipi";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo7_reg: ldo7 {
> - regulator-name = "vdd_pllm,x,u,a_p_c_s";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - ldo8_reg: ldo8 {
> - regulator-name = "vdd_ddr_hs";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> - };
> - };
> - };
> -
> - spi@7000da00 {
> - status = "okay";
> - spi-max-frequency = <25000000>;
> - spi-flash@1 {
> - compatible = "winbond,w25q32";
> - reg = <1>;
> - spi-max-frequency = <20000000>;
> - };
> - };
> -
> - ahub {
> - i2s@70080400 {
> - status = "okay";
> - };
> - };
> -
> - pmc {
> - status = "okay";
> - nvidia,invert-interrupt;
> - };
> -
> - sdhci@78000000 {
> - status = "okay";
> - cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> - wp-gpios = <&gpio 155 0>; /* gpio PT3 */
> - power-gpios = <&gpio 31 0>; /* gpio PD7 */
> - bus-width = <4>;
> - };
> -
> - sdhci@78000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_5v_in_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_5v_in";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - chargepump_5v_reg: regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "chargepump_5v";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-boot-on;
> - regulator-always-on;
> - enable-active-high;
> - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
> - };
> -
> - ddr_reg: regulator@2 {
> - compatible = "regulator-fixed";
> - reg = <2>;
> - regulator-name = "vdd_ddr";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
> - vin-supply = <&vdd_5v_in_reg>;
> - };
> -
> - vdd_5v_sata_reg: regulator@3 {
> - compatible = "regulator-fixed";
> - reg = <3>;
> - regulator-name = "vdd_5v_sata";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 30 0>; /* gpio PD6 */
> - vin-supply = <&vdd_5v_in_reg>;
> - };
> -
> - usb1_vbus_reg: regulator@4 {
> - compatible = "regulator-fixed";
> - reg = <4>;
> - regulator-name = "usb1_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 68 0>; /* GPIO PI4 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v_in_reg>;
> - };
> -
> - usb3_vbus_reg: regulator@5 {
> - compatible = "regulator-fixed";
> - reg = <5>;
> - regulator-name = "usb3_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 63 0>; /* GPIO PH7 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v_in_reg>;
> - };
> -
> - sys_3v3_reg: regulator@6 {
> - compatible = "regulator-fixed";
> - reg = <6>;
> - regulator-name = "sys_3v3,vdd_3v3_alw";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
> - vin-supply = <&vdd_5v_in_reg>;
> - };
> -
> - sys_3v3_pexs_reg: regulator@7 {
> - compatible = "regulator-fixed";
> - reg = <7>;
> - regulator-name = "sys_3v3_pexs";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 95 0>; /* gpio PL7 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra30-beaver.dtsp b/arch/arm/boot/dts/tegra30-beaver.dtsp
> new file mode 100644
> index 0000000..af23c94
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-beaver.dtsp
> @@ -0,0 +1,373 @@
> +/dts-v1/;
> +
> +#include "tegra30.dtsip"
> +
> +/ {
> + model = "NVIDIA Tegra30 Beaver evaluation board";
> + compatible = "nvidia,beaver", "nvidia,tegra30";
> +
> + memory {
> + reg = <0x80000000 0x80000000>;
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + sdmmc1_clk_pz0 {
> + nvidia,pins = "sdmmc1_clk_pz0";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc1_cmd_pz1 {
> + nvidia,pins = "sdmmc1_cmd_pz1",
> + "sdmmc1_dat0_py7",
> + "sdmmc1_dat1_py6",
> + "sdmmc1_dat2_py5",
> + "sdmmc1_dat3_py4";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc3_clk_pa6 {
> + nvidia,pins = "sdmmc3_clk_pa6";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc3_cmd_pa7 {
> + nvidia,pins = "sdmmc3_cmd_pa7",
> + "sdmmc3_dat0_pb7",
> + "sdmmc3_dat1_pb6",
> + "sdmmc3_dat2_pb5",
> + "sdmmc3_dat3_pb4";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc4_clk_pcc4 {
> + nvidia,pins = "sdmmc4_clk_pcc4",
> + "sdmmc4_rst_n_pcc3";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc4_dat0_paa0 {
> + nvidia,pins = "sdmmc4_dat0_paa0",
> + "sdmmc4_dat1_paa1",
> + "sdmmc4_dat2_paa2",
> + "sdmmc4_dat3_paa3",
> + "sdmmc4_dat4_paa4",
> + "sdmmc4_dat5_paa5",
> + "sdmmc4_dat6_paa6",
> + "sdmmc4_dat7_paa7";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + dap2_fs_pa2 {
> + nvidia,pins = "dap2_fs_pa2",
> + "dap2_sclk_pa3",
> + "dap2_din_pa4",
> + "dap2_dout_pa5";
> + nvidia,function = "i2s1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdio3 {
> + nvidia,pins = "drive_sdio3";
> + nvidia,high-speed-mode = <0>;
> + nvidia,schmitt = <0>;
> + nvidia,pull-down-strength = <46>;
> + nvidia,pull-up-strength = <42>;
> + nvidia,slew-rate-rising = <1>;
> + nvidia,slew-rate-falling = <1>;
> + };
> + };
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c700 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + tps62361 {
> + compatible = "ti,tps62361";
> + reg = <0x60>;
> +
> + regulator-name = "tps62361-vout";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + ti,vsel0-state-high;
> + ti,vsel1-state-high;
> + };
> +
> + pmic: tps65911@2d {
> + compatible = "ti,tps65911";
> + reg = <0x2d>;
> +
> + interrupts = <0 86 0x4>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + vcc1-supply = <&vdd_5v_in_reg>;
> + vcc2-supply = <&vdd_5v_in_reg>;
> + vcc3-supply = <&vio_reg>;
> + vcc4-supply = <&vdd_5v_in_reg>;
> + vcc5-supply = <&vdd_5v_in_reg>;
> + vcc6-supply = <&vdd2_reg>;
> + vcc7-supply = <&vdd_5v_in_reg>;
> + vccio-supply = <&vdd_5v_in_reg>;
> +
> + regulators {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd1_reg: vdd1 {
> + regulator-name = "vddio_ddr_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + vdd2_reg: vdd2 {
> + regulator-name = "vdd_1v5_gen";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> + vddctrl_reg: vddctrl {
> + regulator-name = "vdd_cpu,vdd_sys";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + vio_reg: vio {
> + regulator-name = "vdd_1v8_gen";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: ldo1 {
> + regulator-name = "vdd_pexa,vdd_pexb";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + ldo2_reg: ldo2 {
> + regulator-name = "vdd_sata,avdd_plle";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + /* LDO3 is not connected to anything */
> +
> + ldo4_reg: ldo4 {
> + regulator-name = "vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: ldo5 {
> + regulator-name = "vddio_sdmmc,avdd_vdac";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo6_reg: ldo6 {
> + regulator-name = "avdd_dsi_csi,pwrdet_mipi";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo7_reg: ldo7 {
> + regulator-name = "vdd_pllm,x,u,a_p_c_s";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + ldo8_reg: ldo8 {
> + regulator-name = "vdd_ddr_hs";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> + };
> + };
> + };
> +
> + spi@7000da00 {
> + status = "okay";
> + spi-max-frequency = <25000000>;
> + spi-flash@1 {
> + compatible = "winbond,w25q32";
> + reg = <1>;
> + spi-max-frequency = <20000000>;
> + };
> + };
> +
> + ahub {
> + i2s@70080400 {
> + status = "okay";
> + };
> + };
> +
> + pmc {
> + status = "okay";
> + nvidia,invert-interrupt;
> + };
> +
> + sdhci@78000000 {
> + status = "okay";
> + cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> + wp-gpios = <&gpio 155 0>; /* gpio PT3 */
> + power-gpios = <&gpio 31 0>; /* gpio PD7 */
> + bus-width = <4>;
> + };
> +
> + sdhci@78000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_5v_in_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_5v_in";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + chargepump_5v_reg: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "chargepump_5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + enable-active-high;
> + gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
> + };
> +
> + ddr_reg: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "vdd_ddr";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
> + vin-supply = <&vdd_5v_in_reg>;
> + };
> +
> + vdd_5v_sata_reg: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "vdd_5v_sata";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 30 0>; /* gpio PD6 */
> + vin-supply = <&vdd_5v_in_reg>;
> + };
> +
> + usb1_vbus_reg: regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "usb1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 68 0>; /* GPIO PI4 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v_in_reg>;
> + };
> +
> + usb3_vbus_reg: regulator@5 {
> + compatible = "regulator-fixed";
> + reg = <5>;
> + regulator-name = "usb3_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 63 0>; /* GPIO PH7 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v_in_reg>;
> + };
> +
> + sys_3v3_reg: regulator@6 {
> + compatible = "regulator-fixed";
> + reg = <6>;
> + regulator-name = "sys_3v3,vdd_3v3_alw";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
> + vin-supply = <&vdd_5v_in_reg>;
> + };
> +
> + sys_3v3_pexs_reg: regulator@7 {
> + compatible = "regulator-fixed";
> + reg = <7>;
> + regulator-name = "sys_3v3_pexs";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 95 0>; /* gpio PL7 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
> deleted file mode 100644
> index adc88aa..0000000
> --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
> +++ /dev/null
> @@ -1,93 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra30-cardhu.dtsi"
> -
> -/* This dts file support the cardhu A02 version of board */
> -
> -/ {
> - model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
> - compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - ddr_reg: regulator@100 {
> - compatible = "regulator-fixed";
> - reg = <100>;
> - regulator-name = "vdd_ddr";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 6 0>;
> - };
> -
> - sys_3v3_reg: regulator@101 {
> - compatible = "regulator-fixed";
> - reg = <101>;
> - regulator-name = "sys_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 7 0>;
> - };
> -
> - usb1_vbus_reg: regulator@102 {
> - compatible = "regulator-fixed";
> - reg = <102>;
> - regulator-name = "usb1_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 68 0>; /* GPIO PI4 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v0_reg>;
> - };
> -
> - usb3_vbus_reg: regulator@103 {
> - compatible = "regulator-fixed";
> - reg = <103>;
> - regulator-name = "usb3_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 63 0>; /* GPIO PH7 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v0_reg>;
> - };
> -
> - vdd_5v0_reg: regulator@104 {
> - compatible = "regulator-fixed";
> - reg = <104>;
> - regulator-name = "5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&pmic 2 0>;
> - };
> -
> - vdd_bl_reg: regulator@105 {
> - compatible = "regulator-fixed";
> - reg = <105>;
> - regulator-name = "vdd_bl";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 83 0>; /* GPIO PK3 */
> - };
> - };
> -
> - sdhci@78000400 {
> - status = "okay";
> - power-gpios = <&gpio 28 0>; /* gpio PD4 */
> - bus-width = <4>;
> - };
> -};
> -
> diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
> new file mode 100644
> index 0000000..64b7184
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dtsp
> @@ -0,0 +1,93 @@
> +/dts-v1/;
> +
> +#include "tegra30-cardhu.dtsip"
> +
> +/* This dts file support the cardhu A02 version of board */
> +
> +/ {
> + model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
> + compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ddr_reg: regulator@100 {
> + compatible = "regulator-fixed";
> + reg = <100>;
> + regulator-name = "vdd_ddr";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 6 0>;
> + };
> +
> + sys_3v3_reg: regulator@101 {
> + compatible = "regulator-fixed";
> + reg = <101>;
> + regulator-name = "sys_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 7 0>;
> + };
> +
> + usb1_vbus_reg: regulator@102 {
> + compatible = "regulator-fixed";
> + reg = <102>;
> + regulator-name = "usb1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 68 0>; /* GPIO PI4 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_reg>;
> + };
> +
> + usb3_vbus_reg: regulator@103 {
> + compatible = "regulator-fixed";
> + reg = <103>;
> + regulator-name = "usb3_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 63 0>; /* GPIO PH7 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_reg>;
> + };
> +
> + vdd_5v0_reg: regulator@104 {
> + compatible = "regulator-fixed";
> + reg = <104>;
> + regulator-name = "5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&pmic 2 0>;
> + };
> +
> + vdd_bl_reg: regulator@105 {
> + compatible = "regulator-fixed";
> + reg = <105>;
> + regulator-name = "vdd_bl";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 83 0>; /* GPIO PK3 */
> + };
> + };
> +
> + sdhci@78000400 {
> + status = "okay";
> + power-gpios = <&gpio 28 0>; /* gpio PD4 */
> + bus-width = <4>;
> + };
> +};
> +
> diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
> deleted file mode 100644
> index 08163e1..0000000
> --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "tegra30-cardhu.dtsi"
> -
> -/* This dts file support the cardhu A04 and later versions of board */
> -
> -/ {
> - model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
> - compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - ddr_reg: regulator@100 {
> - compatible = "regulator-fixed";
> - regulator-name = "ddr";
> - reg = <100>;
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 7 0>;
> - };
> -
> - sys_3v3_reg: regulator@101 {
> - compatible = "regulator-fixed";
> - reg = <101>;
> - regulator-name = "sys_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&pmic 6 0>;
> - };
> -
> - usb1_vbus_reg: regulator@102 {
> - compatible = "regulator-fixed";
> - reg = <102>;
> - regulator-name = "usb1_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 238 0>; /* GPIO PDD6 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v0_reg>;
> - };
> -
> - usb3_vbus_reg: regulator@103 {
> - compatible = "regulator-fixed";
> - reg = <103>;
> - regulator-name = "usb3_vbus";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 236 0>; /* GPIO PDD4 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v0_reg>;
> - };
> -
> - vdd_5v0_reg: regulator@104 {
> - compatible = "regulator-fixed";
> - reg = <104>;
> - regulator-name = "5v0";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&pmic 8 0>;
> - };
> -
> - vdd_bl_reg: regulator@105 {
> - compatible = "regulator-fixed";
> - reg = <105>;
> - regulator-name = "vdd_bl";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 234 0>; /* GPIO PDD2 */
> - };
> -
> - vdd_bl2_reg: regulator@106 {
> - compatible = "regulator-fixed";
> - reg = <106>;
> - regulator-name = "vdd_bl2";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 232 0>; /* GPIO PDD0 */
> - };
> - };
> -
> - sdhci@78000400 {
> - status = "okay";
> - power-gpios = <&gpio 27 0>; /* gpio PD3 */
> - bus-width = <4>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
> new file mode 100644
> index 0000000..fc0d771
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dtsp
> @@ -0,0 +1,104 @@
> +/dts-v1/;
> +
> +#include "tegra30-cardhu.dtsip"
> +
> +/* This dts file support the cardhu A04 and later versions of board */
> +
> +/ {
> + model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
> + compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ddr_reg: regulator@100 {
> + compatible = "regulator-fixed";
> + regulator-name = "ddr";
> + reg = <100>;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 7 0>;
> + };
> +
> + sys_3v3_reg: regulator@101 {
> + compatible = "regulator-fixed";
> + reg = <101>;
> + regulator-name = "sys_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pmic 6 0>;
> + };
> +
> + usb1_vbus_reg: regulator@102 {
> + compatible = "regulator-fixed";
> + reg = <102>;
> + regulator-name = "usb1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 238 0>; /* GPIO PDD6 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_reg>;
> + };
> +
> + usb3_vbus_reg: regulator@103 {
> + compatible = "regulator-fixed";
> + reg = <103>;
> + regulator-name = "usb3_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 236 0>; /* GPIO PDD4 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_reg>;
> + };
> +
> + vdd_5v0_reg: regulator@104 {
> + compatible = "regulator-fixed";
> + reg = <104>;
> + regulator-name = "5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&pmic 8 0>;
> + };
> +
> + vdd_bl_reg: regulator@105 {
> + compatible = "regulator-fixed";
> + reg = <105>;
> + regulator-name = "vdd_bl";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 234 0>; /* GPIO PDD2 */
> + };
> +
> + vdd_bl2_reg: regulator@106 {
> + compatible = "regulator-fixed";
> + reg = <106>;
> + regulator-name = "vdd_bl2";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 232 0>; /* GPIO PDD0 */
> + };
> + };
> +
> + sdhci@78000400 {
> + status = "okay";
> + power-gpios = <&gpio 27 0>; /* gpio PD3 */
> + bus-width = <4>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
> deleted file mode 100644
> index 1749927..0000000
> --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
> +++ /dev/null
> @@ -1,500 +0,0 @@
> -/include/ "tegra30.dtsi"
> -
> -/**
> - * This file contains common DT entry for all fab version of Cardhu.
> - * There is multiple fab version of Cardhu starting from A01 to A07.
> - * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
> - * A02 will have different sets of GPIOs for fixed regulator compare to
> - * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
> - * compatible with fab version A04. Based on Cardhu fab version, the
> - * related dts file need to be chosen like for Cardhu fab version A02,
> - * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
> - * tegra30-cardhu-a04.dts.
> - * The identification of board is done in two ways, by looking the sticker
> - * on PCB and by reading board id eeprom.
> - * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
> - * number is the fab version like here it is 002 and hence fab version A02.
> - * The (downstream internal) U-Boot of Cardhu display the board-id as
> - * follows:
> - * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
> - * In this Fab version is 02 i.e. A02.
> - * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
> - * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
> - * wide.
> - */
> -
> -/ {
> - model = "NVIDIA Tegra30 Cardhu evaluation board";
> - compatible = "nvidia,cardhu", "nvidia,tegra30";
> -
> - memory {
> - reg = <0x80000000 0x40000000>;
> - };
> -
> - pinmux {
> - pinctrl-names = "default";
> - pinctrl-0 = <&state_default>;
> -
> - state_default: pinmux {
> - sdmmc1_clk_pz0 {
> - nvidia,pins = "sdmmc1_clk_pz0";
> - nvidia,function = "sdmmc1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc1_cmd_pz1 {
> - nvidia,pins = "sdmmc1_cmd_pz1",
> - "sdmmc1_dat0_py7",
> - "sdmmc1_dat1_py6",
> - "sdmmc1_dat2_py5",
> - "sdmmc1_dat3_py4";
> - nvidia,function = "sdmmc1";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc3_clk_pa6 {
> - nvidia,pins = "sdmmc3_clk_pa6";
> - nvidia,function = "sdmmc3";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc3_cmd_pa7 {
> - nvidia,pins = "sdmmc3_cmd_pa7",
> - "sdmmc3_dat0_pb7",
> - "sdmmc3_dat1_pb6",
> - "sdmmc3_dat2_pb5",
> - "sdmmc3_dat3_pb4";
> - nvidia,function = "sdmmc3";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc4_clk_pcc4 {
> - nvidia,pins = "sdmmc4_clk_pcc4",
> - "sdmmc4_rst_n_pcc3";
> - nvidia,function = "sdmmc4";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdmmc4_dat0_paa0 {
> - nvidia,pins = "sdmmc4_dat0_paa0",
> - "sdmmc4_dat1_paa1",
> - "sdmmc4_dat2_paa2",
> - "sdmmc4_dat3_paa3",
> - "sdmmc4_dat4_paa4",
> - "sdmmc4_dat5_paa5",
> - "sdmmc4_dat6_paa6",
> - "sdmmc4_dat7_paa7";
> - nvidia,function = "sdmmc4";
> - nvidia,pull = <2>;
> - nvidia,tristate = <0>;
> - };
> - dap2_fs_pa2 {
> - nvidia,pins = "dap2_fs_pa2",
> - "dap2_sclk_pa3",
> - "dap2_din_pa4",
> - "dap2_dout_pa5";
> - nvidia,function = "i2s1";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - sdio3 {
> - nvidia,pins = "drive_sdio3";
> - nvidia,high-speed-mode = <0>;
> - nvidia,schmitt = <0>;
> - nvidia,pull-down-strength = <46>;
> - nvidia,pull-up-strength = <42>;
> - nvidia,slew-rate-rising = <1>;
> - nvidia,slew-rate-falling = <1>;
> - };
> - uart3_txd_pw6 {
> - nvidia,pins = "uart3_txd_pw6",
> - "uart3_cts_n_pa1",
> - "uart3_rts_n_pc0",
> - "uart3_rxd_pw7";
> - nvidia,function = "uartc";
> - nvidia,pull = <0>;
> - nvidia,tristate = <0>;
> - };
> - };
> - };
> -
> - serial@70006000 {
> - status = "okay";
> - };
> -
> - serial@70006200 {
> - compatible = "nvidia,tegra30-hsuart";
> - status = "okay";
> - };
> -
> - i2c@7000c000 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c400 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000c500 {
> - status = "okay";
> - clock-frequency = <100000>;
> -
> - /* ALS and Proximity sensor */
> - isl29028@44 {
> - compatible = "isil,isl29028";
> - reg = <0x44>;
> - interrupt-parent = <&gpio>;
> - interrupts = <88 0x04>; /*gpio PL0 */
> - };
> - };
> -
> - i2c@7000c700 {
> - status = "okay";
> - clock-frequency = <100000>;
> - };
> -
> - i2c@7000d000 {
> - status = "okay";
> - clock-frequency = <100000>;
> -
> - wm8903: wm8903@1a {
> - compatible = "wlf,wm8903";
> - reg = <0x1a>;
> - interrupt-parent = <&gpio>;
> - interrupts = <179 0x04>; /* gpio PW3 */
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - micdet-cfg = <0>;
> - micdet-delay = <100>;
> - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> - };
> -
> - tps62361 {
> - compatible = "ti,tps62361";
> - reg = <0x60>;
> -
> - regulator-name = "tps62361-vout";
> - regulator-min-microvolt = <500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-boot-on;
> - regulator-always-on;
> - ti,vsel0-state-high;
> - ti,vsel1-state-high;
> - };
> -
> - pmic: tps65911@2d {
> - compatible = "ti,tps65911";
> - reg = <0x2d>;
> -
> - interrupts = <0 86 0x4>;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> -
> - ti,system-power-controller;
> -
> - #gpio-cells = <2>;
> - gpio-controller;
> -
> - vcc1-supply = <&vdd_ac_bat_reg>;
> - vcc2-supply = <&vdd_ac_bat_reg>;
> - vcc3-supply = <&vio_reg>;
> - vcc4-supply = <&vdd_5v0_reg>;
> - vcc5-supply = <&vdd_ac_bat_reg>;
> - vcc6-supply = <&vdd2_reg>;
> - vcc7-supply = <&vdd_ac_bat_reg>;
> - vccio-supply = <&vdd_ac_bat_reg>;
> -
> - regulators {
> - vdd1_reg: vdd1 {
> - regulator-name = "vddio_ddr_1v2";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - vdd2_reg: vdd2 {
> - regulator-name = "vdd_1v5_gen";
> - regulator-min-microvolt = <1500000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - };
> -
> - vddctrl_reg: vddctrl {
> - regulator-name = "vdd_cpu,vdd_sys";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> -
> - vio_reg: vio {
> - regulator-name = "vdd_1v8_gen";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo1_reg: ldo1 {
> - regulator-name = "vdd_pexa,vdd_pexb";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - ldo2_reg: ldo2 {
> - regulator-name = "vdd_sata,avdd_plle";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - /* LDO3 is not connected to anything */
> -
> - ldo4_reg: ldo4 {
> - regulator-name = "vdd_rtc";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - ldo5_reg: ldo5 {
> - regulator-name = "vddio_sdmmc,avdd_vdac";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - ldo6_reg: ldo6 {
> - regulator-name = "avdd_dsi_csi,pwrdet_mipi";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo7_reg: ldo7 {
> - regulator-name = "vdd_pllm,x,u,a_p_c_s";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - ldo8_reg: ldo8 {
> - regulator-name = "vdd_ddr_hs";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - };
> - };
> - };
> - };
> -
> - spi@7000da00 {
> - status = "okay";
> - spi-max-frequency = <25000000>;
> - spi-flash@1 {
> - compatible = "winbond,w25q32";
> - reg = <1>;
> - spi-max-frequency = <20000000>;
> - };
> - };
> -
> - ahub {
> - i2s@70080400 {
> - status = "okay";
> - };
> - };
> -
> - pmc {
> - status = "okay";
> - nvidia,invert-interrupt;
> - };
> -
> - sdhci@78000000 {
> - status = "okay";
> - cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> - wp-gpios = <&gpio 155 0>; /* gpio PT3 */
> - power-gpios = <&gpio 31 0>; /* gpio PD7 */
> - bus-width = <4>;
> - };
> -
> - sdhci@78000600 {
> - status = "okay";
> - bus-width = <8>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vdd_ac_bat_reg: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "vdd_ac_bat";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-always-on;
> - };
> -
> - cam_1v8_reg: regulator@1 {
> - compatible = "regulator-fixed";
> - reg = <1>;
> - regulator-name = "cam_1v8";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - enable-active-high;
> - gpio = <&gpio 220 0>; /* gpio PBB4 */
> - vin-supply = <&vio_reg>;
> - };
> -
> - cp_5v_reg: regulator@2 {
> - compatible = "regulator-fixed";
> - reg = <2>;
> - regulator-name = "cp_5v";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - regulator-boot-on;
> - regulator-always-on;
> - enable-active-high;
> - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
> - };
> -
> - emmc_3v3_reg: regulator@3 {
> - compatible = "regulator-fixed";
> - reg = <3>;
> - regulator-name = "emmc_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 25 0>; /* gpio PD1 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - modem_3v3_reg: regulator@4 {
> - compatible = "regulator-fixed";
> - reg = <4>;
> - regulator-name = "modem_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpio = <&gpio 30 0>; /* gpio PD6 */
> - };
> -
> - pex_hvdd_3v3_reg: regulator@5 {
> - compatible = "regulator-fixed";
> - reg = <5>;
> - regulator-name = "pex_hvdd_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpio = <&gpio 95 0>; /* gpio PL7 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_cam1_ldo_reg: regulator@6 {
> - compatible = "regulator-fixed";
> - reg = <6>;
> - regulator-name = "vdd_cam1_ldo";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - enable-active-high;
> - gpio = <&gpio 142 0>; /* gpio PR6 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_cam2_ldo_reg: regulator@7 {
> - compatible = "regulator-fixed";
> - reg = <7>;
> - regulator-name = "vdd_cam2_ldo";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - enable-active-high;
> - gpio = <&gpio 143 0>; /* gpio PR7 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_cam3_ldo_reg: regulator@8 {
> - compatible = "regulator-fixed";
> - reg = <8>;
> - regulator-name = "vdd_cam3_ldo";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpio = <&gpio 144 0>; /* gpio PS0 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_com_reg: regulator@9 {
> - compatible = "regulator-fixed";
> - reg = <9>;
> - regulator-name = "vdd_com";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 24 0>; /* gpio PD0 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_fuse_3v3_reg: regulator@10 {
> - compatible = "regulator-fixed";
> - reg = <10>;
> - regulator-name = "vdd_fuse_3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpio = <&gpio 94 0>; /* gpio PL6 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_pnl1_reg: regulator@11 {
> - compatible = "regulator-fixed";
> - reg = <11>;
> - regulator-name = "vdd_pnl1";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - regulator-boot-on;
> - enable-active-high;
> - gpio = <&gpio 92 0>; /* gpio PL4 */
> - vin-supply = <&sys_3v3_reg>;
> - };
> -
> - vdd_vid_reg: regulator@12 {
> - compatible = "regulator-fixed";
> - reg = <12>;
> - regulator-name = "vddio_vid";
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - enable-active-high;
> - gpio = <&gpio 152 0>; /* GPIO PT0 */
> - gpio-open-drain;
> - vin-supply = <&vdd_5v0_reg>;
> - };
> - };
> -
> - sound {
> - compatible = "nvidia,tegra-audio-wm8903-cardhu",
> - "nvidia,tegra-audio-wm8903";
> - nvidia,model = "NVIDIA Tegra Cardhu";
> -
> - nvidia,audio-routing =
> - "Headphone Jack", "HPOUTR",
> - "Headphone Jack", "HPOUTL",
> - "Int Spk", "ROP",
> - "Int Spk", "RON",
> - "Int Spk", "LOP",
> - "Int Spk", "LON",
> - "Mic Jack", "MICBIAS",
> - "IN1L", "Mic Jack";
> -
> - nvidia,i2s-controller = <&tegra_i2s1>;
> - nvidia,audio-codec = <&wm8903>;
> -
> - nvidia,spkr-en-gpios = <&wm8903 2 0>;
> - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsip b/arch/arm/boot/dts/tegra30-cardhu.dtsip
> new file mode 100644
> index 0000000..75ff544
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsip
> @@ -0,0 +1,500 @@
> +#include "tegra30.dtsip"
> +
> +/**
> + * This file contains common DT entry for all fab version of Cardhu.
> + * There is multiple fab version of Cardhu starting from A01 to A07.
> + * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
> + * A02 will have different sets of GPIOs for fixed regulator compare to
> + * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
> + * compatible with fab version A04. Based on Cardhu fab version, the
> + * related dts file need to be chosen like for Cardhu fab version A02,
> + * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
> + * tegra30-cardhu-a04.dts.
> + * The identification of board is done in two ways, by looking the sticker
> + * on PCB and by reading board id eeprom.
> + * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
> + * number is the fab version like here it is 002 and hence fab version A02.
> + * The (downstream internal) U-Boot of Cardhu display the board-id as
> + * follows:
> + * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
> + * In this Fab version is 02 i.e. A02.
> + * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
> + * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
> + * wide.
> + */
> +
> +/ {
> + model = "NVIDIA Tegra30 Cardhu evaluation board";
> + compatible = "nvidia,cardhu", "nvidia,tegra30";
> +
> + memory {
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + pinmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + sdmmc1_clk_pz0 {
> + nvidia,pins = "sdmmc1_clk_pz0";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc1_cmd_pz1 {
> + nvidia,pins = "sdmmc1_cmd_pz1",
> + "sdmmc1_dat0_py7",
> + "sdmmc1_dat1_py6",
> + "sdmmc1_dat2_py5",
> + "sdmmc1_dat3_py4";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc3_clk_pa6 {
> + nvidia,pins = "sdmmc3_clk_pa6";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc3_cmd_pa7 {
> + nvidia,pins = "sdmmc3_cmd_pa7",
> + "sdmmc3_dat0_pb7",
> + "sdmmc3_dat1_pb6",
> + "sdmmc3_dat2_pb5",
> + "sdmmc3_dat3_pb4";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc4_clk_pcc4 {
> + nvidia,pins = "sdmmc4_clk_pcc4",
> + "sdmmc4_rst_n_pcc3";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdmmc4_dat0_paa0 {
> + nvidia,pins = "sdmmc4_dat0_paa0",
> + "sdmmc4_dat1_paa1",
> + "sdmmc4_dat2_paa2",
> + "sdmmc4_dat3_paa3",
> + "sdmmc4_dat4_paa4",
> + "sdmmc4_dat5_paa5",
> + "sdmmc4_dat6_paa6",
> + "sdmmc4_dat7_paa7";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <2>;
> + nvidia,tristate = <0>;
> + };
> + dap2_fs_pa2 {
> + nvidia,pins = "dap2_fs_pa2",
> + "dap2_sclk_pa3",
> + "dap2_din_pa4",
> + "dap2_dout_pa5";
> + nvidia,function = "i2s1";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + sdio3 {
> + nvidia,pins = "drive_sdio3";
> + nvidia,high-speed-mode = <0>;
> + nvidia,schmitt = <0>;
> + nvidia,pull-down-strength = <46>;
> + nvidia,pull-up-strength = <42>;
> + nvidia,slew-rate-rising = <1>;
> + nvidia,slew-rate-falling = <1>;
> + };
> + uart3_txd_pw6 {
> + nvidia,pins = "uart3_txd_pw6",
> + "uart3_cts_n_pa1",
> + "uart3_rts_n_pc0",
> + "uart3_rxd_pw7";
> + nvidia,function = "uartc";
> + nvidia,pull = <0>;
> + nvidia,tristate = <0>;
> + };
> + };
> + };
> +
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + serial@70006200 {
> + compatible = "nvidia,tegra30-hsuart";
> + status = "okay";
> + };
> +
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + /* ALS and Proximity sensor */
> + isl29028@44 {
> + compatible = "isil,isl29028";
> + reg = <0x44>;
> + interrupt-parent = <&gpio>;
> + interrupts = <88 0x04>; /*gpio PL0 */
> + };
> + };
> +
> + i2c@7000c700 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + wm8903: wm8903@1a {
> + compatible = "wlf,wm8903";
> + reg = <0x1a>;
> + interrupt-parent = <&gpio>;
> + interrupts = <179 0x04>; /* gpio PW3 */
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + micdet-cfg = <0>;
> + micdet-delay = <100>;
> + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
> + };
> +
> + tps62361 {
> + compatible = "ti,tps62361";
> + reg = <0x60>;
> +
> + regulator-name = "tps62361-vout";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + ti,vsel0-state-high;
> + ti,vsel1-state-high;
> + };
> +
> + pmic: tps65911@2d {
> + compatible = "ti,tps65911";
> + reg = <0x2d>;
> +
> + interrupts = <0 86 0x4>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + vcc1-supply = <&vdd_ac_bat_reg>;
> + vcc2-supply = <&vdd_ac_bat_reg>;
> + vcc3-supply = <&vio_reg>;
> + vcc4-supply = <&vdd_5v0_reg>;
> + vcc5-supply = <&vdd_ac_bat_reg>;
> + vcc6-supply = <&vdd2_reg>;
> + vcc7-supply = <&vdd_ac_bat_reg>;
> + vccio-supply = <&vdd_ac_bat_reg>;
> +
> + regulators {
> + vdd1_reg: vdd1 {
> + regulator-name = "vddio_ddr_1v2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + vdd2_reg: vdd2 {
> + regulator-name = "vdd_1v5_gen";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> + vddctrl_reg: vddctrl {
> + regulator-name = "vdd_cpu,vdd_sys";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + vio_reg: vio {
> + regulator-name = "vdd_1v8_gen";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: ldo1 {
> + regulator-name = "vdd_pexa,vdd_pexb";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + ldo2_reg: ldo2 {
> + regulator-name = "vdd_sata,avdd_plle";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + /* LDO3 is not connected to anything */
> +
> + ldo4_reg: ldo4 {
> + regulator-name = "vdd_rtc";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: ldo5 {
> + regulator-name = "vddio_sdmmc,avdd_vdac";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo6_reg: ldo6 {
> + regulator-name = "avdd_dsi_csi,pwrdet_mipi";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo7_reg: ldo7 {
> + regulator-name = "vdd_pllm,x,u,a_p_c_s";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + ldo8_reg: ldo8 {
> + regulator-name = "vdd_ddr_hs";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> + };
> + };
> + };
> +
> + spi@7000da00 {
> + status = "okay";
> + spi-max-frequency = <25000000>;
> + spi-flash@1 {
> + compatible = "winbond,w25q32";
> + reg = <1>;
> + spi-max-frequency = <20000000>;
> + };
> + };
> +
> + ahub {
> + i2s@70080400 {
> + status = "okay";
> + };
> + };
> +
> + pmc {
> + status = "okay";
> + nvidia,invert-interrupt;
> + };
> +
> + sdhci@78000000 {
> + status = "okay";
> + cd-gpios = <&gpio 69 0>; /* gpio PI5 */
> + wp-gpios = <&gpio 155 0>; /* gpio PT3 */
> + power-gpios = <&gpio 31 0>; /* gpio PD7 */
> + bus-width = <4>;
> + };
> +
> + sdhci@78000600 {
> + status = "okay";
> + bus-width = <8>;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_ac_bat_reg: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vdd_ac_bat";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + cam_1v8_reg: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "cam_1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + gpio = <&gpio 220 0>; /* gpio PBB4 */
> + vin-supply = <&vio_reg>;
> + };
> +
> + cp_5v_reg: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "cp_5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + enable-active-high;
> + gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
> + };
> +
> + emmc_3v3_reg: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "emmc_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 25 0>; /* gpio PD1 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + modem_3v3_reg: regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "modem_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio 30 0>; /* gpio PD6 */
> + };
> +
> + pex_hvdd_3v3_reg: regulator@5 {
> + compatible = "regulator-fixed";
> + reg = <5>;
> + regulator-name = "pex_hvdd_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio 95 0>; /* gpio PL7 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_cam1_ldo_reg: regulator@6 {
> + compatible = "regulator-fixed";
> + reg = <6>;
> + regulator-name = "vdd_cam1_ldo";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + enable-active-high;
> + gpio = <&gpio 142 0>; /* gpio PR6 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_cam2_ldo_reg: regulator@7 {
> + compatible = "regulator-fixed";
> + reg = <7>;
> + regulator-name = "vdd_cam2_ldo";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + enable-active-high;
> + gpio = <&gpio 143 0>; /* gpio PR7 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_cam3_ldo_reg: regulator@8 {
> + compatible = "regulator-fixed";
> + reg = <8>;
> + regulator-name = "vdd_cam3_ldo";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio 144 0>; /* gpio PS0 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_com_reg: regulator@9 {
> + compatible = "regulator-fixed";
> + reg = <9>;
> + regulator-name = "vdd_com";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 24 0>; /* gpio PD0 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_fuse_3v3_reg: regulator@10 {
> + compatible = "regulator-fixed";
> + reg = <10>;
> + regulator-name = "vdd_fuse_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio 94 0>; /* gpio PL6 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_pnl1_reg: regulator@11 {
> + compatible = "regulator-fixed";
> + reg = <11>;
> + regulator-name = "vdd_pnl1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&gpio 92 0>; /* gpio PL4 */
> + vin-supply = <&sys_3v3_reg>;
> + };
> +
> + vdd_vid_reg: regulator@12 {
> + compatible = "regulator-fixed";
> + reg = <12>;
> + regulator-name = "vddio_vid";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio 152 0>; /* GPIO PT0 */
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_reg>;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-wm8903-cardhu",
> + "nvidia,tegra-audio-wm8903";
> + nvidia,model = "NVIDIA Tegra Cardhu";
> +
> + nvidia,audio-routing =
> + "Headphone Jack", "HPOUTR",
> + "Headphone Jack", "HPOUTL",
> + "Int Spk", "ROP",
> + "Int Spk", "RON",
> + "Int Spk", "LOP",
> + "Int Spk", "LON",
> + "Mic Jack", "MICBIAS",
> + "IN1L", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&wm8903>;
> +
> + nvidia,spkr-en-gpios = <&wm8903 2 0>;
> + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> deleted file mode 100644
> index 572a45b..0000000
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ /dev/null
> @@ -1,579 +0,0 @@
> -/include/ "skeleton.dtsi"
> -
> -/ {
> - compatible = "nvidia,tegra30";
> - interrupt-parent = <&intc>;
> -
> - aliases {
> - serial0 = &uarta;
> - serial1 = &uartb;
> - serial2 = &uartc;
> - serial3 = &uartd;
> - serial4 = &uarte;
> - };
> -
> - host1x {
> - compatible = "nvidia,tegra30-host1x", "simple-bus";
> - reg = <0x50000000 0x00024000>;
> - interrupts = <0 65 0x04 /* mpcore syncpt */
> - 0 67 0x04>; /* mpcore general */
> - clocks = <&tegra_car 28>;
> -
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - ranges = <0x54000000 0x54000000 0x04000000>;
> -
> - mpe {
> - compatible = "nvidia,tegra30-mpe";
> - reg = <0x54040000 0x00040000>;
> - interrupts = <0 68 0x04>;
> - clocks = <&tegra_car 60>;
> - };
> -
> - vi {
> - compatible = "nvidia,tegra30-vi";
> - reg = <0x54080000 0x00040000>;
> - interrupts = <0 69 0x04>;
> - clocks = <&tegra_car 164>;
> - };
> -
> - epp {
> - compatible = "nvidia,tegra30-epp";
> - reg = <0x540c0000 0x00040000>;
> - interrupts = <0 70 0x04>;
> - clocks = <&tegra_car 19>;
> - };
> -
> - isp {
> - compatible = "nvidia,tegra30-isp";
> - reg = <0x54100000 0x00040000>;
> - interrupts = <0 71 0x04>;
> - clocks = <&tegra_car 23>;
> - };
> -
> - gr2d {
> - compatible = "nvidia,tegra30-gr2d";
> - reg = <0x54140000 0x00040000>;
> - interrupts = <0 72 0x04>;
> - clocks = <&tegra_car 21>;
> - };
> -
> - gr3d {
> - compatible = "nvidia,tegra30-gr3d";
> - reg = <0x54180000 0x00040000>;
> - clocks = <&tegra_car 24 &tegra_car 98>;
> - clock-names = "3d", "3d2";
> - };
> -
> - dc@54200000 {
> - compatible = "nvidia,tegra30-dc";
> - reg = <0x54200000 0x00040000>;
> - interrupts = <0 73 0x04>;
> - clocks = <&tegra_car 27>, <&tegra_car 179>;
> - clock-names = "disp1", "parent";
> -
> - rgb {
> - status = "disabled";
> - };
> - };
> -
> - dc@54240000 {
> - compatible = "nvidia,tegra30-dc";
> - reg = <0x54240000 0x00040000>;
> - interrupts = <0 74 0x04>;
> - clocks = <&tegra_car 26>, <&tegra_car 179>;
> - clock-names = "disp2", "parent";
> -
> - rgb {
> - status = "disabled";
> - };
> - };
> -
> - hdmi {
> - compatible = "nvidia,tegra30-hdmi";
> - reg = <0x54280000 0x00040000>;
> - interrupts = <0 75 0x04>;
> - clocks = <&tegra_car 51>, <&tegra_car 189>;
> - clock-names = "hdmi", "parent";
> - status = "disabled";
> - };
> -
> - tvo {
> - compatible = "nvidia,tegra30-tvo";
> - reg = <0x542c0000 0x00040000>;
> - interrupts = <0 76 0x04>;
> - clocks = <&tegra_car 169>;
> - status = "disabled";
> - };
> -
> - dsi {
> - compatible = "nvidia,tegra30-dsi";
> - reg = <0x54300000 0x00040000>;
> - clocks = <&tegra_car 48>;
> - status = "disabled";
> - };
> - };
> -
> - timer@50004600 {
> - compatible = "arm,cortex-a9-twd-timer";
> - reg = <0x50040600 0x20>;
> - interrupts = <1 13 0xf04>;
> - };
> -
> - intc: interrupt-controller {
> - compatible = "arm,cortex-a9-gic";
> - reg = <0x50041000 0x1000
> - 0x50040100 0x0100>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - };
> -
> - cache-controller {
> - compatible = "arm,pl310-cache";
> - reg = <0x50043000 0x1000>;
> - arm,data-latency = <6 6 2>;
> - arm,tag-latency = <5 5 2>;
> - cache-unified;
> - cache-level = <2>;
> - };
> -
> - timer@60005000 {
> - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> - reg = <0x60005000 0x400>;
> - interrupts = <0 0 0x04
> - 0 1 0x04
> - 0 41 0x04
> - 0 42 0x04
> - 0 121 0x04
> - 0 122 0x04>;
> - };
> -
> - tegra_car: clock {
> - compatible = "nvidia,tegra30-car";
> - reg = <0x60006000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - apbdma: dma {
> - compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
> - reg = <0x6000a000 0x1400>;
> - interrupts = <0 104 0x04
> - 0 105 0x04
> - 0 106 0x04
> - 0 107 0x04
> - 0 108 0x04
> - 0 109 0x04
> - 0 110 0x04
> - 0 111 0x04
> - 0 112 0x04
> - 0 113 0x04
> - 0 114 0x04
> - 0 115 0x04
> - 0 116 0x04
> - 0 117 0x04
> - 0 118 0x04
> - 0 119 0x04
> - 0 128 0x04
> - 0 129 0x04
> - 0 130 0x04
> - 0 131 0x04
> - 0 132 0x04
> - 0 133 0x04
> - 0 134 0x04
> - 0 135 0x04
> - 0 136 0x04
> - 0 137 0x04
> - 0 138 0x04
> - 0 139 0x04
> - 0 140 0x04
> - 0 141 0x04
> - 0 142 0x04
> - 0 143 0x04>;
> - clocks = <&tegra_car 34>;
> - };
> -
> - ahb: ahb {
> - compatible = "nvidia,tegra30-ahb";
> - reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
> - };
> -
> - gpio: gpio {
> - compatible = "nvidia,tegra30-gpio";
> - reg = <0x6000d000 0x1000>;
> - interrupts = <0 32 0x04
> - 0 33 0x04
> - 0 34 0x04
> - 0 35 0x04
> - 0 55 0x04
> - 0 87 0x04
> - 0 89 0x04
> - 0 125 0x04>;
> - #gpio-cells = <2>;
> - gpio-controller;
> - #interrupt-cells = <2>;
> - interrupt-controller;
> - };
> -
> - pinmux: pinmux {
> - compatible = "nvidia,tegra30-pinmux";
> - reg = <0x70000868 0xd4 /* Pad control registers */
> - 0x70003000 0x3e4>; /* Mux registers */
> - };
> -
> - /*
> - * There are two serial driver i.e. 8250 based simple serial
> - * driver and APB DMA based serial driver for higher baudrate
> - * and performace. To enable the 8250 based driver, the compatible
> - * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
> - * the APB DMA based serial driver, the comptible is
> - * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
> - */
> - uarta: serial@70006000 {
> - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> - reg = <0x70006000 0x40>;
> - reg-shift = <2>;
> - interrupts = <0 36 0x04>;
> - clock-frequency = <408000000>;
> - nvidia,dma-request-selector = <&apbdma 8>;
> - clocks = <&tegra_car 6>;
> - status = "disabled";
> - };
> -
> - uartb: serial@70006040 {
> - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> - reg = <0x70006040 0x40>;
> - reg-shift = <2>;
> - clock-frequency = <408000000>;
> - interrupts = <0 37 0x04>;
> - nvidia,dma-request-selector = <&apbdma 9>;
> - clocks = <&tegra_car 160>;
> - status = "disabled";
> - };
> -
> - uartc: serial@70006200 {
> - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> - reg = <0x70006200 0x100>;
> - reg-shift = <2>;
> - clock-frequency = <408000000>;
> - interrupts = <0 46 0x04>;
> - nvidia,dma-request-selector = <&apbdma 10>;
> - clocks = <&tegra_car 55>;
> - status = "disabled";
> - };
> -
> - uartd: serial@70006300 {
> - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> - reg = <0x70006300 0x100>;
> - reg-shift = <2>;
> - clock-frequency = <408000000>;
> - interrupts = <0 90 0x04>;
> - nvidia,dma-request-selector = <&apbdma 19>;
> - clocks = <&tegra_car 65>;
> - status = "disabled";
> - };
> -
> - uarte: serial@70006400 {
> - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> - reg = <0x70006400 0x100>;
> - reg-shift = <2>;
> - clock-frequency = <408000000>;
> - interrupts = <0 91 0x04>;
> - nvidia,dma-request-selector = <&apbdma 20>;
> - clocks = <&tegra_car 66>;
> - status = "disabled";
> - };
> -
> - pwm: pwm {
> - compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
> - reg = <0x7000a000 0x100>;
> - #pwm-cells = <2>;
> - clocks = <&tegra_car 17>;
> - };
> -
> - rtc {
> - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
> - reg = <0x7000e000 0x100>;
> - interrupts = <0 2 0x04>;
> - };
> -
> - i2c@7000c000 {
> - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> - reg = <0x7000c000 0x100>;
> - interrupts = <0 38 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 12>, <&tegra_car 182>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000c400 {
> - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> - reg = <0x7000c400 0x100>;
> - interrupts = <0 84 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 54>, <&tegra_car 182>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000c500 {
> - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> - reg = <0x7000c500 0x100>;
> - interrupts = <0 92 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 67>, <&tegra_car 182>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000c700 {
> - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> - reg = <0x7000c700 0x100>;
> - interrupts = <0 120 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 103>, <&tegra_car 182>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - i2c@7000d000 {
> - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> - reg = <0x7000d000 0x100>;
> - interrupts = <0 53 0x04>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 47>, <&tegra_car 182>;
> - clock-names = "div-clk", "fast-clk";
> - status = "disabled";
> - };
> -
> - spi@7000d400 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000d400 0x200>;
> - interrupts = <0 59 0x04>;
> - nvidia,dma-request-selector = <&apbdma 15>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 41>;
> - status = "disabled";
> - };
> -
> - spi@7000d600 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000d600 0x200>;
> - interrupts = <0 82 0x04>;
> - nvidia,dma-request-selector = <&apbdma 16>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 44>;
> - status = "disabled";
> - };
> -
> - spi@7000d800 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000d480 0x200>;
> - interrupts = <0 83 0x04>;
> - nvidia,dma-request-selector = <&apbdma 17>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 46>;
> - status = "disabled";
> - };
> -
> - spi@7000da00 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000da00 0x200>;
> - interrupts = <0 93 0x04>;
> - nvidia,dma-request-selector = <&apbdma 18>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 68>;
> - status = "disabled";
> - };
> -
> - spi@7000dc00 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000dc00 0x200>;
> - interrupts = <0 94 0x04>;
> - nvidia,dma-request-selector = <&apbdma 27>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 104>;
> - status = "disabled";
> - };
> -
> - spi@7000de00 {
> - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> - reg = <0x7000de00 0x200>;
> - interrupts = <0 79 0x04>;
> - nvidia,dma-request-selector = <&apbdma 28>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&tegra_car 105>;
> - status = "disabled";
> - };
> -
> - kbc {
> - compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
> - reg = <0x7000e200 0x100>;
> - interrupts = <0 85 0x04>;
> - clocks = <&tegra_car 36>;
> - status = "disabled";
> - };
> -
> - pmc {
> - compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
> - reg = <0x7000e400 0x400>;
> - };
> -
> - memory-controller {
> - compatible = "nvidia,tegra30-mc";
> - reg = <0x7000f000 0x010
> - 0x7000f03c 0x1b4
> - 0x7000f200 0x028
> - 0x7000f284 0x17c>;
> - interrupts = <0 77 0x04>;
> - };
> -
> - iommu {
> - compatible = "nvidia,tegra30-smmu";
> - reg = <0x7000f010 0x02c
> - 0x7000f1f0 0x010
> - 0x7000f228 0x05c>;
> - nvidia,#asids = <4>; /* # of ASIDs */
> - dma-window = <0 0x40000000>; /* IOVA start & length */
> - nvidia,ahb = <&ahb>;
> - };
> -
> - ahub {
> - compatible = "nvidia,tegra30-ahub";
> - reg = <0x70080000 0x200
> - 0x70080200 0x100>;
> - interrupts = <0 103 0x04>;
> - nvidia,dma-request-selector = <&apbdma 1>;
> - clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
> - <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
> - <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
> - <&tegra_car 110>, <&tegra_car 162>;
> - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
> - "i2s3", "i2s4", "dam0", "dam1", "dam2",
> - "spdif_in";
> - ranges;
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - tegra_i2s0: i2s@70080300 {
> - compatible = "nvidia,tegra30-i2s";
> - reg = <0x70080300 0x100>;
> - nvidia,ahub-cif-ids = <4 4>;
> - clocks = <&tegra_car 30>;
> - status = "disabled";
> - };
> -
> - tegra_i2s1: i2s@70080400 {
> - compatible = "nvidia,tegra30-i2s";
> - reg = <0x70080400 0x100>;
> - nvidia,ahub-cif-ids = <5 5>;
> - clocks = <&tegra_car 11>;
> - status = "disabled";
> - };
> -
> - tegra_i2s2: i2s@70080500 {
> - compatible = "nvidia,tegra30-i2s";
> - reg = <0x70080500 0x100>;
> - nvidia,ahub-cif-ids = <6 6>;
> - clocks = <&tegra_car 18>;
> - status = "disabled";
> - };
> -
> - tegra_i2s3: i2s@70080600 {
> - compatible = "nvidia,tegra30-i2s";
> - reg = <0x70080600 0x100>;
> - nvidia,ahub-cif-ids = <7 7>;
> - clocks = <&tegra_car 101>;
> - status = "disabled";
> - };
> -
> - tegra_i2s4: i2s@70080700 {
> - compatible = "nvidia,tegra30-i2s";
> - reg = <0x70080700 0x100>;
> - nvidia,ahub-cif-ids = <8 8>;
> - clocks = <&tegra_car 102>;
> - status = "disabled";
> - };
> - };
> -
> - sdhci@78000000 {
> - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> - reg = <0x78000000 0x200>;
> - interrupts = <0 14 0x04>;
> - clocks = <&tegra_car 14>;
> - status = "disabled";
> - };
> -
> - sdhci@78000200 {
> - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> - reg = <0x78000200 0x200>;
> - interrupts = <0 15 0x04>;
> - clocks = <&tegra_car 9>;
> - status = "disabled";
> - };
> -
> - sdhci@78000400 {
> - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> - reg = <0x78000400 0x200>;
> - interrupts = <0 19 0x04>;
> - clocks = <&tegra_car 69>;
> - status = "disabled";
> - };
> -
> - sdhci@78000600 {
> - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> - reg = <0x78000600 0x200>;
> - interrupts = <0 31 0x04>;
> - clocks = <&tegra_car 15>;
> - status = "disabled";
> - };
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - cpu@0 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <0>;
> - };
> -
> - cpu@1 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <1>;
> - };
> -
> - cpu@2 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <2>;
> - };
> -
> - cpu@3 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a9";
> - reg = <3>;
> - };
> - };
> -
> - pmu {
> - compatible = "arm,cortex-a9-pmu";
> - interrupts = <0 144 0x04
> - 0 145 0x04
> - 0 146 0x04
> - 0 147 0x04>;
> - };
> -};
> diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
> new file mode 100644
> index 0000000..d25975e
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30.dtsip
> @@ -0,0 +1,579 @@
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "nvidia,tegra30";
> + interrupt-parent = <&intc>;
> +
> + aliases {
> + serial0 = &uarta;
> + serial1 = &uartb;
> + serial2 = &uartc;
> + serial3 = &uartd;
> + serial4 = &uarte;
> + };
> +
> + host1x {
> + compatible = "nvidia,tegra30-host1x", "simple-bus";
> + reg = <0x50000000 0x00024000>;
> + interrupts = <0 65 0x04 /* mpcore syncpt */
> + 0 67 0x04>; /* mpcore general */
> + clocks = <&tegra_car 28>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0x54000000 0x54000000 0x04000000>;
> +
> + mpe {
> + compatible = "nvidia,tegra30-mpe";
> + reg = <0x54040000 0x00040000>;
> + interrupts = <0 68 0x04>;
> + clocks = <&tegra_car 60>;
> + };
> +
> + vi {
> + compatible = "nvidia,tegra30-vi";
> + reg = <0x54080000 0x00040000>;
> + interrupts = <0 69 0x04>;
> + clocks = <&tegra_car 164>;
> + };
> +
> + epp {
> + compatible = "nvidia,tegra30-epp";
> + reg = <0x540c0000 0x00040000>;
> + interrupts = <0 70 0x04>;
> + clocks = <&tegra_car 19>;
> + };
> +
> + isp {
> + compatible = "nvidia,tegra30-isp";
> + reg = <0x54100000 0x00040000>;
> + interrupts = <0 71 0x04>;
> + clocks = <&tegra_car 23>;
> + };
> +
> + gr2d {
> + compatible = "nvidia,tegra30-gr2d";
> + reg = <0x54140000 0x00040000>;
> + interrupts = <0 72 0x04>;
> + clocks = <&tegra_car 21>;
> + };
> +
> + gr3d {
> + compatible = "nvidia,tegra30-gr3d";
> + reg = <0x54180000 0x00040000>;
> + clocks = <&tegra_car 24 &tegra_car 98>;
> + clock-names = "3d", "3d2";
> + };
> +
> + dc@54200000 {
> + compatible = "nvidia,tegra30-dc";
> + reg = <0x54200000 0x00040000>;
> + interrupts = <0 73 0x04>;
> + clocks = <&tegra_car 27>, <&tegra_car 179>;
> + clock-names = "disp1", "parent";
> +
> + rgb {
> + status = "disabled";
> + };
> + };
> +
> + dc@54240000 {
> + compatible = "nvidia,tegra30-dc";
> + reg = <0x54240000 0x00040000>;
> + interrupts = <0 74 0x04>;
> + clocks = <&tegra_car 26>, <&tegra_car 179>;
> + clock-names = "disp2", "parent";
> +
> + rgb {
> + status = "disabled";
> + };
> + };
> +
> + hdmi {
> + compatible = "nvidia,tegra30-hdmi";
> + reg = <0x54280000 0x00040000>;
> + interrupts = <0 75 0x04>;
> + clocks = <&tegra_car 51>, <&tegra_car 189>;
> + clock-names = "hdmi", "parent";
> + status = "disabled";
> + };
> +
> + tvo {
> + compatible = "nvidia,tegra30-tvo";
> + reg = <0x542c0000 0x00040000>;
> + interrupts = <0 76 0x04>;
> + clocks = <&tegra_car 169>;
> + status = "disabled";
> + };
> +
> + dsi {
> + compatible = "nvidia,tegra30-dsi";
> + reg = <0x54300000 0x00040000>;
> + clocks = <&tegra_car 48>;
> + status = "disabled";
> + };
> + };
> +
> + timer@50004600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0x50040600 0x20>;
> + interrupts = <1 13 0xf04>;
> + };
> +
> + intc: interrupt-controller {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0x50041000 0x1000
> + 0x50040100 0x0100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + cache-controller {
> + compatible = "arm,pl310-cache";
> + reg = <0x50043000 0x1000>;
> + arm,data-latency = <6 6 2>;
> + arm,tag-latency = <5 5 2>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + timer@60005000 {
> + compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> + reg = <0x60005000 0x400>;
> + interrupts = <0 0 0x04
> + 0 1 0x04
> + 0 41 0x04
> + 0 42 0x04
> + 0 121 0x04
> + 0 122 0x04>;
> + };
> +
> + tegra_car: clock {
> + compatible = "nvidia,tegra30-car";
> + reg = <0x60006000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apbdma: dma {
> + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
> + reg = <0x6000a000 0x1400>;
> + interrupts = <0 104 0x04
> + 0 105 0x04
> + 0 106 0x04
> + 0 107 0x04
> + 0 108 0x04
> + 0 109 0x04
> + 0 110 0x04
> + 0 111 0x04
> + 0 112 0x04
> + 0 113 0x04
> + 0 114 0x04
> + 0 115 0x04
> + 0 116 0x04
> + 0 117 0x04
> + 0 118 0x04
> + 0 119 0x04
> + 0 128 0x04
> + 0 129 0x04
> + 0 130 0x04
> + 0 131 0x04
> + 0 132 0x04
> + 0 133 0x04
> + 0 134 0x04
> + 0 135 0x04
> + 0 136 0x04
> + 0 137 0x04
> + 0 138 0x04
> + 0 139 0x04
> + 0 140 0x04
> + 0 141 0x04
> + 0 142 0x04
> + 0 143 0x04>;
> + clocks = <&tegra_car 34>;
> + };
> +
> + ahb: ahb {
> + compatible = "nvidia,tegra30-ahb";
> + reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
> + };
> +
> + gpio: gpio {
> + compatible = "nvidia,tegra30-gpio";
> + reg = <0x6000d000 0x1000>;
> + interrupts = <0 32 0x04
> + 0 33 0x04
> + 0 34 0x04
> + 0 35 0x04
> + 0 55 0x04
> + 0 87 0x04
> + 0 89 0x04
> + 0 125 0x04>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + };
> +
> + pinmux: pinmux {
> + compatible = "nvidia,tegra30-pinmux";
> + reg = <0x70000868 0xd4 /* Pad control registers */
> + 0x70003000 0x3e4>; /* Mux registers */
> + };
> +
> + /*
> + * There are two serial driver i.e. 8250 based simple serial
> + * driver and APB DMA based serial driver for higher baudrate
> + * and performace. To enable the 8250 based driver, the compatible
> + * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
> + * the APB DMA based serial driver, the comptible is
> + * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
> + */
> + uarta: serial@70006000 {
> + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> + reg = <0x70006000 0x40>;
> + reg-shift = <2>;
> + interrupts = <0 36 0x04>;
> + clock-frequency = <408000000>;
> + nvidia,dma-request-selector = <&apbdma 8>;
> + clocks = <&tegra_car 6>;
> + status = "disabled";
> + };
> +
> + uartb: serial@70006040 {
> + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> + reg = <0x70006040 0x40>;
> + reg-shift = <2>;
> + clock-frequency = <408000000>;
> + interrupts = <0 37 0x04>;
> + nvidia,dma-request-selector = <&apbdma 9>;
> + clocks = <&tegra_car 160>;
> + status = "disabled";
> + };
> +
> + uartc: serial@70006200 {
> + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> + reg = <0x70006200 0x100>;
> + reg-shift = <2>;
> + clock-frequency = <408000000>;
> + interrupts = <0 46 0x04>;
> + nvidia,dma-request-selector = <&apbdma 10>;
> + clocks = <&tegra_car 55>;
> + status = "disabled";
> + };
> +
> + uartd: serial@70006300 {
> + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> + reg = <0x70006300 0x100>;
> + reg-shift = <2>;
> + clock-frequency = <408000000>;
> + interrupts = <0 90 0x04>;
> + nvidia,dma-request-selector = <&apbdma 19>;
> + clocks = <&tegra_car 65>;
> + status = "disabled";
> + };
> +
> + uarte: serial@70006400 {
> + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
> + reg = <0x70006400 0x100>;
> + reg-shift = <2>;
> + clock-frequency = <408000000>;
> + interrupts = <0 91 0x04>;
> + nvidia,dma-request-selector = <&apbdma 20>;
> + clocks = <&tegra_car 66>;
> + status = "disabled";
> + };
> +
> + pwm: pwm {
> + compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
> + reg = <0x7000a000 0x100>;
> + #pwm-cells = <2>;
> + clocks = <&tegra_car 17>;
> + };
> +
> + rtc {
> + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
> + reg = <0x7000e000 0x100>;
> + interrupts = <0 2 0x04>;
> + };
> +
> + i2c@7000c000 {
> + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> + reg = <0x7000c000 0x100>;
> + interrupts = <0 38 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 12>, <&tegra_car 182>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000c400 {
> + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> + reg = <0x7000c400 0x100>;
> + interrupts = <0 84 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 54>, <&tegra_car 182>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000c500 {
> + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> + reg = <0x7000c500 0x100>;
> + interrupts = <0 92 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 67>, <&tegra_car 182>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000c700 {
> + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> + reg = <0x7000c700 0x100>;
> + interrupts = <0 120 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 103>, <&tegra_car 182>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + i2c@7000d000 {
> + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
> + reg = <0x7000d000 0x100>;
> + interrupts = <0 53 0x04>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 47>, <&tegra_car 182>;
> + clock-names = "div-clk", "fast-clk";
> + status = "disabled";
> + };
> +
> + spi@7000d400 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000d400 0x200>;
> + interrupts = <0 59 0x04>;
> + nvidia,dma-request-selector = <&apbdma 15>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 41>;
> + status = "disabled";
> + };
> +
> + spi@7000d600 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000d600 0x200>;
> + interrupts = <0 82 0x04>;
> + nvidia,dma-request-selector = <&apbdma 16>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 44>;
> + status = "disabled";
> + };
> +
> + spi@7000d800 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000d480 0x200>;
> + interrupts = <0 83 0x04>;
> + nvidia,dma-request-selector = <&apbdma 17>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 46>;
> + status = "disabled";
> + };
> +
> + spi@7000da00 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000da00 0x200>;
> + interrupts = <0 93 0x04>;
> + nvidia,dma-request-selector = <&apbdma 18>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 68>;
> + status = "disabled";
> + };
> +
> + spi@7000dc00 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000dc00 0x200>;
> + interrupts = <0 94 0x04>;
> + nvidia,dma-request-selector = <&apbdma 27>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 104>;
> + status = "disabled";
> + };
> +
> + spi@7000de00 {
> + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
> + reg = <0x7000de00 0x200>;
> + interrupts = <0 79 0x04>;
> + nvidia,dma-request-selector = <&apbdma 28>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car 105>;
> + status = "disabled";
> + };
> +
> + kbc {
> + compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
> + reg = <0x7000e200 0x100>;
> + interrupts = <0 85 0x04>;
> + clocks = <&tegra_car 36>;
> + status = "disabled";
> + };
> +
> + pmc {
> + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
> + reg = <0x7000e400 0x400>;
> + };
> +
> + memory-controller {
> + compatible = "nvidia,tegra30-mc";
> + reg = <0x7000f000 0x010
> + 0x7000f03c 0x1b4
> + 0x7000f200 0x028
> + 0x7000f284 0x17c>;
> + interrupts = <0 77 0x04>;
> + };
> +
> + iommu {
> + compatible = "nvidia,tegra30-smmu";
> + reg = <0x7000f010 0x02c
> + 0x7000f1f0 0x010
> + 0x7000f228 0x05c>;
> + nvidia,#asids = <4>; /* # of ASIDs */
> + dma-window = <0 0x40000000>; /* IOVA start & length */
> + nvidia,ahb = <&ahb>;
> + };
> +
> + ahub {
> + compatible = "nvidia,tegra30-ahub";
> + reg = <0x70080000 0x200
> + 0x70080200 0x100>;
> + interrupts = <0 103 0x04>;
> + nvidia,dma-request-selector = <&apbdma 1>;
> + clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
> + <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
> + <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
> + <&tegra_car 110>, <&tegra_car 162>;
> + clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
> + "i2s3", "i2s4", "dam0", "dam1", "dam2",
> + "spdif_in";
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + tegra_i2s0: i2s@70080300 {
> + compatible = "nvidia,tegra30-i2s";
> + reg = <0x70080300 0x100>;
> + nvidia,ahub-cif-ids = <4 4>;
> + clocks = <&tegra_car 30>;
> + status = "disabled";
> + };
> +
> + tegra_i2s1: i2s@70080400 {
> + compatible = "nvidia,tegra30-i2s";
> + reg = <0x70080400 0x100>;
> + nvidia,ahub-cif-ids = <5 5>;
> + clocks = <&tegra_car 11>;
> + status = "disabled";
> + };
> +
> + tegra_i2s2: i2s@70080500 {
> + compatible = "nvidia,tegra30-i2s";
> + reg = <0x70080500 0x100>;
> + nvidia,ahub-cif-ids = <6 6>;
> + clocks = <&tegra_car 18>;
> + status = "disabled";
> + };
> +
> + tegra_i2s3: i2s@70080600 {
> + compatible = "nvidia,tegra30-i2s";
> + reg = <0x70080600 0x100>;
> + nvidia,ahub-cif-ids = <7 7>;
> + clocks = <&tegra_car 101>;
> + status = "disabled";
> + };
> +
> + tegra_i2s4: i2s@70080700 {
> + compatible = "nvidia,tegra30-i2s";
> + reg = <0x70080700 0x100>;
> + nvidia,ahub-cif-ids = <8 8>;
> + clocks = <&tegra_car 102>;
> + status = "disabled";
> + };
> + };
> +
> + sdhci@78000000 {
> + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> + reg = <0x78000000 0x200>;
> + interrupts = <0 14 0x04>;
> + clocks = <&tegra_car 14>;
> + status = "disabled";
> + };
> +
> + sdhci@78000200 {
> + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> + reg = <0x78000200 0x200>;
> + interrupts = <0 15 0x04>;
> + clocks = <&tegra_car 9>;
> + status = "disabled";
> + };
> +
> + sdhci@78000400 {
> + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> + reg = <0x78000400 0x200>;
> + interrupts = <0 19 0x04>;
> + clocks = <&tegra_car 69>;
> + status = "disabled";
> + };
> +
> + sdhci@78000600 {
> + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
> + reg = <0x78000600 0x200>;
> + interrupts = <0 31 0x04>;
> + clocks = <&tegra_car 15>;
> + status = "disabled";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <3>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 144 0x04
> + 0 145 0x04
> + 0 146 0x04
> + 0 147 0x04>;
> + };
> +};
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-14 6:38 ` Hiroshi Doyu
(?)
@ 2013-02-14 17:54 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-14 17:54 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
I like the concept here; I was thinking about doing this today, but you
beat me to it:-) Feel free to create the Tegra30 header too, and modify
all the *.dts* files.
To address other comments in this thread: Yes, I think that we will want
to modify the clock driver to include this header to avoid
duplication/errors (that will require adjusting Linux's include path),
and also remove the list of IDs from the binding document; it can just
refer the the new header by name and cause the header to *be* part of
the binding document.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 17:54 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-14 17:54 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: linux-tegra, devicetree-discuss, Russell King, linux-arm-kernel,
linux-kernel
On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
I like the concept here; I was thinking about doing this today, but you
beat me to it:-) Feel free to create the Tegra30 header too, and modify
all the *.dts* files.
To address other comments in this thread: Yes, I think that we will want
to modify the clock driver to include this header to avoid
duplication/errors (that will require adjusting Linux's include path),
and also remove the list of IDs from the binding document; it can just
refer the the new header by name and cause the header to *be* part of
the binding document.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-14 17:54 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-14 17:54 UTC (permalink / raw)
To: linux-arm-kernel
On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> To replace magic number in "clocks = <&tegra_car 28>;"
I like the concept here; I was thinking about doing this today, but you
beat me to it:-) Feel free to create the Tegra30 header too, and modify
all the *.dts* files.
To address other comments in this thread: Yes, I think that we will want
to modify the clock driver to include this header to avoid
duplication/errors (that will require adjusting Linux's include path),
and also remove the list of IDs from the binding document; it can just
refer the the new header by name and cause the header to *be* part of
the binding document.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
2013-02-14 17:41 ` Rob Herring
@ 2013-02-14 18:31 ` Olof Johansson
0 siblings, 0 replies; 59+ messages in thread
From: Olof Johansson @ 2013-02-14 18:31 UTC (permalink / raw)
To: Rob Herring
Cc: Stephen Warren, Grant Likely, Arnd Bergmann,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On Thu, Feb 14, 2013 at 9:41 AM, Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Just a reminder to use -M for git format-patch. Why -M for format-patch
> is not the default I wonder.
Also, don't quote a huge patch just to make a 2-line comment. :-)
-M is likely not the default because classic patch does not understand it.
-Olof
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
@ 2013-02-14 18:31 ` Olof Johansson
0 siblings, 0 replies; 59+ messages in thread
From: Olof Johansson @ 2013-02-14 18:31 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Feb 14, 2013 at 9:41 AM, Rob Herring <robherring2@gmail.com> wrote:
> Just a reminder to use -M for git format-patch. Why -M for format-patch
> is not the default I wonder.
Also, don't quote a huge patch just to make a 2-line comment. :-)
-M is likely not the default because classic patch does not understand it.
-Olof
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/9] ARM: dt: add header to define GPIO flags
2013-02-13 21:33 ` Stephen Warren
@ 2013-02-14 20:48 ` Hiroshi Doyu
-1 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 20:48 UTC (permalink / raw)
To: swarren-3lzwWm7+Weoh9ZMKESR00Q
Cc: grant.likely-s3s/WqlpOiPyB63q8FvJNQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, olof-nZhT3qVonbNeoWH0uzbU5w,
arnd-r2nGTMty4D4, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote @ Wed, 13 Feb 2013 22:33:10 +0100:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Many GPIO device tree bindings use the same flags. Create a header to
> define those.
>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/gpio.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/arm/boot/dts/gpio.h
>
> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
> new file mode 100644
> index 0000000..4c9da69
> --- /dev/null
> +++ b/arch/arm/boot/dts/gpio.h
> @@ -0,0 +1,10 @@
> +/*
> + * This header provides constants for most GPIO bindings.
> + *
> + * Most GPIO bindings include a flags cell as part of the GPIO specifier.
> + * In most cases, the format of the flags cell uses the standard values
> + * defined in this header.
> + */
#ifdef _DTS_GPIO_H
#define _DTS_GPIO_H
> +
> +#define GPIO_ACTIVE_HIGH 0
> +#define GPIO_ACTIVE_LOW 1
#endif /* _DTS_GPIO_H */
To avoid multple inclusion problems, do we want the above
ifdef/define/endif for other DT header files as well?
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
@ 2013-02-14 20:48 ` Hiroshi Doyu
0 siblings, 0 replies; 59+ messages in thread
From: Hiroshi Doyu @ 2013-02-14 20:48 UTC (permalink / raw)
To: linux-arm-kernel
Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 13 Feb 2013 22:33:10 +0100:
> From: Stephen Warren <swarren@nvidia.com>
>
> Many GPIO device tree bindings use the same flags. Create a header to
> define those.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> arch/arm/boot/dts/gpio.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/arm/boot/dts/gpio.h
>
> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
> new file mode 100644
> index 0000000..4c9da69
> --- /dev/null
> +++ b/arch/arm/boot/dts/gpio.h
> @@ -0,0 +1,10 @@
> +/*
> + * This header provides constants for most GPIO bindings.
> + *
> + * Most GPIO bindings include a flags cell as part of the GPIO specifier.
> + * In most cases, the format of the flags cell uses the standard values
> + * defined in this header.
> + */
#ifdef _DTS_GPIO_H
#define _DTS_GPIO_H
> +
> +#define GPIO_ACTIVE_HIGH 0
> +#define GPIO_ACTIVE_LOW 1
#endif /* _DTS_GPIO_H */
To avoid multple inclusion problems, do we want the above
ifdef/define/endif for other DT header files as well?
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/9] ARM: dt: add header to define GPIO flags
2013-02-14 20:48 ` Hiroshi Doyu
@ 2013-02-14 23:29 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-14 23:29 UTC (permalink / raw)
To: Hiroshi Doyu
Cc: grant.likely-s3s/WqlpOiPyB63q8FvJNQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, olof-nZhT3qVonbNeoWH0uzbU5w,
arnd-r2nGTMty4D4, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On 02/14/2013 01:48 PM, Hiroshi Doyu wrote:
> Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote @ Wed, 13 Feb 2013 22:33:10 +0100:
>> Many GPIO device tree bindings use the same flags. Create a header to
>> define those.
... [discussion about adding include guards]
> To avoid multple inclusion problems, do we want the above
> ifdef/define/endif for other DT header files as well?
Yes, we should probably add include guards to all the files. I'll update
my patch series.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
@ 2013-02-14 23:29 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-14 23:29 UTC (permalink / raw)
To: linux-arm-kernel
On 02/14/2013 01:48 PM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 13 Feb 2013 22:33:10 +0100:
>> Many GPIO device tree bindings use the same flags. Create a header to
>> define those.
... [discussion about adding include guards]
> To avoid multple inclusion problems, do we want the above
> ifdef/define/endif for other DT header files as well?
Yes, we should probably add include guards to all the files. I'll update
my patch series.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-14 17:54 ` Stephen Warren
(?)
@ 2013-02-19 5:31 ` Shawn Guo
-1 siblings, 0 replies; 59+ messages in thread
From: Shawn Guo @ 2013-02-19 5:31 UTC (permalink / raw)
To: Stephen Warren
Cc: Hiroshi Doyu, linux-tegra, devicetree-discuss, Russell King,
linux-kernel, linux-arm-kernel
On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
>
> I like the concept here; I was thinking about doing this today, but you
> beat me to it:-) Feel free to create the Tegra30 header too, and modify
> all the *.dts* files.
>
> To address other comments in this thread: Yes, I think that we will want
> to modify the clock driver to include this header to avoid
> duplication/errors (that will require adjusting Linux's include path),
> and also remove the list of IDs from the binding document; it can just
> refer the the new header by name and cause the header to *be* part of
> the binding document.
I like it, since doing so will help us hijack kernel to have dts stay
in the tree rather than going to a separate repository :)
Seriously, is maintaining dts in a separate repository still a plan?
If yes, we will have duplication problem someday anyway.
For reason of it, I vote for having dts stay in the kernel tree.
Shawn
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-19 5:31 ` Shawn Guo
0 siblings, 0 replies; 59+ messages in thread
From: Shawn Guo @ 2013-02-19 5:31 UTC (permalink / raw)
To: Stephen Warren
Cc: Hiroshi Doyu, linux-tegra, devicetree-discuss, Russell King,
linux-kernel, linux-arm-kernel
On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
>
> I like the concept here; I was thinking about doing this today, but you
> beat me to it:-) Feel free to create the Tegra30 header too, and modify
> all the *.dts* files.
>
> To address other comments in this thread: Yes, I think that we will want
> to modify the clock driver to include this header to avoid
> duplication/errors (that will require adjusting Linux's include path),
> and also remove the list of IDs from the binding document; it can just
> refer the the new header by name and cause the header to *be* part of
> the binding document.
I like it, since doing so will help us hijack kernel to have dts stay
in the tree rather than going to a separate repository :)
Seriously, is maintaining dts in a separate repository still a plan?
If yes, we will have duplication problem someday anyway.
For reason of it, I vote for having dts stay in the kernel tree.
Shawn
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-19 5:31 ` Shawn Guo
0 siblings, 0 replies; 59+ messages in thread
From: Shawn Guo @ 2013-02-19 5:31 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
> > To replace magic number in "clocks = <&tegra_car 28>;"
>
> I like the concept here; I was thinking about doing this today, but you
> beat me to it:-) Feel free to create the Tegra30 header too, and modify
> all the *.dts* files.
>
> To address other comments in this thread: Yes, I think that we will want
> to modify the clock driver to include this header to avoid
> duplication/errors (that will require adjusting Linux's include path),
> and also remove the list of IDs from the binding document; it can just
> refer the the new header by name and cause the header to *be* part of
> the binding document.
I like it, since doing so will help us hijack kernel to have dts stay
in the tree rather than going to a separate repository :)
Seriously, is maintaining dts in a separate repository still a plan?
If yes, we will have duplication problem someday anyway.
For reason of it, I vote for having dts stay in the kernel tree.
Shawn
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
2013-02-19 5:31 ` Shawn Guo
(?)
@ 2013-02-19 17:35 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-19 17:35 UTC (permalink / raw)
To: Shawn Guo
Cc: Hiroshi Doyu, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 02/18/2013 10:31 PM, Shawn Guo wrote:
> On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
>> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
>>> To replace magic number in "clocks = <&tegra_car 28>;"
>>
>> I like the concept here; I was thinking about doing this today, but you
>> beat me to it:-) Feel free to create the Tegra30 header too, and modify
>> all the *.dts* files.
>>
>> To address other comments in this thread: Yes, I think that we will want
>> to modify the clock driver to include this header to avoid
>> duplication/errors (that will require adjusting Linux's include path),
>> and also remove the list of IDs from the binding document; it can just
>> refer the the new header by name and cause the header to *be* part of
>> the binding document.
>
> I like it, since doing so will help us hijack kernel to have dts stay
> in the tree rather than going to a separate repository :)
Well, at least the header files would need to stay in the kernel. The
.txt binding documentation wouldn't have to though.
I guess this is a good argument for not putting these header files into
Documentation/devicetree/bindings, and adding that to the include path,
but rather putting the headers somewhere else.
> Seriously, is maintaining dts in a separate repository still a plan?
> If yes, we will have duplication problem someday anyway.
>
> For reason of it, I vote for having dts stay in the kernel tree.
>
> Shawn
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-19 17:35 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-19 17:35 UTC (permalink / raw)
To: Shawn Guo
Cc: Hiroshi Doyu, linux-tegra, devicetree-discuss, Russell King,
linux-kernel, linux-arm-kernel
On 02/18/2013 10:31 PM, Shawn Guo wrote:
> On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
>> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
>>> To replace magic number in "clocks = <&tegra_car 28>;"
>>
>> I like the concept here; I was thinking about doing this today, but you
>> beat me to it:-) Feel free to create the Tegra30 header too, and modify
>> all the *.dts* files.
>>
>> To address other comments in this thread: Yes, I think that we will want
>> to modify the clock driver to include this header to avoid
>> duplication/errors (that will require adjusting Linux's include path),
>> and also remove the list of IDs from the binding document; it can just
>> refer the the new header by name and cause the header to *be* part of
>> the binding document.
>
> I like it, since doing so will help us hijack kernel to have dts stay
> in the tree rather than going to a separate repository :)
Well, at least the header files would need to stay in the kernel. The
.txt binding documentation wouldn't have to though.
I guess this is a good argument for not putting these header files into
Documentation/devicetree/bindings, and adding that to the include path,
but rather putting the headers somewhere else.
> Seriously, is maintaining dts in a separate repository still a plan?
> If yes, we will have duplication problem someday anyway.
>
> For reason of it, I vote for having dts stay in the kernel tree.
>
> Shawn
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/1] ARM: dt: add header to define tegra20 clocks
@ 2013-02-19 17:35 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-02-19 17:35 UTC (permalink / raw)
To: linux-arm-kernel
On 02/18/2013 10:31 PM, Shawn Guo wrote:
> On Thu, Feb 14, 2013 at 10:54:28AM -0700, Stephen Warren wrote:
>> On 02/13/2013 11:38 PM, Hiroshi Doyu wrote:
>>> To replace magic number in "clocks = <&tegra_car 28>;"
>>
>> I like the concept here; I was thinking about doing this today, but you
>> beat me to it:-) Feel free to create the Tegra30 header too, and modify
>> all the *.dts* files.
>>
>> To address other comments in this thread: Yes, I think that we will want
>> to modify the clock driver to include this header to avoid
>> duplication/errors (that will require adjusting Linux's include path),
>> and also remove the list of IDs from the binding document; it can just
>> refer the the new header by name and cause the header to *be* part of
>> the binding document.
>
> I like it, since doing so will help us hijack kernel to have dts stay
> in the tree rather than going to a separate repository :)
Well, at least the header files would need to stay in the kernel. The
.txt binding documentation wouldn't have to though.
I guess this is a good argument for not putting these header files into
Documentation/devicetree/bindings, and adding that to the include path,
but rather putting the headers somewhere else.
> Seriously, is maintaining dts in a separate repository still a plan?
> If yes, we will have duplication problem someday anyway.
>
> For reason of it, I vote for having dts stay in the kernel tree.
>
> Shawn
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/9] ARM: dt: add header to define GPIO flags
2013-02-13 21:33 ` Stephen Warren
@ 2013-03-04 8:34 ` Grant Likely
-1 siblings, 0 replies; 59+ messages in thread
From: Grant Likely @ 2013-03-04 8:34 UTC (permalink / raw)
To: Stephen Warren, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On Wed, 13 Feb 2013 14:33:10 -0700, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Many GPIO device tree bindings use the same flags. Create a header to
> define those.
>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/gpio.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/arm/boot/dts/gpio.h
>
> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
> new file mode 100644
> index 0000000..4c9da69
> --- /dev/null
> +++ b/arch/arm/boot/dts/gpio.h
Stephen, you know better than this. This is common code. Don't put it
under arch/arm.
g.
> @@ -0,0 +1,10 @@
> +/*
> + * This header provides constants for most GPIO bindings.
> + *
> + * Most GPIO bindings include a flags cell as part of the GPIO specifier.
> + * In most cases, the format of the flags cell uses the standard values
> + * defined in this header.
> + */
> +
> +#define GPIO_ACTIVE_HIGH 0
> +#define GPIO_ACTIVE_LOW 1
> --
> 1.7.10.4
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
@ 2013-03-04 8:34 ` Grant Likely
0 siblings, 0 replies; 59+ messages in thread
From: Grant Likely @ 2013-03-04 8:34 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 13 Feb 2013 14:33:10 -0700, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Many GPIO device tree bindings use the same flags. Create a header to
> define those.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> arch/arm/boot/dts/gpio.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/arm/boot/dts/gpio.h
>
> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
> new file mode 100644
> index 0000000..4c9da69
> --- /dev/null
> +++ b/arch/arm/boot/dts/gpio.h
Stephen, you know better than this. This is common code. Don't put it
under arch/arm.
g.
> @@ -0,0 +1,10 @@
> +/*
> + * This header provides constants for most GPIO bindings.
> + *
> + * Most GPIO bindings include a flags cell as part of the GPIO specifier.
> + * In most cases, the format of the flags cell uses the standard values
> + * defined in this header.
> + */
> +
> +#define GPIO_ACTIVE_HIGH 0
> +#define GPIO_ACTIVE_LOW 1
> --
> 1.7.10.4
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
2013-02-13 21:33 ` [PATCH 6/9] ARM: tegra: use pre-processor for all device trees Stephen Warren
@ 2013-03-04 8:44 ` Grant Likely
0 siblings, 0 replies; 59+ messages in thread
From: Grant Likely @ 2013-03-04 8:44 UTC (permalink / raw)
To: Stephen Warren, Rob Herring, Olof Johansson, Arnd Bergmann
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On Wed, 13 Feb 2013 14:33:15 -0700, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> This enables a C pre-processor pass on all Tegra device trees. This
> allows future use of #defines and header files in order to define names
> for various constants, such as the IDs and flags in GPIO specifiers.
> Use of those features will increase the readability of the device tree
> files.
>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
> arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
Two comments;
1) Use '-M' when posting patches that rename files, it makes for a much
smaller diff. :-)
2) Now that I see this patch, it's rather striking that .dtsp and .dtsip
are horible extensions (so are .dts and .dtsi for that matter, but
this just kicks it up a notch). Can we not do something better?
Can we do something else here; First, does the old style /include/
directives cause any problems existing .dts files? I know it won't work
if a /include/'ed file uses a #include statement, but the other way
around should be fine. Can we instead move the entire tree over to
building with the CPP enabled? Overall it will be less horribleness for
the end user.
g.
> arch/arm/boot/dts/tegra114-pluto.dts | 21 -
> arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
> arch/arm/boot/dts/tegra114.dtsi | 153 -----
> arch/arm/boot/dts/tegra114.dtsip | 153 +++++
> arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
> arch/arm/boot/dts/tegra20-colibri-512.dtsip | 491 ++++++++++++++++
> arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
> arch/arm/boot/dts/tegra20-harmony.dtsp | 660 ++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
> arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
> arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
> arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
> arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
> arch/arm/boot/dts/tegra20-paz00.dtsp | 505 +++++++++++++++++
> arch/arm/boot/dts/tegra20-plutux.dts | 56 --
> arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-seaboard.dts | 812 ---------------------------
> arch/arm/boot/dts/tegra20-seaboard.dtsp | 812 +++++++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
> arch/arm/boot/dts/tegra20-tamonten.dtsip | 489 ++++++++++++++++
> arch/arm/boot/dts/tegra20-tec.dts | 56 --
> arch/arm/boot/dts/tegra20-tec.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
> arch/arm/boot/dts/tegra20-trimslice.dtsp | 367 ++++++++++++
> arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
> arch/arm/boot/dts/tegra20-ventana.dtsp | 611 ++++++++++++++++++++
> arch/arm/boot/dts/tegra20-whistler.dts | 563 -------------------
> arch/arm/boot/dts/tegra20-whistler.dtsp | 563 +++++++++++++++++++
> arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
> arch/arm/boot/dts/tegra20.dtsip | 556 ++++++++++++++++++
> arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
> arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
> arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
> arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
> arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
> arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 -----------------
> arch/arm/boot/dts/tegra30-cardhu.dtsip | 500 +++++++++++++++++
> arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
> arch/arm/boot/dts/tegra30.dtsip | 579 +++++++++++++++++++
> 42 files changed, 7157 insertions(+), 7157 deletions(-)
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
@ 2013-03-04 8:44 ` Grant Likely
0 siblings, 0 replies; 59+ messages in thread
From: Grant Likely @ 2013-03-04 8:44 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 13 Feb 2013 14:33:15 -0700, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This enables a C pre-processor pass on all Tegra device trees. This
> allows future use of #defines and header files in order to define names
> for various constants, such as the IDs and flags in GPIO specifiers.
> Use of those features will increase the readability of the device tree
> files.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
> arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
Two comments;
1) Use '-M' when posting patches that rename files, it makes for a much
smaller diff. :-)
2) Now that I see this patch, it's rather striking that .dtsp and .dtsip
are horible extensions (so are .dts and .dtsi for that matter, but
this just kicks it up a notch). Can we not do something better?
Can we do something else here; First, does the old style /include/
directives cause any problems existing .dts files? I know it won't work
if a /include/'ed file uses a #include statement, but the other way
around should be fine. Can we instead move the entire tree over to
building with the CPP enabled? Overall it will be less horribleness for
the end user.
g.
> arch/arm/boot/dts/tegra114-pluto.dts | 21 -
> arch/arm/boot/dts/tegra114-pluto.dtsp | 21 +
> arch/arm/boot/dts/tegra114.dtsi | 153 -----
> arch/arm/boot/dts/tegra114.dtsip | 153 +++++
> arch/arm/boot/dts/tegra20-colibri-512.dtsi | 491 ----------------
> arch/arm/boot/dts/tegra20-colibri-512.dtsip | 491 ++++++++++++++++
> arch/arm/boot/dts/tegra20-harmony.dts | 660 ----------------------
> arch/arm/boot/dts/tegra20-harmony.dtsp | 660 ++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-iris-512.dts | 89 ---
> arch/arm/boot/dts/tegra20-iris-512.dtsp | 89 +++
> arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 --
> arch/arm/boot/dts/tegra20-medcom-wide.dtsp | 58 ++
> arch/arm/boot/dts/tegra20-paz00.dts | 505 -----------------
> arch/arm/boot/dts/tegra20-paz00.dtsp | 505 +++++++++++++++++
> arch/arm/boot/dts/tegra20-plutux.dts | 56 --
> arch/arm/boot/dts/tegra20-plutux.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-seaboard.dts | 812 ---------------------------
> arch/arm/boot/dts/tegra20-seaboard.dtsp | 812 +++++++++++++++++++++++++++
> arch/arm/boot/dts/tegra20-tamonten.dtsi | 489 ----------------
> arch/arm/boot/dts/tegra20-tamonten.dtsip | 489 ++++++++++++++++
> arch/arm/boot/dts/tegra20-tec.dts | 56 --
> arch/arm/boot/dts/tegra20-tec.dtsp | 56 ++
> arch/arm/boot/dts/tegra20-trimslice.dts | 367 ------------
> arch/arm/boot/dts/tegra20-trimslice.dtsp | 367 ++++++++++++
> arch/arm/boot/dts/tegra20-ventana.dts | 611 --------------------
> arch/arm/boot/dts/tegra20-ventana.dtsp | 611 ++++++++++++++++++++
> arch/arm/boot/dts/tegra20-whistler.dts | 563 -------------------
> arch/arm/boot/dts/tegra20-whistler.dtsp | 563 +++++++++++++++++++
> arch/arm/boot/dts/tegra20.dtsi | 556 ------------------
> arch/arm/boot/dts/tegra20.dtsip | 556 ++++++++++++++++++
> arch/arm/boot/dts/tegra30-beaver.dts | 373 ------------
> arch/arm/boot/dts/tegra30-beaver.dtsp | 373 ++++++++++++
> arch/arm/boot/dts/tegra30-cardhu-a02.dts | 93 ---
> arch/arm/boot/dts/tegra30-cardhu-a02.dtsp | 93 +++
> arch/arm/boot/dts/tegra30-cardhu-a04.dts | 104 ----
> arch/arm/boot/dts/tegra30-cardhu-a04.dtsp | 104 ++++
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 500 -----------------
> arch/arm/boot/dts/tegra30-cardhu.dtsip | 500 +++++++++++++++++
> arch/arm/boot/dts/tegra30.dtsi | 579 -------------------
> arch/arm/boot/dts/tegra30.dtsip | 579 +++++++++++++++++++
> 42 files changed, 7157 insertions(+), 7157 deletions(-)
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 1/9] ARM: dt: add header to define GPIO flags
2013-03-04 8:34 ` Grant Likely
@ 2013-03-04 17:13 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-03-04 17:13 UTC (permalink / raw)
To: Grant Likely
Cc: Rob Herring, Olof Johansson, Arnd Bergmann,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On 03/04/2013 01:34 AM, Grant Likely wrote:
> On Wed, 13 Feb 2013 14:33:10 -0700, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Many GPIO device tree bindings use the same flags. Create a header to
>> define those.
>>
>> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/gpio.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>> create mode 100644 arch/arm/boot/dts/gpio.h
>>
>> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
>> new file mode 100644
>> index 0000000..4c9da69
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/gpio.h
>
> Stephen, you know better than this. This is common code. Don't put it
> under arch/arm.
In V2 of the patch which modifies the dtc+cpp include path:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-February/028591.html
... I have moved the common headers to top-level include/dt-bindings, so
it is shared across all arch. I didn't repost all the changes to the *.h
and *.dts* files yet; I was waiting for any comments on the patch above.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 1/9] ARM: dt: add header to define GPIO flags
@ 2013-03-04 17:13 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-03-04 17:13 UTC (permalink / raw)
To: linux-arm-kernel
On 03/04/2013 01:34 AM, Grant Likely wrote:
> On Wed, 13 Feb 2013 14:33:10 -0700, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Many GPIO device tree bindings use the same flags. Create a header to
>> define those.
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>> arch/arm/boot/dts/gpio.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>> create mode 100644 arch/arm/boot/dts/gpio.h
>>
>> diff --git a/arch/arm/boot/dts/gpio.h b/arch/arm/boot/dts/gpio.h
>> new file mode 100644
>> index 0000000..4c9da69
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/gpio.h
>
> Stephen, you know better than this. This is common code. Don't put it
> under arch/arm.
In V2 of the patch which modifies the dtc+cpp include path:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-February/028591.html
... I have moved the common headers to top-level include/dt-bindings, so
it is shared across all arch. I didn't repost all the changes to the *.h
and *.dts* files yet; I was waiting for any comments on the patch above.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
2013-03-04 8:44 ` Grant Likely
@ 2013-03-04 17:22 ` Stephen Warren
-1 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-03-04 17:22 UTC (permalink / raw)
To: Grant Likely
Cc: Rob Herring, Olof Johansson, Arnd Bergmann,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On 03/04/2013 01:44 AM, Grant Likely wrote:
> On Wed, 13 Feb 2013 14:33:15 -0700, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> This enables a C pre-processor pass on all Tegra device trees. This
>> allows future use of #defines and header files in order to define names
>> for various constants, such as the IDs and flags in GPIO specifiers.
>> Use of those features will increase the readability of the device tree
>> files.
>>
>> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
>> arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
>
> Two comments;
> 1) Use '-M' when posting patches that rename files, it makes for a much
> smaller diff. :-)
Yes, I forgot this:-( I reposted just this patch with -M IIRC (but maybe
I don't!)
> 2) Now that I see this patch, it's rather striking that .dtsp and .dtsip
> are horible extensions (so are .dts and .dtsi for that matter, but
> this just kicks it up a notch). Can we not do something better?
>
> Can we do something else here; First, does the old style /include/
> directives cause any problems existing .dts files? I know it won't work
> if a /include/'ed file uses a #include statement, but the other way
> around should be fine. Can we instead move the entire tree over to
> building with the CPP enabled? Overall it will be less horribleness for
> the end user.
I think syntactically, now that the *.dtsp->*.dtb rule uses gcc -x
assembler-with-cpp, the only issue would be *.dts that have a # in the
very first column. That's probably rare enough that we can ignore the
issue. A quick grep certainly shows this isn't an issue with any file in
arch/*/boot/dts in the kernel tree right now.
The main reason I didn't go down this route is that dependencies don't
work, at least with the kbuild rules as currently implemented. The
reason is that with /include/, dependencies are emitted by dtc, and with
#include, dependencies are emitted by cpp. Currently, the *.dts->*.dtb
rules only look at the dtc-emitted dependencies, and the *.dtsp->*.dtb
rules only look at the cpp-emitted dependencies.
The solution here would be to augment the dtc+cpp rule to merge together
the two sets of dependencies in a post-processing step. This might be
easy; I'd have to look at the existing dependency post-processing script
to see if it already handles a case like this.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 6/9] ARM: tegra: use pre-processor for all device trees
@ 2013-03-04 17:22 ` Stephen Warren
0 siblings, 0 replies; 59+ messages in thread
From: Stephen Warren @ 2013-03-04 17:22 UTC (permalink / raw)
To: linux-arm-kernel
On 03/04/2013 01:44 AM, Grant Likely wrote:
> On Wed, 13 Feb 2013 14:33:15 -0700, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> This enables a C pre-processor pass on all Tegra device trees. This
>> allows future use of #defines and header files in order to define names
>> for various constants, such as the IDs and flags in GPIO specifiers.
>> Use of those features will increase the readability of the device tree
>> files.
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>> arch/arm/boot/dts/tegra114-dalmore.dts | 21 -
>> arch/arm/boot/dts/tegra114-dalmore.dtsp | 21 +
>
> Two comments;
> 1) Use '-M' when posting patches that rename files, it makes for a much
> smaller diff. :-)
Yes, I forgot this:-( I reposted just this patch with -M IIRC (but maybe
I don't!)
> 2) Now that I see this patch, it's rather striking that .dtsp and .dtsip
> are horible extensions (so are .dts and .dtsi for that matter, but
> this just kicks it up a notch). Can we not do something better?
>
> Can we do something else here; First, does the old style /include/
> directives cause any problems existing .dts files? I know it won't work
> if a /include/'ed file uses a #include statement, but the other way
> around should be fine. Can we instead move the entire tree over to
> building with the CPP enabled? Overall it will be less horribleness for
> the end user.
I think syntactically, now that the *.dtsp->*.dtb rule uses gcc -x
assembler-with-cpp, the only issue would be *.dts that have a # in the
very first column. That's probably rare enough that we can ignore the
issue. A quick grep certainly shows this isn't an issue with any file in
arch/*/boot/dts in the kernel tree right now.
The main reason I didn't go down this route is that dependencies don't
work, at least with the kbuild rules as currently implemented. The
reason is that with /include/, dependencies are emitted by dtc, and with
#include, dependencies are emitted by cpp. Currently, the *.dts->*.dtb
rules only look at the dtc-emitted dependencies, and the *.dtsp->*.dtb
rules only look at the cpp-emitted dependencies.
The solution here would be to augment the dtc+cpp rule to merge together
the two sets of dependencies in a post-processing step. This might be
easy; I'd have to look at the existing dependency post-processing script
to see if it already handles a case like this.
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2013-03-04 17:22 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-02-13 21:33 [PATCH 0/9] ARM: tegra: use new dtc+cpp feature Stephen Warren
2013-02-13 21:33 ` Stephen Warren
[not found] ` <1360791198-29462-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-13 21:33 ` [PATCH 1/9] ARM: dt: add header to define GPIO flags Stephen Warren
2013-02-13 21:33 ` Stephen Warren
[not found] ` <1360791198-29462-2-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-14 20:48 ` Hiroshi Doyu
2013-02-14 20:48 ` Hiroshi Doyu
[not found] ` <20130214.224816.1898594449880044716.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-14 23:29 ` Stephen Warren
2013-02-14 23:29 ` Stephen Warren
2013-03-04 8:34 ` Grant Likely
2013-03-04 8:34 ` Grant Likely
2013-03-04 17:13 ` Stephen Warren
2013-03-04 17:13 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 2/9] ARM: dt: add header to define IRQ flags Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 3/9] ARM: dt: create a DT header for the GIC Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 4/9] ARM: tegra: device tree whitespace cleanup Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 5/9] ARM: tegra: fix sort order of USB PHY nodes Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 6/9] ARM: tegra: use pre-processor for all device trees Stephen Warren
[not found] ` <1360791198-29462-7-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-14 17:41 ` Rob Herring
[not found] ` <511D21E7.5090307-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-02-14 18:31 ` Olof Johansson
2013-02-14 18:31 ` Olof Johansson
2013-03-04 8:44 ` Grant Likely
2013-03-04 8:44 ` Grant Likely
2013-03-04 17:22 ` Stephen Warren
2013-03-04 17:22 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 7/9] ARM: tegra: create a DT header defining GPIO IDs Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 8/9] ARM: tegra: convert device tree files to use GPIO defines Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 21:33 ` [PATCH 9/9] ARM: tegra: convert device tree files to use IRQ defines Stephen Warren
2013-02-13 21:33 ` Stephen Warren
2013-02-13 22:21 ` [PATCH 6/9] ARM: tegra: use pre-processor for all device trees Stephen Warren
2013-02-13 22:21 ` Stephen Warren
2013-02-14 6:38 ` [PATCH 1/1] ARM: dt: add header to define tegra20 clocks Hiroshi Doyu
2013-02-14 6:38 ` Hiroshi Doyu
2013-02-14 6:38 ` Hiroshi Doyu
[not found] ` <1360823899-17846-1-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-14 10:12 ` Peter De Schrijver
2013-02-14 10:12 ` Peter De Schrijver
2013-02-14 10:12 ` Peter De Schrijver
[not found] ` <20130214101220.GI3073-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-02-14 13:42 ` Hiroshi Doyu
2013-02-14 13:42 ` Hiroshi Doyu
2013-02-14 13:42 ` Hiroshi Doyu
[not found] ` <20130214.154250.475978229890081002.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-14 14:58 ` Peter De Schrijver
2013-02-14 14:58 ` Peter De Schrijver
2013-02-14 14:58 ` Peter De Schrijver
2013-02-14 17:54 ` Stephen Warren
2013-02-14 17:54 ` Stephen Warren
2013-02-14 17:54 ` Stephen Warren
2013-02-19 5:31 ` Shawn Guo
2013-02-19 5:31 ` Shawn Guo
2013-02-19 5:31 ` Shawn Guo
[not found] ` <20130219053148.GC3108-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-02-19 17:35 ` Stephen Warren
2013-02-19 17:35 ` Stephen Warren
2013-02-19 17:35 ` Stephen Warren
2013-02-14 17:03 ` [PATCH 0/9] ARM: tegra: use new dtc+cpp feature Tony Lindgren
2013-02-14 17:03 ` Tony Lindgren
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.