[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 README                     |   10 ++++++++++
 arch/arm/cpu/armv7/start.S |   19 +++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/README b/README
index d8cb394..f2b1c88 100644
--- a/README
+++ b/README
@@ -485,6 +485,16 @@ The following options need to be configured:
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 
+		CONFIG_ARM_ERRATA_742230
+		CONFIG_ARM_ERRATA_743622
+		CONFIG_ARM_ERRATA_751472
+
+		If set, the workarounds for these ARM errata are applied early
+		during U-Boot startup. Note that these options force the
+		workarounds to be applied; no CPU-type/version detection
+		exists, unlike the similar options in the Linux kernel. Do not
+		set these options unless they apply!
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 6b59529d..30f02d3 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
+
+#ifdef CONFIG_ARM_ERRATA_742230
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 4		@ set bit #4
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 6		@ set bit #6
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_751472
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 11	@ set bit #11
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)
 
-- 
1.7.10.4

[U-Boot] [PATCH 2/3] ARM: tegra: enable some CPU errata workarounds

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such,
some CPU errata exist, and must be worked around.

These must be worked around in the bootloader, since in general, the
kernel (especially a multi-platform kernel) needs to support being
launched in non-secure mode (normal world), and hence may not be able
to write to the CP15 register to enable these workarounds.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 include/configs/tegra20-common.h |    6 ++++++
 include/configs/tegra30-common.h |    6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 33e5f52..186e023 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -26,6 +26,12 @@
 #include "tegra-common.h"
 
 /*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_742230
+#define CONFIG_ARM_ERRATA_751472
+
+/*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 04517e1..f6c07c6 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -26,6 +26,12 @@
 #include "tegra-common.h"
 
 /*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+
+/*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
-- 
1.7.10.4

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/cpu/armv7/Makefile            |    2 +-
 arch/arm/cpu/armv7/mx6/Makefile        |    1 -
 arch/arm/cpu/armv7/mx6/lowlevel_init.S |   35 --------------------------------
 arch/arm/cpu/armv7/mx6/soc.c           |    4 ++++
 include/configs/mx6_common.h           |   23 +++++++++++++++++++++
 include/configs/mx6qarm2.h             |    3 +++
 include/configs/mx6qsabre_common.h     |    3 +++
 include/configs/mx6qsabrelite.h        |    3 +++
 8 files changed, 37 insertions(+), 37 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/mx6/lowlevel_init.S
 create mode 100644 include/configs/mx6_common.h

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee8c2b3..4668b3c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index cbce411..4f9ca68 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 COBJS	= soc.o clock.o
-SOBJS   = lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
deleted file mode 100644
index 7b60ca7..0000000
--- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-.section ".text.init", "x"
-
-#include <linux/linkage.h>
-
-.macro init_arm_errata
-	/* ARM erratum ID #743622 */
-	mrc	p15, 0, r10, c15, c0, 1		/* read diagnostic register */
-	orr	r10, r10, #1 << 6		/* set bit #6 */
-	/* ARM erratum ID #751472 */
-	orr	r10, r10, #1 << 11		/* set bit #11 */
-	mcr	p15, 0, r10, c15, c0, 1		/* write diagnostic register */
-.endm
-
-ENTRY(lowlevel_init)
-	init_arm_errata
-	mov pc, lr
-ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a8aad5d..8176249 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -193,3 +193,7 @@ const struct boot_mode soc_boot_modes[] = {
 	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 	{NULL,		0},
 };
+
+void s_init(void)
+{
+}
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
new file mode 100644
index 0000000..b333937
--- /dev/null
+++ b/include/configs/mx6_common.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MX6_COMMON_H
+#define __MX6_COMMON_H
+
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+
+#endif
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 138e460..bd52cde 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -24,6 +24,9 @@
 
 #define CONFIG_MX6
 #define CONFIG_MX6Q
+
+#include "mx6_common.h"
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index d76357c..b634997 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -19,6 +19,9 @@
 
 #define CONFIG_MX6
 #define CONFIG_MX6Q
+
+#include "mx6_common.h"
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 752f098..682012e 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -24,6 +24,9 @@
 
 #define CONFIG_MX6
 #define CONFIG_MX6Q
+
+#include "mx6_common.h"
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
1.7.10.4

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Fabio Estevam]

On Tue, Feb 26, 2013 at 7:28 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Now that U-Boot has common CONFIG_ options to work around some ARM CPU
> errata, enable the relevant options on MX6, and remove the custom
> lowlevel_init.S, since it's just duplicated code now.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Looks good, thanks.

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Liu Hui-R64343]

>-----Original Message-----
From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
>On Behalf Of Stephen Warren
>Sent: Wednesday, February 27, 2013 6:28 AM
>To: Tom Warren
>Cc: u-boot at lists.denx.de; Stephen Warren
>Subject: [U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config
>options
>
>From: Stephen Warren <swarren@nvidia.com>
>
>Now that U-Boot has common CONFIG_ options to work around some ARM
>CPU errata, enable the relevant options on MX6, and remove the custom
>lowlevel_init.S, since it's just duplicated code now.
>
>Signed-off-by: Stephen Warren <swarren@nvidia.com>
>---
> arch/arm/cpu/armv7/Makefile            |    2 +-
> arch/arm/cpu/armv7/mx6/Makefile        |    1 -
> arch/arm/cpu/armv7/mx6/lowlevel_init.S |   35 --------------------------------
> arch/arm/cpu/armv7/mx6/soc.c           |    4 ++++
> include/configs/mx6_common.h           |   23 +++++++++++++++++++++
> include/configs/mx6qarm2.h             |    3 +++
> include/configs/mx6qsabre_common.h     |    3 +++
> include/configs/mx6qsabrelite.h        |    3 +++
> 8 files changed, 37 insertions(+), 37 deletions(-)  delete mode 100644
>arch/arm/cpu/armv7/mx6/lowlevel_init.S
> create mode 100644 include/configs/mx6_common.h

Acked-by: Jason Liu <r64343@freescale.com>

>
>diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
>index ee8c2b3..4668b3c 100644
>--- a/arch/arm/cpu/armv7/Makefile
>+++ b/arch/arm/cpu/armv7/Makefile
>@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
> COBJS	+= cpu.o
> COBJS	+= syslib.o
>
>-ifneq
>($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_T
>EGRA),)
>+ifneq
>+($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_
>TEGRA)$(C
>+ONFIG_MX6),)
> SOBJS	+= lowlevel_init.o
> endif
>
>diff --git a/arch/arm/cpu/armv7/mx6/Makefile
>b/arch/arm/cpu/armv7/mx6/Makefile index cbce411..4f9ca68 100644
>--- a/arch/arm/cpu/armv7/mx6/Makefile
>+++ b/arch/arm/cpu/armv7/mx6/Makefile
>@@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
> LIB	= $(obj)lib$(SOC).o
>
> COBJS	= soc.o clock.o
>-SOBJS   = lowlevel_init.o
>
> SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
>diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S
>b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
>deleted file mode 100644
>index 7b60ca7..0000000

[..]
>--
>1.7.10.4
>
>_______________________________________________
>U-Boot mailing list
>U-Boot at lists.denx.de
>http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Simon Glass]

On Tue, Feb 26, 2013 at 2:28 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Various errata exist in the Cortex-A9 CPU, and may be worked around by
> setting some bits in a CP15 diagnostic register. Add code to implement
> the workarounds, enabled by new CONFIG_ options.
>
> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
> and modified to remove the logic to conditionally apply the WAR (since we
> know exactly which CPU we're running on given the U-Boot configuration),
> and use r0 instead of r10 for consistency with the rest of U-Boot's
> cpu_init_cp15().
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Simon Glass <sjg@chromium.org>

Good to have. Although I wonder why we wouldn't want to probe it in
U-Boot as with Linux?

> ---
>  README                     |   10 ++++++++++
>  arch/arm/cpu/armv7/start.S |   19 +++++++++++++++++++
>  2 files changed, 29 insertions(+)
>
> diff --git a/README b/README
> index d8cb394..f2b1c88 100644
> --- a/README
> +++ b/README
> @@ -485,6 +485,16 @@ The following options need to be configured:
>                 Thumb2 this flag will result in Thumb2 code generated by
>                 GCC.
>
> +               CONFIG_ARM_ERRATA_742230
> +               CONFIG_ARM_ERRATA_743622
> +               CONFIG_ARM_ERRATA_751472
> +
> +               If set, the workarounds for these ARM errata are applied early
> +               during U-Boot startup. Note that these options force the
> +               workarounds to be applied; no CPU-type/version detection
> +               exists, unlike the similar options in the Linux kernel. Do not
> +               set these options unless they apply!
> +
>  - Linux Kernel Interface:
>                 CONFIG_CLOCKS_IN_MHZ
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 6b59529d..30f02d3 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15)
>         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
>  #endif
>         mcr     p15, 0, r0, c1, c0, 0
> +
> +#ifdef CONFIG_ARM_ERRATA_742230
> +       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
> +       orr     r0, r0, #1 << 4         @ set bit #4
> +       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_743622
> +       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
> +       orr     r0, r0, #1 << 6         @ set bit #6
> +       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_751472
> +       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
> +       orr     r0, r0, #1 << 11        @ set bit #11
> +       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
> +#endif
> +
>         mov     pc, lr                  @ back to my caller
>  ENDPROC(cpu_init_cp15)
>
> --
> 1.7.10.4
>

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Stephen Warren]

On 02/27/2013 05:30 PM, Simon Glass wrote:
> On Tue, Feb 26, 2013 at 2:28 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Various errata exist in the Cortex-A9 CPU, and may be worked around by
>> setting some bits in a CP15 diagnostic register. Add code to implement
>> the workarounds, enabled by new CONFIG_ options.
>>
>> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
>> and modified to remove the logic to conditionally apply the WAR (since we
>> know exactly which CPU we're running on given the U-Boot configuration),
>> and use r0 instead of r10 for consistency with the rest of U-Boot's
>> cpu_init_cp15().
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> 
> Acked-by: Simon Glass <sjg@chromium.org>
> 
> Good to have. Although I wonder why we wouldn't want to probe it in
> U-Boot as with Linux?

I figured it wasn't worth the complexity initially. Right now, U-Boot is
built for a specific board (or just perhaps a small set of almost
identical boards), so we know exactly which CPU rev is present. If this
becomes false (e.g. DT works so well we can do a combined
Tegra20+Tegra30 U-Boot), we can always add the conditional logic in when
we need it.

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Simon Glass]

HI Stephen,

On Wed, Feb 27, 2013 at 4:36 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 02/27/2013 05:30 PM, Simon Glass wrote:
>> On Tue, Feb 26, 2013 at 2:28 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> From: Stephen Warren <swarren@nvidia.com>
>>>
>>> Various errata exist in the Cortex-A9 CPU, and may be worked around by
>>> setting some bits in a CP15 diagnostic register. Add code to implement
>>> the workarounds, enabled by new CONFIG_ options.
>>>
>>> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
>>> and modified to remove the logic to conditionally apply the WAR (since we
>>> know exactly which CPU we're running on given the U-Boot configuration),
>>> and use r0 instead of r10 for consistency with the rest of U-Boot's
>>> cpu_init_cp15().
>>>
>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>> Good to have. Although I wonder why we wouldn't want to probe it in
>> U-Boot as with Linux?
>
> I figured it wasn't worth the complexity initially. Right now, U-Boot is
> built for a specific board (or just perhaps a small set of almost
> identical boards), so we know exactly which CPU rev is present. If this
> becomes false (e.g. DT works so well we can do a combined
> Tegra20+Tegra30 U-Boot), we can always add the conditional logic in when
> we need it.

Fair enough, thank you.

Regards,
Simon

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Stephen Warren]

On 02/26/2013 03:28 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Various errata exist in the Cortex-A9 CPU, and may be worked around by
> setting some bits in a CP15 diagnostic register. Add code to implement
> the workarounds, enabled by new CONFIG_ options.
> 
> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
> and modified to remove the logic to conditionally apply the WAR (since we
> know exactly which CPU we're running on given the U-Boot configuration),
> and use r0 instead of r10 for consistency with the rest of U-Boot's
> cpu_init_cp15().

Hmmm. Lets hold off on this series; there are some conditions under
which the kernel has to be able to apply these WARs anyway (e.g. SMP CPU
power saving), which may impact which of the WARs the bootloader should
apply even when booting the initial CPU 0. I'll repost once that's been
resolved.

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Stephen Warren]

On 02/28/2013 10:08 AM, Stephen Warren wrote:
> On 02/26/2013 03:28 PM, Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Various errata exist in the Cortex-A9 CPU, and may be worked around by
>> setting some bits in a CP15 diagnostic register. Add code to implement
>> the workarounds, enabled by new CONFIG_ options.
>>
>> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
>> and modified to remove the logic to conditionally apply the WAR (since we
>> know exactly which CPU we're running on given the U-Boot configuration),
>> and use r0 instead of r10 for consistency with the rest of U-Boot's
>> cpu_init_cp15().
> 
> Hmmm. Lets hold off on this series; there are some conditions under
> which the kernel has to be able to apply these WARs anyway (e.g. SMP CPU
> power saving), which may impact which of the WARs the bootloader should
> apply even when booting the initial CPU 0. I'll repost once that's been
> resolved.

Tom,

It looks like the bootloader should always apply these WARs for CPU 0.
We just have to make sure that the kernel applies them for CPUs 1..n
if/when running in secure mode.

In other words, I think these patches are good to go in as-is. Since
there are no changes to the patches, I won't repost them, unless you
need me to.

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Tom Warren]

Stephen,

> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Friday, March 01, 2013 2:54 PM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren
> Subject: Re: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata
> workarounds
> 
> On 02/28/2013 10:08 AM, Stephen Warren wrote:
> > On 02/26/2013 03:28 PM, Stephen Warren wrote:
> >> From: Stephen Warren <swarren@nvidia.com>
> >>
> >> Various errata exist in the Cortex-A9 CPU, and may be worked around
> >> by setting some bits in a CP15 diagnostic register. Add code to
> >> implement the workarounds, enabled by new CONFIG_ options.
> >>
> >> This code was taken from the Linux kernel, v3.8,
> >> arch/arm/mm/proc-v7.S, and modified to remove the logic to
> >> conditionally apply the WAR (since we know exactly which CPU we're
> >> running on given the U-Boot configuration), and use r0 instead of r10
> >> for consistency with the rest of U-Boot's cpu_init_cp15().
> >
> > Hmmm. Lets hold off on this series; there are some conditions under
> > which the kernel has to be able to apply these WARs anyway (e.g. SMP
> > CPU power saving), which may impact which of the WARs the bootloader
> > should apply even when booting the initial CPU 0. I'll repost once
> > that's been resolved.
> 
> Tom,
> 
> It looks like the bootloader should always apply these WARs for CPU 0.
> We just have to make sure that the kernel applies them for CPUs 1..n
> if/when running in secure mode.
> 
> In other words, I think these patches are good to go in as-is. Since there are
> no changes to the patches, I won't repost them, unless you need me to.

No, I'll take 'em into /next as-is next week. Thanks

--
nvpublic

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Tom Warren]

Stephen & Albert,

> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Friday, March 01, 2013 2:54 PM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren
> Subject: Re: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata
> workarounds
> 
> On 02/28/2013 10:08 AM, Stephen Warren wrote:
> > On 02/26/2013 03:28 PM, Stephen Warren wrote:
> >> From: Stephen Warren <swarren@nvidia.com>
> >>
> >> Various errata exist in the Cortex-A9 CPU, and may be worked around
> >> by setting some bits in a CP15 diagnostic register. Add code to
> >> implement the workarounds, enabled by new CONFIG_ options.
> >>
> >> This code was taken from the Linux kernel, v3.8,
> >> arch/arm/mm/proc-v7.S, and modified to remove the logic to
> >> conditionally apply the WAR (since we know exactly which CPU we're
> >> running on given the U-Boot configuration), and use r0 instead of r10
> >> for consistency with the rest of U-Boot's cpu_init_cp15().
> >
> > Hmmm. Lets hold off on this series; there are some conditions under
> > which the kernel has to be able to apply these WARs anyway (e.g. SMP
> > CPU power saving), which may impact which of the WARs the bootloader
> > should apply even when booting the initial CPU 0. I'll repost once
> > that's been resolved.
> 
> Tom,
> 
> It looks like the bootloader should always apply these WARs for CPU 0.
> We just have to make sure that the kernel applies them for CPUs 1..n if/when
> running in secure mode.
> 
> In other words, I think these patches are good to go in as-is. Since there
> are no changes to the patches, I won't repost them, unless you need me to.

I can take these in via the Tegra tree, but the bulk of the changes are for ARM, not Tegra.
Albert - do you want to take this directly into the ARM repo, or would you prefer me to take it?

Tom
--
nvpublic

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Albert ARIBAUD]

Hi Tom,

On Mon, 4 Mar 2013 08:30:11 -0800, Tom Warren <TWarren@nvidia.com>
wrote:

> Stephen & Albert,
> 
> > -----Original Message-----
> > From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> > Sent: Friday, March 01, 2013 2:54 PM
> > To: Tom Warren
> > Cc: u-boot at lists.denx.de; Stephen Warren
> > Subject: Re: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata
> > workarounds
> > 
> > On 02/28/2013 10:08 AM, Stephen Warren wrote:
> > > On 02/26/2013 03:28 PM, Stephen Warren wrote:
> > >> From: Stephen Warren <swarren@nvidia.com>
> > >>
> > >> Various errata exist in the Cortex-A9 CPU, and may be worked around
> > >> by setting some bits in a CP15 diagnostic register. Add code to
> > >> implement the workarounds, enabled by new CONFIG_ options.
> > >>
> > >> This code was taken from the Linux kernel, v3.8,
> > >> arch/arm/mm/proc-v7.S, and modified to remove the logic to
> > >> conditionally apply the WAR (since we know exactly which CPU we're
> > >> running on given the U-Boot configuration), and use r0 instead of r10
> > >> for consistency with the rest of U-Boot's cpu_init_cp15().
> > >
> > > Hmmm. Lets hold off on this series; there are some conditions under
> > > which the kernel has to be able to apply these WARs anyway (e.g. SMP
> > > CPU power saving), which may impact which of the WARs the bootloader
> > > should apply even when booting the initial CPU 0. I'll repost once
> > > that's been resolved.
> > 
> > Tom,
> > 
> > It looks like the bootloader should always apply these WARs for CPU 0.
> > We just have to make sure that the kernel applies them for CPUs 1..n if/when
> > running in secure mode.
> > 
> > In other words, I think these patches are good to go in as-is. Since there
> > are no changes to the patches, I won't repost them, unless you need me to.
> 
> I can take these in via the Tegra tree, but the bulk of the changes are for ARM, not Tegra.
> Albert - do you want to take this directly into the ARM repo, or would you prefer me to take it?

I will take them in tonight.

> Tom
> --
> nvpublic

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Tom Warren]

Albert,

> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
> Sent: Monday, March 04, 2013 11:00 AM
> To: Tom Warren
> Cc: Stephen Warren; u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata
> workarounds
> 
> Hi Tom,
> 
> On Mon, 4 Mar 2013 08:30:11 -0800, Tom Warren <TWarren@nvidia.com>
> wrote:
> 
> > Stephen & Albert,
> >
> > > -----Original Message-----
> > > From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> > > Sent: Friday, March 01, 2013 2:54 PM
> > > To: Tom Warren
> > > Cc: u-boot at lists.denx.de; Stephen Warren
> > > Subject: Re: [U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9
> > > errata workarounds
> > >
> > > On 02/28/2013 10:08 AM, Stephen Warren wrote:
> > > > On 02/26/2013 03:28 PM, Stephen Warren wrote:
> > > >> From: Stephen Warren <swarren@nvidia.com>
> > > >>
> > > >> Various errata exist in the Cortex-A9 CPU, and may be worked
> > > >> around by setting some bits in a CP15 diagnostic register. Add
> > > >> code to implement the workarounds, enabled by new CONFIG_ options.
> > > >>
> > > >> This code was taken from the Linux kernel, v3.8,
> > > >> arch/arm/mm/proc-v7.S, and modified to remove the logic to
> > > >> conditionally apply the WAR (since we know exactly which CPU
> > > >> we're running on given the U-Boot configuration), and use r0
> > > >> instead of r10 for consistency with the rest of U-Boot's
> cpu_init_cp15().
> > > >
> > > > Hmmm. Lets hold off on this series; there are some conditions
> > > > under which the kernel has to be able to apply these WARs anyway
> > > > (e.g. SMP CPU power saving), which may impact which of the WARs
> > > > the bootloader should apply even when booting the initial CPU 0.
> > > > I'll repost once that's been resolved.
> > >
> > > Tom,
> > >
> > > It looks like the bootloader should always apply these WARs for CPU 0.
> > > We just have to make sure that the kernel applies them for CPUs 1..n
> > > if/when running in secure mode.
> > >
> > > In other words, I think these patches are good to go in as-is. Since
> > > there are no changes to the patches, I won't repost them, unless you
> need me to.
> >
> > I can take these in via the Tegra tree, but the bulk of the changes are
> for ARM, not Tegra.
> > Albert - do you want to take this directly into the ARM repo, or would you
> prefer me to take it?
> 
> I will take them in tonight.
Thanks. I'll assign the Tegra patch to you in Patchwork & take 'em out of u-boot-tegra/next.

Tom
> 
> > Tom
> 
> Amicalement,
> --
> Albert.
--
nvpublic

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Stefano Babic]

On 26/02/2013 23:28, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Now that U-Boot has common CONFIG_ options to work around some ARM CPU
> errata, enable the relevant options on MX6, and remove the custom
> lowlevel_init.S, since it's just duplicated code now.
> 
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---

Hi Stephen,

applied to u-boot-imx. It is not effective until Alber apply 1/3, but it
does not hurt.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Stephen Warren]

On 03/07/2013 10:24 AM, Stefano Babic wrote:
> On 26/02/2013 23:28, Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Now that U-Boot has common CONFIG_ options to work around some ARM CPU
>> errata, enable the relevant options on MX6, and remove the custom
>> lowlevel_init.S, since it's just duplicated code now.
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
> 
> Hi Stephen,
> 
> applied to u-boot-imx. It is not effective until Alber apply 1/3, but it
> does not hurt.

If you do that, then won't the imx6-specific WAR code be removed before
the generic implementation is added, so that there will be a period
where the WAR won't be enabled? I suppose if you send your pull request
after Albert has merged the generic implementation there won't be an
issue in u-boot-arm, but until u-boot-imx picks up the latest
u-boot-arm, the issue will exist there.

[U-Boot] [PATCH 3/3] ARM: mx6: use common CPU errata config options

[Stefano Babic]

On 07/03/2013 20:19, Stephen Warren wrote:
> On 03/07/2013 10:24 AM, Stefano Babic wrote:
>> On 26/02/2013 23:28, Stephen Warren wrote:
>>> From: Stephen Warren <swarren@nvidia.com>
>>>
>>> Now that U-Boot has common CONFIG_ options to work around some ARM CPU
>>> errata, enable the relevant options on MX6, and remove the custom
>>> lowlevel_init.S, since it's just duplicated code now.
>>>
>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>> ---
>>
>> Hi Stephen,
>>
>> applied to u-boot-imx. It is not effective until Alber apply 1/3, but it
>> does not hurt.
> 
> If you do that, then won't the imx6-specific WAR code be removed before
> the generic implementation is added, so that there will be a period
> where the WAR won't be enabled?

You're right - there is a period where it is not enabled. I hope it is
quite short, and I will track this patchset to check when flows into
u-boot-arm.

> I suppose if you send your pull request
> after Albert has merged the generic implementation there won't be an
> issue in u-boot-arm, but until u-boot-imx picks up the latest
> u-boot-arm, the issue will exist there.

Right - there is some "grey zone" when a patchset belongs to different
areas. My supposition (please correct if I am wrong) is that this
patchset is ready to be merged and will not require another iteration,
and I do not want to delay it while expecting something from my side.
When Albert will pick it up the rest, everything will be fine.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/3] ARM: implement some Cortex-A9 errata workarounds

[Albert ARIBAUD]

Hi Stephen,

On Tue, 26 Feb 2013 15:28:27 -0700, Stephen Warren
<swarren@wwwdotorg.org> wrote:

> From: Stephen Warren <swarren@nvidia.com>
> 
> Various errata exist in the Cortex-A9 CPU, and may be worked around by
> setting some bits in a CP15 diagnostic register. Add code to implement
> the workarounds, enabled by new CONFIG_ options.
> 
> This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
> and modified to remove the logic to conditionally apply the WAR (since we
> know exactly which CPU we're running on given the U-Boot configuration),
> and use r0 instead of r10 for consistency with the rest of U-Boot's
> cpu_init_cp15().
> 
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  README                     |   10 ++++++++++
>  arch/arm/cpu/armv7/start.S |   19 +++++++++++++++++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/README b/README
> index d8cb394..f2b1c88 100644
> --- a/README
> +++ b/README
> @@ -485,6 +485,16 @@ The following options need to be configured:
>  		Thumb2 this flag will result in Thumb2 code generated by
>  		GCC.
>  
> +		CONFIG_ARM_ERRATA_742230
> +		CONFIG_ARM_ERRATA_743622
> +		CONFIG_ARM_ERRATA_751472
> +
> +		If set, the workarounds for these ARM errata are applied early
> +		during U-Boot startup. Note that these options force the
> +		workarounds to be applied; no CPU-type/version detection
> +		exists, unlike the similar options in the Linux kernel. Do not
> +		set these options unless they apply!
> +
>  - Linux Kernel Interface:
>  		CONFIG_CLOCKS_IN_MHZ
>  
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 6b59529d..30f02d3 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15)
>  	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
>  #endif
>  	mcr	p15, 0, r0, c1, c0, 0
> +
> +#ifdef CONFIG_ARM_ERRATA_742230
> +	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
> +	orr	r0, r0, #1 << 4		@ set bit #4
> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_743622
> +	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
> +	orr	r0, r0, #1 << 6		@ set bit #6
> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_751472
> +	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
> +	orr	r0, r0, #1 << 11	@ set bit #11
> +	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
> +#endif
> +
>  	mov	pc, lr			@ back to my caller
>  ENDPROC(cpu_init_cp15)
>  

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 2/3] ARM: tegra: enable some CPU errata workarounds

[Albert ARIBAUD]

Hi Stephen,

On Tue, 26 Feb 2013 15:28:28 -0700, Stephen Warren
<swarren@wwwdotorg.org> wrote:

> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such,
> some CPU errata exist, and must be worked around.
> 
> These must be worked around in the bootloader, since in general, the
> kernel (especially a multi-platform kernel) needs to support being
> launched in non-secure mode (normal world), and hence may not be able
> to write to the CP15 register to enable these workarounds.
> 
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  include/configs/tegra20-common.h |    6 ++++++
>  include/configs/tegra30-common.h |    6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
> index 33e5f52..186e023 100644
> --- a/include/configs/tegra20-common.h
> +++ b/include/configs/tegra20-common.h
> @@ -26,6 +26,12 @@
>  #include "tegra-common.h"
>  
>  /*
> + * Errata configuration
> + */
> +#define CONFIG_ARM_ERRATA_742230
> +#define CONFIG_ARM_ERRATA_751472
> +
> +/*
>   * NS16550 Configuration
>   */
>  #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
> diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
> index 04517e1..f6c07c6 100644
> --- a/include/configs/tegra30-common.h
> +++ b/include/configs/tegra30-common.h
> @@ -26,6 +26,12 @@
>  #include "tegra-common.h"
>  
>  /*
> + * Errata configuration
> + */
> +#define CONFIG_ARM_ERRATA_743622
> +#define CONFIG_ARM_ERRATA_751472
> +
> +/*
>   * NS16550 Configuration
>   */
>  #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.