* [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
2018-08-15 18:20 [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask Ley Foon Tan
@ 2018-08-15 10:21 ` Marek Vasut
2018-08-15 10:32 ` Ley Foon Tan
0 siblings, 1 reply; 4+ messages in thread
From: Marek Vasut @ 2018-08-15 10:21 UTC (permalink / raw)
To: u-boot
On 08/15/2018 08:20 PM, Ley Foon Tan wrote:
> Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> index 813dff2..297f9e1 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> @@ -146,9 +146,9 @@ struct socfpga_system_manager {
> #define SYSMGR_FPGAINTF_SDMMC BIT(8)
> #define SYSMGR_FPGAINTF_SPIM0 BIT(16)
> #define SYSMGR_FPGAINTF_SPIM1 BIT(24)
> -#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
> -#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
> -#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
Wasn't the point here to unreset the OCP bits alongside the standard
EMAC resets too ?
> +#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
> +#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
> +#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
>
> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
> #define SYSMGR_SDMMC_DRVSEL_SHIFT 0
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
2018-08-15 10:21 ` Marek Vasut
@ 2018-08-15 10:32 ` Ley Foon Tan
2018-08-15 10:40 ` Marek Vasut
0 siblings, 1 reply; 4+ messages in thread
From: Ley Foon Tan @ 2018-08-15 10:32 UTC (permalink / raw)
To: u-boot
On Wed, Aug 15, 2018 at 6:21 PM, Marek Vasut <marex@denx.de> wrote:
> On 08/15/2018 08:20 PM, Ley Foon Tan wrote:
>> Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>> arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> index 813dff2..297f9e1 100644
>> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> @@ -146,9 +146,9 @@ struct socfpga_system_manager {
>> #define SYSMGR_FPGAINTF_SDMMC BIT(8)
>> #define SYSMGR_FPGAINTF_SPIM0 BIT(16)
>> #define SYSMGR_FPGAINTF_SPIM1 BIT(24)
>> -#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
>> -#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
>> -#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
>
> Wasn't the point here to unreset the OCP bits alongside the standard
> EMAC resets too ?
No, these registers are nothing related to reset. These for FPGA
interface registers if we route the peripheral pins to use FPGA IO.
>
>> +#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
>> +#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
>> +#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
>>
>> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
>> #define SYSMGR_SDMMC_DRVSEL_SHIFT 0
>>
>
>
> --
Regards
Ley Foon
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
2018-08-15 10:32 ` Ley Foon Tan
@ 2018-08-15 10:40 ` Marek Vasut
0 siblings, 0 replies; 4+ messages in thread
From: Marek Vasut @ 2018-08-15 10:40 UTC (permalink / raw)
To: u-boot
On 08/15/2018 12:32 PM, Ley Foon Tan wrote:
> On Wed, Aug 15, 2018 at 6:21 PM, Marek Vasut <marex@denx.de> wrote:
>> On 08/15/2018 08:20 PM, Ley Foon Tan wrote:
>>> Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
>>>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>> arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++---
>>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>>> index 813dff2..297f9e1 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>>> @@ -146,9 +146,9 @@ struct socfpga_system_manager {
>>> #define SYSMGR_FPGAINTF_SDMMC BIT(8)
>>> #define SYSMGR_FPGAINTF_SPIM0 BIT(16)
>>> #define SYSMGR_FPGAINTF_SPIM1 BIT(24)
>>> -#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
>>> -#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
>>> -#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
>>
>> Wasn't the point here to unreset the OCP bits alongside the standard
>> EMAC resets too ?
> No, these registers are nothing related to reset. These for FPGA
> interface registers if we route the peripheral pins to use FPGA IO.
OK, applied.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
@ 2018-08-15 18:20 Ley Foon Tan
2018-08-15 10:21 ` Marek Vasut
0 siblings, 1 reply; 4+ messages in thread
From: Ley Foon Tan @ 2018-08-15 18:20 UTC (permalink / raw)
To: u-boot
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
index 813dff2..297f9e1 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -146,9 +146,9 @@ struct socfpga_system_manager {
#define SYSMGR_FPGAINTF_SDMMC BIT(8)
#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
-#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
-#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
-#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
+#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
--
2.2.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2018-08-15 18:20 [U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask Ley Foon Tan
2018-08-15 10:21 ` Marek Vasut
2018-08-15 10:32 ` Ley Foon Tan
2018-08-15 10:40 ` Marek Vasut
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