* [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support
@ 2013-05-28 8:55 Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
` (6 more replies)
0 siblings, 7 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This series contain the support for Freescale Vybrid VF610 CPU and VF610TWR board.
Vybird devices are built on an asymmetrical-multiprocessing architecture
using ARM cores. The families in the Vybrid portfolio span entry-level,
single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs
with multiple communication and connectivity options.
Part of the Vybrid platform, VF610 is a dual-core eMPU combining the ARM
Cortex A5 and Cortex M4 cores.
VF610 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI.
VF610 also shares some IPs with ColdFire family, such as eDMA and DSPI.
VF610 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU.
More documents for this soc can be found at:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID
To align with the description in the above documents, "VF610" is used as the SoC name instead of "MVF600".
The u-boot runs on Cortex A5 core.
Changes in v4:
- Rename "MVF600" to "VF610"
- Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled
- Reorganize the definitions
- Correct the spaces and tabs
- Rename mvf_pins.h to iomux-vf610.h
- Add README.vf610 about fuse assignments for MAC addresses
- Rename directory name 'mvf600' to 'vf610'
- Rename directory 'arch-mvf600' to 'arch-vf610'
- Add Vybrid VF610 to mxc_ocotp document
- Rename directory name 'mvf600twr' to 'vf610twr'
- Rename mvf600twr.h to vf610twr.h
- Use NEW_PAD_CTRL instead of MUX_PAD_CTRL
- Remove CONFIG_ETHPRIME option
- Add CONFIG_CMD_MEMSET option
Changes in v3:
- Rename the common functions and enums
- Move the structure definitions to imx-regs.h
- Define PAD_CTL_PUE with PKE enabled
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
- Replace BOOT_FROM by BOOT_OFFSET
- Enable CONFIG_OF_LIBFDT option
- Add useful define instead of raw number
- Use clrsetbits_le32 to set the single bits
- Move setup_iomux_enet() to board_early_init_f and remove board_eth_init()
- Remove redundant define
- Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h
Changes in v2:
- Remove vybrid-common directory
- Rename directory name 'vybrid' to 'mvf600'
- Add generic.c file
- Rewrite get_reset_cause() to make it readable
- Remove reset_cpu(), and use the function in imx_watchdog.c
- Rewrite timer.c file
- Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
- Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
- Remove useless CONFIG_SYS_ defines
- Move CONFIG_MACH_TYPE to board configuration file
- Define C structures and access C structures to set/read registers
- Remove useless errata
- Remove useless macros
- Rename directory 'arch-vybrid' to 'arch-mvf600'
- Use common iomux-v3 code
- Use common FEC driver fec_mxc.c
- Add watchdog support
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
----------------------------------------------------------------
Alison Wang (7):
arm: vf610: Add IOMUX support for Vybrid VF610
arm: vf610: Add Vybrid VF610 CPU support
net: fec_mxc: Add support for Vybrid VF610
arm: vf610: Add watchdog support for Vybrid VF610
arm: vf610: Add uart support for Vybrid VF610
arm: vf610: Add Vybrid VF610 to mxc_ocotp document
arm: vf610: Add basic support for Vybrid VF610TWR board
MAINTAINERS | 4 +
Makefile | 2 +-
arch/arm/cpu/armv7/vf610/Makefile | 42 +++++++++++
arch/arm/cpu/armv7/vf610/generic.c | 324 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/vf610/timer.c | 103 ++++++++++++++++++++++++++
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++
arch/arm/include/asm/arch-vf610/clock.h | 39 ++++++++++
arch/arm/include/asm/arch-vf610/crm_regs.h | 225 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-vf610/imx-regs.h | 419 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 +++++++++++++++++++++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 18 +++++
board/freescale/vf610twr/Makefile | 39 ++++++++++
board/freescale/vf610twr/imximage.cfg | 33 +++++++++
board/freescale/vf610twr/vf610twr.c | 410 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mxc_ocotp | 1 +
doc/README.vf610 | 10 +++
drivers/net/fec_mxc.c | 4 +-
drivers/serial/Makefile | 1 +
drivers/serial/serial_lpuart.c | 132 +++++++++++++++++++++++++++++++++
drivers/watchdog/Makefile | 2 +-
include/configs/vf610twr.h | 140 +++++++++++++++++++++++++++++++++++
23 files changed, 2052 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/cpu/armv7/vf610/Makefile
create mode 100644 arch/arm/cpu/armv7/vf610/generic.c
create mode 100644 arch/arm/cpu/armv7/vf610/timer.c
create mode 100644 arch/arm/include/asm/arch-vf610/clock.h
create mode 100644 arch/arm/include/asm/arch-vf610/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-vf610/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-vf610/iomux-vf610.h
create mode 100644 board/freescale/vf610twr/Makefile
create mode 100644 board/freescale/vf610twr/imximage.cfg
create mode 100644 board/freescale/vf610twr/vf610twr.c
create mode 100644 doc/README.vf610
create mode 100644 drivers/serial/serial_lpuart.c
create mode 100644 include/configs/vf610twr.h
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-05-28 18:57 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support Alison Wang
` (5 subsequent siblings)
6 siblings, 2 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds the IOMUX support for Vybrid VF610 platform.
There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v4:
- Rename "MVF600" to "VF610"
- Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled
- Reorganize the definitions
- Correct the spaces and tabs
Changes in v3:
- Define PAD_CTL_PUE with PKE enabled
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++++++++++++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 8bba8a5..9492326 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
COBJS-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 7fe5ce7..35880c7 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (sel_input_ofs)
__raw_writel(sel_input, base + sel_input_ofs);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+ base + pad_ctrl_ofs);
+#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#endif
}
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 0b4e763..ebf54cf 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_SPEED_MED (1 << 12)
+#define PAD_CTL_SPEED_HIGH (3 << 12)
+
+#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_25ohm (6 << 6)
+#define PAD_CTL_DSE_20ohm (7 << 6)
+
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE (1 << 3)
+#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+
#else
#define PAD_CTL_DVS (1 << 13)
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-05-28 19:16 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610 Alison Wang
` (4 subsequent siblings)
6 siblings, 2 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v4:
- Rename mvf_pins.h to iomux-vf610.h
- Add README.vf610 about fuse assignments for MAC addresses
- Rename directory name 'mvf600' to 'vf610'
- Rename directory 'arch-mvf600' to 'arch-vf610'
Changes in v3:
- Rename the common functions and enums
- Move the structure definitions to imx-regs.h
Changes in v2:
- Remove vybrid-common directory
- Rename directory name 'vybrid' to 'mvf600'
- Add generic.c file
- Rewrite get_reset_cause() to make it readable
- Remove reset_cpu(), and use the function in imx_watchdog.c
- Rewrite timer.c file
- Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk()
- Remove lowlevel_init.S, and add clock_init() in board_early_init_f()
- Remove useless CONFIG_SYS_ defines
- Move CONFIG_MACH_TYPE to board configuration file
- Define C structures and access C structures to set/read registers
- Remove useless errata
- Remove useless macros
- Rename directory 'arch-vybrid' to 'arch-mvf600'
Makefile | 2 +-
arch/arm/cpu/armv7/vf610/Makefile | 42 +++
arch/arm/cpu/armv7/vf610/generic.c | 324 ++++++++++++++++++++
arch/arm/cpu/armv7/vf610/timer.c | 103 +++++++
arch/arm/include/asm/arch-vf610/clock.h | 39 +++
arch/arm/include/asm/arch-vf610/crm_regs.h | 225 ++++++++++++++
arch/arm/include/asm/arch-vf610/imx-regs.h | 419 ++++++++++++++++++++++++++
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 +++++++
doc/README.vf610 | 10 +
9 files changed, 1264 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/vf610/Makefile
create mode 100644 arch/arm/cpu/armv7/vf610/generic.c
create mode 100644 arch/arm/cpu/armv7/vf610/timer.c
create mode 100644 arch/arm/include/asm/arch-vf610/clock.h
create mode 100644 arch/arm/include/asm/arch-vf610/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-vf610/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-vf610/iomux-vf610.h
create mode 100644 doc/README.vf610
diff --git a/Makefile b/Makefile
index c52f0f1..363180c 100644
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile
new file mode 100644
index 0000000..9232cd4
--- /dev/null
+++ b/arch/arm/cpu/armv7/vf610/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += generic.o
+COBJS += timer.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
new file mode 100644
index 0000000..87f2a86
--- /dev/null
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&ccm->ccgr6);
+ if (enable)
+ reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
+ else
+ reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
+ writel(reg, &ccm->ccgr6);
+}
+#endif
+
+static u32 get_mcu_main_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_ccsr, ccm_cacrr, armclk_div;
+ u32 sysclk_sel, pll_pfd_sel = 0;
+ u32 freq = 0;
+
+ ccm_ccsr = readl(&ccm->ccsr);
+ sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+ sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+ armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+ armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+ armclk_div += 1;
+
+ switch (sysclk_sel) {
+ case 0:
+ freq = FASE_CLK_FREQ;
+ break;
+ case 1:
+ freq = SLOW_CLK_FREQ;
+ break;
+ case 2:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL2_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL2_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL2_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL2_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL2_PFD4_FREQ;
+ break;
+ case 3:
+ freq = PLL2_MAIN_FREQ;
+ break;
+ case 4:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL1_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL1_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL1_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL1_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL1_PFD4_FREQ;
+ break;
+ case 5:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ default:
+ printf("unsupported system clock select\n");
+ }
+
+ return freq / armclk_div;
+}
+
+static u32 get_bus_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, busclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+ busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+ busclk_div += 1;
+
+ return get_mcu_main_clk() / busclk_div;
+}
+
+static u32 get_ipg_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, ipgclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+ ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+ ipgclk_div += 1;
+
+ return get_bus_clk() / ipgclk_div;
+}
+
+static u32 get_uart_clk(void)
+{
+ return get_ipg_clk();
+}
+
+static u32 get_sdhc_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+ u32 freq = 0;
+
+ ccm_cscmr1 = readl(&ccm->cscmr1);
+ sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+ sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+ ccm_cscdr2 = readl(&ccm->cscdr2);
+ sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+ sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+ sdhc_clk_div += 1;
+
+ switch (sdhc_clk_sel) {
+ case 0:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL3_PFD3_FREQ;
+ break;
+ case 2:
+ freq = PLL1_PFD3_FREQ;
+ break;
+ case 3:
+ freq = get_bus_clk();
+ break;
+ }
+
+ return freq / sdhc_clk_div;
+}
+
+u32 get_fec_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr2, rmii_clk_sel;
+ u32 freq = 0;
+
+ ccm_cscmr2 = readl(&ccm->cscmr2);
+ rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+ rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+ switch (rmii_clk_sel) {
+ case 0:
+ freq = ENET_EXTERNAL_CLK;
+ break;
+ case 1:
+ freq = AUDIO_EXTERNAL_CLK;
+ break;
+ case 2:
+ freq = PLL5_MAIN_FREQ;
+ break;
+ case 3:
+ freq = PLL5_MAIN_FREQ / 2;
+ break;
+ }
+
+ return freq;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_BUS_CLK:
+ return get_bus_clk();
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_UART_CLK:
+ return get_uart_clk();
+ case MXC_ESDHC_CLK:
+ return get_sdhc_clk();
+ case MXC_FEC_CLK:
+ return get_fec_clk();
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* Dump some core clocks */
+int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ printf("\n");
+ printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
+ printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
+ "display clocks",
+ ""
+);
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ u32 value = readl(&fuse->mac_addr0);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+ cause &= 0xff;
+
+ switch (cause) {
+ case 0x08:
+ return "WDOG";
+ case 0x20:
+ return "JTAG HIGH-Z";
+ case 0x80:
+ return "EXTERNAL RESET";
+ case 0xfd:
+ return "POR";
+ default:
+ return "unknown reset";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale Vybrid VF610 at %d MHz\n",
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c
new file mode 100644
index 0000000..f8fbed7
--- /dev/null
+++ b/arch/arm/cpu/armv7/vf610/timer.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, mxc_get_clock(MXC_IPG_CLK));
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ usec = usec * mxc_get_clock(MXC_IPG_CLK) + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ __raw_writel(0, &cur_pit->mcr);
+
+ __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1);
+ __raw_writel(0, &cur_pit->tctrl1);
+ __raw_writel(1, &cur_pit->tctrl1);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = us_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+}
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
new file mode 100644
index 0000000..04e418c
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_BUS_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_FEC_CLK,
+};
+
+void enable_ocotp_clk(unsigned char enable);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
new file mode 100644
index 0000000..e3f703d
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+ u32 ccr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr;
+ u32 cscmr1;
+ u32 cscdr1;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscmr2;
+ u32 cscdr4;
+ u32 ctor;
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr;
+ u32 cgpr;
+ u32 ccgr0;
+ u32 ccgr1;
+ u32 ccgr2;
+ u32 ccgr3;
+ u32 ccgr4;
+ u32 ccgr5;
+ u32 ccgr6;
+ u32 ccgr7;
+ u32 ccgr8;
+ u32 ccgr9;
+ u32 ccgr10;
+ u32 ccgr11;
+ u32 cmeor0;
+ u32 cmeor1;
+ u32 cmeor2;
+ u32 cmeor3;
+ u32 cmeor4;
+ u32 cmeor5;
+ u32 cppdsr;
+ u32 ccowr;
+ u32 ccpgr0;
+ u32 ccpgr1;
+ u32 ccpgr2;
+ u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+ u32 pll3_ctrl;
+ u32 resv0[3];
+ u32 pll7_ctrl;
+ u32 resv1[3];
+ u32 pll2_ctrl;
+ u32 resv2[3];
+ u32 pll2_ss;
+ u32 resv3[3];
+ u32 pll2_num;
+ u32 resv4[3];
+ u32 pll2_denom;
+ u32 resv5[3];
+ u32 pll4_ctrl;
+ u32 resv6[3];
+ u32 pll4_num;
+ u32 resv7[3];
+ u32 pll4_denom;
+ u32 pll6_ctrl;
+ u32 resv8[3];
+ u32 pll6_num;
+ u32 resv9[3];
+ u32 pll6_denom;
+ u32 resv10[3];
+ u32 pll5_ctrl;
+ u32 resv11[3];
+ u32 pll3_pfd;
+ u32 resv12[3];
+ u32 pll2_pfd;
+ u32 resv13[3];
+ u32 reg_1p1;
+ u32 resv14[3];
+ u32 reg_3p0;
+ u32 resv15[3];
+ u32 reg_2p5;
+ u32 resv16[7];
+ u32 ana_misc0;
+ u32 resv17[3];
+ u32 ana_misc1;
+ u32 resv18[63];
+ u32 anadig_digprog;
+ u32 resv19[3];
+ u32 pll1_ctrl;
+ u32 resv20[3];
+ u32 pll1_ss;
+ u32 resv21[3];
+ u32 pll1_num;
+ u32 resv22[3];
+ u32 pll1_denom;
+ u32 resv23[3];
+ u32 pll1_pdf;
+ u32 resv24[3];
+ u32 pll_lock;
+};
+#endif
+
+#define CCM_CCR_FIRC_EN (1 << 16)
+#define CCM_CCR_OSCNT_MASK 0xff
+#define CCM_CCR_OSCNT(v) ((v) & 0xff)
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
+#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
+#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
+
+#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
+#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
+#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
+#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
+#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
+#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
+#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
+#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
+
+#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
+#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
+#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
+#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
+
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
+#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
+#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
+#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
+#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
+#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
+#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
+
+#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
+
+#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
+#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
+
+#define CCM_REG_CTRL_MASK 0xffffffff
+#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
+#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
+#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
+#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
+#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
+#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+
+#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL2_CTRL_DIV_SELECT 1
+#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL1_CTRL_DIV_SELECT 1
+
+#define FASE_CLK_FREQ 24000000
+#define SLOW_CLK_FREQ 32000
+#define PLL1_PFD1_FREQ 500000000
+#define PLL1_PFD2_FREQ 452000000
+#define PLL1_PFD3_FREQ 396000000
+#define PLL1_PFD4_FREQ 528000000
+#define PLL1_MAIN_FREQ 528000000
+#define PLL2_PFD1_FREQ 500000000
+#define PLL2_PFD2_FREQ 396000000
+#define PLL2_PFD3_FREQ 339000000
+#define PLL2_PFD4_FREQ 413000000
+#define PLL2_MAIN_FREQ 528000000
+#define PLL3_MAIN_FREQ 480000000
+#define PLL3_PFD3_FREQ 298000000
+#define PLL5_MAIN_FREQ 500000000
+
+#define ENET_EXTERNAL_CLK 50000000
+#define AUDIO_EXTERNAL_CLK 24576000
+
+#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
new file mode 100644
index 0000000..c9df32a
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
+#define IRAM_SIZE 0x00080000 /* 512 KB */
+
+#define AIPS0_BASE_ADDR 0x40000000
+#define AIPS1_BASE_ADDR 0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
+#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
+#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+
+/* MSCM interrupt rounter */
+#define MSCM_IRSPRC_CP0_EN 1
+#define MSCM_IRSPRC_NUM 112
+
+/* DDRMC */
+#define DDRMC_PHY_DQ_TIMING 0x00002613
+#define DDRMC_PHY_DQS_TIMING 0x00002615
+#define DDRMC_PHY_CTRL 0x01210080
+#define DDRMC_PHY_MASTER_CTRL 0x0001012a
+#define DDRMC_PHY_SLAVE_CTRL 0x00012020
+
+#define DDRMC_PHY50_DDR3_MODE (1 << 12)
+#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
+
+#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
+#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
+#define DDRMC_CR00_START 1
+#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
+#define DDRMC_CR10_TRST_PWRON(v) (v)
+#define DDRMC_CR11_CKE_INACTIVE(v) (v)
+#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
+#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
+#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
+#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
+#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
+#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
+#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
+#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
+#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
+#define DDRMC_CR17_TMOD(v) ((v) & 0xff)
+#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
+#define DDRMC_CR20_AP_EN (1 << 24)
+#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
+#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
+#define DDRMC_CR21_CCMAP_EN 1
+#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
+#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
+#define DDRMC_CR23_TDLL(v) ((v) & 0xff)
+#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
+#define DDRMC_CR25_TREF_EN (1 << 16)
+#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
+#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
+#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
+#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
+#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
+#define DDRMC_CR33_EN_QK_SREF (1 << 16)
+#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
+#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
+#define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
+#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
+#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
+#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
+#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
+#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
+#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
+#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
+#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
+#define DDRMC_CR70_REF_PER_ZQ(v) (v)
+#define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
+#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
+#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
+#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
+#define DDRMC_CR74_BANKSPLT_EN (1 << 24)
+#define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
+#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
+#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
+#define DDRMC_CR75_RW_PG_EN (1 << 24)
+#define DDRMC_CR75_RW_EN (1 << 16)
+#define DDRMC_CR75_PRI_EN (1 << 8)
+#define DDRMC_CR75_PLEN 1
+#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
+#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
+#define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
+#define DDRMC_CR76_CS_EN 1
+#define DDRMC_CR77_CS_MAP (1 << 24)
+#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
+#define DDRMC_CR77_SWAP_EN 1
+#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
+#define DDRMC_CR79_CTLUPD_AREF (1 << 24)
+#define DDRMC_CR82_INT_MASK 0x1fffffff
+#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
+#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
+#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
+#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
+#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
+#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
+#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
+#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
+#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
+#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
+#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
+#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
+#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
+#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
+#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
+#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
+#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
+#define DDRMC_CR158_TWR(v) ((v) & 0x3f)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr1;
+ u32 srsr;
+ u32 secr;
+ u32 gpsr;
+ u32 sicr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr0;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 hab0;
+ u32 hab1;
+ u32 hab2;
+ u32 hab3;
+ u32 hab4;
+ u32 hab5;
+ u32 misc0;
+ u32 misc1;
+ u32 misc2;
+ u32 misc3;
+};
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+ u32 mcr;
+ u32 recv0[55];
+ u32 ltmr64h;
+ u32 ltmr64l;
+ u32 recv1[6];
+ u32 ldval0;
+ u32 cval0;
+ u32 tctrl0;
+ u32 tflg0;
+ u32 ldval1;
+ u32 cval1;
+ u32 tctrl1;
+ u32 tflg1;
+ u32 ldval2;
+ u32 cval2;
+ u32 tctrl2;
+ u32 tflg2;
+ u32 ldval3;
+ u32 cval3;
+ u32 tctrl3;
+ u32 tflg3;
+ u32 ldval4;
+ u32 cval4;
+ u32 tctrl4;
+ u32 tflg4;
+ u32 ldval5;
+ u32 cval5;
+ u32 tctrl5;
+ u32 tflg5;
+ u32 ldval6;
+ u32 cval6;
+ u32 tctrl6;
+ u32 tflg6;
+ u32 ldval7;
+ u32 cval7;
+ u32 tctrl7;
+ u32 tflg7;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+ u16 wcr;
+ u16 wsr;
+ u16 wrsr;
+ u16 wicr;
+ u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+ u32 cr[162];
+ u32 rsvd[94];
+ u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctrl;
+ u32 rsvd2[3];
+ u32 read_fuse_data;
+ u32 rsvd3[7];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd4[3];
+ u32 crc_value;
+ u32 rsvd5[3];
+ u32 version;
+ u32 rsvd6[0xdb];
+
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[0x17];
+};
+
+struct fuse_bank4_regs {
+ u32 sjc_resp0;
+ u32 rsvd0[3];
+ u32 sjc_resp1;
+ u32 rsvd1[3];
+ u32 mac_addr0;
+ u32 rsvd2[3];
+ u32 mac_addr1;
+ u32 rsvd3[3];
+ u32 mac_addr2;
+ u32 rsvd4[3];
+ u32 mac_addr3;
+ u32 rsvd5[3];
+ u32 gp1;
+ u32 rsvd6[3];
+ u32 gp2;
+ u32 rsvd7[3];
+};
+
+/* UART */
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+ u32 ircp0ir;
+ u32 ircp1ir;
+ u32 rsvd1[6];
+ u32 ircpgir;
+ u32 rsvd2[23];
+ u16 irsprc[112];
+ u16 rsvd3[848];
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
new file mode 100644
index 0000000..1c728fa
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_VF610_H__
+#define __IOMUX_VF610_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+
+enum {
+ VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+};
+
+#endif /* __IOMUX_VF610_H__ */
diff --git a/doc/README.vf610 b/doc/README.vf610
new file mode 100644
index 0000000..38cf5cf
--- /dev/null
+++ b/doc/README.vf610
@@ -0,0 +1,10 @@
+U-Boot for Freescale Vybrid VF610
+
+This file contains information for the port of U-Boot to the Freescale Vybrid
+VF610 SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in word 2 and the
+ 32 lsbs in word 3.
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-05-28 19:21 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog " Alison Wang
` (3 subsequent siblings)
6 siblings, 2 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4: None
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4dbcdca..da95e28 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -516,9 +516,7 @@ static int fec_open(struct eth_device *edev)
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(&fec->eth->r_cntrl) &
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog support for Vybrid VF610
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
` (2 preceding siblings ...)
2013-05-28 8:55 ` [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610 Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart " Alison Wang
` (2 subsequent siblings)
6 siblings, 1 reply; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds watchdog support for Vybrid VF610 platform.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v4:
- Rename mvf600 to vf610
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 13e7c37..e96acab 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
COBJS-y += imx_watchdog.o
endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart support for Vybrid VF610
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
` (3 preceding siblings ...)
2013-05-28 8:55 ` [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog " Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board Alison Wang
6 siblings, 1 reply; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v4: None
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile | 1 +
drivers/serial/serial_lpuart.c | 132 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 133 insertions(+)
create mode 100644 drivers/serial/serial_lpuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..bb6559b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 0000000..51d5666
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define US1_TDRE (1 << 7)
+#define US1_RDRF (1 << 5)
+#define UC2_TE (1 << 3)
+#define UC2_RE (1 << 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
+ u16 sbr;
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd->baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr >> 8, &base->ubdh);
+ __raw_writeb(sbr & 0xff, &base->ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(&base->us1) & US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(&base->us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, &base->us1);
+
+ return __raw_readb(&base->ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(&base->us1) & US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, &base->ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(&base->urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(&base->uc2);
+ ctrl &= ~UC2_RE;
+ ctrl &= ~UC2_TE;
+ __raw_writeb(ctrl, &base->uc2);
+
+ __raw_writeb(0, &base->umodem);
+ __raw_writeb(0, &base->uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = "lpuart_serial",
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(&lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lpuart_serial_drv;
+}
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
` (4 preceding siblings ...)
2013-05-28 8:55 ` [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart " Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-05-31 16:10 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board Alison Wang
6 siblings, 2 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
This patch adds Vybrid VF610 to mxc_ocotp document.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Changes in v4: New
Changes in v3: None
Changes in v2: None
doc/README.mxc_ocotp | 1 +
1 file changed, 1 insertion(+)
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
index 9a53311..7a2863c 100644
--- a/doc/README.mxc_ocotp
+++ b/doc/README.mxc_ocotp
@@ -2,6 +2,7 @@ Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP)
on MXC
This IP can be found on the following SoCs:
+ - Vybrid VF610,
- i.MX6.
Note that this IP is different from albeit similar to the IPs of the same name
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
` (5 preceding siblings ...)
2013-05-28 8:55 ` [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document Alison Wang
@ 2013-05-28 8:55 ` Alison Wang
2013-05-28 19:57 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
6 siblings, 2 replies; 31+ messages in thread
From: Alison Wang @ 2013-05-28 8:55 UTC (permalink / raw)
To: u-boot
VF610TWR is a board based on Vybrid VF610 SoC.
This patch adds basic support for Vybrid VF610TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
---
Changes in v4:
- Rename directory name 'mvf600twr' to 'vf610twr'
- Rename mvf600twr.h to vf610twr.h
- Use NEW_PAD_CTRL instead of MUX_PAD_CTRL
- Remove CONFIG_ETHPRIME option
- Add CONFIG_CMD_MEMSET option
Changes in v3:
- Replace BOOT_FROM by BOOT_OFFSET
- Enable CONFIG_OF_LIBFDT option
- Add useful define instead of raw number
- Use clrsetbits_le32 to set the single bits
- Move setup_iomux_enet() to board_early_init_f and remove board_eth_init()
- Remove redundant define
- Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h
Changes in v2:
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Remove useless CONFIG_SYS_ defines
- Define C structures and access C structures to set/read registers
- Move CONFIG_MACH_TYPE to board configuration file
- Use common iomux-v3 code
MAINTAINERS | 4 +
board/freescale/vf610twr/Makefile | 39 ++++
board/freescale/vf610twr/imximage.cfg | 33 +++
board/freescale/vf610twr/vf610twr.c | 410 ++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/vf610twr.h | 140 ++++++++++++
6 files changed, 627 insertions(+)
create mode 100644 board/freescale/vf610twr/Makefile
create mode 100644 board/freescale/vf610twr/imximage.cfg
create mode 100644 board/freescale/vf610twr/vf610twr.c
create mode 100644 include/configs/vf610twr.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c05433a..e4113d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1057,6 +1057,10 @@ Eric Nelson <eric.nelson@boundarydevices.com>
nitrogen6s i.MX6S 512MB
nitrogen6s1g i.MX6S 1GB
+Alison Wang <b18965@freescale.com>
+
+ vf610twr VF610
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile
new file mode 100644
index 0000000..7416228
--- /dev/null
+++ b/board/freescale/vf610twr/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 0000000..b00d4c1
--- /dev/null
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 0000000..04fa882
--- /dev/null
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,410 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+ writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+ &ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+ writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+ writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+ writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+ writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+ writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+ DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+ writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+ DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+ writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+ writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+ &ddrmr->cr[17]);
+ writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+ writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+ writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+ DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+ writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+ writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+ writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+ writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+ writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+ writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+ writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+ writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+ writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+ writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+ writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+ writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+ writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+ DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+ writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+ writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+ &ddrmr->cr[48]);
+
+ writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+ writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+ writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+ writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+ writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+ writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+ DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+ writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+ DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+ &ddrmr->cr[74]);
+ writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+ DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+ writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+ DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+ writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+ DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+ writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+ writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+ writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+ writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+ &ddrmr->cr[87]);
+ writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+ writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+ writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+ writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+ writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+ writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+ writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+ writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+ &ddrmr->cr[117]);
+ writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+ &ddrmr->cr[118]);
+
+ writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+ &ddrmr->cr[120]);
+ writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+ &ddrmr->cr[121]);
+ writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+ writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+ &ddrmr->cr[123]);
+ writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+ writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+ writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+ &ddrmr->cr[132]);
+ writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+ &ddrmr->cr[139]);
+
+ writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+ writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+ &ddrmr->cr[155]);
+ writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+ ddr_phy_init();
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+ udelay(200);
+}
+
+int dram_init(void)
+{
+ setup_iomux_ddr();
+
+ ddr_ctrl_init();
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ static const iomux_v3_cfg_t enet0_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eSDHC1 is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t esdhc1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+ };
+ s32 status = 0;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+ return status;
+}
+#endif
+
+static void clock_init(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+ CCM_CCGR0_UART1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+ CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+ CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+ CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+ CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+ CCM_CCGR3_ANADIG_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+ CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+ CCM_CCGR4_GPC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+ CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+ CCM_CCGR7_SDHC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+ CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+ ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+ clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+ ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+ clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+ CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+ clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+ CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+ CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+ CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+ CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+ CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+ CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+ clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+ CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+ CCM_CACRR_ARM_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+ CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+ clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+ CCM_CSCDR1_RMII_CLK_EN);
+ clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+ CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+ CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+ struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ clock_init();
+ mscm_init();
+
+ setup_iomux_uart();
+ setup_iomux_enet();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: vf610twr\n");
+
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 2f39f26..3fdf41e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -262,6 +262,7 @@ mx6qsabrelite arm armv7 mx6qsabrelite freesca
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
+vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
eco5pk arm armv7 eco5pk 8dtech omap3
nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
new file mode 100644
index 0000000..77fe893
--- /dev/null
+++ b/include/configs/vf610twr.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid vf610twr board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE 4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE UART1_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_TEXT_BASE 0x3f008000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80010000
+#define CONFIG_SYS_MEMTEST_END 0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR 0x80010000
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM (0x80000000)
+#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
@ 2013-05-28 18:57 ` Benoît Thébaudeau
2013-05-29 5:29 ` Wang Huan-B18965
2013-06-03 9:03 ` Stefano Babic
1 sibling, 1 reply; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-28 18:57 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 10:55:41 AM, Alison Wang wrote:
> This patch adds the IOMUX support for Vybrid VF610 platform.
>
> There is a little difference for IOMUXC module between VF610 and i.MX
> platform, the muxmode and pad configuration share one 32bit register on
> VF610, but they are two independent registers on I.MX platform. A
> CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
[...]
> diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
> index 7fe5ce7..35880c7 100644
> --- a/arch/arm/imx-common/iomux-v3.c
> +++ b/arch/arm/imx-common/iomux-v3.c
> @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
> if (sel_input_ofs)
> __raw_writel(sel_input, base + sel_input_ofs);
>
> +#ifdef CONFIG_IOMUX_SHARE_CONF_REG
Where is this one defined? I don't see it in include/configs/vf610twr.h.
Why not use "#ifdef CONFIG_VF610" since this is a platform-dependent code, and
not a board-specific config option?
> + if (!(pad_ctrl & NO_PAD_CTRL))
> + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
> + base + pad_ctrl_ofs);
> +#else
> if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
> +#endif
> }
>
> void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
[...]
Apart from that, this patch is OK.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 8:55 ` [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support Alison Wang
@ 2013-05-28 19:16 ` Benoît Thébaudeau
2013-05-28 19:30 ` Benoît Thébaudeau
2013-05-29 5:32 ` Wang Huan-B18965
2013-06-03 9:03 ` Stefano Babic
1 sibling, 2 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-28 19:16 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 10:55:42 AM, Alison Wang wrote:
> This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
>
> It aligns Vybrid VF610 platform with i.MX platform. As there are
> some differences between VF610 and i.MX platforms, the specific
> codes are in the arch/arm/cpu/armv7/vf610 directory.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
[...]
> diff --git a/doc/README.vf610 b/doc/README.vf610
> new file mode 100644
> index 0000000..38cf5cf
> --- /dev/null
> +++ b/doc/README.vf610
> @@ -0,0 +1,10 @@
> +U-Boot for Freescale Vybrid VF610
> +
> +This file contains information for the port of U-Boot to the Freescale
> Vybrid
> +VF610 SoC.
> +
> +1. CONVENTIONS FOR FUSE ASSIGNMENTS
> +-----------------------------------
> +
> +1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in word 2 and
> the
> + 32 lsbs in word 3.
The hunk below is still missing:
doc/README.mxc_ocotp:
---
on MXC
This IP can be found on the following SoCs:
+ - Vybrid VF610,
- i.MX6.
Note that this IP is different from albeit similar to the IPs of the same name
---
Apart from that, this patch is correct.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610 Alison Wang
@ 2013-05-28 19:21 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-28 19:21 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 10:55:43 AM, Alison Wang wrote:
> This patch adds FEC support for Vybrid VF610 platform.
>
> In function fec_open(), RCR register is only set as RGMII mode. But RCR
> register should be set as RMII mode for VF610 platform.
> This configuration is already done in fec_reg_setup(), so this piece of
> code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
> FEC_RCNTRL_MII_MODE bits.
[...]
Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 19:16 ` Benoît Thébaudeau
@ 2013-05-28 19:30 ` Benoît Thébaudeau
2013-05-29 5:37 ` Wang Huan-B18965
2013-05-29 5:32 ` Wang Huan-B18965
1 sibling, 1 reply; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-28 19:30 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 9:16:20 PM, Beno?t Th?baudeau wrote:
> Hi Alison,
>
> On Tuesday, May 28, 2013 10:55:42 AM, Alison Wang wrote:
> > This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
> >
> > It aligns Vybrid VF610 platform with i.MX platform. As there are
> > some differences between VF610 and i.MX platforms, the specific
> > codes are in the arch/arm/cpu/armv7/vf610 directory.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
>
> [...]
>
> > diff --git a/doc/README.vf610 b/doc/README.vf610
> > new file mode 100644
> > index 0000000..38cf5cf
> > --- /dev/null
> > +++ b/doc/README.vf610
> > @@ -0,0 +1,10 @@
> > +U-Boot for Freescale Vybrid VF610
> > +
> > +This file contains information for the port of U-Boot to the Freescale
> > Vybrid
> > +VF610 SoC.
> > +
> > +1. CONVENTIONS FOR FUSE ASSIGNMENTS
> > +-----------------------------------
> > +
> > +1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in word 2
> > and
> > the
> > + 32 lsbs in word 3.
>
> The hunk below is still missing:
>
> doc/README.mxc_ocotp:
> ---
> on MXC
>
> This IP can be found on the following SoCs:
> + - Vybrid VF610,
> - i.MX6.
>
> Note that this IP is different from albeit similar to the IPs of the same
> name
> ---
I have just noticed that this was actually in 6/7. Why are you putting this into
a separate patch?
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
2013-05-28 8:55 ` [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board Alison Wang
@ 2013-05-28 19:57 ` Benoît Thébaudeau
2013-05-29 5:52 ` Wang Huan-B18965
2013-06-03 9:03 ` Stefano Babic
1 sibling, 1 reply; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-28 19:57 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 10:55:47 AM, Alison Wang wrote:
> VF610TWR is a board based on Vybrid VF610 SoC.
>
> This patch adds basic support for Vybrid VF610TWR board.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
[...]
> diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
> new file mode 100644
> index 0000000..77fe893
> --- /dev/null
> +++ b/include/configs/vf610twr.h
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale Vybrid vf610twr board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_VF610
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_MACH_TYPE 4146
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/* Enable passing of ATAGs */
> +#define CONFIG_CMDLINE_TAG
> +
> +#define CONFIG_CMD_FUSE
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_FSL_LPUART
> +#define LPUART_BASE UART1_BASE
> +
> +/* Allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_UART_PORT (1)
> +#define CONFIG_BAUDRATE 115200
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_FEC_MXC_PHYADDR 0
Why don't you add support for the 2nd FEC? Do you plan to do it later?
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_SYS_TEXT_BASE 0x3f008000
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
> +#undef CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_CMD_MEMTEST
> +#define CONFIG_SYS_MEMTEST_START 0x80010000
> +#define CONFIG_SYS_MEMTEST_END 0x87C00000
Please make sure to have runtime-tested this address range with the mtest
command since bad mtest addresses are the reason why CONFIG_CMD_MEMTEST has been
removed from the default commands.
[...]
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-28 18:57 ` Benoît Thébaudeau
@ 2013-05-29 5:29 ` Wang Huan-B18965
2013-05-29 6:21 ` Stefano Babic
0 siblings, 1 reply; 31+ messages in thread
From: Wang Huan-B18965 @ 2013-05-29 5:29 UTC (permalink / raw)
To: u-boot
Hi, Benoit,
> > diff --git a/arch/arm/imx-common/iomux-v3.c
> > b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7..35880c7 100644
> > --- a/arch/arm/imx-common/iomux-v3.c
> > +++ b/arch/arm/imx-common/iomux-v3.c
> > @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
> > if (sel_input_ofs)
> > __raw_writel(sel_input, base + sel_input_ofs);
> >
> > +#ifdef CONFIG_IOMUX_SHARE_CONF_REG
>
> Where is this one defined? I don't see it in include/configs/vf610twr.h.
>
[Alison Wang] CONFIG_IOMUX_SHARE_CONF_REG is defined in arch/arm/include/asm/arch-vf610/imx-regs.h. Because this is not a board configuration, it is related to the SOC.
Please refer to Stefano's comments below which also could be found in the email on May 15th.
Stefano wrote:
> +
> +/* MUX mode and PAD ctrl are in one register */
> +#define CONFIG_IOMUX_SHARE_CONF_REG
NAK. This is not a board configuration, it is related to the SOC. This
setup should flow into the related imx-regs.h for this SOC. When you set
CONFIG_MVF600, this value should be set automatically.
> Why not use "#ifdef CONFIG_VF610" since this is a platform-dependent
> code, and not a board-specific config option?
[Alison Wang] I use this CONFIG_IOMUX_SHARE_CONF_REG option, because this part of codes
not only could be used on VF610 platform, but also could be used on VF620 or other platforms.
When it is used on VF620 or others, you could just enable CONFIG_IOMUX_SHARE_CONF_REG
in the related imx-regs.h.
Otherwise, if "ifdef CONFIG_VF610" is used, you need to add "#if defined(CONFIG_VF610) || defined(CONFIG_VF620)"
When this part of codes is also used on VF620. Then when this part of codes is used on VF630 too, this line
will be very very long.
>
> > + if (!(pad_ctrl & NO_PAD_CTRL))
> > + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
> > + base + pad_ctrl_ofs);
> > +#else
> > if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> > __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
> > +#endif
> > }
> >
> > void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
>
> [...]
>
> Apart from that, this patch is OK.
>
Thanks.
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 19:16 ` Benoît Thébaudeau
2013-05-28 19:30 ` Benoît Thébaudeau
@ 2013-05-29 5:32 ` Wang Huan-B18965
1 sibling, 0 replies; 31+ messages in thread
From: Wang Huan-B18965 @ 2013-05-29 5:32 UTC (permalink / raw)
To: u-boot
Hi, Benoit,
> The hunk below is still missing:
>
> doc/README.mxc_ocotp:
> ---
> on MXC
>
> This IP can be found on the following SoCs:
> + - Vybrid VF610,
> - i.MX6.
>
> Note that this IP is different from albeit similar to the IPs of the
> same name
[Alison Wang] It is not missing, it is in the 6/7 patch.
> ---
>
> Apart from that, this patch is correct.
>
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 19:30 ` Benoît Thébaudeau
@ 2013-05-29 5:37 ` Wang Huan-B18965
2013-05-29 14:46 ` Benoît Thébaudeau
0 siblings, 1 reply; 31+ messages in thread
From: Wang Huan-B18965 @ 2013-05-29 5:37 UTC (permalink / raw)
To: u-boot
Hi, Benoit,
> > > diff --git a/doc/README.vf610 b/doc/README.vf610 new file mode
> > > 100644 index 0000000..38cf5cf
> > > --- /dev/null
> > > +++ b/doc/README.vf610
> > > @@ -0,0 +1,10 @@
> > > +U-Boot for Freescale Vybrid VF610
> > > +
> > > +This file contains information for the port of U-Boot to the
> > > +Freescale
> > > Vybrid
> > > +VF610 SoC.
> > > +
> > > +1. CONVENTIONS FOR FUSE ASSIGNMENTS
> > > +-----------------------------------
> > > +
> > > +1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in
> > > +word 2
> > > and
> > > the
> > > + 32 lsbs in word 3.
> >
> > The hunk below is still missing:
> >
> > doc/README.mxc_ocotp:
> > ---
> > on MXC
> >
> > This IP can be found on the following SoCs:
> > + - Vybrid VF610,
> > - i.MX6.
> >
> > Note that this IP is different from albeit similar to the IPs of the
> > same name
> > ---
>
> I have just noticed that this was actually in 6/7. Why are you putting
> this into a separate patch?
[Alison Wang] Because patch 2/7 is about VF610 CPU support, and doc/README.vf610 is also a document about
VF610 SoC. Doc/README.mxc_ocotp is the document about a driver (IP OCOTP), so this driver document should be
separated from CPU patch 2/7.
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
2013-05-28 19:57 ` Benoît Thébaudeau
@ 2013-05-29 5:52 ` Wang Huan-B18965
2013-05-29 14:49 ` Benoît Thébaudeau
0 siblings, 1 reply; 31+ messages in thread
From: Wang Huan-B18965 @ 2013-05-29 5:52 UTC (permalink / raw)
To: u-boot
Hi, Benoit,
> > +
> > +#define CONFIG_CMD_PING
> > +#define CONFIG_CMD_DHCP
> > +#define CONFIG_CMD_MII
> > +#define CONFIG_CMD_NET
> > +#define CONFIG_FEC_MXC
> > +#define CONFIG_MII
> > +#define IMX_FEC_BASE ENET_BASE_ADDR
> > +#define CONFIG_FEC_XCV_TYPE RMII
> > +#define CONFIG_FEC_MXC_PHYADDR 0
>
> Why don't you add support for the 2nd FEC? Do you plan to do it later?
[Alison Wang] In u-boot, one FEC is enough for user. We do not plan to do it later.
>
> > +#define CONFIG_PHYLIB
> > +#define CONFIG_PHY_MICREL
> > +
> > +#define CONFIG_BOOTDELAY 3
> > +
> > +#define CONFIG_SYS_TEXT_BASE 0x3f008000
> > +
> > +/* Miscellaneous configurable options */
> > +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser
> */
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
> > +#undef CONFIG_AUTO_COMPLETE
> > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> > +#define CONFIG_SYS_PBSIZE \
> > + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args
> */
> > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > +
> > +#define CONFIG_CMD_MEMTEST
> > +#define CONFIG_SYS_MEMTEST_START 0x80010000
> > +#define CONFIG_SYS_MEMTEST_END 0x87C00000
>
> Please make sure to have runtime-tested this address range with the
> mtest command since bad mtest addresses are the reason why
> CONFIG_CMD_MEMTEST has been removed from the default commands.
[Alison Wang] Thanks for your reminder, we have tested.
>
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-29 5:29 ` Wang Huan-B18965
@ 2013-05-29 6:21 ` Stefano Babic
2013-05-29 14:54 ` Benoît Thébaudeau
0 siblings, 1 reply; 31+ messages in thread
From: Stefano Babic @ 2013-05-29 6:21 UTC (permalink / raw)
To: u-boot
On 29/05/2013 07:29, Wang Huan-B18965 wrote:
>> Where is this one defined? I don't see it in include/configs/vf610twr.h.
>>
> [Alison Wang] CONFIG_IOMUX_SHARE_CONF_REG is defined in arch/arm/include/asm/arch-vf610/imx-regs.h. Because this is not a board configuration, it is related to the SOC.
>
> Please refer to Stefano's comments below which also could be found in the email on May 15th.
>
> Stefano wrote:
>> +
>> +/* MUX mode and PAD ctrl are in one register */
>> +#define CONFIG_IOMUX_SHARE_CONF_REG
>
> NAK. This is not a board configuration, it is related to the SOC. This
> setup should flow into the related imx-regs.h for this SOC. When you set
> CONFIG_MVF600, this value should be set automatically.
>
>> Why not use "#ifdef CONFIG_VF610" since this is a platform-dependent
>> code, and not a board-specific config option?
> [Alison Wang] I use this CONFIG_IOMUX_SHARE_CONF_REG option, because this part of codes
> not only could be used on VF610 platform, but also could be used on VF620 or other platforms.
> When it is used on VF620 or others, you could just enable CONFIG_IOMUX_SHARE_CONF_REG
> in the related imx-regs.h.
> Otherwise, if "ifdef CONFIG_VF610" is used, you need to add "#if defined(CONFIG_VF610) || defined(CONFIG_VF620)"
> When this part of codes is also used on VF620. Then when this part of codes is used on VF630 too, this line
> will be very very long.
Agree. This is a property of the processor and should be automatically
set. It should not flow into board config file, and having a family of
processor we cannot use ifdef CONFIG_VF610.
IMHO the patch is ok.
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-29 5:37 ` Wang Huan-B18965
@ 2013-05-29 14:46 ` Benoît Thébaudeau
2013-05-31 8:59 ` Stefano Babic
0 siblings, 1 reply; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-29 14:46 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Wednesday, May 29, 2013 7:37:32 AM, Wang Huan-B18965 wrote:
> Hi, Benoit,
>
> > > > diff --git a/doc/README.vf610 b/doc/README.vf610 new file mode
> > > > 100644 index 0000000..38cf5cf
> > > > --- /dev/null
> > > > +++ b/doc/README.vf610
> > > > @@ -0,0 +1,10 @@
> > > > +U-Boot for Freescale Vybrid VF610
> > > > +
> > > > +This file contains information for the port of U-Boot to the
> > > > +Freescale
> > > > Vybrid
> > > > +VF610 SoC.
> > > > +
> > > > +1. CONVENTIONS FOR FUSE ASSIGNMENTS
> > > > +-----------------------------------
> > > > +
> > > > +1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in
> > > > +word 2
> > > > and
> > > > the
> > > > + 32 lsbs in word 3.
> > >
> > > The hunk below is still missing:
> > >
> > > doc/README.mxc_ocotp:
> > > ---
> > > on MXC
> > >
> > > This IP can be found on the following SoCs:
> > > + - Vybrid VF610,
> > > - i.MX6.
> > >
> > > Note that this IP is different from albeit similar to the IPs of the
> > > same name
> > > ---
> >
> > I have just noticed that this was actually in 6/7. Why are you putting
> > this into a separate patch?
> [Alison Wang] Because patch 2/7 is about VF610 CPU support, and
> doc/README.vf610 is also a document about
> VF610 SoC. Doc/README.mxc_ocotp is the document about a driver (IP OCOTP), so
> this driver document should be
> separated from CPU patch 2/7.
I don't think so: It's part of what comes with the addition of the VF610
platform, so 6/7 could be merged into 2/7. But it does not really matter. It's
probably also fine if you keep what you did.
Stefano, any opinion?
Best regards,
Beno?t
--------------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
2013-05-29 5:52 ` Wang Huan-B18965
@ 2013-05-29 14:49 ` Benoît Thébaudeau
0 siblings, 0 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-29 14:49 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Wednesday, May 29, 2013 7:52:33 AM, Wang Huan-B18965 wrote:
> Hi, Benoit,
>
> > > +
> > > +#define CONFIG_CMD_PING
> > > +#define CONFIG_CMD_DHCP
> > > +#define CONFIG_CMD_MII
> > > +#define CONFIG_CMD_NET
> > > +#define CONFIG_FEC_MXC
> > > +#define CONFIG_MII
> > > +#define IMX_FEC_BASE ENET_BASE_ADDR
> > > +#define CONFIG_FEC_XCV_TYPE RMII
> > > +#define CONFIG_FEC_MXC_PHYADDR 0
> >
> > Why don't you add support for the 2nd FEC? Do you plan to do it later?
> [Alison Wang] In u-boot, one FEC is enough for user. We do not plan to do it
> later.
> >
> > > +#define CONFIG_PHYLIB
> > > +#define CONFIG_PHY_MICREL
> > > +
> > > +#define CONFIG_BOOTDELAY 3
> > > +
> > > +#define CONFIG_SYS_TEXT_BASE 0x3f008000
> > > +
> > > +/* Miscellaneous configurable options */
> > > +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser
> > */
> > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
> > > +#undef CONFIG_AUTO_COMPLETE
> > > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> > > +#define CONFIG_SYS_PBSIZE \
> > > + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> > > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args
> > */
> > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > +
> > > +#define CONFIG_CMD_MEMTEST
> > > +#define CONFIG_SYS_MEMTEST_START 0x80010000
> > > +#define CONFIG_SYS_MEMTEST_END 0x87C00000
> >
> > Please make sure to have runtime-tested this address range with the
> > mtest command since bad mtest addresses are the reason why
> > CONFIG_CMD_MEMTEST has been removed from the default commands.
> [Alison Wang] Thanks for your reminder, we have tested.
OK, then, for this patch:
Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-29 6:21 ` Stefano Babic
@ 2013-05-29 14:54 ` Benoît Thébaudeau
0 siblings, 0 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-29 14:54 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Wednesday, May 29, 2013 8:21:00 AM, Stefano Babic wrote:
> On 29/05/2013 07:29, Wang Huan-B18965 wrote:
>
> >> Where is this one defined? I don't see it in include/configs/vf610twr.h.
> >>
> > [Alison Wang] CONFIG_IOMUX_SHARE_CONF_REG is defined in
> > arch/arm/include/asm/arch-vf610/imx-regs.h. Because this is not a board
> > configuration, it is related to the SOC.
> >
> > Please refer to Stefano's comments below which also could be found in the
> > email on May 15th.
> >
> > Stefano wrote:
> >> +
> >> +/* MUX mode and PAD ctrl are in one register */
> >> +#define CONFIG_IOMUX_SHARE_CONF_REG
> >
> > NAK. This is not a board configuration, it is related to the SOC. This
> > setup should flow into the related imx-regs.h for this SOC. When you set
> > CONFIG_MVF600, this value should be set automatically.
> >
> >> Why not use "#ifdef CONFIG_VF610" since this is a platform-dependent
> >> code, and not a board-specific config option?
> > [Alison Wang] I use this CONFIG_IOMUX_SHARE_CONF_REG option, because this
> > part of codes
> > not only could be used on VF610 platform, but also could be used on VF620
> > or other platforms.
> > When it is used on VF620 or others, you could just enable
> > CONFIG_IOMUX_SHARE_CONF_REG
> > in the related imx-regs.h.
> > Otherwise, if "ifdef CONFIG_VF610" is used, you need to add "#if
> > defined(CONFIG_VF610) || defined(CONFIG_VF620)"
> > When this part of codes is also used on VF620. Then when this part of codes
> > is used on VF630 too, this line
> > will be very very long.
>
> Agree. This is a property of the processor and should be automatically
> set. It should not flow into board config file, and having a family of
> processor we cannot use ifdef CONFIG_VF610.
>
> IMHO the patch is ok.
>
> Acked-by: Stefano Babic <sbabic@denx.de>
I agree:
Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-29 14:46 ` Benoît Thébaudeau
@ 2013-05-31 8:59 ` Stefano Babic
2013-05-31 16:10 ` Benoît Thébaudeau
0 siblings, 1 reply; 31+ messages in thread
From: Stefano Babic @ 2013-05-31 8:59 UTC (permalink / raw)
To: u-boot
On 29/05/2013 16:46, Beno?t Th?baudeau wrote:
> Hi Alison,
>
Hi Benoit,
>>> I have just noticed that this was actually in 6/7. Why are you putting
>>> this into a separate patch?
>> [Alison Wang] Because patch 2/7 is about VF610 CPU support, and
>> doc/README.vf610 is also a document about
>> VF610 SoC. Doc/README.mxc_ocotp is the document about a driver (IP OCOTP), so
>> this driver document should be
>> separated from CPU patch 2/7.
>
> I don't think so: It's part of what comes with the addition of the VF610
> platform, so 6/7 could be merged into 2/7. But it does not really matter. It's
> probably also fine if you keep what you did.
>
> Stefano, any opinion?
Strictly speaking, you're right. But as you mentioned, it does not
really matter. Without reposting, I can myself squash 6/7 into 2/7 by
merging the patchset.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-31 8:59 ` Stefano Babic
@ 2013-05-31 16:10 ` Benoît Thébaudeau
0 siblings, 0 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-31 16:10 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Friday, May 31, 2013 10:59:03 AM, Stefano Babic wrote:
> On 29/05/2013 16:46, Beno?t Th?baudeau wrote:
> > Hi Alison,
> >
>
> Hi Benoit,
>
> >>> I have just noticed that this was actually in 6/7. Why are you putting
> >>> this into a separate patch?
> >> [Alison Wang] Because patch 2/7 is about VF610 CPU support, and
> >> doc/README.vf610 is also a document about
> >> VF610 SoC. Doc/README.mxc_ocotp is the document about a driver (IP OCOTP),
> >> so
> >> this driver document should be
> >> separated from CPU patch 2/7.
> >
> > I don't think so: It's part of what comes with the addition of the VF610
> > platform, so 6/7 could be merged into 2/7. But it does not really matter.
> > It's
> > probably also fine if you keep what you did.
> >
> > Stefano, any opinion?
>
> Strictly speaking, you're right. But as you mentioned, it does not
> really matter. Without reposting, I can myself squash 6/7 into 2/7 by
> merging the patchset.
OK.
Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document
2013-05-28 8:55 ` [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document Alison Wang
@ 2013-05-31 16:10 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Benoît Thébaudeau @ 2013-05-31 16:10 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Tuesday, May 28, 2013 10:55:46 AM, Alison Wang wrote:
> This patch adds Vybrid VF610 to mxc_ocotp document.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> Changes in v4: New
>
> Changes in v3: None
>
> Changes in v2: None
>
> doc/README.mxc_ocotp | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
> index 9a53311..7a2863c 100644
> --- a/doc/README.mxc_ocotp
> +++ b/doc/README.mxc_ocotp
> @@ -2,6 +2,7 @@ Driver implementing the fuse API for Freescale's On-Chip OTP
> Controller (OCOTP)
> on MXC
>
> This IP can be found on the following SoCs:
> + - Vybrid VF610,
> - i.MX6.
>
> Note that this IP is different from albeit similar to the IPs of the same
> name
Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document
2013-05-28 8:55 ` [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document Alison Wang
2013-05-31 16:10 ` Benoît Thébaudeau
@ 2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds Vybrid VF610 to mxc_ocotp document.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
At the end, I left this patch without squashing to not drop also
Benoit's reviewed-by. As we have already said, it does not really matter.
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
2013-05-28 8:55 ` [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board Alison Wang
2013-05-28 19:57 ` Benoît Thébaudeau
@ 2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> VF610TWR is a board based on Vybrid VF610 SoC.
>
> This patch adds basic support for Vybrid VF610TWR board.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart " Alison Wang
@ 2013-06-03 9:03 ` Stefano Babic
0 siblings, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds lpuart support for Vybrid VF610 platform.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog " Alison Wang
@ 2013-06-03 9:03 ` Stefano Babic
0 siblings, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds watchdog support for Vybrid VF610 platform.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610 Alison Wang
2013-05-28 19:21 ` Benoît Thébaudeau
@ 2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds FEC support for Vybrid VF610 platform.
>
> In function fec_open(), RCR register is only set as RGMII mode. But RCR
> register should be set as RMII mode for VF610 platform.
> This configuration is already done in fec_reg_setup(), so this piece of
> code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
> FEC_RCNTRL_MII_MODE bits.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
2013-05-28 18:57 ` Benoît Thébaudeau
@ 2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds the IOMUX support for Vybrid VF610 platform.
>
> There is a little difference for IOMUXC module between VF610 and i.MX
> platform, the muxmode and pad configuration share one 32bit register on
> VF610, but they are two independent registers on I.MX platform. A
> CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
2013-05-28 8:55 ` [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support Alison Wang
2013-05-28 19:16 ` Benoît Thébaudeau
@ 2013-06-03 9:03 ` Stefano Babic
1 sibling, 0 replies; 31+ messages in thread
From: Stefano Babic @ 2013-06-03 9:03 UTC (permalink / raw)
To: u-boot
On 28/05/2013 10:55, Alison Wang wrote:
> This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
>
> It aligns Vybrid VF610 platform with i.MX platform. As there are
> some differences between VF610 and i.MX platforms, the specific
> codes are in the arch/arm/cpu/armv7/vf610 directory.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2013-06-03 9:03 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-28 8:55 [U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support Alison Wang
2013-05-28 8:55 ` [U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610 Alison Wang
2013-05-28 18:57 ` Benoît Thébaudeau
2013-05-29 5:29 ` Wang Huan-B18965
2013-05-29 6:21 ` Stefano Babic
2013-05-29 14:54 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support Alison Wang
2013-05-28 19:16 ` Benoît Thébaudeau
2013-05-28 19:30 ` Benoît Thébaudeau
2013-05-29 5:37 ` Wang Huan-B18965
2013-05-29 14:46 ` Benoît Thébaudeau
2013-05-31 8:59 ` Stefano Babic
2013-05-31 16:10 ` Benoît Thébaudeau
2013-05-29 5:32 ` Wang Huan-B18965
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610 Alison Wang
2013-05-28 19:21 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog " Alison Wang
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 5/7] arm: vf610: Add uart " Alison Wang
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document Alison Wang
2013-05-31 16:10 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
2013-05-28 8:55 ` [U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board Alison Wang
2013-05-28 19:57 ` Benoît Thébaudeau
2013-05-29 5:52 ` Wang Huan-B18965
2013-05-29 14:49 ` Benoît Thébaudeau
2013-06-03 9:03 ` Stefano Babic
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