Link between Intel documentation events and perf list events

Link between Intel documentation events and perf list events

[Manuel Selva]

Hi all,

I am starting to deal with performance registers on an Intel core 
i5-2520M dual core (and hyperthreaded) processor. In this context I 
reached the CPUID x86 instruction. Playing with this instruction I am 
able to get some information about my cpu performance monitoring unit. 
According to this instruction my Last-level cache misses event is available.

My question is about the link between events reported in Intel 
documentation and events listed by perf list. Is the perf list 
cache-misses event the same than the one mentioned as Last-level cache 
missesin Intel documentation ?

Thanks,

--------
Manu

Re: Link between Intel documentation events and perf list events

[Andi Kleen]

Manuel Selva <manuel.selva@insa-lyon.fr> writes:

> My question is about the link between events reported in Intel
> documentation and events listed by perf list. Is the perf list
> cache-misses event the same than the one mentioned as Last-level cache
> missesin Intel documentation ?

Yes it is

(at least currently, perf events are not particularly well defined
and have changed in the past. However this one is proably not likely
to change)

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only

Re: Link between Intel documentation events and perf list events

[Manuel Selva]

Thanks for the answer Andi.

On a more general sense, how one can link perf events (as reported by 
perf list) to hardware documentation ? Is there some document explaining 
that or should I dig into the perf code source code in the Linux kernel ?

Manu

On 07/02/2013 05:55 AM, Andi Kleen wrote:
> Manuel Selva<manuel.selva@insa-lyon.fr>  writes:
>
>> My question is about the link between events reported in Intel
>> documentation and events listed by perf list. Is the perf list
>> cache-misses event the same than the one mentioned as Last-level cache
>> missesin Intel documentation ?
> Yes it is
>
> (at least currently, perf events are not particularly well defined
> and have changed in the past. However this one is proably not likely
> to change)
>
> -Andi
>

Re: Link between Intel documentation events and perf list events

[Andreas Hollmann]

Hi,

since Kernel version 3.7 you can lookup the used raw event in
/sys/device/cpu/events and compare it
to Table 18-1 SDM Volume 3B: System Programming Guide, Part 2.

$ cd /sys/devices/cpu/events/
$ echo *; cat *
branch-instructions branch-misses cache-misses cache-references
cpu-cycles instructions
event=0xc4
event=0xc5
event=0x2e,umask=0x41
event=0x2e,umask=0x4f
event=0x3c
event=0xc0

Here is commit from Jiri Olsa that makes it possible.
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a47473939db20e3961b200eb00acf5fcf084d755

Regards,
Andreas



2013/7/2 Manuel Selva <manuel.selva@insa-lyon.fr>:
> Thanks for the answer Andi.
>
> On a more general sense, how one can link perf events (as reported by perf
> list) to hardware documentation ? Is there some document explaining that or
> should I dig into the perf code source code in the Linux kernel ?
>
> Manu
>
>
> On 07/02/2013 05:55 AM, Andi Kleen wrote:
>>
>> Manuel Selva<manuel.selva@insa-lyon.fr>  writes:
>>
>>> My question is about the link between events reported in Intel
>>> documentation and events listed by perf list. Is the perf list
>>> cache-misses event the same than the one mentioned as Last-level cache
>>> missesin Intel documentation ?
>>
>> Yes it is
>>
>> (at least currently, perf events are not particularly well defined
>> and have changed in the past. However this one is proably not likely
>> to change)
>>
>> -Andi
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-perf-users"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: Link between Intel documentation events and perf list events

[Manuel Selva]

Thanks again for the help.Your answer suggests that events listed as 
Hardware event by perf listare what is called Architecural Events for 
Intel processors, isn't it ?

On my Sandy Bridge core i5-2520M, perf list reports 10 hardware events, 
where as they are only 7 entriesin the table 18-1 of Intel documentation 
you mentioned. So I am wondering what are these 3 additional events;

event=0x00,umask=0x03 (ref-cycles)
event=0xb1,umask=0x01,inv,cmask=0x01 (stalled-cycles-backend)
event=0x0e,umask=0x01,inv,cmask=0x01 (stalled-cycles-frontend)

Looking at table 19-7 in the same Intel document, I can see non 
architectural events for my core i5-2xxx. In this table I can see that:

ref-cycles                       ==> Can't find it
stalled-cycles-backend ==> Counts total number of uops to be dispatched 
per- thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.
stalled-cycles-frontend ==> Increments each cycle the # of Uops issued 
by the RAT to RS.Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 
of this core.

So my question is what is ref-cycles andwhat is the common property of 
event displayed as Hardware Event by perf ?

Manu

On 07/02/2013 02:39 PM, Andreas Hollmann wrote:
> Hi,
>
> since Kernel version 3.7 you can lookup the used raw event in
> /sys/device/cpu/events and compare it
> to Table 18-1 SDM Volume 3B: System Programming Guide, Part 2.
>
> $ cd /sys/devices/cpu/events/
> $ echo *; cat *
> branch-instructions branch-misses cache-misses cache-references
> cpu-cycles instructions
> event=0xc4
> event=0xc5
> event=0x2e,umask=0x41
> event=0x2e,umask=0x4f
> event=0x3c
> event=0xc0
>
> Here is commit from Jiri Olsa that makes it possible.
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a47473939db20e3961b200eb00acf5fcf084d755
>
> Regards,
> Andreas
>
>
>
> 2013/7/2 Manuel Selva <manuel.selva@insa-lyon.fr>:
>> Thanks for the answer Andi.
>>
>> On a more general sense, how one can link perf events (as reported by perf
>> list) to hardware documentation ? Is there some document explaining that or
>> should I dig into the perf code source code in the Linux kernel ?
>>
>> Manu
>>
>>
>> On 07/02/2013 05:55 AM, Andi Kleen wrote:
>>> Manuel Selva<manuel.selva@insa-lyon.fr>  writes:
>>>
>>>> My question is about the link between events reported in Intel
>>>> documentation and events listed by perf list. Is the perf list
>>>> cache-misses event the same than the one mentioned as Last-level cache
>>>> missesin Intel documentation ?
>>> Yes it is
>>>
>>> (at least currently, perf events are not particularly well defined
>>> and have changed in the past. However this one is proably not likely
>>> to change)
>>>
>>> -Andi
>>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-perf-users"
>> in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: Link between Intel documentation events and perf list events

[Andi Kleen]

On Tue, Jul 02, 2013 at 09:46:48AM +0200, Manuel Selva wrote:
> On a more general sense, how one can link perf events (as reported
> by perf list) to hardware documentation ? Is there some document
> explaining that or should I dig into the perf code source code in
> the Linux kernel ?

http://github.com/andikleen/pmu-tools has a event-rmap tool 
that can do that.

-Andi

Re: Link between Intel documentation events and perf list events

[Andi Kleen]

On Tue, Jul 02, 2013 at 03:33:18PM +0200, Manuel Selva wrote:
> Thanks again for the help.Your answer suggests that events listed as
> Hardware event by perf listare what is called Architecural Events
> for Intel processors, isn't it ?

perf uses a superset of the architectural events
(but only a small subset of a full Intel event list)

Also it supports setting the other events in raw form
(or various add-on tools exist to provide them as names)

> On my Sandy Bridge core i5-2520M, perf list reports 10 hardware
> events, where as they are only 7 entriesin the table 18-1 of Intel
> documentation you mentioned. So I am wondering what are these 3
> additional events;

Not all events supported by perf are in sysfs.

> 
> event=0x00,umask=0x03 (ref-cycles)
> event=0xb1,umask=0x01,inv,cmask=0x01 (stalled-cycles-backend)
> event=0x0e,umask=0x01,inv,cmask=0x01 (stalled-cycles-frontend)
> 
> Looking at table 19-7 in the same Intel document, I can see non
> architectural events for my core i5-2xxx. In this table I can see
> that:
> 
> ref-cycles                       ==> Can't find it

This is typically called CPU_CLK_UNHALTED.REF_TSC or so
in the Intel documentation.

> stalled-cycles-backend ==> Counts total number of uops to be
> dispatched per- thread each cycle. Set Cmask = 1, INV =1 to count
> stall cycles.
> stalled-cycles-frontend ==> Increments each cycle the # of Uops
> issued by the RAT to RS.Set Cmask = 1, Inv = 1, Any= 1to count
> stalled cycles of this core.

These two are very broken. Just ignore them.

-Andi

Re: Link between Intel documentation events and perf list events

[Manuel Selva]

[-- Attachment #1: Type: text/plain, Size: 2312 bytes --]

Thanks.

I still have question on perf, and because I can't find an answer on the 
net I am asking here again. I wrote a simple C program calling CPUID to 
get information about my laptop performance monitoring units (putting 
0XA in eax register before calling cpuid)

In the results located in ebx I see a 1 bit for the core cycle event and 
a 1 bit for the instruction retired event. According to Intel 
documentation these ones means that theassociated events are not 
available. But I can use these events with perf, and user libraries such 
as PAPI are telling me that they are available.

I attached to this mail my program, is there any problem in it, where is 
my mistake ?

Manu

On 07/02/2013 04:49 PM, Andi Kleen wrote:
> On Tue, Jul 02, 2013 at 03:33:18PM +0200, Manuel Selva wrote:
>> Thanks again for the help.Your answer suggests that events listed as
>> Hardware event by perf listare what is called Architecural Events
>> for Intel processors, isn't it ?
> perf uses a superset of the architectural events
> (but only a small subset of a full Intel event list)
>
> Also it supports setting the other events in raw form
> (or various add-on tools exist to provide them as names)
>
>> On my Sandy Bridge core i5-2520M, perf list reports 10 hardware
>> events, where as they are only 7 entriesin the table 18-1 of Intel
>> documentation you mentioned. So I am wondering what are these 3
>> additional events;
> Not all events supported by perf are in sysfs.
>
>> event=0x00,umask=0x03 (ref-cycles)
>> event=0xb1,umask=0x01,inv,cmask=0x01 (stalled-cycles-backend)
>> event=0x0e,umask=0x01,inv,cmask=0x01 (stalled-cycles-frontend)
>>
>> Looking at table 19-7 in the same Intel document, I can see non
>> architectural events for my core i5-2xxx. In this table I can see
>> that:
>>
>> ref-cycles                       ==> Can't find it
> This is typically called CPU_CLK_UNHALTED.REF_TSC or so
> in the Intel documentation.
>
>> stalled-cycles-backend ==> Counts total number of uops to be
>> dispatched per- thread each cycle. Set Cmask = 1, INV =1 to count
>> stall cycles.
>> stalled-cycles-frontend ==> Increments each cycle the # of Uops
>> issued by the RAT to RS.Set Cmask = 1, Inv = 1, Any= 1to count
>> stalled cycles of this core.
> These two are very broken. Just ignore them.
>
> -Andi


[-- Attachment #2: cpuid.c --]
[-- Type: text/x-csrc, Size: 2111 bytes --]

#include <stdio.h>

int main() {

    unsigned int resultEax;
    unsigned int resultEbx;
    unsigned int resultEdx;

    __asm__("movl $0xa, %%eax" : ); // Moves 0xA in EAX: CPUID input param to get performance monitoring info
    __asm__("cpuid" : );
    __asm__("movl %%eax, %0" :"=r"(resultEax) : :);
    __asm__("movl %%ebx, %0" :"=r"(resultEbx) : :);
    __asm__("movl %%edx, %0" :"=r"(resultEdx) : :);

    printf("%-82s =  %2u\n", "Version ID of architectural performance monitoring" , resultEax & 255U); // Bits 07 to 00
    printf("%-82s =  %2u\n", "Number of general-purpose performance monitoring counter per logical processor", (resultEax >> 8) & 255); // Bits 15 to 08
    printf("%-82s =  %2u\n", "Bit width of general-purpose performance monitoring counter", (resultEax >> 16) & 255); // Bits 23 to 16
    printf("%-82s =  %2u\n", "Length of EBX bit vector to enumerate architectural performance monitoring events", (resultEax >> 24) & 255); // Bits 31 to 24
    printf("\n");

    printf("%-82s =  %2u\n", "Core cycle event (0 if available, 1 if not)", resultEbx & 1); // Bits 00
    printf("%-82s =  %2u\n", "Instruction retired event (0 if available, 1 if not)", (resultEbx >> 1) & 1); // Bits 01
    printf("%-82s =  %2u\n", "Reference cycles event (0 if available, 1 if not)", (resultEbx >> 2) & 1); // Bits 02
    printf("%-82s =  %2u\n", "Last level cache reference event (0 if available, 1 if not)", (resultEbx >> 3) & 1); // Bits 03
    printf("%-82s =  %2u\n", "Last level cache misses event (0 if available, 1 if not)", (resultEbx >> 4) & 1); // Bits 04
    printf("%-82s =  %2u\n", "Branch instruction retired event (0 if available, 1 if not)", (resultEbx >> 5) & 1); // Bits 05
    printf("%-82s =  %2u\n", "Branch mispredict retired event (0 if available, 1 if not)", (resultEbx >> 6) & 1); // Bits 06
    printf("\n");

    printf("%-82s =  %2u\n", "Number of fixed-function performance counters", (resultEdx >> 0) & 15); // Bits 04 to 00
    printf("%-82s =  %2u\n", "Bit width of fixed-function performance counters", (resultEdx >> 5) & 255); // Bits 12 to 05

    return 0;
}

Re: Link between Intel documentation events and perf list events

[Andi Kleen]

>     __asm__("movl $0xa, %%eax" : ); // Moves 0xA in EAX: CPUID input param to get performance monitoring info
>     __asm__("cpuid" : );
>     __asm__("movl %%eax, %0" :"=r"(resultEax) : :);
>     __asm__("movl %%ebx, %0" :"=r"(resultEbx) : :);
>     __asm__("movl %%edx, %0" :"=r"(resultEdx) : :);

This is not a correct way to write gcc inline assembler, you cannot 
assume that registers stay valid between assembler statements.

The easiest way is to use the macros from cpuid.h.

Here's a valid test program. Various Intel CPUs report REF_TSC (2) not
there, but it's really there, just not quite following the
descriptions. Other than that the architectural events are generally
available.

#include <cpuid.h>
#include <stdio.h>
int main()
{
	unsigned a, b, c, d;
	/* check __get_cpuid_max here */
	__cpuid(10, a, b, c, d);
	printf("eax: %x ebx %x ecx %x edx %x\n", a, b, c, d);
	int i;
	for (i = 0; i < 10; i++) 
		if (b & (1 << i))
			printf("event %d not supported\n", i);
	return 0;
}


-Andi

Re: Link between Intel documentation events and perf list events

[Manuel Selva]

Thanks, the correct program is reporting all events as available.

Manu

On 07/03/2013 03:28 PM, Andi Kleen wrote:
> #include <cpuid.h>
> #include <stdio.h>
> int main()
> {
> 	unsigned a, b, c, d;
> 	/* check __get_cpuid_max here */
> 	__cpuid(10, a, b, c, d);
> 	printf("eax: %x ebx %x ecx %x edx %x\n", a, b, c, d);
> 	int i;
> 	for (i = 0; i < 10; i++)
> 		if (b & (1 << i))
> 			printf("event %d not supported\n", i);
> 	return 0;
> }