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From: "Yan, Zheng" <zheng.z.yan@intel.com>
To: "Yan, Zheng" <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
	mingo@elte.hu, eranian@google.com, ak@linux.intel.com
Subject: Re: [PATCH] perf, x86: Add Silvermont (22nm Atom) support
Date: Thu, 18 Jul 2013 13:39:28 +0800	[thread overview]
Message-ID: <51E77F90.3040007@intel.com> (raw)
In-Reply-To: <1374125767-9411-1-git-send-email-zheng.z.yan@intel.com>

On 07/18/2013 01:36 PM, Yan, Zheng wrote:
> From: "Yan, Zheng" <zheng.z.yan@intel.com>
> 
> Compare to old atom, Silvermont has offcore and has more events
> that support PEBS.
> 
> Silvermont has two offcore response configuration MSRs, but the
> event code for OFFCORE_RSP_1 is 0x02b7. To avoid complicating
> intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to define offcore
> MSRs. So intel_fixup_er() can find the code for OFFCORE_RSP_1
> by x86_pmu.extra_regs[1].event.
>

Document is at http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf, but it has no PEBS event list.

  reply	other threads:[~2013-07-18  5:39 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-18  5:36 [PATCH] perf, x86: Add Silvermont (22nm Atom) support Yan, Zheng
2013-07-18  5:39 ` Yan, Zheng [this message]
2013-07-18  8:42   ` Peter Zijlstra
2013-07-18 11:00     ` Yan, Zheng
2013-07-18  8:23 ` Peter Zijlstra
2013-07-18  8:27   ` Yan, Zheng
2013-07-18  9:02     ` Peter Zijlstra
2013-07-18 10:48       ` Yan, Zheng
2013-07-18 11:46         ` Peter Zijlstra
2013-07-19  2:26     ` Yan, Zheng
2013-07-18  8:29 ` Peter Zijlstra
2013-07-18  8:41 ` Peter Zijlstra

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