From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> To: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Subject: Re: [PATCH v2 16/22] iommu/tegra: smmu: Get "nvidia,swgroup" from DT Date: Thu, 18 Jul 2013 14:28:42 -0600 [thread overview] Message-ID: <51E84FFA.8020509@wwwdotorg.org> (raw) In-Reply-To: <1373021097-32420-17-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote: > This provides the info about which H/W Accelerators are supported on > Tegra SoC. This info is passed from DT. This is necessary to have the > unified SMMU driver among Tegra SoCs. Instead of using platform data, > DT passes "nvidia,swgroup" now. DT is mandatory in Tegra. > diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt > +- nvidia,swgroups: A bitmap of supported HardWare Accelerators(HWA). > + Each bit represents one swgroup. The assignments may be found in header > + file <dt-bindings/memory/tegra-swgroup.h>. There needs to be a default for this field if one is not specified so that existing DTs continue to work without modification. How many cells big is this property? Is this really a bitmap of HWAs? Surely it's a bitmap of SMMU client IDs? > Example: > - smmu { > + iommu { The node name shouldn't be interpreted by anything, so there should be no need to change it at all. Certainly, it should not be changed by this patch, since this patch is all about SMMU client IDs. > + nvidia,swgroups = TEGRA30_SWGROUP_ALL; As I mentioned before, macros shouldn't include syntax/structure, just data values. > diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c > @@ -265,7 +265,7 @@ struct smmu_client { > struct device *dev; > struct list_head list; > struct smmu_as *as; > - u32 hwgrp; > + u64 hwgrp; Why is that "hwgrp" not "swgrp"? Don't they represent the same thing? > @@ -307,6 +307,8 @@ struct smmu_device { > struct device *dev; > struct page *avp_vector_page; /* dummy page shared by all AS's */ > > + u64 swgroup; /* swgroup ID bitmap */ If that's a bitmap, then it represents multiple things, so "swgroups"? > @@ -382,10 +384,10 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) > */ > #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) > > -#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) > +#define smmu_client_hwgrp(c) (c->as->smmu->swgroup) hwgrp-vs-swgrp inconsistency again. Is this series git bisectable? I worry that by the time patch 14 is applied, the SMMU starts affecting client devices, whereas none of those client devices have swgroup values defined as their client data, and hence without this patch also applied, things might blow up in interesting ways. I wonder why the code was ever using dev->platform_data in this way; the platform data for a device should have its structure/semantics defined by the driver for that device, not by an SMMU that happens to affect that device. Ick! > static int __smmu_client_set_hwgrp(struct smmu_client *c, > - unsigned long map, int on) > + u64 map, int on) > { > int i; > struct smmu_as *as = c->as; > @@ -398,12 +400,11 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, > if (!on) > map = smmu_client_hwgrp(c); > > - for_each_set_bit(i, &map, HWGRP_COUNT) { > + for_each_set_bit(i, (unsigned long *)&map, > + sizeof(map) * BITS_PER_BYTE) { Why change the type if it just forces you to add this cast? > offs = HWGRP_ASID_REG(i); > val = smmu_read(smmu, offs); > if (on) { > - if (WARN_ON(val & mask)) > - goto err_hw_busy; Why?
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 16/22] iommu/tegra: smmu: Get "nvidia,swgroup" from DT Date: Thu, 18 Jul 2013 14:28:42 -0600 [thread overview] Message-ID: <51E84FFA.8020509@wwwdotorg.org> (raw) In-Reply-To: <1373021097-32420-17-git-send-email-hdoyu@nvidia.com> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote: > This provides the info about which H/W Accelerators are supported on > Tegra SoC. This info is passed from DT. This is necessary to have the > unified SMMU driver among Tegra SoCs. Instead of using platform data, > DT passes "nvidia,swgroup" now. DT is mandatory in Tegra. > diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt > +- nvidia,swgroups: A bitmap of supported HardWare Accelerators(HWA). > + Each bit represents one swgroup. The assignments may be found in header > + file <dt-bindings/memory/tegra-swgroup.h>. There needs to be a default for this field if one is not specified so that existing DTs continue to work without modification. How many cells big is this property? Is this really a bitmap of HWAs? Surely it's a bitmap of SMMU client IDs? > Example: > - smmu { > + iommu { The node name shouldn't be interpreted by anything, so there should be no need to change it at all. Certainly, it should not be changed by this patch, since this patch is all about SMMU client IDs. > + nvidia,swgroups = TEGRA30_SWGROUP_ALL; As I mentioned before, macros shouldn't include syntax/structure, just data values. > diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c > @@ -265,7 +265,7 @@ struct smmu_client { > struct device *dev; > struct list_head list; > struct smmu_as *as; > - u32 hwgrp; > + u64 hwgrp; Why is that "hwgrp" not "swgrp"? Don't they represent the same thing? > @@ -307,6 +307,8 @@ struct smmu_device { > struct device *dev; > struct page *avp_vector_page; /* dummy page shared by all AS's */ > > + u64 swgroup; /* swgroup ID bitmap */ If that's a bitmap, then it represents multiple things, so "swgroups"? > @@ -382,10 +384,10 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) > */ > #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) > > -#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) > +#define smmu_client_hwgrp(c) (c->as->smmu->swgroup) hwgrp-vs-swgrp inconsistency again. Is this series git bisectable? I worry that by the time patch 14 is applied, the SMMU starts affecting client devices, whereas none of those client devices have swgroup values defined as their client data, and hence without this patch also applied, things might blow up in interesting ways. I wonder why the code was ever using dev->platform_data in this way; the platform data for a device should have its structure/semantics defined by the driver for that device, not by an SMMU that happens to affect that device. Ick! > static int __smmu_client_set_hwgrp(struct smmu_client *c, > - unsigned long map, int on) > + u64 map, int on) > { > int i; > struct smmu_as *as = c->as; > @@ -398,12 +400,11 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, > if (!on) > map = smmu_client_hwgrp(c); > > - for_each_set_bit(i, &map, HWGRP_COUNT) { > + for_each_set_bit(i, (unsigned long *)&map, > + sizeof(map) * BITS_PER_BYTE) { Why change the type if it just forces you to add this cast? > offs = HWGRP_ASID_REG(i); > val = smmu_read(smmu, offs); > if (on) { > - if (WARN_ON(val & mask)) > - goto err_hw_busy; Why?
next prev parent reply other threads:[~2013-07-18 20:28 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-07-05 10:44 [PATCH v2 00/22] Unified SMMU driver among Tegra SoCs Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-1-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-05 10:44 ` [PATCH v2 01/22] [HACK] of: dev_node has struct device pointer Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-2-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 22:57 ` Stephen Warren 2013-07-16 22:57 ` Stephen Warren [not found] ` <51E5CFBF.5080407-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-16 23:16 ` Thierry Reding 2013-07-16 23:16 ` Thierry Reding [not found] ` <20130716231629.GA12189-RcKxWJ4Cfj3FNiLNb7+IINdj8bHVeoWogfoxzgwHRXE@public.gmane.org> 2013-07-29 10:13 ` Hiroshi Doyu 2013-07-29 10:13 ` Hiroshi Doyu [not found] ` <20130729.131344.1221933042559369096.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 13:13 ` Lorenzo Pieralisi 2013-07-29 13:13 ` Lorenzo Pieralisi 2013-07-05 10:44 ` [PATCH v2 02/22] ARM: tegra: Populate AHB/IOMMU earlier than others Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-3-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:03 ` Stephen Warren 2013-07-16 23:03 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 03/22] ARM: tegra: Create a DT header defining swgroups ID Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-4-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:07 ` Stephen Warren 2013-07-16 23:07 ` Stephen Warren [not found] ` <51E5D220.1070708-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 10:53 ` Hiroshi Doyu 2013-07-29 10:53 ` Hiroshi Doyu [not found] ` <20130729.135336.943359637886118972.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 17:45 ` Stephen Warren 2013-07-29 17:45 ` Stephen Warren [not found] ` <51F6AA2B.7050509-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-30 4:56 ` Hiroshi Doyu 2013-07-30 4:56 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 04/22] ARM: dt: tegra30: iommu: Add "nvidia,swgroup" Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-5-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:10 ` Stephen Warren 2013-07-16 23:10 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 05/22] ARM: dt: tegra30: iommu: Add "nvidia,memory-client" Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-6-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:14 ` [PATCH v2 05/22] ARM: dt: tegra30: iommu: Add "nvidia, memory-client" Stephen Warren 2013-07-16 23:14 ` Stephen Warren [not found] ` <51E5D3D9.2090608-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 11:06 ` [PATCH v2 05/22] ARM: dt: tegra30: iommu: Add "nvidia,memory-client" Hiroshi Doyu 2013-07-29 11:06 ` Hiroshi Doyu [not found] ` <20130729.140646.649065361266278007.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 17:47 ` Stephen Warren 2013-07-29 17:47 ` [PATCH v2 05/22] ARM: dt: tegra30: iommu: Add "nvidia, memory-client" Stephen Warren [not found] ` <51F6AA98.4020701-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-30 5:11 ` [PATCH v2 05/22] ARM: dt: tegra30: iommu: Add "nvidia,memory-client" Hiroshi Doyu 2013-07-30 5:11 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 06/22] ARM: dt: tegra114: iommu: Fix IOMMU register address Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-7-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:18 ` Stephen Warren 2013-07-16 23:18 ` Stephen Warren [not found] ` <51E5D4C5.4090109-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-16 23:27 ` Thierry Reding 2013-07-16 23:27 ` Thierry Reding 2013-07-05 10:44 ` [PATCH v2 07/22] ARM: dt: tegra114: iommu: Add "nvidia,swgroups" Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 08/22] ARM: dt: tegra114: Add "nvidia,memory-client" Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 09/22] amba: Move AHB to core_initcall Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-10-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:20 ` Stephen Warren 2013-07-16 23:20 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 10/22] iommu/tegra: smmu: Move IOMMU " Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-11-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-16 23:21 ` Stephen Warren 2013-07-16 23:21 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 11/22] iommu/tegra: smmu: Add Tegra 114 support Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-12-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:01 ` Stephen Warren 2013-07-18 20:01 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 12/22] iommu/tegra: smmu: Select ARM_DMA_USE_IOMMU in Kconfig Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 13/22] iommu/tegra: smmu: Create default IOVA maps Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-14-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:10 ` Stephen Warren 2013-07-18 20:10 ` Stephen Warren [not found] ` <51E84BB5.9010303-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 11:24 ` Hiroshi Doyu 2013-07-29 11:24 ` Hiroshi Doyu [not found] ` <20130729.142409.995770519696534476.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 17:50 ` Stephen Warren 2013-07-29 17:50 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 14/22] iommu/tegra: smmu: Register platform_device to IOMMU dynamically Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-15-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:17 ` Stephen Warren 2013-07-18 20:17 ` Stephen Warren [not found] ` <51E84D51.2030404-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 11:27 ` Hiroshi Doyu 2013-07-29 11:27 ` Hiroshi Doyu [not found] ` <20130729.142752.1020949402019811407.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 17:54 ` Stephen Warren 2013-07-29 17:54 ` Stephen Warren [not found] ` <51F6AC41.30007-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-30 5:18 ` Hiroshi Doyu 2013-07-30 5:18 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 15/22] iommu/tegra: smmu: Calculate ASID register offset by ID Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-16-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:18 ` Stephen Warren 2013-07-18 20:18 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 16/22] iommu/tegra: smmu: Get "nvidia,swgroup" from DT Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-17-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:28 ` Stephen Warren [this message] 2013-07-18 20:28 ` Stephen Warren [not found] ` <51E84FFA.8020509-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 11:39 ` Hiroshi Doyu 2013-07-29 11:39 ` Hiroshi Doyu [not found] ` <20130729.143950.524913713971518557.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 18:00 ` Stephen Warren 2013-07-29 18:00 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 17/22] iommu/tegra: smmu: Unfied driver for Tegra SoCs Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 18/22] iommu/tegra: smmu: Use dt-bindings MACRO Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-19-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:30 ` Stephen Warren 2013-07-18 20:30 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 19/22] iommu/tegra: smmu: Workaround PCIe IOMMU'able Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-20-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:33 ` Stephen Warren 2013-07-18 20:33 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 20/22] iommu/tegra: smmu: Get "nvidia,memory-client" from DT Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 20/22] iommu/tegra: smmu: Get "nvidia, memory-client" " Hiroshi Doyu [not found] ` <1373021097-32420-21-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:40 ` [PATCH v2 20/22] iommu/tegra: smmu: Get "nvidia,memory-client" " Stephen Warren 2013-07-18 20:40 ` Stephen Warren 2013-07-18 20:40 ` Stephen Warren 2013-07-05 10:44 ` [PATCH v2 21/22] iommu/tegra: smmu: Support Multiple ASID Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-22-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:43 ` Stephen Warren 2013-07-18 20:43 ` Stephen Warren [not found] ` <51E8535A.30605-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-29 10:31 ` Hiroshi Doyu 2013-07-29 10:31 ` Hiroshi Doyu [not found] ` <20130729.133155.1836775489422797370.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-29 17:41 ` Stephen Warren 2013-07-29 17:41 ` Stephen Warren [not found] ` <51F6A943.8000004-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-30 5:22 ` Hiroshi Doyu 2013-07-30 5:22 ` Hiroshi Doyu 2013-07-05 10:44 ` [PATCH v2 22/22] ARM: dma-mapping: Drop GFP_COMP for DMA memory allocations Hiroshi Doyu 2013-07-05 10:44 ` Hiroshi Doyu [not found] ` <1373021097-32420-23-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-18 20:45 ` Stephen Warren 2013-07-18 20:45 ` Stephen Warren 2013-07-05 11:03 ` [PATCH v2 00/22] Unified SMMU driver among Tegra SoCs Marc Dietrich 2013-07-05 11:03 ` Marc Dietrich [not found] ` <4999563.JlU6BysXQl-D3pzGp0ZKuDWZbiwp4sFPyrtisivX6KghOMvlBiLbJSELgA04lAiVw@public.gmane.org> 2013-07-05 11:08 ` Hiroshi Doyu 2013-07-05 11:08 ` Hiroshi Doyu 2013-07-08 8:47 ` Hiroshi Doyu [not found] ` <20130708.114736.1280783845180530098.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-08 15:49 ` Stephen Warren [not found] ` <51DADF91.30009-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2013-07-08 17:11 ` Hiroshi Doyu [not found] ` <20130708.201148.1964850060334610089.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-07-08 17:37 ` Stephen Warren 2013-09-23 17:07 ` Hiroshi Doyu
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