[uq/master PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore

[uq/master PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore

[Marcelo Tosatti]

The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on:

- APIC LVT Timer register.
- TSC value.

Change the order to respect the dependency.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 376fc70..d04c6ae 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1044,6 +1044,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
     entry->data = value;
 }
 
+static int kvm_put_tscdeadline_msr(X86CPU *cpu)
+{
+    CPUX86State *env = &cpu->env;
+    struct {
+        struct kvm_msrs info;
+        struct kvm_msr_entry entries[1];
+    } msr_data;
+    struct kvm_msr_entry *msrs = msr_data.entries;
+
+    if (!has_msr_tsc_deadline) {
+        return 0;
+    }
+
+    kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
+
+    msr_data.info.nmsrs = 1;
+
+    return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
+}
+
 static int kvm_put_msrs(X86CPU *cpu, int level)
 {
     CPUX86State *env = &cpu->env;
@@ -1067,9 +1087,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
     if (has_msr_tsc_adjust) {
         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
     }
-    if (has_msr_tsc_deadline) {
-        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
-    }
     if (has_msr_misc_enable) {
         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
                           env->msr_ia32_misc_enable);
@@ -1708,6 +1725,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
             return ret;
         }
     }
+
+    ret = kvm_put_tscdeadline_msr(x86_cpu);
+    if (ret < 0) {
+        return ret;
+    }
+
     ret = kvm_put_vcpu_events(x86_cpu, level);
     if (ret < 0) {
         return ret;

Re: [uq/master PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore

[Paolo Bonzini]

Il 19/08/2013 19:13, Marcelo Tosatti ha scritto:
> 
> The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on:
> 
> - APIC LVT Timer register.
> - TSC value.
> 
> Change the order to respect the dependency.

Do you have a testcase?

Paolo

> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
> 
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index 376fc70..d04c6ae 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -1044,6 +1044,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
>      entry->data = value;
>  }
>  
> +static int kvm_put_tscdeadline_msr(X86CPU *cpu)
> +{
> +    CPUX86State *env = &cpu->env;
> +    struct {
> +        struct kvm_msrs info;
> +        struct kvm_msr_entry entries[1];
> +    } msr_data;
> +    struct kvm_msr_entry *msrs = msr_data.entries;
> +
> +    if (!has_msr_tsc_deadline) {
> +        return 0;
> +    }
> +
> +    kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
> +
> +    msr_data.info.nmsrs = 1;
> +
> +    return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
> +}
> +
>  static int kvm_put_msrs(X86CPU *cpu, int level)
>  {
>      CPUX86State *env = &cpu->env;
> @@ -1067,9 +1087,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
>      if (has_msr_tsc_adjust) {
>          kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
>      }
> -    if (has_msr_tsc_deadline) {
> -        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
> -    }
>      if (has_msr_misc_enable) {
>          kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
>                            env->msr_ia32_misc_enable);
> @@ -1708,6 +1725,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
>              return ret;
>          }
>      }
> +
> +    ret = kvm_put_tscdeadline_msr(x86_cpu);
> +    if (ret < 0) {
> +        return ret;
> +    }
> +
>      ret = kvm_put_vcpu_events(x86_cpu, level);
>      if (ret < 0) {
>          return ret;
> 

Re: [uq/master PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore

[Marcelo Tosatti]

On Mon, Aug 19, 2013 at 08:57:58PM +0200, Paolo Bonzini wrote:
> Il 19/08/2013 19:13, Marcelo Tosatti ha scritto:
> > 
> > The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on:
> > 
> > - APIC LVT Timer register.
> > - TSC value.
> > 
> > Change the order to respect the dependency.
> 
> Do you have a testcase?
> 
> Paolo

Autotest:

python ConfigTest.py --guestname=RHEL.7  --driveformat=virtio_scsi
--nicmodel=e1000 --mem=2048 --vcpu=4
--testcase=timedrift..ntp.with_migration --nrepeat=10

Re: [uq/master PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore

[Paolo Bonzini]

Il 19/08/2013 22:01, Marcelo Tosatti ha scritto:
> On Mon, Aug 19, 2013 at 08:57:58PM +0200, Paolo Bonzini wrote:
>> Il 19/08/2013 19:13, Marcelo Tosatti ha scritto:
>>>
>>> The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on:
>>>
>>> - APIC LVT Timer register.
>>> - TSC value.
>>>
>>> Change the order to respect the dependency.
>>
>> Do you have a testcase?
>>
>> Paolo
> 
> Autotest:
> 
> python ConfigTest.py --guestname=RHEL.7  --driveformat=virtio_scsi
> --nicmodel=e1000 --mem=2048 --vcpu=4
> --testcase=timedrift..ntp.with_migration --nrepeat=10

Thanks, applied.

Paolo