[U-Boot] [PATCH v2 0/11] Support for the kmp204x reference design

[U-Boot] [PATCH v2 0/11] Support for the kmp204x reference design

[Valentin Longchamp]

This series includes all the needed patches to run u-boot on Keymile's
kmp204x reference design.

The kmp204x is a reference design based on Freescale's P2040/P2041 SoC.
It is supposed to be a reference platform for future boards. There is
currently only one board that is based on this design which is called
kmlion1.

The first 10 patches of the series are small changes to the generic
Keymile board support code as well as minor changes to some Freescale
drivers and CPU support.

The final patch 11 is where the new kmp204x code is introduced. It is
mostly based on the existing P2041rdb code by Freescale which was
adapted to our design.

Changes in v2:
- Introduce CONFIG_KM_I2C_ABORT #define to avoid #if !defined in
  common.c
- add CONFIG_KM_COMMON_ETH_INIT for the km board that need the common.c
  board_eth_init
- when refresh rate gets halved for extended range temperature
  operations, the srt bit in the mode register 2 is set.
- Remove patch "5/8 fsl: do not define FSL_SRIO_PCIE_BOOT_MASTER for all
  P2041 systems" from the series as it is not needed with current u-boot.
- fix the defines used in kmp204x/law.c for the lbus local address
  windows.
- fix the header files to include Freescale's copyrights
- integrate Scott's feedback

Valentin Longchamp (11):
  km-powerpc: move SYS_MALLOC_LEN out of keymile-common.h
  km-powerpc: move CONFIG_FLASH_CFI_MTD to km83xx-common.h
  KM: fix typo in default environment
  KM: add CONFIG_KM_I2C_ABORT option
  km: add CONFIG_KM_COMMON_ETH_INIT for km common eth init
  mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it
  net/fman: add a fm_enable_port function
  mtd/fsl_elbc: take NAND_ECC_SOFT_BCH config option into account
  fsl/mpc85xx: introduce fsl_print_rcw function
  fsl/mpc85xx: define common serdes_clock_to_string function
  mpc85xx: introduce the kmp204x reference design support

 MAINTAINERS                                        |   1 +
 arch/powerpc/cpu/mpc85xx/Makefile                  |   1 +
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c     |  21 +
 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c         |  43 ++
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c      |  17 +
 .../powerpc/cpu/mpc8xxx/ddr/common_timing_params.h |   1 +
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c           |   7 +-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c    |   4 +
 .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c        |   5 +
 arch/powerpc/include/asm/fsl_ddr_dimm_params.h     |   1 +
 arch/powerpc/include/asm/fsl_rcw.h                 |  19 +
 arch/powerpc/include/asm/fsl_serdes.h              |   1 +
 board/freescale/b4860qds/b4860qds.c                |  29 +-
 board/freescale/corenet_ds/corenet_ds.c            |  38 +-
 board/freescale/p2041rdb/p2041rdb.c                |  14 -
 board/freescale/t4qds/t4qds.c                      |  28 +-
 board/keymile/common/common.c                      |   8 +-
 board/keymile/kmp204x/Makefile                     |  48 +++
 board/keymile/kmp204x/ddr.c                        |  80 ++++
 board/keymile/kmp204x/eth.c                        |  87 ++++
 board/keymile/kmp204x/kmp204x.c                    | 285 +++++++++++++
 board/keymile/kmp204x/kmp204x.h                    |  31 ++
 board/keymile/kmp204x/law.c                        |  56 +++
 board/keymile/kmp204x/pbi.cfg                      |  51 +++
 board/keymile/kmp204x/pci.c                        |  51 +++
 board/keymile/kmp204x/rcw_kmp204x.cfg              |  11 +
 board/keymile/kmp204x/tlb.c                        | 126 ++++++
 boards.cfg                                         |   1 +
 drivers/mtd/nand/fsl_elbc_nand.c                   |   6 +-
 drivers/net/fm/init.c                              |   7 +
 include/configs/km/keymile-common.h                |   4 +-
 include/configs/km/km-powerpc.h                    |   4 +-
 include/configs/km/km83xx-common.h                 |   4 +
 include/configs/km/km_arm.h                        |   2 +
 include/configs/km/kmp204x-common.h                | 462 +++++++++++++++++++++
 include/configs/km82xx.h                           |   2 +
 include/configs/kmp204x.h                          |  84 ++++
 include/fm_eth.h                                   |   1 +
 38 files changed, 1534 insertions(+), 107 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
 create mode 100644 arch/powerpc/include/asm/fsl_rcw.h
 create mode 100644 board/keymile/kmp204x/Makefile
 create mode 100644 board/keymile/kmp204x/ddr.c
 create mode 100644 board/keymile/kmp204x/eth.c
 create mode 100644 board/keymile/kmp204x/kmp204x.c
 create mode 100644 board/keymile/kmp204x/kmp204x.h
 create mode 100644 board/keymile/kmp204x/law.c
 create mode 100644 board/keymile/kmp204x/pbi.cfg
 create mode 100644 board/keymile/kmp204x/pci.c
 create mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg
 create mode 100644 board/keymile/kmp204x/tlb.c
 create mode 100644 include/configs/km/kmp204x-common.h
 create mode 100644 include/configs/kmp204x.h

-- 
1.8.0.1

[U-Boot] [PATCH v2 01/11] km-powerpc: move SYS_MALLOC_LEN out of keymile-common.h

[Valentin Longchamp]

It can be set to a different value for kmp204x, because we are
restricted to SRAM.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 include/configs/km/keymile-common.h | 2 --
 include/configs/km/km83xx-common.h  | 2 ++
 include/configs/km82xx.h            | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 3b15c4e..ab4e2f8 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -98,8 +98,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
 /* UBI Support for all Keymile boards */
 #define CONFIG_CMD_UBI
 #define CONFIG_RBTREE
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index eb0e5b6..cdfa83a 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -80,6 +80,8 @@
 
 /* Reserve 768 kB for Mon */
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /*
  * Initial RAM Base Address Setup
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index 3c2117f..ae36768 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -225,6 +225,7 @@
 #define CONFIG_SYS_RAMBOOT
 #endif
 
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 #define CONFIG_SYS_MONITOR_LEN		(768 << 10)
 
 #define CONFIG_ENV_IS_IN_FLASH
-- 
1.8.0.1

[U-Boot] [PATCH v2 02/11] km-powerpc: move CONFIG_FLASH_CFI_MTD to km83xx-common.h

[Valentin Longchamp]

This is because kmp204x.h does not have FLASH, so this must not be
defined for all powerpc boards.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 include/configs/km/km-powerpc.h    | 1 -
 include/configs/km/km83xx-common.h | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index b84f12d..33b3c9e 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -40,7 +40,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #define CONFIG_ENV_SIZE		0x04000		/* Size of Environment */
-#define CONFIG_FLASH_CFI_MTD
 
 #define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
 
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index cdfa83a..a0e69e4 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -15,6 +15,8 @@
 #include "keymile-common.h"
 #include "km-powerpc.h"
 
+#define CONFIG_FLASH_CFI_MTD
+
 #ifndef MTDIDS_DEFAULT
 # define MTDIDS_DEFAULT	"nor0=boot"
 #endif /* MTDIDS_DEFAULT */
-- 
1.8.0.1

[U-Boot] [PATCH v2 03/11] KM: fix typo in default environment

[Valentin Longchamp]

The ip kernel parameter had a typo in it (we've been lucky that it has
worked until now).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 include/configs/km/keymile-common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index ab4e2f8..1ac2c35 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -183,7 +183,7 @@
 	"add_default="							\
 		"setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off3"				\
+		":${hostname}:${netdev}:off:"				\
 		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
 		" mem=${kernelmem} init=${init}"			\
 		CONFIG_KM_ECC_MODE					\
-- 
1.8.0.1

[U-Boot] [PATCH v2 04/11] KM: add CONFIG_KM_I2C_ABORT option

[Valentin Longchamp]

This must be defined for all the keymile boards that use the common
i2c_abort function that is used to "reset" the I2C bus. These are
currently km82xx and km_arm boards. This patch defines them for both
architectures.

The kmp204x and km83xx boards use other functions and thus do not define
this.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

---
Changes in v2:
- Introduce CONFIG_KM_I2C_ABORT #define to avoid #if !defined in
  common.c

 board/keymile/common/common.c | 6 +-----
 include/configs/km/km_arm.h   | 1 +
 include/configs/km82xx.h      | 1 +
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index ef93ed3..421ef8a 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -40,10 +40,6 @@
 #include "common.h"
 #include <i2c.h>
 
-#if !defined(CONFIG_MPC83xx)
-static void i2c_write_start_seq(void);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -94,7 +90,7 @@ int set_km_env(void)
 }
 
 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
-#if !defined(CONFIG_MPC83xx)
+#if defined(CONFIG_KM_I2C_ABORT)
 static void i2c_write_start_seq(void)
 {
 	set_sda(1);
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 766d76e..ac84e16 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -59,6 +59,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
+#define CONFIG_KM_I2C_ABORT
 
 /* SPI NOR Flash default params, used by sf commands */
 #define CONFIG_SF_DEFAULT_SPEED		8100000
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index ae36768..974b060 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -247,6 +247,7 @@
 #define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed */
 #define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address */
+#define CONFIG_KM_I2C_ABORT
 
 /*
  * Software (bit-bang) I2C driver configuration
-- 
1.8.0.1

[U-Boot] [PATCH v2 05/11] km: add CONFIG_KM_COMMON_ETH_INIT for km common eth init

[Valentin Longchamp]

This must be defined by a board support file that want to use the
keymile common.c board_eth_init function that requires ethernet_present
to be defined.

Currently all the km architectures use it but the kmp204x architecture
later supported in this series does use another board_eth_init function
and thus does not define it.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

---
Changes in v2:
- add CONFIG_KM_COMMON_ETH_INIT for the km board that need the common.c
  board_eth_init

 board/keymile/common/common.c   | 2 ++
 include/configs/km/km-powerpc.h | 3 +++
 include/configs/km/km_arm.h     | 1 +
 3 files changed, 6 insertions(+)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 421ef8a..a4afba9 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -179,6 +179,7 @@ void i2c_init_board(void)
 }
 #endif
 
+#if defined(CONFIG_KM_COMMON_ETH_INIT)
 int board_eth_init(bd_t *bis)
 {
 	if (ethernet_present())
@@ -186,6 +187,7 @@ int board_eth_init(bd_t *bis)
 
 	return -1;
 }
+#endif
 
 /*
  * do_setboardid command
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 33b3c9e..9b882cc 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -33,6 +33,9 @@
 #define CONFIG_CMD_DTT
 #define CONFIG_JFFS2_CMDLINE
 
+/* standard km ethernet_present for piggy */
+#define CONFIG_KM_COMMON_ETH_INIT
+
 /* EEprom support 24C08, 24C16, 24C64 */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index ac84e16..ad6628e 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -179,6 +179,7 @@
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
 
 /*
  * UBI related stuff
-- 
1.8.0.1

[U-Boot] [PATCH v2 06/11] mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

[Valentin Longchamp]

If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

---
Changes in v2:
- when refresh rate gets halved for extended range temperature
  operations, the srt bit in the mode register 2 is set.

 arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h  | 1 +
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c             | 7 ++++++-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c      | 4 ++++
 arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 5 +++++
 arch/powerpc/include/asm/fsl_ddr_dimm_params.h       | 1 +
 5 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 06706ed..48de019 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -28,6 +28,7 @@ typedef struct {
 	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
 
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
 	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 26c42f7..108e4d6 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -764,6 +764,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
 {
 	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
@@ -781,6 +782,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 		rtt_wr = popts->rtt_wr_override_value;
 	else
 		rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+	if (common_dimm->extended_op_srt)
+		srt = common_dimm->extended_op_srt;
+
 	esdmode2 = (0
 		| ((rtt_wr & 0x3) << 9)
 		| ((srt & 0x1) << 7)
@@ -1625,7 +1630,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
 	set_ddr_sdram_interval(ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 3e7c269..7e4dfd1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -320,6 +320,10 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 *       = 3.9 us@ext temperature range
 	 */
 	pdimm->refresh_rate_ps = 7800000;
+	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
+		pdimm->refresh_rate_ps = 3900000;
+		pdimm->extended_op_srt = 1;
+	}
 
 	/*
 	 * min four active window delay time
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e958e13..d5e09e5 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -92,6 +92,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	unsigned int tRRD_ps = 0;
 	unsigned int tRC_ps = 0;
 	unsigned int refresh_rate_ps = 0;
+	unsigned int extended_op_srt = 1;
 	unsigned int tIS_ps = 0;
 	unsigned int tIH_ps = 0;
 	unsigned int tDS_ps = 0;
@@ -166,6 +167,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
 		refresh_rate_ps = max(refresh_rate_ps,
 				      dimm_params[i].refresh_rate_ps);
+		/* extended_op_srt is either 0 or 1, 0 having priority */
+		extended_op_srt = min(extended_op_srt,
+				      dimm_params[i].extended_op_srt);
 
 		/*
 		 * Find maximum tDQSQ_max_ps to find slowest.
@@ -195,6 +199,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	outpdimm->tRRD_ps = tRRD_ps;
 	outpdimm->tRC_ps = tRC_ps;
 	outpdimm->refresh_rate_ps = refresh_rate_ps;
+	outpdimm->extended_op_srt = extended_op_srt;
 	outpdimm->tIS_ps = tIS_ps;
 	outpdimm->tIH_ps = tIH_ps;
 	outpdimm->tDS_ps = tDS_ps;
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index ffe4db8..6c8376f 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -77,6 +77,7 @@ typedef struct dimm_params_s {
 	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
 
 	/* DDR3 doesn't need these as below */
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-- 
1.8.0.1

[U-Boot] [PATCH v2 07/11] net/fman: add a fm_enable_port function

[Valentin Longchamp]

This can be useful if we want to disable an interface in u-boot and
later reenable them, so that it looks available when trying to fix the
FDT or for the kernel.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 drivers/net/fm/init.c | 7 +++++++
 include/fm_eth.h      | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 5908c32..820277e 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -158,6 +158,13 @@ void fm_disable_port(enum fm_port port)
 	fman_disable_port(port);
 }
 
+void fm_enable_port(enum fm_port port)
+{
+	int i = fm_port_to_index(port);
+
+	fm_info[i].enabled = 1;
+}
+
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
 {
 	int i = fm_port_to_index(port);
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 8fcf172..b464e04 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -162,5 +162,6 @@ void fm_info_set_phy_address(enum fm_port port, int address);
 int fm_info_get_phy_address(enum fm_port port);
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
 void fm_disable_port(enum fm_port port);
+void fm_enable_port(enum fm_port port);
 
 #endif
-- 
1.8.0.1

[U-Boot] [PATCH v2 08/11] mtd/fsl_elbc: take NAND_ECC_SOFT_BCH config option into account

[Valentin Longchamp]

NAND_ECC_SOFT was the only option available while the SOFT_BCH option
may also be used.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
---
Changes in v2: None

 drivers/mtd/nand/fsl_elbc_nand.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 0fa776a..a023f97 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -771,8 +771,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 		nand->ecc.steps = 1;
 		nand->ecc.strength = 1;
 	} else {
-		/* otherwise fall back to default software ECC */
+		/* otherwise fall back to software ECC */
+#if defined(CONFIG_NAND_ECC_BCH)
+		nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
 		nand->ecc.mode = NAND_ECC_SOFT;
+#endif
 	}
 
 	ret = nand_scan_ident(mtd, 1, NULL);
-- 
1.8.0.1

[U-Boot] [PATCH v2 09/11] fsl/mpc85xx: introduce fsl_print_rcw function

[Valentin Longchamp]

The RCW gets printed on a lot of FSL 85xx devices and it is always done
the same way.

The fsl_print_rcw function performs this exact same task.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 arch/powerpc/cpu/mpc85xx/Makefile          |  1 +
 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c | 43 ++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_rcw.h         | 19 +++++++++++++
 board/freescale/b4860qds/b4860qds.c        | 13 ++-------
 board/freescale/corenet_ds/corenet_ds.c    | 24 +++++++----------
 board/freescale/t4qds/t4qds.c              | 12 ++-------
 6 files changed, 76 insertions(+), 36 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
 create mode 100644 arch/powerpc/include/asm/fsl_rcw.h

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 4669883..8c51619 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -114,6 +114,7 @@ COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
+COBJS-$(CONFIG_FSL_CORENET)	+= fsl_corenet_rcw.o
 
 # SoC specific SERDES support
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
new file mode 100644
index 0000000..ca3a566
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_FSL_CORENET
+void fsl_print_rcw(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+}
+#endif
+
diff --git a/arch/powerpc/include/asm/fsl_rcw.h b/arch/powerpc/include/asm/fsl_rcw.h
new file mode 100644
index 0000000..077f176
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_rcw.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_RCW_H
+#define __ASM_PPC_FSL_RCW_H
+
+void fsl_print_rcw(void);
+
+#endif /* __ASM_PPC_FSL_RCW_H */
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index a39c17a..e9817c0 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -33,6 +33,7 @@
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <asm/fsl_rcw.h>
 #include <fm_eth.h>
 
 #include "../common/qixis.h"
@@ -51,8 +52,6 @@ int checkboard(void)
 	char buf[64];
 	u8 sw;
 	struct cpu_type *cpu = gd->arch.cpu;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	unsigned int i;
 	static const char *const freq[] = {"100", "125", "156.25", "161.13",
 						"122.88", "122.88", "122.88"};
 	int clock;
@@ -80,15 +79,7 @@ int checkboard(void)
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
-	puts("Reset Configuration Word (RCW):");
-	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-		u32 rcw = in_be32(&gur->rcwsr[i]);
-
-		if ((i % 4) == 0)
-			printf("\n       %08x:", i * 4);
-		printf(" %08x", rcw);
-	}
-	puts("\n");
+	fsl_print_rcw();
 
 	/*
 	 * Display the actual SERDES reference clocks as configured by the
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 48f7155..33e2aa5 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -32,6 +32,7 @@
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <asm/fsl_rcw.h>
 #include <fm_eth.h>
 
 #include "../common/ngpixis.h"
@@ -43,8 +44,6 @@ int checkboard (void)
 {
 	u8 sw;
 	struct cpu_type *cpu = gd->arch.cpu;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	unsigned int i;
 	static const char * const freq[] = {"100", "125", "156.25", "212.5" };
 
 	printf("Board: %sDS, ", cpu->name);
@@ -66,15 +65,7 @@ int checkboard (void)
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
-	puts("Reset Configuration Word (RCW):");
-	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-		u32 rcw = in_be32(&gur->rcwsr[i]);
-
-		if ((i % 4) == 0)
-			printf("\n       %08x:", i * 4);
-		printf(" %08x", rcw);
-	}
-	puts("\n");
+	fsl_print_rcw();
 
 	/* Display the actual SERDES reference clocks as configured by the
 	 * dip switches on the board.  Note that the SWx registers could
@@ -86,11 +77,14 @@ int checkboard (void)
 	puts("SERDES Reference Clocks: ");
 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
 	|| defined(CONFIG_P5040DS)
-	sw = in_8(&PIXIS_SW(5));
-	for (i = 0; i < 3; i++) {
-		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+	{
+		unsigned int i;
+		sw = in_8(&PIXIS_SW(5));
+		for (i = 0; i < 3; i++) {
+			unsigned int clock = (sw >> (6 - (2 * i))) & 3;
 
-		printf("Bank%u=%sMhz ", i+1, freq[clock]);
+			printf("Bank%u=%sMhz ", i+1, freq[clock]);
+		}
 	}
 #ifdef CONFIG_P5040DS
 	/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index f0f280b..3ec1509 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -33,6 +33,7 @@
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <asm/fsl_rcw.h>
 #include <fm_eth.h>
 
 #include "../common/qixis.h"
@@ -59,7 +60,6 @@ int checkboard(void)
 	char buf[64];
 	u8 sw;
 	struct cpu_type *cpu = gd->arch.cpu;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	unsigned int i;
 
 	printf("Board: %sQDS, ", cpu->name);
@@ -87,15 +87,7 @@ int checkboard(void)
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
-	puts("Reset Configuration Word (RCW):");
-	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-		u32 rcw = in_be32(&gur->rcwsr[i]);
-
-		if ((i % 4) == 0)
-			printf("\n       %08x:", i * 4);
-		printf(" %08x", rcw);
-	}
-	puts("\n");
+	fsl_print_rcw();
 
 	/*
 	 * Display the actual SERDES reference clocks as configured by the
-- 
1.8.0.1

[U-Boot] [PATCH v2 10/11] fsl/mpc85xx: define common serdes_clock_to_string function

[Valentin Longchamp]

This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2: None

 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 +++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c  | 17 +++++++++++++++++
 arch/powerpc/include/asm/fsl_serdes.h          |  1 +
 board/freescale/b4860qds/b4860qds.c            | 16 ----------------
 board/freescale/corenet_ds/corenet_ds.c        | 14 --------------
 board/freescale/p2041rdb/p2041rdb.c            | 14 --------------
 board/freescale/t4qds/t4qds.c                  | 16 ----------------
 7 files changed, 39 insertions(+), 60 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 93eca76..ff78070 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -201,3 +201,24 @@ void fsl_serdes_init(void)
 #endif
 
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328123";
+	default:
+#if defined(CONFIG_T4240QDS)
+		return "???";
+#else
+		return "122.88";
+#endif
+	}
+}
+
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index b621adf..4bee5bc 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -874,3 +874,20 @@ void fsl_serdes_init(void)
 	}
 #endif
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328123";
+	default:
+		return "150";
+	}
+}
+
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index ccb91fb..dfac186 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -99,6 +99,7 @@ enum srds {
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index e9817c0..b46482a 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -367,22 +367,6 @@ static int serdes_refclock(u8 sw, u8 sdclk)
 	return ret;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	case SRDS_PLLCR0_RFCK_SEL_161_13:
-		return "161.13";
-	default:
-		return "122.88";
-	}
-}
-
 #define NUM_SRDS_BANKS	2
 
 int misc_init_r(void)
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 33e2aa5..d6ad3a3 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -148,20 +148,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch(clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	default:
-		return "150";
-	}
-}
-
 #define NUM_SRDS_BANKS	3
 
 int misc_init_r(void)
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 44d3e0c..f61dd64 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -186,20 +186,6 @@ unsigned long get_board_sys_clk(unsigned long dummy)
 	}
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	default:
-		return "150";
-	}
-}
-
 #define NUM_SRDS_BANKS	2
 
 int misc_init_r(void)
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 3ec1509..44be6b3 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -595,22 +595,6 @@ unsigned long get_board_ddr_clk(void)
 	return 66666666;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	case SRDS_PLLCR0_RFCK_SEL_161_13:
-		return "161.1328125";
-	default:
-		return "???";
-	}
-}
-
 int misc_init_r(void)
 {
 	u8 sw;
-- 
1.8.0.1

[U-Boot] [PATCH v2 11/11] mpc85xx: introduce the kmp204x reference design support

[Valentin Longchamp]

This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.

The peripherals used by this design are:
- DDR3 RAM with SPD support
- SPI NOR Flash as boot medium
- NAND Flash
- 2 PCIe busses (hosts 1 and 3)
- 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
- 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
  FPGA
- 2 HW I2C busses
- last but not least, the mandatory serial port

The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
support and was changed according to our design (that means essentially
removing what is not present on the designs and a few adaptations).

There is currently only one prototype board that is based on this design
and this patch also introduces it. The board is called kmlion1.

Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
Changes in v2:
- Remove patch "5/8 fsl: do not define FSL_SRIO_PCIE_BOOT_MASTER for all
  P2041 systems" from the series as it is not needed with current u-boot.
- fix the defines used in kmp204x/law.c for the lbus local address
  windows.
- fix the header files to include Freescale's copyrights
- integrate Scott's feedback

 MAINTAINERS                           |   1 +
 board/keymile/kmp204x/Makefile        |  48 ++++
 board/keymile/kmp204x/ddr.c           |  80 ++++++
 board/keymile/kmp204x/eth.c           |  87 +++++++
 board/keymile/kmp204x/kmp204x.c       | 285 +++++++++++++++++++++
 board/keymile/kmp204x/kmp204x.h       |  31 +++
 board/keymile/kmp204x/law.c           |  56 +++++
 board/keymile/kmp204x/pbi.cfg         |  51 ++++
 board/keymile/kmp204x/pci.c           |  51 ++++
 board/keymile/kmp204x/rcw_kmp204x.cfg |  11 +
 board/keymile/kmp204x/tlb.c           | 126 ++++++++++
 boards.cfg                            |   1 +
 include/configs/km/kmp204x-common.h   | 462 ++++++++++++++++++++++++++++++++++
 include/configs/kmp204x.h             |  84 +++++++
 14 files changed, 1374 insertions(+)
 create mode 100644 board/keymile/kmp204x/Makefile
 create mode 100644 board/keymile/kmp204x/ddr.c
 create mode 100644 board/keymile/kmp204x/eth.c
 create mode 100644 board/keymile/kmp204x/kmp204x.c
 create mode 100644 board/keymile/kmp204x/kmp204x.h
 create mode 100644 board/keymile/kmp204x/law.c
 create mode 100644 board/keymile/kmp204x/pbi.cfg
 create mode 100644 board/keymile/kmp204x/pci.c
 create mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg
 create mode 100644 board/keymile/kmp204x/tlb.c
 create mode 100644 include/configs/km/kmp204x-common.h
 create mode 100644 include/configs/kmp204x.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 081cf96..fff77f0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -778,6 +778,7 @@ Valentin Longchamp <valentin.longchamp@keymile.com>
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
 	kmcoge5un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
+	kmcoge4		MPC85xx (P2041 SoC)
 
 Nishanth Menon <nm@ti.com>
 
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
new file mode 100644
index 0000000..35d17ce
--- /dev/null
+++ b/board/keymile/kmp204x/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \
+	../common/common.o ../common/ivm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
new file mode 100644
index 0000000..7b218ed
--- /dev/null
+++ b/board/keymile/kmp204x/ddr.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+
+	/* automatic calibration for nb of cycles between read and DQS pre */
+	popts->cpo_override = 0xFF;
+
+	/* 1/2 clk delay between wr command and data strobe */
+	popts->write_data_delay = 4;
+	/* clk lauched 1/2 applied cylcle after address command */
+	popts->clk_adjust = 4;
+	/* 1T timing: command/address held for only 1 cycle */
+	popts->twoT_en = 0;
+
+	/* we have only one module, half str should be OK */
+	popts->half_strength_driver_enable = 1;
+
+	/* wrlvl values overriden as recommended by ddr init func */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x6;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+	puts("Initializing with SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	return dram_size;
+}
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
new file mode 100644
index 0000000..f05f0be
--- /dev/null
+++ b/board/keymile/kmp204x/eth.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+
+	printf("Initializing Fman\n");
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	/* DTESC1/2 don't have a PHY, they are temporarily disabled
+	 * so that u-boot doesn't try to unsuccessfuly enable them */
+	fm_disable_port(FM1_DTSEC1);
+	fm_disable_port(FM1_DTSEC2);
+
+	/*
+	 * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
+	 * This is the debug interface, the only one used in u-boot
+	 */
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+	fm_info_set_mdio(FM1_DTSEC5,
+			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+	ret = cpu_eth_init(bis);
+
+	/* reenable DTSEC1/2 for later (kernel) */
+	fm_enable_port(FM1_DTSEC1);
+	fm_enable_port(FM1_DTSEC2);
+#endif
+
+	return ret;
+}
+
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
+
+#define mv88E1118_PAGE_REG	22
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
+		/* driver config is good */
+		if (phydev->drv->config)
+			phydev->drv->config(phydev);
+
+		/* but we still need to fix the LEDs */
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
new file mode 100644
index 0000000..3f2b268
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_rcw.h>
+#include <fm_eth.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
+
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	fsl_print_rcw();
+
+	return 0;
+}
+
+/* TODO: implement the I2C functions */
+void i2c_write_start_seq(void)
+{
+	return;
+}
+
+int i2c_make_abort(void)
+{
+	return 1;
+}
+
+#define ZL30158_RST	8
+#define ZL30343_RST	9
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
+	setbits_be32(&gur->ddrclkdr, 0x001f000f);
+
+	/* take the Zarlinks out of reset as soon as possible */
+	qrio_prst(ZL30158_RST, false, false);
+	qrio_prst(ZL30343_RST, false, false);
+
+	/* and set their reset to power-up only */
+	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
+	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	set_liodns();
+	setup_portals();
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+	return 66666666;
+}
+
+#define WDMASK_OFF	0x16
+
+static void qrio_wdmask(u8 bit, bool wden)
+{
+	u16 wdmask;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+	if (wden)
+		wdmask |= (1 << bit);
+	else
+		wdmask &= ~(1 << bit);
+
+	out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF	0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+	u16 prst;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	qrio_wdmask(bit, wden);
+
+	prst = in_be16(qrio_base + PRST_OFF);
+
+	if (en)
+		prst &= ~(1 << bit);
+	else
+		prst |= (1 << bit);
+
+	out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF	0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+	u32 prstcfg;
+	u8 i;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+	for (i = 0; i < 2; i++) {
+		if (mode & (1<<i))
+			set_bit(2*bit+i, &prstcfg);
+		else
+			clear_bit(2*bit+i, &prstcfg);
+	}
+
+	out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
+
+
+#define BOOTCOUNT_OFF	0x12
+
+void bootcount_store(ulong counter)
+{
+	u8 val;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	val = (counter <= 255) ? (u8)counter : 255;
+	out_8(qrio_base + BOOTCOUNT_OFF, val);
+}
+
+ulong bootcount_load(void)
+{
+	u8 val;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	val = in_8(qrio_base + BOOTCOUNT_OFF);
+	return val;
+}
+
+#define NUM_SRDS_BANKS	2
+#define PHY_RST		15
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
+		SRDS_PLLCR0_RFCK_SEL_125};
+	unsigned int i;
+
+	/* check SERDES reference clocks */
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 actual = in_be32(&regs->bank[i].pllcr0);
+		actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (actual != expected[i]) {
+			printf("Warning: SERDES bank %u expects reference \
+			       clock %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected[i]),
+			       serdes_clock_to_string(actual));
+		}
+	}
+
+	/* take the mgmt eth phy out of reset */
+	qrio_prst(PHY_RST, false, false);
+
+	return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_read_eeprom();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_LAST_STAGE_INIT)
+int last_stage_init(void)
+{
+	set_km_env();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+	int node, i, ret;
+	char *tmp, *end;
+	unsigned char mac_addr[6];
+
+	/* get the mac addr from env */
+	tmp = getenv("ethaddr");
+	if (!tmp) {
+		printf("ethaddr env variable not defined\n");
+		return;
+	}
+	for (i = 0; i < 6; i++) {
+		mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+		if (tmp)
+			tmp = (*end) ? end+1 : end;
+	}
+
+	/* find the correct fdt ethernet path and correct it */
+	node = fdt_path_offset(blob, "/soc/fman/ethernet at e8000");
+	if (node < 0) {
+		printf("no /soc/fman/ethernet path offset\n");
+		return;
+	}
+	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting local-mac-address property\n");
+		return;
+	}
+}
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_fman_mac_addresses(blob);
+#endif
+}
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
new file mode 100644
index 0000000..97c034e
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define PRSTCFG_POWUP_UNIT_CORE_RST	0x0
+#define PRSTCFG_POWUP_UNIT_RST		0x1
+#define PRSTCFG_POWUP_RST		0x3
+
+void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_prstcfg(u8 bit, u8 mode);
+
+void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c
new file mode 100644
index 0000000..37edf3c
--- /dev/null
+++ b/board/keymile/kmp204x/law.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
new file mode 100644
index 0000000..0b99d51
--- /dev/null
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -0,0 +1,51 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 27170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
new file mode 100644
index 0000000..589b0b4
--- /dev/null
+++ b/board/keymile/kmp204x/pci.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#include "kmp204x.h"
+
+#define PCIE_SW_RST	14
+#define HOOPER_SW_RST	12
+
+void pci_init_board(void)
+{
+	qrio_prst(PCIE_SW_RST, false, false);
+	qrio_prst(HOOPER_SW_RST, false, false);
+	/* Hooper is not direcly PCIe capable */
+	mdelay(50);
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
new file mode 100644
index 0000000..832850d
--- /dev/null
+++ b/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for kmp204x boards
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+14600000 00000000 28200000 00000000
+148E70CF CFC02000 58000000 41000000
+00000000 00000000 00000000 F4429000
+00000000 00000000 00000000 00000000
diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c
new file mode 100644
index 0000000..9909825
--- /dev/null
+++ b/board/keymile/kmp204x/tlb.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	/* TLB 1 */
+	/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+	/* QRIO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64K, 1),
+	/* *I*G* - PCI1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI3 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI1&3 I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_128K, 1),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	/* LBAPP1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	/* LBAPP2 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_32K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 6a368de..b818f1e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -744,6 +744,7 @@ tuge1                        powerpc     mpc83xx     km83xx              keymile
 tuxx1                        powerpc     mpc83xx     km83xx              keymile        -           tuxx1:TUXX1
 kmopti2                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KMOPTI2
 kmsupx5                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KMSUPX5
+kmlion1                      powerpc     mpc85xx     kmp204x             keymile        -           kmp204x:KMLION1
 sbc8548                      powerpc     mpc85xx     sbc8548             -              -           sbc8548
 sbc8548_PCI_33               powerpc     mpc85xx     sbc8548             -              -           sbc8548:PCI,33
 sbc8548_PCI_33_PCIE          powerpc     mpc85xx     sbc8548             -              -           sbc8548:PCI,33,PCIE
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
new file mode 100644
index 0000000..48381d4
--- /dev/null
+++ b/include/configs/km/kmp204x-common.h
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_KMP204X_H
+#define _CONFIG_KMP204X_H
+
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P2041
+
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth2\0"
+
+/* common KM defines */
+#include "keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* Environment in SPI Flash */
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SIZE			0x04000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no brackets! */
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00800000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x54
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* resereved pram area at the end of memroy [hex] */
+#define CONFIG_KM_RESERVED_PRAM	0x0
+/* enable protected RAM */
+#define CONFIG_PRAM		0
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2000000
+#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
+			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
+			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
+			       | OR_FCM_RST	/* 1 clk read setup */	\
+			       | OR_FCM_PGS	/* Large page size */	\
+			       | OR_FCM_CST)	/* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE		0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
+				| OR_GPCM_BCTLD /* no LCTL assert */ \
+				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x118000
+#define CONFIG_SYS_I2C2_OFFSET		0x118100
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         20000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+/* RGMII (FM1 at DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_PHYLIB		/* recommended PHY management */
+#define CONFIG_ETHPRIME		"FM1 at DTSEC5"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * additionnal command line configuration.
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+/* we don't need flash support */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_FLASH_CFI_MTD
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+/* TODO: should be fixed with correct nand ctrl*/
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT		"nand0=fsl_elbc_nand"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"fsl_elbc_nand:"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
+
+/* TODO: we should add PRAM support, that comes with km-powerpc.h */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"		\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	""
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	""
+
+#endif /* _CONFIG_KMP204X_H */
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
new file mode 100644
index 0000000..8cde3c5
--- /dev/null
+++ b/include/configs/kmp204x.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* KMLION1 */
+#if defined(CONFIG_KMLION1)
+#define CONFIG_HOSTNAME		kmlion1
+#define CONFIG_KM_BOARD_NAME	"kmlion1"
+
+#else
+#error ("Board not supported")
+#endif
+
+#define CONFIG_KMP204X
+
+#include "km/kmp204x-common.h"
+
+#if defined(CONFIG_KMLION1)
+/* App1 Local bus */
+#define CONFIG_SYS_LBAPP1_BASE		0xD0000000
+#define CONFIG_SYS_LBAPP1_BASE_PHYS	0xFD0000000ull
+
+#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app1 Base Address */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_LBAPP1_BR_PRELIM
+/* Local bus app1 Options */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_LBAPP1_OR_PRELIM
+
+/* App2 Local bus */
+#define CONFIG_SYS_LBAPP2_BASE		0xE0000000
+#define CONFIG_SYS_LBAPP2_BASE_PHYS	0xFE0000000ull
+
+#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app2 Base Address */
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
+/* Local bus app2 Options */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
+#endif
+
+#endif	/* __CONFIG_H */
-- 
1.8.0.1

[U-Boot] [PATCH v2 09/11] fsl/mpc85xx: introduce fsl_print_rcw function

[York Sun]

On 08/28/2013 07:04 AM, Valentin Longchamp wrote:
> The RCW gets printed on a lot of FSL 85xx devices and it is always done
> the same way.
> 
> The fsl_print_rcw function performs this exact same task.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> ---
> Changes in v2: None
> 
>  arch/powerpc/cpu/mpc85xx/Makefile          |  1 +
>  arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c | 43 ++++++++++++++++++++++++++++++
>  arch/powerpc/include/asm/fsl_rcw.h         | 19 +++++++++++++
>  board/freescale/b4860qds/b4860qds.c        | 13 ++-------
>  board/freescale/corenet_ds/corenet_ds.c    | 24 +++++++----------
>  board/freescale/t4qds/t4qds.c              | 12 ++-------
>  6 files changed, 76 insertions(+), 36 deletions(-)
>  create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
>  create mode 100644 arch/powerpc/include/asm/fsl_rcw.h
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
> index 4669883..8c51619 100644
> --- a/arch/powerpc/cpu/mpc85xx/Makefile
> +++ b/arch/powerpc/cpu/mpc85xx/Makefile
> @@ -114,6 +114,7 @@ COBJS-$(CONFIG_QE)	+= qe_io.o
>  COBJS-$(CONFIG_CPM2)	+= serial_scc.o
>  COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
>  COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
> +COBJS-$(CONFIG_FSL_CORENET)	+= fsl_corenet_rcw.o
>  
>  # SoC specific SERDES support
>  COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
> new file mode 100644
> index 0000000..ca3a566
> --- /dev/null
> +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c
> @@ -0,0 +1,43 @@
> +/*
> + * (C) Copyright 2013 Keymile AG
> + * Valentin Longchamp <valentin.longchamp@keymile.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
>

Please retain original copyright when you move partial code to a new
file. Also please use the new license string.

Also apply to other part of this patch.

York

[U-Boot] [PATCH v2 06/11] mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

[York Sun]

On 08/28/2013 07:04 AM, Valentin Longchamp wrote:
> If the DDR3 module supports industrial temperature range and requires
> the x2 refresh rate for that temp range, the refresh period must be
> 3.9us instead of 7.8 us.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> 
> ---
> 

Can you add a line in commit message about on which board, what model
memory modules have been verified?

York

[U-Boot] [PATCH v2 11/11] mpc85xx: introduce the kmp204x reference design support

[York Sun]

On 08/28/2013 07:04 AM, Valentin Longchamp wrote:
> This patch introduces the support for Keymile's kmp204x reference
> design. This design is based on Freescale's P2040/P2041 SoC.
> 
> The peripherals used by this design are:
> - DDR3 RAM with SPD support
> - SPI NOR Flash as boot medium
> - NAND Flash
> - 2 PCIe busses (hosts 1 and 3)
> - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
> - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
>   FPGA
> - 2 HW I2C busses
> - last but not least, the mandatory serial port
> 
> The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
> support and was changed according to our design (that means essentially
> removing what is not present on the designs and a few adaptations).
> 
> There is currently only one prototype board that is based on this design
> and this patch also introduces it. The board is called kmlion1.
> 
> Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> ---
> Changes in v2:
> - Remove patch "5/8 fsl: do not define FSL_SRIO_PCIE_BOOT_MASTER for all
>   P2041 systems" from the series as it is not needed with current u-boot.
> - fix the defines used in kmp204x/law.c for the lbus local address
>   windows.
> - fix the header files to include Freescale's copyrights
> - integrate Scott's feedback
> 
>
Please use the new license header string.

York

[U-Boot] [PATCH v2 11/11] mpc85xx: introduce the kmp204x reference design support

[York Sun]

On 08/28/2013 07:04 AM, Valentin Longchamp wrote:
> This patch introduces the support for Keymile's kmp204x reference
> design. This design is based on Freescale's P2040/P2041 SoC.
> 
> The peripherals used by this design are:
> - DDR3 RAM with SPD support
> - SPI NOR Flash as boot medium
> - NAND Flash
> - 2 PCIe busses (hosts 1 and 3)
> - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
> - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
>   FPGA
> - 2 HW I2C busses
> - last but not least, the mandatory serial port
> 
> The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
> support and was changed according to our design (that means essentially
> removing what is not present on the designs and a few adaptations).
> 
> There is currently only one prototype board that is based on this design
> and this patch also introduces it. The board is called kmlion1.
> 
> Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> ---
> Changes in v2:
> - Remove patch "5/8 fsl: do not define FSL_SRIO_PCIE_BOOT_MASTER for all
>   P2041 systems" from the series as it is not needed with current u-boot.
> - fix the defines used in kmp204x/law.c for the lbus local address
>   windows.
> - fix the header files to include Freescale's copyrights
> - integrate Scott's feedback
> 
>  MAINTAINERS                           |   1 +
>  board/keymile/kmp204x/Makefile        |  48 ++++
>  board/keymile/kmp204x/ddr.c           |  80 ++++++
>  board/keymile/kmp204x/eth.c           |  87 +++++++
>  board/keymile/kmp204x/kmp204x.c       | 285 +++++++++++++++++++++
>  board/keymile/kmp204x/kmp204x.h       |  31 +++
>  board/keymile/kmp204x/law.c           |  56 +++++
>  board/keymile/kmp204x/pbi.cfg         |  51 ++++
>  board/keymile/kmp204x/pci.c           |  51 ++++
>  board/keymile/kmp204x/rcw_kmp204x.cfg |  11 +
>  board/keymile/kmp204x/tlb.c           | 126 ++++++++++
>  boards.cfg                            |   1 +
>  include/configs/km/kmp204x-common.h   | 462 ++++++++++++++++++++++++++++++++++
>  include/configs/kmp204x.h             |  84 +++++++
>  14 files changed, 1374 insertions(+)
>  create mode 100644 board/keymile/kmp204x/Makefile
>  create mode 100644 board/keymile/kmp204x/ddr.c
>  create mode 100644 board/keymile/kmp204x/eth.c
>  create mode 100644 board/keymile/kmp204x/kmp204x.c
>  create mode 100644 board/keymile/kmp204x/kmp204x.h
>  create mode 100644 board/keymile/kmp204x/law.c
>  create mode 100644 board/keymile/kmp204x/pbi.cfg
>  create mode 100644 board/keymile/kmp204x/pci.c
>  create mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg
>  create mode 100644 board/keymile/kmp204x/tlb.c
>  create mode 100644 include/configs/km/kmp204x-common.h
>  create mode 100644 include/configs/kmp204x.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 081cf96..fff77f0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -778,6 +778,7 @@ Valentin Longchamp <valentin.longchamp@keymile.com>
>  	mgcoge3un	ARM926EJS (Kirkwood SoC)
>  	kmcoge5un	ARM926EJS (Kirkwood SoC)
>  	portl2		ARM926EJS (Kirkwood SoC)
> +	kmcoge4		MPC85xx (P2041 SoC)
>  

Do you mean "kmlion1" instead of "kmcoge4" here? See below boards.cfg file.

<snip>

> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -744,6 +744,7 @@ tuge1                        powerpc     mpc83xx     km83xx              keymile
>  tuxx1                        powerpc     mpc83xx     km83xx              keymile        -           tuxx1:TUXX1
>  kmopti2                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KMOPTI2
>  kmsupx5                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KMSUPX5
> +kmlion1                      powerpc     mpc85xx     kmp204x             keymile        -           kmp204x:KMLION1
>  sbc8548                      powerpc     mpc85xx     sbc8548             -              -           sbc8548
>  sbc8548_PCI_33               powerpc     mpc85xx     sbc8548             -              -           sbc8548:PCI,33
>  sbc8548_PCI_33_PCIE          powerpc     mpc85xx     sbc8548             -              -           sbc8548:PCI,33,PCIE

No need to resend this patch. I need to fix it for the new boards.cfg
format anyway. Just need your confirmation.

York