* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
@ 2013-08-31 21:38 Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 01/22] i.MX6: MX6Q: update USBOH3 pad declarations to match MX6DL Eric Nelson
` (22 more replies)
0 siblings, 23 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
This patch series updates the pad declarations in the files
arch/arm/include/asm/arch-mx6/mx6q_pins.h and mx6dl_pins.h to
have consistent naming when a given pad is used for the same
purpose.
Most of the differences were simply changes in abbreviations between
the two files, and where possible, the form used in the Linux kernel
was used, even when the names are redundant (which is common - search
for ANATOP_ANATOP).
The primary exception to this is in patch number 5 for the pads
setting up the PL301_AXI uses for various pads. The kernel declarations
for those inexplicably have the processor architecture included in
the pad name.
You can get a picture of how the pads differ by running the following
commands in arch/arm/include/asm/arch-mx6:
for t in q dl ; do \
grep MX6_ mx6${t}-pins.h | \
awk '{print $1}' | \
sort > 6${t}.lst; \
done \
diff 6*.lst
Doing a quick 'wc -l' after this patch series shows that around
2/3 of the differences are accounted for, and the majority of
the remaining differences do reflect differences between the
i.MX6DQ and i.MX6DLS processor variants.
The primary reason this patch set is sent as an RFC is the overall
feeling that there must be a better way and the fact that none of
these pads is actually used by any current code in U-Boot and the
vast majority of these changes will never do so (OBSERVABILITY
pads, for instance).
In-Reply-To:
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 01/22] i.MX6: MX6Q: update USBOH3 pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 02/22] i.MX6: MX6Q: update SDMA " Eric Nelson
` (21 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
It appears that a number of USBOH3 pad declarations were
abbreviated in a number of different ways. This patch
simply changes them to match the MX6DL forms.
The new forms also match the structure used in Freescale's
Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 92 +++++++++++++++----------------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 94df007..317e0aa 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -931,7 +931,7 @@ enum {
MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
- MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
@@ -1044,7 +1044,7 @@ enum {
MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
- MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
@@ -1052,7 +1052,7 @@ enum {
MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
- MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
@@ -1363,38 +1363,38 @@ enum {
MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
@@ -1422,7 +1422,7 @@ enum {
MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
- MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
@@ -1433,103 +1433,103 @@ enum {
MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
- MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
@@ -1537,16 +1537,16 @@ enum {
MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
- MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
- MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
@@ -1554,8 +1554,8 @@ enum {
MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
- MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
- MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 02/22] i.MX6: MX6Q: update SDMA pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 01/22] i.MX6: MX6Q: update USBOH3 pad declarations to match MX6DL Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 03/22] i.MX6: MX6Q: update PCIE " Eric Nelson
` (20 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
It appears that a number of SDMA pad declarations were
abbreviated in a number of different ways. This patch
simply changes them to match the MX6DL forms.
The new forms also match the structure used in Freescale's
Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 60 +++++++++++++++----------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 317e0aa..260644f 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -446,7 +446,7 @@ enum {
MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
@@ -454,7 +454,7 @@ enum {
MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
@@ -462,7 +462,7 @@ enum {
MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
@@ -470,7 +470,7 @@ enum {
MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
@@ -493,21 +493,21 @@ enum {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
- MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
@@ -515,7 +515,7 @@ enum {
MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
@@ -531,14 +531,14 @@ enum {
MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
@@ -554,7 +554,7 @@ enum {
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
@@ -570,7 +570,7 @@ enum {
MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
@@ -578,7 +578,7 @@ enum {
MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
@@ -586,7 +586,7 @@ enum {
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
@@ -594,7 +594,7 @@ enum {
MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
@@ -602,49 +602,49 @@ enum {
MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
- MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
- MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
- MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
@@ -652,7 +652,7 @@ enum {
MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
- MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
+ MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
@@ -660,7 +660,7 @@ enum {
MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
- MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
+ MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
@@ -684,7 +684,7 @@ enum {
MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
- MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
@@ -692,7 +692,7 @@ enum {
MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
- MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
@@ -700,7 +700,7 @@ enum {
MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
- MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
@@ -708,21 +708,21 @@ enum {
MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
- MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
- MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
- MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 03/22] i.MX6: MX6Q: update PCIE pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 01/22] i.MX6: MX6Q: update USBOH3 pad declarations to match MX6DL Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 02/22] i.MX6: MX6Q: update SDMA " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 04/22] i.MX6: MX6Q: update MIPI_CORE " Eric Nelson
` (19 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
It appears that a number of PCIE pad declarations were
abbreviated in a number of different ways. This patch
simply changes them to match the MX6DL forms.
The new forms also match the structure used in Freescale's
Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 62 +++++++++++++++----------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 260644f..8bfd446 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1085,13 +1085,13 @@ enum {
MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
- MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
- MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
@@ -1099,14 +1099,14 @@ enum {
MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
@@ -1178,7 +1178,7 @@ enum {
MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
@@ -1187,7 +1187,7 @@ enum {
MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
@@ -1195,7 +1195,7 @@ enum {
MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
@@ -1204,7 +1204,7 @@ enum {
MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
@@ -1212,7 +1212,7 @@ enum {
MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
@@ -1221,7 +1221,7 @@ enum {
MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
@@ -1229,7 +1229,7 @@ enum {
MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
@@ -1238,7 +1238,7 @@ enum {
MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
@@ -1271,7 +1271,7 @@ enum {
MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
- MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
@@ -1279,7 +1279,7 @@ enum {
MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
- MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
@@ -1288,7 +1288,7 @@ enum {
MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
- MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
@@ -1296,7 +1296,7 @@ enum {
MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
- MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
@@ -1337,7 +1337,7 @@ enum {
MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
@@ -1345,7 +1345,7 @@ enum {
MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
- MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
@@ -1354,7 +1354,7 @@ enum {
MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
- MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
@@ -1362,7 +1362,7 @@ enum {
MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
@@ -1370,7 +1370,7 @@ enum {
MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
@@ -1378,7 +1378,7 @@ enum {
MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
@@ -1386,7 +1386,7 @@ enum {
MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
@@ -1400,7 +1400,7 @@ enum {
MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
@@ -1414,7 +1414,7 @@ enum {
MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
@@ -1428,7 +1428,7 @@ enum {
MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
- MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
@@ -1563,7 +1563,7 @@ enum {
MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
@@ -1571,7 +1571,7 @@ enum {
MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
@@ -1608,7 +1608,7 @@ enum {
MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
- MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
@@ -1616,13 +1616,13 @@ enum {
MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
- MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
- MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 04/22] i.MX6: MX6Q: update MIPI_CORE pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (2 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 03/22] i.MX6: MX6Q: update PCIE " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 05/22] i.MX6: MX6Q/MX6DL: update PL301 AXI interconnect pad declarations Eric Nelson
` (18 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
It appears that a number of MIPI_CORE pad declarations were
abbreviated in a number of different ways. This patch
simply changes them to match the MX6DL forms.
The new forms also match the structure used in Freescale's
Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 100 +++++++++++++++---------------
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 8bfd446..798629a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -39,26 +39,26 @@ enum {
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
@@ -66,7 +66,7 @@ enum {
MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
@@ -80,15 +80,15 @@ enum {
MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
@@ -270,7 +270,7 @@ enum {
MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
@@ -278,7 +278,7 @@ enum {
MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
@@ -286,7 +286,7 @@ enum {
MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
@@ -294,7 +294,7 @@ enum {
MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
@@ -302,39 +302,39 @@ enum {
MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
- MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
- MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
- MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
- MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
- MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
@@ -347,7 +347,7 @@ enum {
MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
- MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
@@ -355,21 +355,21 @@ enum {
MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
- MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
@@ -377,7 +377,7 @@ enum {
MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
@@ -385,7 +385,7 @@ enum {
MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
@@ -393,7 +393,7 @@ enum {
MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
@@ -401,7 +401,7 @@ enum {
MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
@@ -409,7 +409,7 @@ enum {
MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
@@ -417,35 +417,35 @@ enum {
MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
- MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
- MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
@@ -453,7 +453,7 @@ enum {
MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
- MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
@@ -461,7 +461,7 @@ enum {
MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
- MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
@@ -469,7 +469,7 @@ enum {
MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
@@ -477,7 +477,7 @@ enum {
MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
- MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
@@ -514,7 +514,7 @@ enum {
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
@@ -1275,7 +1275,7 @@ enum {
MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
@@ -1283,7 +1283,7 @@ enum {
MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
@@ -1292,7 +1292,7 @@ enum {
MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
@@ -1300,7 +1300,7 @@ enum {
MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
@@ -1308,7 +1308,7 @@ enum {
MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
@@ -1317,7 +1317,7 @@ enum {
MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
@@ -1325,7 +1325,7 @@ enum {
MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
@@ -1334,14 +1334,14 @@ enum {
MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
@@ -1349,7 +1349,7 @@ enum {
MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
@@ -1358,7 +1358,7 @@ enum {
MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
- MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
@@ -1366,7 +1366,7 @@ enum {
MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 05/22] i.MX6: MX6Q/MX6DL: update PL301 AXI interconnect pad declarations
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (3 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 04/22] i.MX6: MX6Q: update MIPI_CORE " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 06/22] i.MX6: MX6Q: update OBSERVE_MUX pad declarations to match MX6DL Eric Nelson
` (17 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The PAD declarations for PL301 pad settings were pretty haphazard
and this patch consolidates the pad names to make it easy to
compare the functions between i.MX6Q and i.MX6DLS.
The new forms of these declarations do not match Freescale's
Linux 3.x headers, where those inconsistencies are also present.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 90 +++++++++++++++---------------
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 66 +++++++++++-----------
2 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index c3d0b70..21ca67a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -190,7 +190,7 @@ enum {
MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__LCDIF_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__LCDIF_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0),
@@ -199,7 +199,7 @@ enum {
MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__LCDIF_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN3__LCDIF_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
@@ -208,7 +208,7 @@ enum {
MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0),
MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0),
@@ -217,7 +217,7 @@ enum {
MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
MX6_PAD_DI0_PIN4__LCDIF_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
@@ -226,7 +226,7 @@ enum {
MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
@@ -234,41 +234,41 @@ enum {
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0),
MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0),
MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0),
@@ -276,7 +276,7 @@ enum {
MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0),
@@ -284,7 +284,7 @@ enum {
MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0),
@@ -292,7 +292,7 @@ enum {
MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0),
@@ -316,7 +316,7 @@ enum {
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0),
@@ -324,7 +324,7 @@ enum {
MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0),
@@ -332,7 +332,7 @@ enum {
MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0),
@@ -340,7 +340,7 @@ enum {
MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0),
@@ -348,7 +348,7 @@ enum {
MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0),
@@ -356,7 +356,7 @@ enum {
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0),
@@ -364,7 +364,7 @@ enum {
MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0),
@@ -372,7 +372,7 @@ enum {
MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0),
@@ -380,7 +380,7 @@ enum {
MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0),
@@ -388,7 +388,7 @@ enum {
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0),
@@ -396,7 +396,7 @@ enum {
MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0),
@@ -404,7 +404,7 @@ enum {
MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0),
@@ -576,7 +576,7 @@ enum {
MX6_PAD_EIM_A23__IPU1_CSI1_D_18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0),
MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0),
- MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0),
MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0),
@@ -584,7 +584,7 @@ enum {
MX6_PAD_EIM_A24__IPU1_CSI1_D_19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0),
MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0),
- MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0),
MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0),
@@ -594,7 +594,7 @@ enum {
MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0),
MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0),
- MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A25__EPDC_SDDO_15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0),
MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0),
MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0),
@@ -632,7 +632,7 @@ enum {
MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0),
MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0),
- MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D17__EPDC_VCOM_0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
@@ -641,7 +641,7 @@ enum {
MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0),
- MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D18__EPDC_VCOM_1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0),
@@ -651,7 +651,7 @@ enum {
MX6_PAD_EIM_D19__UART1_RTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0),
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D19__EPDC_SDDO_12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0),
@@ -677,7 +677,7 @@ enum {
MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D22__EPDC_SDCE_6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0),
@@ -756,7 +756,7 @@ enum {
MX6_PAD_EIM_D30__UART3_RTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0),
MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0),
- MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__PL301_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0),
@@ -766,7 +766,7 @@ enum {
MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0),
MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D31__EPDC_SDCLK = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0),
MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0),
@@ -1169,7 +1169,7 @@ enum {
MX6_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0),
MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0),
MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0),
MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0),
@@ -1177,7 +1177,7 @@ enum {
MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0),
MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0),
@@ -1185,7 +1185,7 @@ enum {
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0),
- MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0),
@@ -1194,7 +1194,7 @@ enum {
MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0),
MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0),
MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0),
MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0),
@@ -1203,7 +1203,7 @@ enum {
MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0),
MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0),
MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0),
MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0),
@@ -1212,7 +1212,7 @@ enum {
MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0),
MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0),
MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0),
@@ -1220,7 +1220,7 @@ enum {
MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0),
- MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0),
MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0),
@@ -1228,7 +1228,7 @@ enum {
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0),
MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0),
@@ -1237,7 +1237,7 @@ enum {
MX6_PAD_KEY_ROW4__UART5_RTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0),
MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0),
MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
@@ -1273,7 +1273,7 @@ enum {
MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 798629a..78b33ba 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -135,7 +135,7 @@ enum {
MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301_PER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
@@ -159,7 +159,7 @@ enum {
MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301_PER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
@@ -234,7 +234,7 @@ enum {
MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
- MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__PL301_PER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
@@ -243,14 +243,14 @@ enum {
MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
- MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301_PER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
- MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301_PER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
@@ -258,7 +258,7 @@ enum {
MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
- MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301_PER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
@@ -541,7 +541,7 @@ enum {
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADDR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
@@ -549,7 +549,7 @@ enum {
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADDR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
@@ -557,7 +557,7 @@ enum {
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADDR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
@@ -565,7 +565,7 @@ enum {
MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADDR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
@@ -573,7 +573,7 @@ enum {
MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADDR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
@@ -581,7 +581,7 @@ enum {
MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADDR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
@@ -589,7 +589,7 @@ enum {
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADDR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
@@ -597,7 +597,7 @@ enum {
MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADDR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
@@ -605,35 +605,35 @@ enum {
MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADDR_22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADDR_23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADDR_24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
@@ -647,7 +647,7 @@ enum {
MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADDR_25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
@@ -655,7 +655,7 @@ enum {
MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADDR_26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
@@ -663,7 +663,7 @@ enum {
MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADDR_27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
@@ -687,7 +687,7 @@ enum {
MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADDR_28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
@@ -695,7 +695,7 @@ enum {
MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADDR_29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
@@ -703,7 +703,7 @@ enum {
MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADDR_30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
@@ -711,7 +711,7 @@ enum {
MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADDR_31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
@@ -907,7 +907,7 @@ enum {
MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADDR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
@@ -916,7 +916,7 @@ enum {
MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301_PER1_HADDR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
@@ -940,7 +940,7 @@ enum {
MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
- MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADDR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
@@ -948,7 +948,7 @@ enum {
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
- MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADDR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
@@ -956,7 +956,7 @@ enum {
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADDR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
@@ -973,7 +973,7 @@ enum {
MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADDR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
@@ -1402,7 +1402,7 @@ enum {
MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HREADYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 06/22] i.MX6: MX6Q: update OBSERVE_MUX pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (4 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 05/22] i.MX6: MX6Q/MX6DL: update PL301 AXI interconnect pad declarations Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 07/22] i.MX6: MX6Q: update MMDC_DEBUG " Eric Nelson
` (16 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The OBSERVE_MUX pad declarations were abbreviated differently
in mx6q_pins.h than in mx6dl_pins.h.
This patch adopts the slightly more verbose form from mx6dl_pins,
because they match the Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 78b33ba..819f46b 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -997,7 +997,7 @@ enum {
MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
- MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
@@ -1005,7 +1005,7 @@ enum {
MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
- MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
@@ -1013,7 +1013,7 @@ enum {
MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
- MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
@@ -1021,7 +1021,7 @@ enum {
MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
- MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
@@ -1029,7 +1029,7 @@ enum {
MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
- MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 07/22] i.MX6: MX6Q: update MMDC_DEBUG pad declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (5 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 06/22] i.MX6: MX6Q: update OBSERVE_MUX pad declarations to match MX6DL Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 08/22] i.MX6: MX6Q/MX6DL: update TRACE pad declarations Eric Nelson
` (15 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The MMDC_DEBUG pad declarations were abbreviated differently
in mx6q_pins.h than in mx6dl_pins.h.
This patch adopts the redundant form from mx6dl_pins, because
they match the Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 60 +++++++++++++++----------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 819f46b..0fbfc54 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -495,7 +495,7 @@ enum {
MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
- MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
@@ -509,7 +509,7 @@ enum {
MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
@@ -540,7 +540,7 @@ enum {
MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__PL301_PER1_HADDR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
@@ -548,7 +548,7 @@ enum {
MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__PL301_PER1_HADDR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
@@ -556,7 +556,7 @@ enum {
MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__PL301_PER1_HADDR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
@@ -572,7 +572,7 @@ enum {
MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__PL301_PER1_HADDR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
@@ -580,7 +580,7 @@ enum {
MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__PL301_PER1_HADDR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
@@ -588,7 +588,7 @@ enum {
MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__PL301_PER1_HADDR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
@@ -596,7 +596,7 @@ enum {
MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PL301_PER1_HADDR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
@@ -604,49 +604,49 @@ enum {
MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__PL301_PER1_HADDR_22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__PL301_PER1_HADDR_23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__PL301_PER1_HADDR_24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__PL301_PER1_HADDR_25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
@@ -654,7 +654,7 @@ enum {
MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__PL301_PER1_HADDR_26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
@@ -662,7 +662,7 @@ enum {
MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__PL301_PER1_HADDR_27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
@@ -670,7 +670,7 @@ enum {
MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
@@ -678,7 +678,7 @@ enum {
MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
@@ -686,7 +686,7 @@ enum {
MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__PL301_PER1_HADDR_28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
@@ -694,7 +694,7 @@ enum {
MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__PL301_PER1_HADDR_29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
@@ -702,7 +702,7 @@ enum {
MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__PL301_PER1_HADDR_30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
@@ -710,7 +710,7 @@ enum {
MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__PL301_PER1_HADDR_31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
@@ -964,7 +964,7 @@ enum {
MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
@@ -972,7 +972,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__PL301_PER1_HADDR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
@@ -1088,7 +1088,7 @@ enum {
MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
- MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
@@ -1102,14 +1102,14 @@ enum {
MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
- MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
- MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
@@ -1117,7 +1117,7 @@ enum {
MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 08/22] i.MX6: MX6Q/MX6DL: update TRACE pad declarations
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (6 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 07/22] i.MX6: MX6Q: update MMDC_DEBUG " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 09/22] i.MX6: MX6Q: update ANATOP " Eric Nelson
` (14 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The TRACE pad declarations were abbreviated differently in
mx6q_pins.h, which labelled them _CHEETAH_ than in
mx6dl_pins.h, which labelled them _SIMBA_.
This patch removes the extraneous tags from both to make
it easier to compare the two.
The Freescale Linux 3.x headers also contain these discrepancies.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 32 +++++++++++++++---------------
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 32 +++++++++++++++---------------
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 21ca67a..195c64d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -18,7 +18,7 @@ enum {
MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10_TRACE_7 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0),
@@ -27,7 +27,7 @@ enum {
MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11_TRACE_8 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0),
@@ -36,7 +36,7 @@ enum {
MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12_TRACE_9 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0),
@@ -45,7 +45,7 @@ enum {
MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13_TRACE_10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0),
@@ -54,7 +54,7 @@ enum {
MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14_TRACE_11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0),
@@ -63,7 +63,7 @@ enum {
MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15_TRACE_12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0),
@@ -72,7 +72,7 @@ enum {
MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16_TRACE_13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0),
@@ -81,7 +81,7 @@ enum {
MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17_TRACE_14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0),
@@ -90,7 +90,7 @@ enum {
MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18_TRACE_15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0),
@@ -107,7 +107,7 @@ enum {
MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4_TRACE_1 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0),
@@ -115,7 +115,7 @@ enum {
MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5_TRACE_2 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0),
@@ -123,7 +123,7 @@ enum {
MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6_TRACE_3 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0),
@@ -131,7 +131,7 @@ enum {
MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7_TRACE_4 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0),
@@ -139,7 +139,7 @@ enum {
MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0),
MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8_TRACE_5 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0),
@@ -147,7 +147,7 @@ enum {
MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0),
MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9_TRACE_6 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0),
@@ -174,7 +174,7 @@ enum {
MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC_TRACE_0 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_DISP_CLK__LCDIF_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 0fbfc54..7a20d65 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1110,7 +1110,7 @@ enum {
MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
@@ -1118,7 +1118,7 @@ enum {
MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
@@ -1126,7 +1126,7 @@ enum {
MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
@@ -1134,7 +1134,7 @@ enum {
MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
@@ -1142,7 +1142,7 @@ enum {
MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
@@ -1150,7 +1150,7 @@ enum {
MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
@@ -1158,7 +1158,7 @@ enum {
MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
@@ -1167,7 +1167,7 @@ enum {
MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
@@ -1175,7 +1175,7 @@ enum {
MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
@@ -1184,7 +1184,7 @@ enum {
MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
@@ -1192,7 +1192,7 @@ enum {
MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
@@ -1201,7 +1201,7 @@ enum {
MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
@@ -1209,7 +1209,7 @@ enum {
MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
@@ -1218,7 +1218,7 @@ enum {
MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
@@ -1226,7 +1226,7 @@ enum {
MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
@@ -1235,7 +1235,7 @@ enum {
MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 09/22] i.MX6: MX6Q: update ANATOP pad declarations
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (7 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 08/22] i.MX6: MX6Q/MX6DL: update TRACE pad declarations Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 10/22] i.MX6: MX6Q: update DI0 MIPI " Eric Nelson
` (13 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The ANATOP pad declarations were abbreviated differently in
mx6q_pins.h, which removed redundant _ANATOP_ labels than in
mx6dl_pins.h.
This patch updates mx6q_pins.h to match mx6dl_pins.h, which
also matches the Freescale Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 48 +++++++++++++++----------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 7a20d65..2d7199a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -19,7 +19,7 @@ enum {
MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
- MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
@@ -27,7 +27,7 @@ enum {
MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
- MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
@@ -40,7 +40,7 @@ enum {
MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
- MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
@@ -71,7 +71,7 @@ enum {
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
- MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
@@ -394,7 +394,7 @@ enum {
MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
@@ -402,7 +402,7 @@ enum {
MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
@@ -410,7 +410,7 @@ enum {
MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
- MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
@@ -999,7 +999,7 @@ enum {
MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
- MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
@@ -1243,7 +1243,7 @@ enum {
MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
@@ -1284,7 +1284,7 @@ enum {
MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
@@ -1293,7 +1293,7 @@ enum {
MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
@@ -1301,7 +1301,7 @@ enum {
MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
@@ -1309,7 +1309,7 @@ enum {
MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
@@ -1318,7 +1318,7 @@ enum {
MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
@@ -1326,7 +1326,7 @@ enum {
MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
@@ -1335,14 +1335,14 @@ enum {
MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
@@ -1350,7 +1350,7 @@ enum {
MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
- MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
@@ -1566,7 +1566,7 @@ enum {
MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
@@ -1574,7 +1574,7 @@ enum {
MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
@@ -1582,13 +1582,13 @@ enum {
MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
- MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
@@ -1596,7 +1596,7 @@ enum {
MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
- MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
@@ -1625,7 +1625,7 @@ enum {
MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
- MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 10/22] i.MX6: MX6Q: update DI0 MIPI pad declarations
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (8 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 09/22] i.MX6: MX6Q: update ANATOP " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 11/22] Additional SIMBA/CHEETAH removal Eric Nelson
` (12 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The MIPI CORE DPHY pad declarations in mx6q_pins.h were
abbreviated differently than in mx6dl_pins.h.
This patch updates them to match the DL versions and the
Freescale Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 2d7199a..64c28ce 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -492,21 +492,21 @@ enum {
MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
- MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
- MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 11/22] Additional SIMBA/CHEETAH removal
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (9 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 10/22] i.MX6: MX6Q: update DI0 MIPI " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 12/22] i.MX6: MX6Q: update USDHC1 pad declarations Eric Nelson
` (11 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 8 ++++----
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 195c64d..339043c 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -154,20 +154,20 @@ enum {
MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__TRCLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_MCLK__SIMBA_TRCTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__TRCTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
@@ -1110,7 +1110,7 @@ enum {
MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
- MX6_PAD_GPIO_5__SIMBA_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0),
MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 64c28ce..0faaeee 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1035,7 +1035,7 @@ enum {
MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
- MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
@@ -1089,21 +1089,21 @@ enum {
MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
- MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 12/22] i.MX6: MX6Q: update USDHC1 pad declarations
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (10 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 11/22] Additional SIMBA/CHEETAH removal Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 13/22] i.MX6: MX6Q: Change CSI0_DATA_EN abbreviation to match MX6DL Eric Nelson
` (10 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
The DISP0_x__USDHC1 pad declarations were abbreviated
differently from MX6DL.
This patch updates them to match the DL versions and the
Freescale Linux 3.x headers.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 0faaeee..57ba749 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -530,14 +530,14 @@ enum {
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
@@ -545,7 +545,7 @@ enum {
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
@@ -553,7 +553,7 @@ enum {
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
@@ -561,7 +561,7 @@ enum {
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
@@ -585,7 +585,7 @@ enum {
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
@@ -608,14 +608,14 @@ enum {
MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 13/22] i.MX6: MX6Q: Change CSI0_DATA_EN abbreviation to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (11 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 12/22] i.MX6: MX6Q: update USDHC1 pad declarations Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 14/22] i.MX6: MX6Q: update SPDIF_EXTCLK " Eric Nelson
` (9 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 57ba749..1b74405 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1097,7 +1097,7 @@ enum {
MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
MX6_PAD_CSI0_MCLK__TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
- MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 14/22] i.MX6: MX6Q: update SPDIF_EXTCLK to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (12 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 13/22] i.MX6: MX6Q: Change CSI0_DATA_EN abbreviation to match MX6DL Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 15/22] i.MX6: MX6Q: update 1588 EVENT declarations " Eric Nelson
` (8 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 1b74405..8ba9316 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -736,7 +736,7 @@ enum {
MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
- MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
+ MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 15/22] i.MX6: MX6Q: update 1588 EVENT declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (13 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 14/22] i.MX6: MX6Q: update SPDIF_EXTCLK " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 16/22] i.MX6: MX6Q: update SNVS " Eric Nelson
` (7 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 8ba9316..94eb2c3 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -716,7 +716,7 @@ enum {
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
- MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
@@ -729,7 +729,7 @@ enum {
MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
- MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
@@ -743,7 +743,7 @@ enum {
MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
- MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 16/22] i.MX6: MX6Q: update SNVS declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (14 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 15/22] i.MX6: MX6Q: update 1588 EVENT declarations " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 17/22] i.MX6: MX6Q: update GPU_DEBUG " Eric Nelson
` (6 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 94eb2c3..f67a893 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -980,7 +980,7 @@ enum {
MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
- MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
@@ -1074,7 +1074,7 @@ enum {
MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
- MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
@@ -1261,7 +1261,7 @@ enum {
MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 17/22] i.MX6: MX6Q: update GPU_DEBUG declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (15 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 16/22] i.MX6: MX6Q: update SNVS " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 18/22] i.MX6: MX6Q: update ETHERNET/OCOTP " Eric Nelson
` (5 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index f67a893..28e841a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1432,7 +1432,7 @@ enum {
MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
@@ -1440,7 +1440,7 @@ enum {
MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
@@ -1448,7 +1448,7 @@ enum {
MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
@@ -1456,7 +1456,7 @@ enum {
MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
@@ -1464,7 +1464,7 @@ enum {
MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
@@ -1472,7 +1472,7 @@ enum {
MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
@@ -1480,7 +1480,7 @@ enum {
MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
@@ -1488,7 +1488,7 @@ enum {
MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
- MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 18/22] i.MX6: MX6Q: update ETHERNET/OCOTP declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (16 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 17/22] i.MX6: MX6Q: update GPU_DEBUG " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 19/22] i.MX6: MX6Q: update MIPI_CORE_DPHY " Eric Nelson
` (4 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 28e841a..84d3bd9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1027,7 +1027,7 @@ enum {
MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
- MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
@@ -1055,7 +1055,7 @@ enum {
MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
- MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
+ MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 19/22] i.MX6: MX6Q: update MIPI_CORE_DPHY declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (17 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 18/22] i.MX6: MX6Q: update ETHERNET/OCOTP " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 20/22] i.MX6: MX6Q: update MIPI_HSI_CTRL " Eric Nelson
` (3 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 84d3bd9..efc7651 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -62,7 +62,7 @@ enum {
MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
@@ -70,12 +70,12 @@ enum {
MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
@@ -1374,7 +1374,7 @@ enum {
MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
@@ -1382,7 +1382,7 @@ enum {
MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
@@ -1390,7 +1390,7 @@ enum {
MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 20/22] i.MX6: MX6Q: update MIPI_HSI_CTRL declarations to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (18 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 19/22] i.MX6: MX6Q: update MIPI_CORE_DPHY " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 21/22] i.MX6: MX6Q: update CAAM_WRAPPER declaration " Eric Nelson
` (2 subsequent siblings)
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index efc7651..2e26452 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -41,21 +41,21 @@ enum {
MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
- MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
@@ -63,7 +63,7 @@ enum {
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
@@ -72,16 +72,16 @@ enum {
MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
- MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
- MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 21/22] i.MX6: MX6Q: update CAAM_WRAPPER declaration to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (19 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 20/22] i.MX6: MX6Q: update MIPI_HSI_CTRL " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 22/22] i.MX6: MX6Q: update CCM_PMIC " Eric Nelson
2013-08-31 21:55 ` [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Otavio Salvador
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 2e26452..cd0625d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1569,7 +1569,7 @@ enum {
MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
- MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 22/22] i.MX6: MX6Q: update CCM_PMIC declaration to match MX6DL
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (20 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 21/22] i.MX6: MX6Q: update CAAM_WRAPPER declaration " Eric Nelson
@ 2013-08-31 21:38 ` Eric Nelson
2013-08-31 21:55 ` [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Otavio Salvador
22 siblings, 0 replies; 30+ messages in thread
From: Eric Nelson @ 2013-08-31 21:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index cd0625d..c9f6770 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -1262,7 +1262,7 @@ enum {
MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
--
1.8.1.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
` (21 preceding siblings ...)
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 22/22] i.MX6: MX6Q: update CCM_PMIC " Eric Nelson
@ 2013-08-31 21:55 ` Otavio Salvador
2013-09-01 17:08 ` Stefano Babic
22 siblings, 1 reply; 30+ messages in thread
From: Otavio Salvador @ 2013-08-31 21:55 UTC (permalink / raw)
To: u-boot
On Sat, Aug 31, 2013 at 6:38 PM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> The primary reason this patch set is sent as an RFC is the overall
> feeling that there must be a better way and the fact that none of
> these pads is actually used by any current code in U-Boot and the
> vast majority of these changes will never do so (OBSERVABILITY
> pads, for instance).
I think it is better to have all the pads there so we don't need to
always recheck if the pad is known or not and make changes on this all
the time.
This will also help in the work of TechNexion guys with the SPL; so I
am all in favor of these changes.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-08-31 21:55 ` [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Otavio Salvador
@ 2013-09-01 17:08 ` Stefano Babic
2013-09-01 18:21 ` Eric Nelson
2013-09-01 18:50 ` Otavio Salvador
0 siblings, 2 replies; 30+ messages in thread
From: Stefano Babic @ 2013-09-01 17:08 UTC (permalink / raw)
To: u-boot
Hi Otavio,
On 31/08/2013 23:55, Otavio Salvador wrote:
> On Sat, Aug 31, 2013 at 6:38 PM, Eric Nelson
> <eric.nelson@boundarydevices.com> wrote:
>> The primary reason this patch set is sent as an RFC is the overall
>> feeling that there must be a better way and the fact that none of
>> these pads is actually used by any current code in U-Boot and the
>> vast majority of these changes will never do so (OBSERVABILITY
>> pads, for instance).
>
> I think it is better to have all the pads there so we don't need to
> always recheck if the pad is known or not and make changes on this all
> the time.
>
I am not sure I have understood your sentence: what do you mean with
"there" ? Are you suggesting another place for the pads ?
> This will also help in the work of TechNexion guys with the SPL; so I
> am all in favor of these changes.
Agree. A full cleanup is necessary before trying to push the changes we
have already discussed.
I tend also to prepare a new branch on u-boot-imx, where I will play the
current status for the imx6 - these changes will not flow into 2013.10,
and maybe having a branch to test will help.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-09-01 17:08 ` Stefano Babic
@ 2013-09-01 18:21 ` Eric Nelson
2013-09-13 17:01 ` Eric Nelson
2013-09-01 18:50 ` Otavio Salvador
1 sibling, 1 reply; 30+ messages in thread
From: Eric Nelson @ 2013-09-01 18:21 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On 09/01/2013 10:08 AM, Stefano Babic wrote:
> Hi Otavio,
>
> On 31/08/2013 23:55, Otavio Salvador wrote:
>> On Sat, Aug 31, 2013 at 6:38 PM, Eric Nelson
>> <eric.nelson@boundarydevices.com> wrote:
>>> The primary reason this patch set is sent as an RFC is the overall
>>> feeling that there must be a better way and the fact that none of
>>> these pads is actually used by any current code in U-Boot and the
>>> vast majority of these changes will never do so (OBSERVABILITY
>>> pads, for instance).
>>
>> I think it is better to have all the pads there so we don't need to
>> always recheck if the pad is known or not and make changes on this all
>> the time.
>>
>
> I am not sure I have understood your sentence: what do you mean with
> "there" ? Are you suggesting another place for the pads ?
>
Note that not all of the defined pad options are currently present
in these headers, including some that are being used by some down-stream
boards:
https://github.com/boundarydevices/u-boot-imx6/commit/b9a39fd1756ab95554f4c49b9cf1cde73a9dbda9
I'm taking a look at the XML files distributed as a part of the
IOMux tool to see if they can be used to produce a more complete set.
>> This will also help in the work of TechNexion guys with the SPL; so I
>> am all in favor of these changes.
>
> Agree. A full cleanup is necessary before trying to push the changes we
> have already discussed.
>
> I tend also to prepare a new branch on u-boot-imx, where I will play the
> current status for the imx6 - these changes will not flow into 2013.10,
> and maybe having a branch to test will help.
>
I think a single patch or patch set to clean things up will save effort
in the long term instead of handling things on a pin-by-pin basis as
new boards are designed.
Regards,
Eric
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-09-01 17:08 ` Stefano Babic
2013-09-01 18:21 ` Eric Nelson
@ 2013-09-01 18:50 ` Otavio Salvador
1 sibling, 0 replies; 30+ messages in thread
From: Otavio Salvador @ 2013-09-01 18:50 UTC (permalink / raw)
To: u-boot
On Sun, Sep 1, 2013 at 2:08 PM, Stefano Babic <sbabic@denx.de> wrote:
> Hi Otavio,
>
> On 31/08/2013 23:55, Otavio Salvador wrote:
>> On Sat, Aug 31, 2013 at 6:38 PM, Eric Nelson
>> <eric.nelson@boundarydevices.com> wrote:
>>> The primary reason this patch set is sent as an RFC is the overall
>>> feeling that there must be a better way and the fact that none of
>>> these pads is actually used by any current code in U-Boot and the
>>> vast majority of these changes will never do so (OBSERVABILITY
>>> pads, for instance).
>>
>> I think it is better to have all the pads there so we don't need to
>> always recheck if the pad is known or not and make changes on this all
>> the time.
>>
>
> I am not sure I have understood your sentence: what do you mean with
> "there" ? Are you suggesting another place for the pads ?
I wasn't clear, sorry.
I am suggesting we put all pins in U-Boot headers so it does not need
to be added on demand. The on demand addition has higher risk of wrong
assignment, duplication and forces every time we're going to work with
the pins the hassle of checking if the needed ones are already defined
or not.
>> This will also help in the work of TechNexion guys with the SPL; so I
>> am all in favor of these changes.
>
> Agree. A full cleanup is necessary before trying to push the changes we
> have already discussed.
>
> I tend also to prepare a new branch on u-boot-imx, where I will play the
> current status for the imx6 - these changes will not flow into 2013.10,
> and maybe having a branch to test will help.
I understand if the SPL rework cannot go to 2013.10 but pin rename and
rework seem safe enough to go. This provides a safer base for SPL work
and multi-soc support later.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-09-01 18:21 ` Eric Nelson
@ 2013-09-13 17:01 ` Eric Nelson
2013-09-13 17:07 ` Otavio Salvador
2013-09-13 17:15 ` Stefano Babic
0 siblings, 2 replies; 30+ messages in thread
From: Eric Nelson @ 2013-09-13 17:01 UTC (permalink / raw)
To: u-boot
On 09/01/2013 11:21 AM, Eric Nelson wrote:
> Hi Stefano,
>
> On 09/01/2013 10:08 AM, Stefano Babic wrote:
>> Hi Otavio,
>>
>> On 31/08/2013 23:55, Otavio Salvador wrote:
>>> On Sat, Aug 31, 2013 at 6:38 PM, Eric Nelson
>>> <eric.nelson@boundarydevices.com> wrote:
>>>> The primary reason this patch set is sent as an RFC is the overall
>>>> feeling that there must be a better way and the fact that none of
>>>> these pads is actually used by any current code in U-Boot and the
>>>> vast majority of these changes will never do so (OBSERVABILITY
>>>> pads, for instance).
>>>
>>> I think it is better to have all the pads there so we don't need to
>>> always recheck if the pad is known or not and make changes on this all
>>> the time.
>>>
>>
>> I am not sure I have understood your sentence: what do you mean with
>> "there" ? Are you suggesting another place for the pads ?
>>
>
> Note that not all of the defined pad options are currently present
> in these headers, including some that are being used by some down-stream
> boards:
> https://github.com/boundarydevices/u-boot-imx6/commit/b9a39fd1756ab95554f4c49b9cf1cde73a9dbda9
>
> I'm taking a look at the XML files distributed as a part of the
> IOMux tool to see if they can be used to produce a more complete set.
>
I finally took some time to walk through the XML files that are a
part of the IOMux tool (scraped through "strings").
They seem to be more complete than any of the other canonical
sources, but only slightly so.
AFAIK, there are six main repositories of this pin-mux declarations.
-- Freescale's 2009.08 U-Boot has files mx6_pins.h for Dual/Quad,
and mx6dl_pins.h for Solo/Dual-Lite:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/include/asm-arm/arch-mx6?h=imx_v2009.08_3.0.35_4.1.0
-- Main-line U-Boot has files mx6q_pins.h for Quad/Dual and mx6dl_pins.h
for Dual-Lite/Solo:
http://git.denx.de/u-boot.git/?p=u-boot.git;a=tree;f=arch/arm/include/asm/arch-mx6;h=bec3aaf4de0813965b19bb6cf8a43b1c78f5e7f1;hb=HEAD
-- The main-line Linux kernel has files imx6q-pinfunc.h for Quad/Dual
and imx6dl-pinfunc.h for Dual-Lite/Solo:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts?id=refs/tags/v3.11
-- Freescale's 3.5.7 tree appears to share the headers with main-line.
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts?h=imx_3.5.7_1.0.0_alpha
-- Freescale's 3.0.35 tree has files iomux-mx6q.h for Quad/Dual and
iomux-mx6dl.h for Dual-Lite/Solo:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/plat-mxc/include/mach
Freescale's IOMux tool has two embedded XML files that describe all
of the pads, mux and pad registers :
https://www.freescale.com/webapp/sps/download/license.jsp?colCode=IMX6_IOMUX_TOOL&appType=file1
The two U-Boot trees and the 3.0.35 Linux kernel appear to have
the same origins, and each seem to have extra declarations for
things that are unlikely to be used or are completely useless
like this declaration:
MX6_PAD_DRAM_D40__MMDC_DRAM_D_40
= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
If a pad has no mux or pad register, I don't think we need a
declaration.
The main-line Linux kernel appears to have been generated from
the IOMux tool (or a similar ancestor), though there are a number
of subtle differences, especially in the use of the "_B" suffix
on some declarations.
Comparing the two (IOMux and main-line) showed that some
pin muxing options aren't represented in main-line yet
and there are some declarations in main-line that I'm not
sure how to produce from the XML (those involving input-select
registers).
Shawn appears to have implemented things in a clean way
for the main-line kernel:
https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/arch/arm/boot/dts/imx6q-pinfunc.h?id=c56009b2f6134e5943a03cf26e4d7fce9745d56b
I recommend that we simply adopt the main-line kernel naming,
and work up a couple of initial patches:
1. simply replace all of the names with their main-line
equivalent, and
2. remove all of the unused (NO_PAD_I,NO_MUX_I) pad
declarations
Each of these should be easy to inspect for correctness
and then we can focus on how to handle the differences
and produce binaries that support both variants.
Let me know your thoughts.
Regards,
Eric
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-09-13 17:01 ` Eric Nelson
@ 2013-09-13 17:07 ` Otavio Salvador
2013-09-13 17:15 ` Stefano Babic
1 sibling, 0 replies; 30+ messages in thread
From: Otavio Salvador @ 2013-09-13 17:07 UTC (permalink / raw)
To: u-boot
On Fri, Sep 13, 2013 at 2:01 PM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> On 09/01/2013 11:21 AM, Eric Nelson wrote:
...
> Shawn appears to have implemented things in a clean way
> for the main-line kernel:
>
> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/arch/arm/boot/dts/imx6q-pinfunc.h?id=c56009b2f6134e5943a03cf26e4d7fce9745d56b
>
> I recommend that we simply adopt the main-line kernel naming,
> and work up a couple of initial patches:
>
> 1. simply replace all of the names with their main-line
> equivalent, and
> 2. remove all of the unused (NO_PAD_I,NO_MUX_I) pad
> declarations
>
> Each of these should be easy to inspect for correctness
> and then we can focus on how to handle the differences
> and produce binaries that support both variants.
>
> Let me know your thoughts.
...
I fully support this idea; this easy:
* comparing code against Linux kernel;
* backporting code from Linux kernel;
* correctness (as we don't need to change it every time we add something "new");
* avoid continuous inspection of this during U-Boot work (often we
need to double check the pins are known and which name has been used);
Regards,
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries
2013-09-13 17:01 ` Eric Nelson
2013-09-13 17:07 ` Otavio Salvador
@ 2013-09-13 17:15 ` Stefano Babic
1 sibling, 0 replies; 30+ messages in thread
From: Stefano Babic @ 2013-09-13 17:15 UTC (permalink / raw)
To: u-boot
Hi Eric,
Thanks for your analyses
On 13/09/2013 19:01, Eric Nelson wrote:
> I recommend that we simply adopt the main-line kernel naming,
> and work up a couple of initial patches:
I fully agree - this makes also code more maintainable if we will be in
sync with kernel.
>
> 1. simply replace all of the names with their main-line
> equivalent, and
> 2. remove all of the unused (NO_PAD_I,NO_MUX_I) pad
> declarations
>
Agree.
> Each of these should be easy to inspect for correctness
> and then we can focus on how to handle the differences
> and produce binaries that support both variants.
I think you proposed the right way to go on ;-)
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2013-09-13 17:15 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-08-31 21:38 [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 01/22] i.MX6: MX6Q: update USBOH3 pad declarations to match MX6DL Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 02/22] i.MX6: MX6Q: update SDMA " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 03/22] i.MX6: MX6Q: update PCIE " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 04/22] i.MX6: MX6Q: update MIPI_CORE " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 05/22] i.MX6: MX6Q/MX6DL: update PL301 AXI interconnect pad declarations Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 06/22] i.MX6: MX6Q: update OBSERVE_MUX pad declarations to match MX6DL Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 07/22] i.MX6: MX6Q: update MMDC_DEBUG " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 08/22] i.MX6: MX6Q/MX6DL: update TRACE pad declarations Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 09/22] i.MX6: MX6Q: update ANATOP " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 10/22] i.MX6: MX6Q: update DI0 MIPI " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 11/22] Additional SIMBA/CHEETAH removal Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 12/22] i.MX6: MX6Q: update USDHC1 pad declarations Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 13/22] i.MX6: MX6Q: Change CSI0_DATA_EN abbreviation to match MX6DL Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 14/22] i.MX6: MX6Q: update SPDIF_EXTCLK " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 15/22] i.MX6: MX6Q: update 1588 EVENT declarations " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 16/22] i.MX6: MX6Q: update SNVS " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 17/22] i.MX6: MX6Q: update GPU_DEBUG " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 18/22] i.MX6: MX6Q: update ETHERNET/OCOTP " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 19/22] i.MX6: MX6Q: update MIPI_CORE_DPHY " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 20/22] i.MX6: MX6Q: update MIPI_HSI_CTRL " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 21/22] i.MX6: MX6Q: update CAAM_WRAPPER declaration " Eric Nelson
2013-08-31 21:38 ` [U-Boot] [PATCH RFC 22/22] i.MX6: MX6Q: update CCM_PMIC " Eric Nelson
2013-08-31 21:55 ` [U-Boot] [PATCH RFC 0/22] i.MX6: Update pad declarations for multiple-arch binaries Otavio Salvador
2013-09-01 17:08 ` Stefano Babic
2013-09-01 18:21 ` Eric Nelson
2013-09-13 17:01 ` Eric Nelson
2013-09-13 17:07 ` Otavio Salvador
2013-09-13 17:15 ` Stefano Babic
2013-09-01 18:50 ` Otavio Salvador
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