[Qemu-devel] [PATCH 00/13] Stage 2 VSX Support

[Qemu-devel] [PATCH 00/13] Stage 2 VSX Support

[Tom Musta]

This patch series continues adding support for the PowerPC Vector Scalar 
Extension
(VSX).  Patches are relative to the Stage 1 delivery (see
http://lists.nongnu.org/archive/html/qemu-ppc/2013-09/msg00231.html).

This series adds the following:

   a) all remaining load and store instructions defined by the V2.06 
Power ISA
      (aka Power7).
   b) The vector and scalar move instructions.
   c) The logical instructions defined by V2.06.
   d) Assorted permute and select instructions.

Tom Musta (13):
   Abandon GEN_VSX_* macros
   Add lxsdx
   Add lxvdsx
   Add lxvw4x
   Add stxsdx
   Add stxvw4x
   Add VSX Scalar Move Instructions
   Add VSX Vector Move Instructions
   Add Power7 VSX Logical Instructions
   Add xxmrgh/xxmrgl
   Add xxsel
   Add xxspltw
   Add xxsldwi

  target-ppc/translate.c |  516 
+++++++++++++++++++++++++++++++++++++++++++++++-
  1 files changed, 508 insertions(+), 8 deletions(-)

[Qemu-devel] [PATCH 01/13] Abandon GEN_VSX_* macros

[Tom Musta]

Abandon GEN_VSX_* macros

This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
did not provide significant value above the general GEN_HANDLER_E
macro.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   12 ++----------
  1 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ab3fed6..1348360 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9507,17 +9507,9 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
  GEN_VAFORM_PAIRED(vsel, vperm, 21),
  GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),

-#undef  GEN_VSX_LXVNX
-#define GEN_VSX_LXVNX(name, opc2, 
opc3)                                        \
-  GEN_HANDLER_E(lxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE, 
PPC2_VSX)
+GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),

-GEN_VSX_LXVNX(d2x, 0x0C, 0x1A),
-
-#undef  GEN_VSX_STXVNX
-#define GEN_VSX_STXVNX(name, opc2, 
opc3)                                       \
-  GEN_HANDLER_E(stxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE, 
PPC2_VSX)
-
-GEN_VSX_STXVNX(d2x, 0x0C, 0x1E),
+GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),

  #undef GEN_XX3FORM_DM
  #define GEN_XX3FORM_DM(name, opc2, opc3) \
-- 
1.7.1

[Qemu-devel] [PATCH 02/13] Add lxsdx

[Tom Musta]

This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.

The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   16 ++++++++++++++++
  1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1348360..4f2d647 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
      }
  }

+static void gen_lxsdx(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+    /* NOTE: cpu_vsrl is undefined */
+    tcg_temp_free(EA);
+}
+
  static void gen_lxvd2x(DisasContext *ctx)
  {
      TCGv EA;
@@ -9507,6 +9522,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
  GEN_VAFORM_PAIRED(vsel, vperm, 21),
  GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),

+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),

  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [PATCH 03/13] Add lxvdsx

[Tom Musta]

This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   16 ++++++++++++++++
  1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4f2d647..f25e699 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7038,6 +7038,21 @@ static void gen_lxvd2x(DisasContext *ctx)
      tcg_temp_free(EA);
  }

+static void gen_lxvdsx(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+    tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+    tcg_temp_free(EA);
+}
+
  static void gen_stxvd2x(DisasContext *ctx)
  {
      TCGv EA;
@@ -9524,6 +9539,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),

  GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),

  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),

-- 
1.7.1

[Qemu-devel] [PATCH 04/13] Add lxvw4x

[Tom Musta]

This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   31 +++++++++++++++++++++++++++++++
  1 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f25e699..465c991 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7053,6 +7053,36 @@ static void gen_lxvdsx(DisasContext *ctx)
      tcg_temp_free(EA);
  }

+static void gen_lxvw4x(DisasContext *ctx)
+{
+    TCGv EA, tmp;
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    tmp = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld32u(ctx, xth, EA);
+    tcg_gen_shli_tl(xth, xth, 32);
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_ld32u(ctx, tmp, EA);
+    tcg_gen_or_tl(xth, xth, tmp);
+
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_ld32u(ctx, xtl, EA);
+    tcg_gen_shli_tl(xtl, xtl, 32);
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_ld32u(ctx, tmp, EA);
+    tcg_gen_or_tl(xtl, xtl, tmp);
+
+    tcg_temp_free(EA);
+    tcg_temp_free(tmp);
+}
+
  static void gen_stxvd2x(DisasContext *ctx)
  {
      TCGv EA;
@@ -9540,6 +9570,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
  GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),

  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),

-- 
1.7.1

Re: [Qemu-devel] [PATCH 04/13] Add lxvw4x

[Richard Henderson]

On 10/04/2013 06:16 AM, Tom Musta wrote:
> +    tcg_gen_shli_tl(xth, xth, 32);
> +    tcg_gen_addi_tl(EA, EA, 4);
> +    gen_qemu_ld32u(ctx, tmp, EA);
> +    tcg_gen_or_tl(xth, xth, tmp);

Better with deposit_i64.


r~

[Qemu-devel] [PATCH 05/13] Add stxsdx

[Tom Musta]

This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   15 +++++++++++++++
  1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 465c991..a4e3a0a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7083,6 +7083,20 @@ static void gen_lxvw4x(DisasContext *ctx)
      tcg_temp_free(tmp);
  }

+static void gen_stxsdx(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+    tcg_temp_free(EA);
+}
+
  static void gen_stxvd2x(DisasContext *ctx)
  {
      TCGv EA;
@@ -9572,6 +9586,7 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, 
PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),

+GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),

  #undef GEN_XX3FORM_DM
-- 
1.7.1

[Qemu-devel] [PATCH 06/13] Add stxvw4x

[Tom Musta]

This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   28 ++++++++++++++++++++++++++++
  1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a4e3a0a..7d71fb9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7113,6 +7113,33 @@ static void gen_stxvd2x(DisasContext *ctx)
      tcg_temp_free(EA);
  }

+static void gen_stxvw4x(DisasContext *ctx)
+{
+    TCGv EA, tmp;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    tmp = tcg_temp_new();
+
+    tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
+    gen_qemu_st32(ctx, tmp, EA);
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+
+    tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_st32(ctx, tmp, EA);
+    tcg_gen_addi_tl(EA, EA, 4);
+    gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+
+    tcg_temp_free(EA);
+    tcg_temp_free(tmp);
+}
+
  static void gen_xxpermdi(DisasContext *ctx)
  {
      if (unlikely(!ctx->vsx_enabled)) {
@@ -9588,6 +9615,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, 
PPC_NONE, PPC2_VSX),

  GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),

  #undef GEN_XX3FORM_DM
  #define GEN_XX3FORM_DM(name, opc2, opc3) \
-- 
1.7.1

[Qemu-devel] [PATCH 07/13] Add VSX Scalar Move Instructions

[Tom Musta]

This patch adds the VSX scalar move instructions:

   - xsabsdp (Scalar Absolute Value Double-Precision)
   - xsnabspd (Scalar Negative Absolute Value Double-Precision)
   - xsnegdp (Scalar Negate Double-Precision)
   - xscpsgndp (Scalar Copy Sign Double-Precision)

A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.

Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   66 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7d71fb9..db54e4f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7158,6 +7158,55 @@ static void gen_xxpermdi(DisasContext *ctx)
          tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), 
cpu_vsrl(xB(ctx->opcode)));
      }
  }
+#define OP_ABS 1
+#define OP_NABS 2
+#define OP_NEG 3
+#define OP_CPSGN 4
+#define SGN_MASK_DP  0x8000000000000000ul
+#define SGN_MASK_SP 0x8000000080000000ul
+
+#define VSX_SCALAR_MOVE(name, op, sgn_mask)                       \
+static void glue(gen_, name)(DisasContext * ctx)                  \
+    {                                                             \
+        TCGv_i64 xb;                                              \
+        if (unlikely(!ctx->vsx_enabled)) {                        \
+            gen_exception(ctx, POWERPC_EXCP_VSXU);                \
+            return;                                               \
+        }                                                         \
+        xb = tcg_temp_new();                                      \
+        tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode)));           \
+        switch (op) {                                             \
+            case OP_ABS: {                                        \
+                tcg_gen_andi_i64(xb, xb, ~(sgn_mask));            \
+                break;                                            \
+            }                                                     \
+            case OP_NABS: {                                       \
+                tcg_gen_ori_i64(xb, xb, (sgn_mask));              \
+                break;                                            \
+            }                                                     \
+            case OP_NEG: {                                        \
+                tcg_gen_xori_i64(xb, xb, (sgn_mask));             \
+                break;                                            \
+            }                                                     \
+            case OP_CPSGN: {                                      \
+                TCGv_i64 xa = tcg_temp_new();                     \
+                tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode)));   \
+                tcg_gen_andi_i64(xa, xa, (sgn_mask));             \
+                tcg_gen_andi_i64(xb, xb, ~(sgn_mask));            \
+                tcg_gen_or_i64(xb, xb, xa);                       \
+                tcg_temp_free(xa);                                \
+                break;                                            \
+            }                                                     \
+        }                                                         \
+        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb);           \
+        tcg_temp_free(xb);                                        \
+    }
+
+VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9617,6 +9666,18 @@ GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, 
PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),

+#undef GEN_XX2FORM
+#define GEN_XX2FORM(name, opc2, opc3, fl2)                           \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#undef GEN_XX3FORM
+#define GEN_XX3FORM(name, opc2, opc3, fl2)                           \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+
  #undef GEN_XX3FORM_DM
  #define GEN_XX3FORM_DM(name, opc2, opc3) \
  GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, 
PPC2_VSX),\
@@ -9636,6 +9697,11 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, 
opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
  GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, 
PPC2_VSX),\
  GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, 
PPC2_VSX)

+GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
+GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
+GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+
  GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),

  #undef GEN_SPE
-- 
1.7.1

[Qemu-devel] [PATCH 08/13] Add VSX Vector Move Instructions

[Tom Musta]

This patch adds the vector move instructions:

   - xvabsdp - Vector Absolute Value Double-Precision
   - xvnabsdp - Vector Negative Absolute Value Double-Precision
   - xvnegdp - Vector Negate Double-Precision
   - xvcpsgndp - Vector Copy Sign Double-Precision
   - xvabssp - Vector Absolute Value Single-Precision
   - xvnabssp - Vector Negative Absolute Value Single-Precision
   - xvnegsp - Vector Negate Single-Precision
   - xvcpsgnsp - Vector Copy Sign Single-Precision

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   68 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index db54e4f..d03675c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7207,6 +7207,66 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
  VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
  VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)

+#define VSX_VECTOR_MOVE(name, op, sgn_mask)                      \
+static void glue(gen_, name)(DisasContext * ctx)                 \
+    {                                                            \
+        TCGv_i64 xbh, xbl;                                       \
+        if (unlikely(!ctx->vsx_enabled)) { \
+            gen_exception(ctx, POWERPC_EXCP_VSXU);               \
+            return;                                              \
+        }                                                        \
+        xbh = tcg_temp_new();                                    \
+        xbl = tcg_temp_new();                                    \
+        tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
+        tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
+        switch (op) {                                            \
+            case OP_ABS: {                                       \
+                tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask));         \
+                tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask));         \
+                break;                                           \
+            }                                                    \
+            case OP_NABS: {                                      \
+                tcg_gen_ori_i64(xbh, xbh, (sgn_mask));           \
+                tcg_gen_ori_i64(xbl, xbl, (sgn_mask));           \
+                break;                                           \
+            }                                                    \
+            case OP_NEG: {                                       \
+                tcg_gen_xori_i64(xbh, xbh, (sgn_mask));          \
+                tcg_gen_xori_i64(xbl, xbl, (sgn_mask));          \
+                break;                                           \
+            }                                                    \
+            case OP_CPSGN: {                                     \
+                TCGv_i64 xah = tcg_temp_new();                   \
+                TCGv_i64 xal = tcg_temp_new();                   \
+                tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
+                tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
+                tcg_gen_andi_i64(xah, xah, (sgn_mask));          \
+                tcg_gen_andi_i64(xal, xal, (sgn_mask));          \
+                tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask));         \
+                tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask));         \
+                tcg_gen_or_i64(xbh, xbh, xah);                   \
+                tcg_gen_or_i64(xbl, xbl, xal);                   \
+                tcg_temp_free(xah);                              \
+                tcg_temp_free(xal);                              \
+                break;                                           \
+            }                                                    \
+        }                                                        \
+        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
+        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
+        tcg_temp_free(xbh);                                      \
+        tcg_temp_free(xbl);                                      \
+    }
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9702,6 +9762,14 @@ GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
  GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
  GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),

+GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
  GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),

  #undef GEN_SPE
-- 
1.7.1

[Qemu-devel] [PATCH 09/13] Add Power7 VSX Logical Instructions

[Tom Musta]

This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):

    - xxland
    - xxlandc
    - xxlor
    - xxlxor
    - xxlnor

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   29 +++++++++++++++++++++++++++++
  1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d03675c..f1ce4fe 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7267,6 +7267,24 @@ VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
  VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)


+#define VSX_LOGICAL(name, tcg_op)                                    \
+static void glue(gen_, name)(DisasContext * ctx)                     \
+ {                                                                \
+        if (unlikely(!ctx->vsx_enabled)) {                           \
+            gen_exception(ctx, POWERPC_EXCP_VSXU);                   \
+ return;                                                  \
+ }                                                            \
+        tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
+ cpu_vsrh(xB(ctx->opcode)));                              \
+        tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
+ cpu_vsrl(xB(ctx->opcode)));                              \
+    }
+
+VSX_LOGICAL(xxland, tcg_gen_and_tl)
+VSX_LOGICAL(xxlandc, tcg_gen_andc_tl)
+VSX_LOGICAL(xxlor, tcg_gen_or_tl)
+VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
+VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9770,6 +9788,17 @@ GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
  GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
  GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
  GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
+
+#undef VSX_LOGICAL
+#define VSX_LOGICAL(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3, fl2)
+
+VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
+VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
+VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
+VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
+VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+
  GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),

  #undef GEN_SPE
-- 
1.7.1

[Qemu-devel] [PATCH 10/13] Add xxmrgh/xxmrgl

[Tom Musta]

This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   44 ++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f1ce4fe..bd62c62 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7286,6 +7286,48 @@ VSX_LOGICAL(xxlor, tcg_gen_or_tl)
  VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
  VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)

+#define VSX_XXMRG(name, high)                               \
+static void glue(gen_, name)(DisasContext * ctx)            \
+    {                                                       \
+        TCGv_i64 a0, a1, b0, b1;                            \
+        if (unlikely(!ctx->vsx_enabled)) {                  \
+            gen_exception(ctx, POWERPC_EXCP_VSXU);          \
+            return;                                         \
+        }                                                   \
+        a0 = tcg_temp_new();                                \
+        a1 = tcg_temp_new();                                \
+        b0 = tcg_temp_new();                                \
+        b1 = tcg_temp_new();                                \
+        if (high) {                                         \
+            tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
+            tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
+            tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
+            tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
+        } else {                                            \
+            tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
+            tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
+            tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
+            tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
+        }                                                   \
+        tcg_gen_andi_i64(a0, a0, 0xFFFFFFFF00000000ul);     \
+        tcg_gen_shli_i64(a1, a1, 32);                       \
+        tcg_gen_shri_i64(b0, b0, 32);                       \
+        tcg_gen_andi_i64(b0, b0, 0x00000000FFFFFFFFul);     \
+        tcg_gen_andi_i64(b1, b1, 0x00000000FFFFFFFFul);     \
+        tcg_gen_or_i64(a0, a0, b0);                         \
+        tcg_gen_or_i64(a1, a1, b1);                         \
+        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), a0);     \
+        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), a1);     \
+        tcg_temp_free(a0);                                  \
+        tcg_temp_free(a1);                                  \
+        tcg_temp_free(b0);                                  \
+        tcg_temp_free(b1);                                  \
+    }
+
+VSX_XXMRG(xxmrghw, 1)
+VSX_XXMRG(xxmrglw, 0)
+
+
  /***                           SPE 
extension                               ***/
  /* Register moves */

@@ -9798,6 +9840,8 @@ VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
  VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
  VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
  VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
+GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),

  GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),

-- 
1.7.1

Re: [Qemu-devel] [PATCH 10/13] Add xxmrgh/xxmrgl

[Richard Henderson]

On 10/04/2013 06:23 AM, Tom Musta wrote:
> +        tcg_gen_andi_i64(a0, a0, 0xFFFFFFFF00000000ul);     \
> +        tcg_gen_shli_i64(a1, a1, 32);                       \
> +        tcg_gen_shri_i64(b0, b0, 32);                       \
> +        tcg_gen_andi_i64(b0, b0, 0x00000000FFFFFFFFul);     \
> +        tcg_gen_andi_i64(b1, b1, 0x00000000FFFFFFFFul);     \
> +        tcg_gen_or_i64(a0, a0, b0);                         \
> +        tcg_gen_or_i64(a1, a1, b1);                         \
> +        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), a0);     \
> +        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), a1);     \

Two deposit operations.


r~

Re: [Qemu-devel] [PATCH 10/13] Add xxmrgh/xxmrgl

[Tom Musta]

On 10/9/2013 3:09 PM, Richard Henderson wrote:
> On 10/04/2013 06:23 AM, Tom Musta wrote:
>> +        tcg_gen_andi_i64(a0, a0, 0xFFFFFFFF00000000ul);     \
>> +        tcg_gen_shli_i64(a1, a1, 32);                       \
>> +        tcg_gen_shri_i64(b0, b0, 32);                       \
>> +        tcg_gen_andi_i64(b0, b0, 0x00000000FFFFFFFFul);     \
>> +        tcg_gen_andi_i64(b1, b1, 0x00000000FFFFFFFFul);     \
>> +        tcg_gen_or_i64(a0, a0, b0);                         \
>> +        tcg_gen_or_i64(a1, a1, b1);                         \
>> +        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), a0);     \
>> +        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), a1);     \
> Two deposit operations.
>
>
> r~
Richard:  Thanks for the comments. I will rework this to use deposit 
(and also lxvw4x and xxspltw).

[Qemu-devel] [PATCH 11/13] Add xxsel

[Tom Musta]

This patch adds the VSX Select (xxsel) instruction.

The xxsel instruction has four VSR operands.  Thus the xC
instruction decoder is added.

The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits.  This
overloading is done in matrix fashion with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   83 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 83 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd62c62..a29db98 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -501,6 +501,7 @@ EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
  EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
  EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
  EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
+EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
  EXTRACT_HELPER(DM, 8, 2);
  /*****************************************************************************/
  /* PowerPC instructions 
table                                                */
@@ -7327,6 +7328,42 @@ static void glue(gen_, name)(DisasContext * 
ctx)            \
  VSX_XXMRG(xxmrghw, 1)
  VSX_XXMRG(xxmrglw, 0)

+static void gen_xxsel(DisasContext * ctx)
+{
+    TCGv_i64 a, b, c;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    a = tcg_temp_new();
+    b = tcg_temp_new();
+    c = tcg_temp_new();
+
+    tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
+    tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+    tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
+
+    tcg_gen_and_i64(b, b, c);
+    tcg_gen_not_i64(c, c);
+    tcg_gen_and_i64(a, a, c);
+    tcg_gen_or_i64(a, a, b);
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), a);
+
+    tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
+    tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+    tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
+
+    tcg_gen_and_i64(b, b, c);
+    tcg_gen_not_i64(c, c);
+    tcg_gen_and_i64(a, a, c);
+    tcg_gen_or_i64(a, a, b);
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), a);
+
+    tcg_temp_free(a);
+    tcg_temp_free(b);
+    tcg_temp_free(c);
+}
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9843,6 +9880,52 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
  GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
  GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),

+#define GEN_XXSEL_ROW(opc3) \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
+
+#define GEN_XXSEL() \
+GEN_XXSEL_ROW(0x00) \
+GEN_XXSEL_ROW(0x01) \
+GEN_XXSEL_ROW(0x02) \
+GEN_XXSEL_ROW(0x03) \
+GEN_XXSEL_ROW(0x04) \
+GEN_XXSEL_ROW(0x05) \
+GEN_XXSEL_ROW(0x06) \
+GEN_XXSEL_ROW(0x07) \
+GEN_XXSEL_ROW(0x08) \
+GEN_XXSEL_ROW(0x09) \
+GEN_XXSEL_ROW(0x0A) \
+GEN_XXSEL_ROW(0x0B) \
+GEN_XXSEL_ROW(0x0C) \
+GEN_XXSEL_ROW(0x0D) \
+GEN_XXSEL_ROW(0x0E) \
+GEN_XXSEL_ROW(0x0F) \
+GEN_XXSEL_ROW(0x10) \
+GEN_XXSEL_ROW(0x11) \
+GEN_XXSEL_ROW(0x12) \
+GEN_XXSEL_ROW(0x13) \
+GEN_XXSEL_ROW(0x14) \
+GEN_XXSEL_ROW(0x15) \
+GEN_XXSEL_ROW(0x16) \
+GEN_XXSEL_ROW(0x17) \
+GEN_XXSEL_ROW(0x18) \
+GEN_XXSEL_ROW(0x19) \
+GEN_XXSEL_ROW(0x1A) \
+GEN_XXSEL_ROW(0x1B) \
+GEN_XXSEL_ROW(0x1C) \
+GEN_XXSEL_ROW(0x1D) \
+GEN_XXSEL_ROW(0x1E) \
+GEN_XXSEL_ROW(0x1F)
+
+GEN_XXSEL()
+
  GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),

  #undef GEN_SPE
-- 
1.7.1

Re: [Qemu-devel] [PATCH 11/13] Add xxsel

[Richard Henderson]

On 10/04/2013 06:24 AM, Tom Musta wrote:
> +    tcg_gen_and_i64(b, b, c);
> +    tcg_gen_not_i64(c, c);
> +    tcg_gen_and_i64(a, a, c);

tcg_gen_andc_i64.

> +#define GEN_XXSEL() \
> +GEN_XXSEL_ROW(0x00) \
> +GEN_XXSEL_ROW(0x01) \

Why bother with defining GEN_XXSEL when its only used once?
Surely just put the rows there.

OTOH, this does suggest that we could do with a better way
to decode the instructions, because this is ugly...


r~

Re: [Qemu-devel] [PATCH 11/13] Add xxsel

[Tom Musta]

On 10/9/2013 3:13 PM, Richard Henderson wrote:
> On 10/04/2013 06:24 AM, Tom Musta wrote:
>> +    tcg_gen_and_i64(b, b, c);
>> +    tcg_gen_not_i64(c, c);
>> +    tcg_gen_and_i64(a, a, c);
> tcg_gen_andc_i64.
>
>> +#define GEN_XXSEL() \
>> +GEN_XXSEL_ROW(0x00) \
>> +GEN_XXSEL_ROW(0x01) \
> Why bother with defining GEN_XXSEL when its only used once?
> Surely just put the rows there.
>
> OTOH, this does suggest that we could do with a better way
> to decode the instructions, because this is ugly...
>
>
> r~
Yeah ... it isn't very pretty.  There was precedent for this (see, for 
example, rldcl).  And the decoding logic very much wants to use 
instruction bits 26:30 and 21:25 as opc2 and opc3 respectively. Perhaps 
I could inject a handler for opcode 60 that would handle the VSX map a 
little more gracefully.

Is your concern aesthetic?  Memory consumption?  And do you feel this is 
a showstopper or something that could be addressed later?

Re: [Qemu-devel] [PATCH 11/13] Add xxsel

[Richard Henderson]

On 10/10/2013 05:27 AM, Tom Musta wrote:
> Is your concern aesthetic?  Memory consumption?  And do you feel this is a
> showstopper or something that could be addressed later?

Aesthetic, and it definitely ought to be addressed outside this patch set.


r~

[Qemu-devel] [PATCH 12/13] Add xxspltw

[Tom Musta]

This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   50 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a29db98..5bab048 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -503,6 +503,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
  EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
  EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
  EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
  /*****************************************************************************/
  /* PowerPC instructions 
table                                                */

@@ -7364,6 +7365,54 @@ static void gen_xxsel(DisasContext * ctx)
      tcg_temp_free(c);
  }

+static void gen_xxspltw(DisasContext *ctx)
+{
+    TCGv_i64 b, b2;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+
+    b = tcg_temp_new();
+    b2 = tcg_temp_new();
+
+    tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+
+    switch (UIM(ctx->opcode)) {
+        case 0: {
+            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
+            tcg_gen_shri_i64(b, b, 32);
+            break;
+        }
+        case 1: {
+            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0x00000000FFFFFFFFul);
+            break;
+        }
+        case 2: {
+            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
+            tcg_gen_shri_i64(b, b, 32);
+            break;
+        }
+        case 3: {
+            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0x00000000FFFFFFFFul);
+            break;
+        }
+    }
+
+    tcg_gen_shli_i64(b2, b, 32);
+    tcg_gen_or_i64(b, b, b2);
+
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), b);
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), b);
+
+    tcg_temp_free(b);
+    tcg_temp_free(b2);
+}
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9879,6 +9928,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
  VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
  GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
  GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),

  #define GEN_XXSEL_ROW(opc3) \
  GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-- 
1.7.1

Re: [Qemu-devel] [PATCH 12/13] Add xxspltw

[Richard Henderson]

On 10/04/2013 06:26 AM, Tom Musta wrote:
> +        case 0: {
> +            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
> +            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
> +            tcg_gen_shri_i64(b, b, 32);
> +            break;
...
> +        case 2: {
> +            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
> +            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
> +            tcg_gen_shri_i64(b, b, 32);
> +            break;

No need for the and.

Perhaps better as

   TCGv_i64 vsr = (uim & 2 ? cpu_vrsl(xb) : cpu_vrsh(xb));
   if (uim & 1) {
       tcg_gen_ext32u_i64(b, vsr);
   } else {
       tcg_gen_shri_i32(b, vsr, 32);
   }

> +    tcg_gen_shli_i64(b2, b, 32);
> +    tcg_gen_or_i64(b, b, b2);

deposit.


r~

[Qemu-devel] [PATCH 13/13] Add xxsldwi

[Tom Musta]

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   62 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 62 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5bab048..2b337ee 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -504,6 +504,7 @@ EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
  EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
  EXTRACT_HELPER(DM, 8, 2);
  EXTRACT_HELPER(UIM, 16, 2);
+EXTRACT_HELPER(SHW, 8, 2);
  /*****************************************************************************/
  /* PowerPC instructions 
table                                                */

@@ -7413,6 +7414,66 @@ static void gen_xxspltw(DisasContext *ctx)
      tcg_temp_free(b2);
  }

+static void gen_xxsldwi(DisasContext *ctx)
+{
+    TCGv_i64 xth, xtl;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    xth = tcg_temp_new();
+    xtl = tcg_temp_new();
+
+    switch (SHW(ctx->opcode)) {
+        case 0: {
+            tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+            tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+            break;
+        }
+        case 1: {
+            TCGv_i64 t0 = tcg_temp_new();
+            tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xth, xth, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xth, xth, t0);
+            tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xtl, xtl, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xtl, xtl, t0);
+            tcg_temp_free(t0);
+            break;
+        }
+        case 2: {
+            tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+            break;
+        }
+        case 3: {
+            TCGv_i64 t0 = tcg_temp_new();
+            tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xth, xth, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xth, xth, t0);
+            tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shli_i64(xtl, xtl, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xtl, xtl, t0);
+            tcg_temp_free(t0);
+            break;
+        }
+    }
+
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
+
+    tcg_temp_free(xth);
+    tcg_temp_free(xtl);
+}
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9929,6 +9990,7 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
  GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
  GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
  GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),

  #define GEN_XXSEL_ROW(opc3) \
  GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-- 
1.7.1