[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[Vignesh R]

By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
768.MHz which is the maximum supported frequency as per AM572x DM
SPRS953A. This helps to increase flash read speed by ~2MB/s.

Tested  on DRA74 Rev G & H, DRA72 Rev B & C EVMs.


Lokesh Vutla (1):
  ARM: dra7xx: Change DPLL_PER_HS13 divider value

Vignesh R (3):
  spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
  configs: dra7xx: Update QSPI speed to 76.8MHz
  ARM: dts: dra7xx: Update spi-max-frequency for QSPI

 arch/arm/cpu/armv7/omap5/hw_data.c |  2 +-
 arch/arm/dts/dra7-evm.dts          |  2 +-
 arch/arm/dts/dra72-evm.dts         |  2 +-
 drivers/spi/ti_qspi.c              | 17 ++++++++++++-----
 include/configs/dra7xx_evm.h       |  2 +-
 5 files changed, 16 insertions(+), 9 deletions(-)

-- 
2.9.2

[U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider value

[Vignesh R]

From: Lokesh Vutla <lokeshvutla@ti.com>

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 62dd275f7ee8..a83f68c366a0 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -160,7 +160,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
-- 
2.9.2

[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Vignesh R]

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 drivers/spi/ti_qspi.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fa7ee229878a..bb72cb03ec24 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
-#define QSPI_FCLK                       192000000
+#define QSPI_FCLK			192000000
+#define QSPI_DRA7XX_FCLK                76800000
 /* clock control */
 #define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
@@ -101,6 +102,7 @@ struct ti_qspi_priv {
 #endif
 	struct ti_qspi_regs *base;
 	void *ctrl_mod_mmap;
+	ulong fclk;
 	unsigned int mode;
 	u32 cmd;
 	u32 dc;
@@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (QSPI_FCLK / hz) - 1;
+		clk_div = (priv->fclk / hz) - 1;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
@@ -366,8 +368,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+	priv->fclk = QSPI_DRA7XX_FCLK;
 #else
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+	priv->fclk = QSPI_FCLK;
 #endif
 
 	ti_spi_set_speed(priv, max_hz);
@@ -520,7 +524,10 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 
 static int ti_qspi_probe(struct udevice *bus)
 {
-	/* Nothing to do in probe */
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+	priv->fclk = dev_get_driver_data(bus);
+
 	return 0;
 }
 
@@ -572,8 +579,8 @@ static const struct dm_spi_ops ti_qspi_ops = {
 };
 
 static const struct udevice_id ti_qspi_ids[] = {
-	{ .compatible = "ti,dra7xxx-qspi" },
-	{ .compatible = "ti,am4372-qspi" },
+	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
+	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
 	{ }
 };
 
-- 
2.9.2

[U-Boot] [PATCH 3/4] configs: dra7xx: Update QSPI speed to 76.8MHz

[Vignesh R]

Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 include/configs/dra7xx_evm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0d51aeb86909..0b78ada4143c 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -157,7 +157,7 @@
 /* SPI */
 #undef	CONFIG_OMAP3_SPI
 #define CONFIG_TI_SPI_MMAP
-#define CONFIG_SF_DEFAULT_SPEED                64000000
+#define CONFIG_SF_DEFAULT_SPEED                76800000
 #define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_0
 #define CONFIG_QSPI_QUAD_SUPPORT
 
-- 
2.9.2

[U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI

[Vignesh R]

According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/dts/dra7-evm.dts  | 2 +-
 arch/arm/dts/dra72-evm.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 429b9edc1b2b..8b77a761d211 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -491,7 +491,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <64000000>;
+	spi-max-frequency = <76800000>;
 	m25p80 at 0 {
 		compatible = "s25fl256s1","spi-flash";
 		spi-max-frequency = <64000000>;
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index ced2f1166d8c..c7c5d40adac7 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -603,7 +603,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <64000000>;
+	spi-max-frequency = <76800000>;
 	m25p80 at 0 {
 		compatible = "s25fl256s1","spi-flash";
 		spi-max-frequency = <64000000>;
-- 
2.9.2

[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[Tom Rini]

On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote:

> By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
> QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
> 768.MHz which is the maximum supported frequency as per AM572x DM
> SPRS953A. This helps to increase flash read speed by ~2MB/s.
> 
> Tested  on DRA74 Rev G & H, DRA72 Rev B & C EVMs.

And for the record, there is no HW that exists "in the wild" that would
not support these options, yes?  Thanks!

-- 
Tom
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[U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider value

[Tom Rini]

On Mon, Jul 25, 2016 at 03:45:44PM +0530, Vignesh R wrote:

> From: Lokesh Vutla <lokeshvutla@ti.com>
> 
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
> clock, so that driver can use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Tom Rini]

On Mon, Jul 25, 2016 at 03:45:45PM +0530, Vignesh R wrote:

> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 3/4] configs: dra7xx: Update QSPI speed to 76.8MHz

[Tom Rini]

On Mon, Jul 25, 2016 at 03:45:46PM +0530, Vignesh R wrote:

> Now that QSPI driver can support 76.8MHz, update the
> CONFIG_SF_DEFAULT_SPEED to the same value.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI

[Tom Rini]

On Mon, Jul 25, 2016 at 03:45:47PM +0530, Vignesh R wrote:

> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
> DRA72 evm. This increase flash read speed by ~2MB/s.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

And similar changes are taking place in Linux-land and the DTS will be
updated there too, right?  Thanks!

-- 
Tom
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[U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI

[Vignesh R]

On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 03:45:47PM +0530, Vignesh R wrote:
> 
>> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
>> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
>> DRA72 evm. This increase flash read speed by ~2MB/s.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
> 
> Reviewed-by: Tom Rini <trini@konsulko.com>
> 
> And similar changes are taking place in Linux-land and the DTS will be
> updated there too, right?  Thanks!

Yes, I will be updating Kernel DTS too...


-- 
Regards
Vignesh

[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[Vignesh R]

On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote:
> 
>> By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
>> QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
>> 768.MHz which is the maximum supported frequency as per AM572x DM
>> SPRS953A. This helps to increase flash read speed by ~2MB/s.
>>
>> Tested  on DRA74 Rev G & H, DRA72 Rev B & C EVMs.
> 
> And for the record, there is no HW that exists "in the wild" that would
> not support these options, yes?  Thanks!
> 

Right, older revs are internal to TI and QSPI is not supported on them
due to erratas.


-- 
Regards
Vignesh

[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Jagan Teki]

On 25 July 2016 at 15:45, Vignesh R <vigneshr@ti.com> wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index fa7ee229878a..bb72cb03ec24 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  /* ti qpsi register bit masks */
>  #define QSPI_TIMEOUT                    2000000
> -#define QSPI_FCLK                       192000000
> +#define QSPI_FCLK                      192000000
> +#define QSPI_DRA7XX_FCLK                76800000
>  /* clock control */
>  #define QSPI_CLK_EN                     BIT(31)
>  #define QSPI_CLK_DIV_MAX                0xffff
> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>  #endif
>         struct ti_qspi_regs *base;
>         void *ctrl_mod_mmap;
> +       ulong fclk;
>         unsigned int mode;
>         u32 cmd;
>         u32 dc;
> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
>         if (!hz)
>                 clk_div = 0;
>         else
> -               clk_div = (QSPI_FCLK / hz) - 1;
> +               clk_div = (priv->fclk / hz) - 1;

Then how this relate to max_hz (priv->max_hz), look like it is not
using anywhere.

-- 
Jagan.

[U-Boot] [PATCH 3/4] configs: dra7xx: Update QSPI speed to 76.8MHz

[Jagan Teki]

On 25 July 2016 at 19:08, Tom Rini <trini@konsulko.com> wrote:
> On Mon, Jul 25, 2016 at 03:45:46PM +0530, Vignesh R wrote:
>
>> Now that QSPI driver can support 76.8MHz, update the
>> CONFIG_SF_DEFAULT_SPEED to the same value.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Vignesh R]

On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
> On 25 July 2016 at 15:45, Vignesh R <vigneshr@ti.com> wrote:
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>> the driver to use the same.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  drivers/spi/ti_qspi.c | 17 ++++++++++++-----
>>  1 file changed, 12 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> index fa7ee229878a..bb72cb03ec24 100644
>> --- a/drivers/spi/ti_qspi.c
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>>
>>  /* ti qpsi register bit masks */
>>  #define QSPI_TIMEOUT                    2000000
>> -#define QSPI_FCLK                       192000000
>> +#define QSPI_FCLK                      192000000
>> +#define QSPI_DRA7XX_FCLK                76800000
>>  /* clock control */
>>  #define QSPI_CLK_EN                     BIT(31)
>>  #define QSPI_CLK_DIV_MAX                0xffff
>> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>>  #endif
>>         struct ti_qspi_regs *base;
>>         void *ctrl_mod_mmap;
>> +       ulong fclk;
>>         unsigned int mode;
>>         u32 cmd;
>>         u32 dc;
>> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
>>         if (!hz)
>>                 clk_div = 0;
>>         else
>> -               clk_div = (QSPI_FCLK / hz) - 1;
>> +               clk_div = (priv->fclk / hz) - 1;
> 
> Then how this relate to max_hz (priv->max_hz), look like it is not
> using anywhere.

I think priv-max_hz defines the max frequency QSPI IP can support (flash
node can always be configured to run at higher or lower frequency which
is specified by spi-max-frequency in flash subnode). What's missing is a
check to see if frequency requested in set_speed() is not greater than
priv->max_hz. I will implement that in another series.


-- 
Regards
Vignesh

[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Jagan Teki]

On 27 July 2016 at 17:40, Vignesh R <vigneshr@ti.com> wrote:
>
>
> On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
>> On 25 July 2016 at 15:45, Vignesh R <vigneshr@ti.com> wrote:
>>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>>> the driver to use the same.
>>>
>>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>>> ---
>>>  drivers/spi/ti_qspi.c | 17 ++++++++++++-----
>>>  1 file changed, 12 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> index fa7ee229878a..bb72cb03ec24 100644
>>> --- a/drivers/spi/ti_qspi.c
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>>>
>>>  /* ti qpsi register bit masks */
>>>  #define QSPI_TIMEOUT                    2000000
>>> -#define QSPI_FCLK                       192000000
>>> +#define QSPI_FCLK                      192000000
>>> +#define QSPI_DRA7XX_FCLK                76800000
>>>  /* clock control */
>>>  #define QSPI_CLK_EN                     BIT(31)
>>>  #define QSPI_CLK_DIV_MAX                0xffff
>>> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>>>  #endif
>>>         struct ti_qspi_regs *base;
>>>         void *ctrl_mod_mmap;
>>> +       ulong fclk;
>>>         unsigned int mode;
>>>         u32 cmd;
>>>         u32 dc;
>>> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
>>>         if (!hz)
>>>                 clk_div = 0;
>>>         else
>>> -               clk_div = (QSPI_FCLK / hz) - 1;
>>> +               clk_div = (priv->fclk / hz) - 1;
>>
>> Then how this relate to max_hz (priv->max_hz), look like it is not
>> using anywhere.
>
> I think priv-max_hz defines the max frequency QSPI IP can support (flash
> node can always be configured to run at higher or lower frequency which
> is specified by spi-max-frequency in flash subnode). What's missing is a
> check to see if frequency requested in set_speed() is not greater than
> priv->max_hz. I will implement that in another series.

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI

[Jagan Teki]

On 25 July 2016 at 19:16, Vignesh R <vigneshr@ti.com> wrote:
>
>
> On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
>> On Mon, Jul 25, 2016 at 03:45:47PM +0530, Vignesh R wrote:
>>
>>> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
>>> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
>>> DRA72 evm. This increase flash read speed by ~2MB/s.
>>>
>>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>>
>> And similar changes are taking place in Linux-land and the DTS will be
>> updated there too, right?  Thanks!
>
> Yes, I will be updating Kernel DTS too...

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider value

[Mugunthan V N]

On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> From: Lokesh Vutla <lokeshvutla@ti.com>
> 
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
> clock, so that driver can use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---

Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N

[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Mugunthan V N]

On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N

[U-Boot] [PATCH 3/4] configs: dra7xx: Update QSPI speed to 76.8MHz

[Mugunthan V N]

On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> Now that QSPI driver can support 76.8MHz, update the
> CONFIG_SF_DEFAULT_SPEED to the same value.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N

[U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI

[Mugunthan V N]

On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
> DRA72 evm. This increase flash read speed by ~2MB/s.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---

Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N

[U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider value

[Jagan Teki]

On 29 July 2016 at 14:12, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
>> From: Lokesh Vutla <lokeshvutla@ti.com>
>>
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
>> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
>> clock, so that driver can use the same.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>
> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[Jagan Teki]

On 25 July 2016 at 15:45, Vignesh R <vigneshr@ti.com> wrote:
> By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
> QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
> 768.MHz which is the maximum supported frequency as per AM572x DM
> SPRS953A. This helps to increase flash read speed by ~2MB/s.
>
> Tested  on DRA74 Rev G & H, DRA72 Rev B & C EVMs.
>
>
> Lokesh Vutla (1):
>   ARM: dra7xx: Change DPLL_PER_HS13 divider value
>
> Vignesh R (3):
>   spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
>   configs: dra7xx: Update QSPI speed to 76.8MHz
>   ARM: dts: dra7xx: Update spi-max-frequency for QSPI

Applied to u-boot-spi/master

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.