[PATCH v4 0/7] ASPEED sgpio driver enhancement.

[PATCH v4 0/7] ASPEED sgpio driver enhancement.

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.

For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Define max number of gpio pins in ast2600 platform data. Old chip
  uses the original hardcoded value.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
  irq_chip data.
- Replace all of_*() APIs with device_*().

Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().

Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
  driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
  number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
  max_ngpios.
* Split sgpio driver patch to 3 patches

Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.

Please help to review.

Thanks,
Steven

Steven Lee (7):
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  ARM: dts: aspeed-g6: Add SGPIO node.
  gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
  gpio: gpio-aspeed-sgpio: Add set_config function
  gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
  gpio: gpio-aspeed-sgpio: Use generic device property APIs

 .../bindings/gpio/aspeed,sgpio.yaml           |  78 ++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt |  46 -----
 arch/arm/boot/dts/aspeed-g6.dtsi              |  30 +++
 drivers/gpio/gpio-aspeed-sgpio.c              | 185 +++++++++++++-----
 4 files changed, 244 insertions(+), 95 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

-- 
2.17.1

[PATCH v4 0/7] ASPEED sgpio driver enhancement.

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.

For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Define max number of gpio pins in ast2600 platform data. Old chip
  uses the original hardcoded value.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
  irq_chip data.
- Replace all of_*() APIs with device_*().

Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().

Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
  driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
  number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
  max_ngpios.
* Split sgpio driver patch to 3 patches

Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.

Please help to review.

Thanks,
Steven

Steven Lee (7):
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  ARM: dts: aspeed-g6: Add SGPIO node.
  gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
  gpio: gpio-aspeed-sgpio: Add set_config function
  gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
  gpio: gpio-aspeed-sgpio: Use generic device property APIs

 .../bindings/gpio/aspeed,sgpio.yaml           |  78 ++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt |  46 -----
 arch/arm/boot/dts/aspeed-g6.dtsi              |  30 +++
 drivers/gpio/gpio-aspeed-sgpio.c              | 185 +++++++++++++-----
 4 files changed, 244 insertions(+), 95 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

-- 
2.17.1


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[PATCH v4 1/7] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Steven Lee]

sgpio-aspeed bindings should be converted to yaml format.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 .../bindings/gpio/aspeed,sgpio.yaml           | 75 +++++++++++++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
 2 files changed, 75 insertions(+), 46 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
new file mode 100644
index 000000000000..b2ae211411ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SGPIO controller
+
+maintainers:
+  - Andrew Jeffery <andrew@aj.id.au>
+
+description:
+  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
+  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
+  support the following options
+  - Support interrupt option for each input port and various interrupt
+    sensitivity option (level-high, level-low, edge-high, edge-low)
+  - Support reset tolerance option for each output port
+  - Directly connected to APB bus and its shift clock is from APB bus clock
+    divided by a programmable value.
+  - Co-work with external signal-chained TTL components (74LV165/74LV595)
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-sgpio
+      - aspeed,ast2500-sgpio
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  clocks:
+    maxItems: 1
+
+  ngpios: true
+
+  bus-frequency: true
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - interrupts
+  - interrupt-controller
+  - ngpios
+  - clocks
+  - bus-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/aspeed-clock.h>
+    sgpio: sgpio@1e780200 {
+        #gpio-cells = <2>;
+        compatible = "aspeed,ast2500-sgpio";
+        gpio-controller;
+        interrupts = <40>;
+        reg = <0x1e780200 0x0100>;
+        clocks = <&syscon ASPEED_CLK_APB>;
+        interrupt-controller;
+        ngpios = <80>;
+        bus-frequency = <12000000>;
+    };
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
deleted file mode 100644
index be329ea4794f..000000000000
--- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Aspeed SGPIO controller Device Tree Bindings
---------------------------------------------
-
-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-support the following options:
-- Support interrupt option for each input port and various interrupt
-  sensitivity option (level-high, level-low, edge-high, edge-low)
-- Support reset tolerance option for each output port
-- Directly connected to APB bus and its shift clock is from APB bus clock
-  divided by a programmable value.
-- Co-work with external signal-chained TTL components (74LV165/74LV595)
-
-Required properties:
-
-- compatible : Should be one of
-  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
-- #gpio-cells : Should be 2, see gpio.txt
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller
-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
-  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
-  output. Up to 80 pins, must be a multiple of 8.
-- clocks : A phandle to the APB clock for SGPM clock division
-- bus-frequency : SGPM CLK frequency
-
-The sgpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-  Example:
-	sgpio: sgpio@1e780200 {
-		#gpio-cells = <2>;
-		compatible = "aspeed,ast2500-sgpio";
-		gpio-controller;
-		interrupts = <40>;
-		reg = <0x1e780200 0x0100>;
-		clocks = <&syscon ASPEED_CLK_APB>;
-		interrupt-controller;
-		ngpios = <8>;
-		bus-frequency = <12000000>;
-	};
-- 
2.17.1

[PATCH v4 1/7] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Steven Lee]

sgpio-aspeed bindings should be converted to yaml format.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 .../bindings/gpio/aspeed,sgpio.yaml           | 75 +++++++++++++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
 2 files changed, 75 insertions(+), 46 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
new file mode 100644
index 000000000000..b2ae211411ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SGPIO controller
+
+maintainers:
+  - Andrew Jeffery <andrew@aj.id.au>
+
+description:
+  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
+  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
+  support the following options
+  - Support interrupt option for each input port and various interrupt
+    sensitivity option (level-high, level-low, edge-high, edge-low)
+  - Support reset tolerance option for each output port
+  - Directly connected to APB bus and its shift clock is from APB bus clock
+    divided by a programmable value.
+  - Co-work with external signal-chained TTL components (74LV165/74LV595)
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-sgpio
+      - aspeed,ast2500-sgpio
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  clocks:
+    maxItems: 1
+
+  ngpios: true
+
+  bus-frequency: true
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - interrupts
+  - interrupt-controller
+  - ngpios
+  - clocks
+  - bus-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/aspeed-clock.h>
+    sgpio: sgpio@1e780200 {
+        #gpio-cells = <2>;
+        compatible = "aspeed,ast2500-sgpio";
+        gpio-controller;
+        interrupts = <40>;
+        reg = <0x1e780200 0x0100>;
+        clocks = <&syscon ASPEED_CLK_APB>;
+        interrupt-controller;
+        ngpios = <80>;
+        bus-frequency = <12000000>;
+    };
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
deleted file mode 100644
index be329ea4794f..000000000000
--- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Aspeed SGPIO controller Device Tree Bindings
---------------------------------------------
-
-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-support the following options:
-- Support interrupt option for each input port and various interrupt
-  sensitivity option (level-high, level-low, edge-high, edge-low)
-- Support reset tolerance option for each output port
-- Directly connected to APB bus and its shift clock is from APB bus clock
-  divided by a programmable value.
-- Co-work with external signal-chained TTL components (74LV165/74LV595)
-
-Required properties:
-
-- compatible : Should be one of
-  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
-- #gpio-cells : Should be 2, see gpio.txt
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller
-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
-  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
-  output. Up to 80 pins, must be a multiple of 8.
-- clocks : A phandle to the APB clock for SGPM clock division
-- bus-frequency : SGPM CLK frequency
-
-The sgpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-  Example:
-	sgpio: sgpio@1e780200 {
-		#gpio-cells = <2>;
-		compatible = "aspeed,ast2500-sgpio";
-		gpio-controller;
-		interrupts = <40>;
-		reg = <0x1e780200 0x0100>;
-		clocks = <&syscon ASPEED_CLK_APB>;
-		interrupt-controller;
-		ngpios = <8>;
-		bus-frequency = <12000000>;
-	};
-- 
2.17.1


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[PATCH v4 2/7] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
and update descriptions to introduce the max number of available gpio
pins that AST2600 supported.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
index b2ae211411ff..0e42eded3c1e 100644
--- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -10,9 +10,10 @@ maintainers:
   - Andrew Jeffery <andrew@aj.id.au>
 
 description:
-  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-  support the following options
+  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
+  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
+  GPIO pins can be programmed to support the following options
   - Support interrupt option for each input port and various interrupt
     sensitivity option (level-high, level-low, edge-high, edge-low)
   - Support reset tolerance option for each output port
@@ -25,6 +26,8 @@ properties:
     enum:
       - aspeed,ast2400-sgpio
       - aspeed,ast2500-sgpio
+      - aspeed,ast2600-sgpiom-80
+      - aspeed,ast2600-sgpiom-128
 
   reg:
     maxItems: 1
-- 
2.17.1

[PATCH v4 2/7] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
and update descriptions to introduce the max number of available gpio
pins that AST2600 supported.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
index b2ae211411ff..0e42eded3c1e 100644
--- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -10,9 +10,10 @@ maintainers:
   - Andrew Jeffery <andrew@aj.id.au>
 
 description:
-  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-  support the following options
+  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
+  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
+  GPIO pins can be programmed to support the following options
   - Support interrupt option for each input port and various interrupt
     sensitivity option (level-high, level-low, edge-high, edge-low)
   - Support reset tolerance option for each output port
@@ -25,6 +26,8 @@ properties:
     enum:
       - aspeed,ast2400-sgpio
       - aspeed,ast2500-sgpio
+      - aspeed,ast2600-sgpiom-80
+      - aspeed,ast2600-sgpiom-128
 
   reg:
     maxItems: 1
-- 
2.17.1


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Re: [PATCH v4 2/7] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
> and update descriptions to introduce the max number of available gpio
> pins that AST2600 supported.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v4 2/7] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
> and update descriptions to introduce the max number of available gpio
> pins that AST2600 supported.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

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[PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Steven Lee]

AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f96607b7b4e2..c09b24824b6d 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -377,6 +377,36 @@
 				#interrupt-cells = <2>;
 			};
 
+			sgpiom0: sgpiom@1e780500 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-128";
+				reg = <0x1e780500 0x100>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <128>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm1_default>;
+				status = "disabled";
+			};
+
+			sgpiom1: sgpiom@1e780600 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-80";
+				reg = <0x1e780600 0x100>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <80>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm2_default>;
+				status = "disabled";
+			};
+
 			gpio1: gpio@1e780800 {
 				#gpio-cells = <2>;
 				gpio-controller;
-- 
2.17.1

[PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Steven Lee]

AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f96607b7b4e2..c09b24824b6d 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -377,6 +377,36 @@
 				#interrupt-cells = <2>;
 			};
 
+			sgpiom0: sgpiom@1e780500 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-128";
+				reg = <0x1e780500 0x100>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <128>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm1_default>;
+				status = "disabled";
+			};
+
+			sgpiom1: sgpiom@1e780600 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-80";
+				reg = <0x1e780600 0x100>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <80>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm2_default>;
+				status = "disabled";
+			};
+
 			gpio1: gpio@1e780800 {
 				#gpio-cells = <2>;
 				gpio-controller;
-- 
2.17.1


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Re: [PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..c09b24824b6d 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -377,6 +377,36 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> +			sgpiom0: sgpiom@1e780500 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-128";
> +				reg = <0x1e780500 0x100>;
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <128>;

Doesn't this affect the way the data is presented on the bus?

My understanding is this should be defined by each platform, not in the dtsi. Having said that, it appears it is specified in aspeed-g5.dtsi (as the value 8?).

> +				clocks = <&syscon ASPEED_CLK_APB2>;
> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> +				status = "disabled";
> +			};
> +
> +			sgpiom1: sgpiom@1e780600 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-80";
> +				reg = <0x1e780600 0x100>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <80>;

As above.

Andrew

Re: [PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..c09b24824b6d 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -377,6 +377,36 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> +			sgpiom0: sgpiom@1e780500 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-128";
> +				reg = <0x1e780500 0x100>;
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <128>;

Doesn't this affect the way the data is presented on the bus?

My understanding is this should be defined by each platform, not in the dtsi. Having said that, it appears it is specified in aspeed-g5.dtsi (as the value 8?).

> +				clocks = <&syscon ASPEED_CLK_APB2>;
> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> +				status = "disabled";
> +			};
> +
> +			sgpiom1: sgpiom@1e780600 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-80";
> +				reg = <0x1e780600 0x100>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <80>;

As above.

Andrew

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Re: [PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Steven Lee]

The 06/08/2021 07:28, Andrew Jeffery wrote:
> On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index f96607b7b4e2..c09b24824b6d 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -377,6 +377,36 @@
> >  				#interrupt-cells = <2>;
> >  			};
> >  
> > +			sgpiom0: sgpiom@1e780500 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-128";
> > +				reg = <0x1e780500 0x100>;
> > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> > +				ngpios = <128>;
> 
> Doesn't this affect the way the data is presented on the bus?
> 

I add ngpios in aspeed-g6.dtsi as it can be overridden by dts files and
driver won't return error if users only add status = "okay" in
dts files without adding ngpios property.

I will remove the property from aspeed-g6.dtsi if we don't need a
default value for ngpios.

> My understanding is this should be defined by each platform, not in the dtsi. Having said that, it appears it is specified in aspeed-g5.dtsi (as the value 8?).
> 

I will remove the property from aspeed-g5 in a separate patch.

Thanks,
Steven

> > +				clocks = <&syscon ASPEED_CLK_APB2>;
> > +				interrupt-controller;
> > +				bus-frequency = <12000000>;
> > +				pinctrl-names = "default";
> > +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> > +				status = "disabled";
> > +			};
> > +
> > +			sgpiom1: sgpiom@1e780600 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-80";
> > +				reg = <0x1e780600 0x100>;
> > +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > +				ngpios = <80>;
> 
> As above.
> 
> Andrew

Re: [PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node.

[Steven Lee]

The 06/08/2021 07:28, Andrew Jeffery wrote:
> On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  arch/arm/boot/dts/aspeed-g6.dtsi | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index f96607b7b4e2..c09b24824b6d 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -377,6 +377,36 @@
> >  				#interrupt-cells = <2>;
> >  			};
> >  
> > +			sgpiom0: sgpiom@1e780500 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-128";
> > +				reg = <0x1e780500 0x100>;
> > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> > +				ngpios = <128>;
> 
> Doesn't this affect the way the data is presented on the bus?
> 

I add ngpios in aspeed-g6.dtsi as it can be overridden by dts files and
driver won't return error if users only add status = "okay" in
dts files without adding ngpios property.

I will remove the property from aspeed-g6.dtsi if we don't need a
default value for ngpios.

> My understanding is this should be defined by each platform, not in the dtsi. Having said that, it appears it is specified in aspeed-g5.dtsi (as the value 8?).
> 

I will remove the property from aspeed-g5 in a separate patch.

Thanks,
Steven

> > +				clocks = <&syscon ASPEED_CLK_APB2>;
> > +				interrupt-controller;
> > +				bus-frequency = <12000000>;
> > +				pinctrl-names = "default";
> > +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> > +				status = "disabled";
> > +			};
> > +
> > +			sgpiom1: sgpiom@1e780600 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-80";
> > +				reg = <0x1e780600 0x100>;
> > +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > +				ngpios = <80>;
> 
> As above.
> 
> Andrew

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[PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.
In the current driver, the maximum number of gpio pins of SoC is hardcoded
as 80 and the gpio pin count mask for GPIO Configuration register is
hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
value to calculate the gpio offset.
The patch adds ast2600 compatibles and platform data that includes the
max number of gpio pins supported by ast2600 and gpio pin count mask for
GPIO Configuration register.
The patch also modifies some functions to pass aspeed_sgpio struct for
calculating gpio offset without using the hardcoded value.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
 1 file changed, 76 insertions(+), 34 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 64e54f8c30d2..8b893356f0ca 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -35,12 +35,18 @@
 #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
 #define ASPEED_SGPIO_ENABLE		BIT(0)
 
+struct aspeed_sgpio_pdata {
+	const u32 pin_mask;
+	int max_ngpios;
+};
+
 struct aspeed_sgpio {
 	struct gpio_chip chip;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
 	int irq;
+	int max_ngpios;
 	int n_sgpio;
 };
 
@@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
-		.names = { "I", "J" },
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0090,
+		.rdata_reg = 0x007C,
+		.irq_regs = 0x0094,
+		.names = { "M", "N", "O", "P" },
 	},
 };
 
@@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 	}
 }
 
-#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
-#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
-#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
+#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
+#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
+#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
 
-static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
 	unsigned int bank;
 
-	bank = GPIO_BANK(offset);
+	bank = GPIO_BANK(offset, gpio);
 
 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
 	return &aspeed_sgpio_banks[bank];
@@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
 		unsigned long *valid_mask, unsigned int ngpios)
 {
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
+	int max_ngpios = sgpio->max_ngpios;
 	int n = sgpio->n_sgpio;
-	int c = SGPIO_OUTPUT_OFFSET - n;
+	int c = max_ngpios - n;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, c);
 
-	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
-	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
-	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
+	/* output GPIOS above max_ngpios */
+	bitmap_set(valid_mask, max_ngpios, n);
+	bitmap_clear(valid_mask, max_ngpios + n, c);
 
 	return 0;
 }
@@ -161,30 +174,30 @@ static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
 	int n = sgpio->n_sgpio;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < sgpio->max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, ngpios - n);
 }
 
-static bool aspeed_sgpio_is_input(unsigned int offset)
+static bool aspeed_sgpio_is_input(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
-	return offset < SGPIO_OUTPUT_OFFSET;
+	return offset < gpio->max_ngpios;
 }
 
 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	unsigned long flags;
 	enum aspeed_sgpio_reg reg;
 	int rc = 0;
 
 	spin_lock_irqsave(&gpio->lock, flags);
 
-	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
-	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
+	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
 
 	spin_unlock_irqrestore(&gpio->lock, flags);
 
@@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	void __iomem *addr_r, *addr_w;
 	u32 reg = 0;
 
-	if (aspeed_sgpio_is_input(offset))
+	if (aspeed_sgpio_is_input(offset, gpio))
 		return -EINVAL;
 
 	/* Since this is an output, read the cached value from rdata, then
@@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 	reg = ioread32(addr_r);
 
 	if (val)
-		reg |= GPIO_BIT(offset);
+		reg |= GPIO_BIT(offset, gpio);
 	else
-		reg &= ~GPIO_BIT(offset);
+		reg &= ~GPIO_BIT(offset, gpio);
 
 	iowrite32(reg, addr_w);
 
@@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 
 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 {
-	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
 }
 
 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
@@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int v
 
 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 {
-	return !!aspeed_sgpio_is_input(offset);
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return !!aspeed_sgpio_is_input(offset, gpio);
 }
 
 static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
@@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
 	WARN_ON(!internal);
 
 	*gpio = internal;
-	*bank = to_bank(*offset);
-	*bit = GPIO_BIT(*offset);
+	*bank = to_bank(*offset, internal);
+	*bit = GPIO_BIT(*offset, internal);
 }
 
 static void aspeed_sgpio_irq_ack(struct irq_data *d)
@@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
+	.max_ngpios = 128,
+	.pin_mask = GENMASK(10, 6),
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
+	.max_ngpios = 80,
+	.pin_mask = GENMASK(10, 6),
+};
+
 static const struct of_device_id aspeed_sgpio_of_table[] = {
 	{ .compatible = "aspeed,ast2400-sgpio" },
 	{ .compatible = "aspeed,ast2500-sgpio" },
+	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = &ast2600_sgpiom_128_pdata, },
+	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = &ast2600_sgpiom_80_pdata, },
 	{}
 };
 
@@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
 
 static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 {
+	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
+	const struct aspeed_sgpio_pdata *pdata;
 	struct aspeed_sgpio *gpio;
-	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
-	int rc;
 	unsigned long apb_freq;
+	int rc;
 
 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 	if (!gpio)
@@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (IS_ERR(gpio->base))
 		return PTR_ERR(gpio->base);
 
+	pdata = device_get_match_data(&pdev->dev);
+	if (pdata) {
+		gpio->max_ngpios = pdata->max_ngpios;
+		pin_mask = pdata->pin_mask;
+	} else {
+		gpio->max_ngpios = MAX_NR_HW_SGPIO;
+		pin_mask = ASPEED_SGPIO_PINS_MASK;
+	}
+
 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
-	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
+	} else if (nr_gpios % 8) {
+		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
+			nr_gpios);
+		return -EINVAL;
+	} else if (nr_gpios > gpio->max_ngpios) {
 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
-			MAX_NR_HW_SGPIO, nr_gpios);
+			gpio->max_ngpios, nr_gpios);
 		return -EINVAL;
 	}
 	gpio->n_sgpio = nr_gpios;
@@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (sgpio_clk_div > (1 << 16) - 1)
 		return -EINVAL;
 
-	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
-		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
-		  ASPEED_SGPIO_ENABLE,
-		  gpio->base + ASPEED_SGPIO_CTRL);
+	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;
+	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+		  ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
 
 	spin_lock_init(&gpio->lock);
 
 	gpio->chip.parent = &pdev->dev;
-	gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
+	gpio->chip.ngpio = gpio->max_ngpios * 2;
 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
 	gpio->chip.direction_input = aspeed_sgpio_dir_in;
 	gpio->chip.direction_output = aspeed_sgpio_dir_out;
-- 
2.17.1

[PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.
In the current driver, the maximum number of gpio pins of SoC is hardcoded
as 80 and the gpio pin count mask for GPIO Configuration register is
hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
value to calculate the gpio offset.
The patch adds ast2600 compatibles and platform data that includes the
max number of gpio pins supported by ast2600 and gpio pin count mask for
GPIO Configuration register.
The patch also modifies some functions to pass aspeed_sgpio struct for
calculating gpio offset without using the hardcoded value.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
 1 file changed, 76 insertions(+), 34 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 64e54f8c30d2..8b893356f0ca 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -35,12 +35,18 @@
 #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
 #define ASPEED_SGPIO_ENABLE		BIT(0)
 
+struct aspeed_sgpio_pdata {
+	const u32 pin_mask;
+	int max_ngpios;
+};
+
 struct aspeed_sgpio {
 	struct gpio_chip chip;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
 	int irq;
+	int max_ngpios;
 	int n_sgpio;
 };
 
@@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
-		.names = { "I", "J" },
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0090,
+		.rdata_reg = 0x007C,
+		.irq_regs = 0x0094,
+		.names = { "M", "N", "O", "P" },
 	},
 };
 
@@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 	}
 }
 
-#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
-#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
-#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
+#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
+#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
+#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
 
-static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
 	unsigned int bank;
 
-	bank = GPIO_BANK(offset);
+	bank = GPIO_BANK(offset, gpio);
 
 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
 	return &aspeed_sgpio_banks[bank];
@@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
 		unsigned long *valid_mask, unsigned int ngpios)
 {
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
+	int max_ngpios = sgpio->max_ngpios;
 	int n = sgpio->n_sgpio;
-	int c = SGPIO_OUTPUT_OFFSET - n;
+	int c = max_ngpios - n;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, c);
 
-	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
-	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
-	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
+	/* output GPIOS above max_ngpios */
+	bitmap_set(valid_mask, max_ngpios, n);
+	bitmap_clear(valid_mask, max_ngpios + n, c);
 
 	return 0;
 }
@@ -161,30 +174,30 @@ static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
 	int n = sgpio->n_sgpio;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < sgpio->max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, ngpios - n);
 }
 
-static bool aspeed_sgpio_is_input(unsigned int offset)
+static bool aspeed_sgpio_is_input(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
-	return offset < SGPIO_OUTPUT_OFFSET;
+	return offset < gpio->max_ngpios;
 }
 
 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	unsigned long flags;
 	enum aspeed_sgpio_reg reg;
 	int rc = 0;
 
 	spin_lock_irqsave(&gpio->lock, flags);
 
-	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
-	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
+	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
 
 	spin_unlock_irqrestore(&gpio->lock, flags);
 
@@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	void __iomem *addr_r, *addr_w;
 	u32 reg = 0;
 
-	if (aspeed_sgpio_is_input(offset))
+	if (aspeed_sgpio_is_input(offset, gpio))
 		return -EINVAL;
 
 	/* Since this is an output, read the cached value from rdata, then
@@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 	reg = ioread32(addr_r);
 
 	if (val)
-		reg |= GPIO_BIT(offset);
+		reg |= GPIO_BIT(offset, gpio);
 	else
-		reg &= ~GPIO_BIT(offset);
+		reg &= ~GPIO_BIT(offset, gpio);
 
 	iowrite32(reg, addr_w);
 
@@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 
 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 {
-	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
 }
 
 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
@@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int v
 
 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 {
-	return !!aspeed_sgpio_is_input(offset);
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return !!aspeed_sgpio_is_input(offset, gpio);
 }
 
 static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
@@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
 	WARN_ON(!internal);
 
 	*gpio = internal;
-	*bank = to_bank(*offset);
-	*bit = GPIO_BIT(*offset);
+	*bank = to_bank(*offset, internal);
+	*bit = GPIO_BIT(*offset, internal);
 }
 
 static void aspeed_sgpio_irq_ack(struct irq_data *d)
@@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
+	.max_ngpios = 128,
+	.pin_mask = GENMASK(10, 6),
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
+	.max_ngpios = 80,
+	.pin_mask = GENMASK(10, 6),
+};
+
 static const struct of_device_id aspeed_sgpio_of_table[] = {
 	{ .compatible = "aspeed,ast2400-sgpio" },
 	{ .compatible = "aspeed,ast2500-sgpio" },
+	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = &ast2600_sgpiom_128_pdata, },
+	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = &ast2600_sgpiom_80_pdata, },
 	{}
 };
 
@@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
 
 static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 {
+	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
+	const struct aspeed_sgpio_pdata *pdata;
 	struct aspeed_sgpio *gpio;
-	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
-	int rc;
 	unsigned long apb_freq;
+	int rc;
 
 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 	if (!gpio)
@@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (IS_ERR(gpio->base))
 		return PTR_ERR(gpio->base);
 
+	pdata = device_get_match_data(&pdev->dev);
+	if (pdata) {
+		gpio->max_ngpios = pdata->max_ngpios;
+		pin_mask = pdata->pin_mask;
+	} else {
+		gpio->max_ngpios = MAX_NR_HW_SGPIO;
+		pin_mask = ASPEED_SGPIO_PINS_MASK;
+	}
+
 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
-	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
+	} else if (nr_gpios % 8) {
+		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
+			nr_gpios);
+		return -EINVAL;
+	} else if (nr_gpios > gpio->max_ngpios) {
 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
-			MAX_NR_HW_SGPIO, nr_gpios);
+			gpio->max_ngpios, nr_gpios);
 		return -EINVAL;
 	}
 	gpio->n_sgpio = nr_gpios;
@@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (sgpio_clk_div > (1 << 16) - 1)
 		return -EINVAL;
 
-	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
-		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
-		  ASPEED_SGPIO_ENABLE,
-		  gpio->base + ASPEED_SGPIO_CTRL);
+	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;
+	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+		  ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
 
 	spin_lock_init(&gpio->lock);
 
 	gpio->chip.parent = &pdev->dev;
-	gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
+	gpio->chip.ngpio = gpio->max_ngpios * 2;
 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
 	gpio->chip.direction_input = aspeed_sgpio_dir_in;
 	gpio->chip.direction_output = aspeed_sgpio_dir_out;
-- 
2.17.1


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Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> In the current driver, the maximum number of gpio pins of SoC is hardcoded
> as 80 and the gpio pin count mask for GPIO Configuration register is
> hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> value to calculate the gpio offset.
> The patch adds ast2600 compatibles and platform data that includes the
> max number of gpio pins supported by ast2600 and gpio pin count mask for
> GPIO Configuration register.
> The patch also modifies some functions to pass aspeed_sgpio struct for
> calculating gpio offset without using the hardcoded value.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
>  1 file changed, 76 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 64e54f8c30d2..8b893356f0ca 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -35,12 +35,18 @@
>  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
>  #define ASPEED_SGPIO_ENABLE		BIT(0)
>  
> +struct aspeed_sgpio_pdata {
> +	const u32 pin_mask;
> +	int max_ngpios;
> +};
> +
>  struct aspeed_sgpio {
>  	struct gpio_chip chip;
>  	struct clk *pclk;
>  	spinlock_t lock;
>  	void __iomem *base;
>  	int irq;
> +	int max_ngpios;
>  	int n_sgpio;
>  };
>  
> @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> aspeed_sgpio_banks[] = {
>  		.val_regs = 0x0038,
>  		.rdata_reg = 0x0078,
>  		.irq_regs = 0x003C,
> -		.names = { "I", "J" },
> +		.names = { "I", "J", "K", "L" },
> +	},
> +	{
> +		.val_regs = 0x0090,
> +		.rdata_reg = 0x007C,
> +		.irq_regs = 0x0094,
> +		.names = { "M", "N", "O", "P" },
>  	},
>  };
>  
> @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
>  	}
>  }
>  
> -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)

I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:

#define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)

There's another fix necessary here too - the x needs to be parenthesised:

#define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)

> +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))

Again, put the context parameter first. And again we should add the parentheses around x in the expression.

>  
> -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> const struct aspeed_sgpio *gpio)
>  {
>  	unsigned int bank;
>  
> -	bank = GPIO_BANK(offset);
> +	bank = GPIO_BANK(offset, gpio);
>  
>  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
>  	return &aspeed_sgpio_banks[bank];
> @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> gpio_chip *gc,
>  		unsigned long *valid_mask, unsigned int ngpios)
>  {
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> +	int max_ngpios = sgpio->max_ngpios;
>  	int n = sgpio->n_sgpio;
> -	int c = SGPIO_OUTPUT_OFFSET - n;
> +	int c = max_ngpios - n;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, c);
>  
> -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> +	/* output GPIOS above max_ngpios */
> +	bitmap_set(valid_mask, max_ngpios, n);
> +	bitmap_clear(valid_mask, max_ngpios + n, c);
>  
>  	return 0;
>  }
> @@ -161,30 +174,30 @@ static void 
> aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
>  	int n = sgpio->n_sgpio;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, ngpios - n);
>  }
>  
> -static bool aspeed_sgpio_is_input(unsigned int offset)
> +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> aspeed_sgpio *gpio)
>  {
> -	return offset < SGPIO_OUTPUT_OFFSET;
> +	return offset < gpio->max_ngpios;
>  }
>  
>  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	unsigned long flags;
>  	enum aspeed_sgpio_reg reg;
>  	int rc = 0;
>  
>  	spin_lock_irqsave(&gpio->lock, flags);
>  
> -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
>  
>  	spin_unlock_irqrestore(&gpio->lock, flags);
>  
> @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> unsigned int offset)
>  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> int val)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	void __iomem *addr_r, *addr_w;
>  	u32 reg = 0;
>  
> -	if (aspeed_sgpio_is_input(offset))
> +	if (aspeed_sgpio_is_input(offset, gpio))
>  		return -EINVAL;
>  
>  	/* Since this is an output, read the cached value from rdata, then
> @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  	reg = ioread32(addr_r);
>  
>  	if (val)
> -		reg |= GPIO_BIT(offset);
> +		reg |= GPIO_BIT(offset, gpio);
>  	else
> -		reg &= ~GPIO_BIT(offset);
> +		reg &= ~GPIO_BIT(offset, gpio);
>  
>  	iowrite32(reg, addr_w);
>  
> @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  
>  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
>  {
> -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
>  }
>  
>  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> offset, int val)
> @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> *gc, unsigned int offset, int v
>  
>  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> int offset)
>  {
> -	return !!aspeed_sgpio_is_input(offset);
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return !!aspeed_sgpio_is_input(offset, gpio);
>  }
>  
>  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
>  	WARN_ON(!internal);
>  
>  	*gpio = internal;
> -	*bank = to_bank(*offset);
> -	*bit = GPIO_BIT(*offset);
> +	*bank = to_bank(*offset, internal);
> +	*bit = GPIO_BIT(*offset, internal);
>  }
>  
>  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> aspeed_sgpio *gpio,
>  	return 0;
>  }
>  
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> +	.max_ngpios = 128,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> +	.max_ngpios = 80,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
>  static const struct of_device_id aspeed_sgpio_of_table[] = {
>  	{ .compatible = "aspeed,ast2400-sgpio" },
>  	{ .compatible = "aspeed,ast2500-sgpio" },

Add .data for these too.

> +	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> &ast2600_sgpiom_128_pdata, },
> +	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> &ast2600_sgpiom_80_pdata, },
>  	{}
>  };
>  
> @@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
>  
>  static int __init aspeed_sgpio_probe(struct platform_device *pdev)
>  {
> +	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
> +	const struct aspeed_sgpio_pdata *pdata;
>  	struct aspeed_sgpio *gpio;
> -	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
> -	int rc;
>  	unsigned long apb_freq;
> +	int rc;
>  
>  	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
>  	if (!gpio)
> @@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  	if (IS_ERR(gpio->base))
>  		return PTR_ERR(gpio->base);
>  
> +	pdata = device_get_match_data(&pdev->dev);
> +	if (pdata) {
> +		gpio->max_ngpios = pdata->max_ngpios;
> +		pin_mask = pdata->pin_mask;
> +	} else {
> +		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> +		pin_mask = ASPEED_SGPIO_PINS_MASK;

Given the refactor I think the MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros are confusing and should be dropped.

Further, I think it would be better to just define these 'default' values in .data for the 2400 and 2500 compatibles and drop this if/else entirely.

> +	}
> +
>  	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
>  	if (rc < 0) {
>  		dev_err(&pdev->dev, "Could not read ngpios property\n");
>  		return -EINVAL;
> -	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
> +	} else if (nr_gpios % 8) {
> +		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
> +			nr_gpios);
> +		return -EINVAL;
> +	} else if (nr_gpios > gpio->max_ngpios) {

I'd prefer this in a separate patch.

>  		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: 
> %d\n",
> -			MAX_NR_HW_SGPIO, nr_gpios);
> +			gpio->max_ngpios, nr_gpios);
>  		return -EINVAL;
>  	}
>  	gpio->n_sgpio = nr_gpios;
> @@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  	if (sgpio_clk_div > (1 << 16) - 1)
>  		return -EINVAL;
>  
> -	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
> -		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
> -		  ASPEED_SGPIO_ENABLE,
> -		  gpio->base + ASPEED_SGPIO_CTRL);
> +	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;

Add a #define for the field starting at bit 6.

Andrew

Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> In the current driver, the maximum number of gpio pins of SoC is hardcoded
> as 80 and the gpio pin count mask for GPIO Configuration register is
> hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> value to calculate the gpio offset.
> The patch adds ast2600 compatibles and platform data that includes the
> max number of gpio pins supported by ast2600 and gpio pin count mask for
> GPIO Configuration register.
> The patch also modifies some functions to pass aspeed_sgpio struct for
> calculating gpio offset without using the hardcoded value.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
>  1 file changed, 76 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 64e54f8c30d2..8b893356f0ca 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -35,12 +35,18 @@
>  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
>  #define ASPEED_SGPIO_ENABLE		BIT(0)
>  
> +struct aspeed_sgpio_pdata {
> +	const u32 pin_mask;
> +	int max_ngpios;
> +};
> +
>  struct aspeed_sgpio {
>  	struct gpio_chip chip;
>  	struct clk *pclk;
>  	spinlock_t lock;
>  	void __iomem *base;
>  	int irq;
> +	int max_ngpios;
>  	int n_sgpio;
>  };
>  
> @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> aspeed_sgpio_banks[] = {
>  		.val_regs = 0x0038,
>  		.rdata_reg = 0x0078,
>  		.irq_regs = 0x003C,
> -		.names = { "I", "J" },
> +		.names = { "I", "J", "K", "L" },
> +	},
> +	{
> +		.val_regs = 0x0090,
> +		.rdata_reg = 0x007C,
> +		.irq_regs = 0x0094,
> +		.names = { "M", "N", "O", "P" },
>  	},
>  };
>  
> @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
>  	}
>  }
>  
> -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)

I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:

#define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)

There's another fix necessary here too - the x needs to be parenthesised:

#define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)

> +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))

Again, put the context parameter first. And again we should add the parentheses around x in the expression.

>  
> -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> const struct aspeed_sgpio *gpio)
>  {
>  	unsigned int bank;
>  
> -	bank = GPIO_BANK(offset);
> +	bank = GPIO_BANK(offset, gpio);
>  
>  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
>  	return &aspeed_sgpio_banks[bank];
> @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> gpio_chip *gc,
>  		unsigned long *valid_mask, unsigned int ngpios)
>  {
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> +	int max_ngpios = sgpio->max_ngpios;
>  	int n = sgpio->n_sgpio;
> -	int c = SGPIO_OUTPUT_OFFSET - n;
> +	int c = max_ngpios - n;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, c);
>  
> -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> +	/* output GPIOS above max_ngpios */
> +	bitmap_set(valid_mask, max_ngpios, n);
> +	bitmap_clear(valid_mask, max_ngpios + n, c);
>  
>  	return 0;
>  }
> @@ -161,30 +174,30 @@ static void 
> aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
>  	int n = sgpio->n_sgpio;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, ngpios - n);
>  }
>  
> -static bool aspeed_sgpio_is_input(unsigned int offset)
> +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> aspeed_sgpio *gpio)
>  {
> -	return offset < SGPIO_OUTPUT_OFFSET;
> +	return offset < gpio->max_ngpios;
>  }
>  
>  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	unsigned long flags;
>  	enum aspeed_sgpio_reg reg;
>  	int rc = 0;
>  
>  	spin_lock_irqsave(&gpio->lock, flags);
>  
> -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
>  
>  	spin_unlock_irqrestore(&gpio->lock, flags);
>  
> @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> unsigned int offset)
>  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> int val)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	void __iomem *addr_r, *addr_w;
>  	u32 reg = 0;
>  
> -	if (aspeed_sgpio_is_input(offset))
> +	if (aspeed_sgpio_is_input(offset, gpio))
>  		return -EINVAL;
>  
>  	/* Since this is an output, read the cached value from rdata, then
> @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  	reg = ioread32(addr_r);
>  
>  	if (val)
> -		reg |= GPIO_BIT(offset);
> +		reg |= GPIO_BIT(offset, gpio);
>  	else
> -		reg &= ~GPIO_BIT(offset);
> +		reg &= ~GPIO_BIT(offset, gpio);
>  
>  	iowrite32(reg, addr_w);
>  
> @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  
>  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
>  {
> -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
>  }
>  
>  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> offset, int val)
> @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> *gc, unsigned int offset, int v
>  
>  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> int offset)
>  {
> -	return !!aspeed_sgpio_is_input(offset);
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return !!aspeed_sgpio_is_input(offset, gpio);
>  }
>  
>  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
>  	WARN_ON(!internal);
>  
>  	*gpio = internal;
> -	*bank = to_bank(*offset);
> -	*bit = GPIO_BIT(*offset);
> +	*bank = to_bank(*offset, internal);
> +	*bit = GPIO_BIT(*offset, internal);
>  }
>  
>  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> aspeed_sgpio *gpio,
>  	return 0;
>  }
>  
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> +	.max_ngpios = 128,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> +	.max_ngpios = 80,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
>  static const struct of_device_id aspeed_sgpio_of_table[] = {
>  	{ .compatible = "aspeed,ast2400-sgpio" },
>  	{ .compatible = "aspeed,ast2500-sgpio" },

Add .data for these too.

> +	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> &ast2600_sgpiom_128_pdata, },
> +	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> &ast2600_sgpiom_80_pdata, },
>  	{}
>  };
>  
> @@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
>  
>  static int __init aspeed_sgpio_probe(struct platform_device *pdev)
>  {
> +	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
> +	const struct aspeed_sgpio_pdata *pdata;
>  	struct aspeed_sgpio *gpio;
> -	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
> -	int rc;
>  	unsigned long apb_freq;
> +	int rc;
>  
>  	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
>  	if (!gpio)
> @@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  	if (IS_ERR(gpio->base))
>  		return PTR_ERR(gpio->base);
>  
> +	pdata = device_get_match_data(&pdev->dev);
> +	if (pdata) {
> +		gpio->max_ngpios = pdata->max_ngpios;
> +		pin_mask = pdata->pin_mask;
> +	} else {
> +		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> +		pin_mask = ASPEED_SGPIO_PINS_MASK;

Given the refactor I think the MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros are confusing and should be dropped.

Further, I think it would be better to just define these 'default' values in .data for the 2400 and 2500 compatibles and drop this if/else entirely.

> +	}
> +
>  	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
>  	if (rc < 0) {
>  		dev_err(&pdev->dev, "Could not read ngpios property\n");
>  		return -EINVAL;
> -	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
> +	} else if (nr_gpios % 8) {
> +		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
> +			nr_gpios);
> +		return -EINVAL;
> +	} else if (nr_gpios > gpio->max_ngpios) {

I'd prefer this in a separate patch.

>  		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: 
> %d\n",
> -			MAX_NR_HW_SGPIO, nr_gpios);
> +			gpio->max_ngpios, nr_gpios);
>  		return -EINVAL;
>  	}
>  	gpio->n_sgpio = nr_gpios;
> @@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  	if (sgpio_clk_div > (1 << 16) - 1)
>  		return -EINVAL;
>  
> -	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
> -		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
> -		  ASPEED_SGPIO_ENABLE,
> -		  gpio->base + ASPEED_SGPIO_CTRL);
> +	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;

Add a #define for the field starting at bit 6.

Andrew

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Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Steven Lee]

The 06/08/2021 07:43, Andrew Jeffery wrote:
> 
> 
> On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins.
> > In the current driver, the maximum number of gpio pins of SoC is hardcoded
> > as 80 and the gpio pin count mask for GPIO Configuration register is
> > hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> > value to calculate the gpio offset.
> > The patch adds ast2600 compatibles and platform data that includes the
> > max number of gpio pins supported by ast2600 and gpio pin count mask for
> > GPIO Configuration register.
> > The patch also modifies some functions to pass aspeed_sgpio struct for
> > calculating gpio offset without using the hardcoded value.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
> >  1 file changed, 76 insertions(+), 34 deletions(-)
> > 
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index 64e54f8c30d2..8b893356f0ca 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -35,12 +35,18 @@
> >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> >  
> > +struct aspeed_sgpio_pdata {
> > +	const u32 pin_mask;
> > +	int max_ngpios;
> > +};
> > +
> >  struct aspeed_sgpio {
> >  	struct gpio_chip chip;
> >  	struct clk *pclk;
> >  	spinlock_t lock;
> >  	void __iomem *base;
> >  	int irq;
> > +	int max_ngpios;
> >  	int n_sgpio;
> >  };
> >  
> > @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> > aspeed_sgpio_banks[] = {
> >  		.val_regs = 0x0038,
> >  		.rdata_reg = 0x0078,
> >  		.irq_regs = 0x003C,
> > -		.names = { "I", "J" },
> > +		.names = { "I", "J", "K", "L" },
> > +	},
> > +	{
> > +		.val_regs = 0x0090,
> > +		.rdata_reg = 0x007C,
> > +		.irq_regs = 0x0094,
> > +		.names = { "M", "N", "O", "P" },
> >  	},
> >  };
> >  
> > @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
> >  	}
> >  }
> >  
> > -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> > -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> > -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> > +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
> 
> I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:
> 
> #define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)
> 
> There's another fix necessary here too - the x needs to be parenthesised:
> 
> #define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)
> 
> > +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> > +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
> 
> Again, put the context parameter first. And again we should add the parentheses around x in the expression.
> 
> >  
> > -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> > +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> > const struct aspeed_sgpio *gpio)
> >  {
> >  	unsigned int bank;
> >  
> > -	bank = GPIO_BANK(offset);
> > +	bank = GPIO_BANK(offset, gpio);
> >  
> >  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
> >  	return &aspeed_sgpio_banks[bank];
> > @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> > gpio_chip *gc,
> >  		unsigned long *valid_mask, unsigned int ngpios)
> >  {
> >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > +	int max_ngpios = sgpio->max_ngpios;
> >  	int n = sgpio->n_sgpio;
> > -	int c = SGPIO_OUTPUT_OFFSET - n;
> > +	int c = max_ngpios - n;
> >  
> > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > +	WARN_ON(ngpios < max_ngpios * 2);
> >  
> >  	/* input GPIOs in the lower range */
> >  	bitmap_set(valid_mask, 0, n);
> >  	bitmap_clear(valid_mask, n, c);
> >  
> > -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> > -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> > -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> > +	/* output GPIOS above max_ngpios */
> > +	bitmap_set(valid_mask, max_ngpios, n);
> > +	bitmap_clear(valid_mask, max_ngpios + n, c);
> >  
> >  	return 0;
> >  }
> > @@ -161,30 +174,30 @@ static void 
> > aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
> >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> >  	int n = sgpio->n_sgpio;
> >  
> > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
> >  
> >  	/* input GPIOs in the lower range */
> >  	bitmap_set(valid_mask, 0, n);
> >  	bitmap_clear(valid_mask, n, ngpios - n);
> >  }
> >  
> > -static bool aspeed_sgpio_is_input(unsigned int offset)
> > +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> > aspeed_sgpio *gpio)
> >  {
> > -	return offset < SGPIO_OUTPUT_OFFSET;
> > +	return offset < gpio->max_ngpios;
> >  }
> >  
> >  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
> >  {
> >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> >  	unsigned long flags;
> >  	enum aspeed_sgpio_reg reg;
> >  	int rc = 0;
> >  
> >  	spin_lock_irqsave(&gpio->lock, flags);
> >  
> > -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> > -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> > +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> > +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
> >  
> >  	spin_unlock_irqrestore(&gpio->lock, flags);
> >  
> > @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> > unsigned int offset)
> >  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> > int val)
> >  {
> >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> >  	void __iomem *addr_r, *addr_w;
> >  	u32 reg = 0;
> >  
> > -	if (aspeed_sgpio_is_input(offset))
> > +	if (aspeed_sgpio_is_input(offset, gpio))
> >  		return -EINVAL;
> >  
> >  	/* Since this is an output, read the cached value from rdata, then
> > @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> > unsigned int offset, int val)
> >  	reg = ioread32(addr_r);
> >  
> >  	if (val)
> > -		reg |= GPIO_BIT(offset);
> > +		reg |= GPIO_BIT(offset, gpio);
> >  	else
> > -		reg &= ~GPIO_BIT(offset);
> > +		reg &= ~GPIO_BIT(offset, gpio);
> >  
> >  	iowrite32(reg, addr_w);
> >  
> > @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> > unsigned int offset, int val)
> >  
> >  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
> >  {
> > -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > +
> > +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
> >  }
> >  
> >  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> > offset, int val)
> > @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> > *gc, unsigned int offset, int v
> >  
> >  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> > int offset)
> >  {
> > -	return !!aspeed_sgpio_is_input(offset);
> > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > +
> > +	return !!aspeed_sgpio_is_input(offset, gpio);
> >  }
> >  
> >  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> >  	WARN_ON(!internal);
> >  
> >  	*gpio = internal;
> > -	*bank = to_bank(*offset);
> > -	*bit = GPIO_BIT(*offset);
> > +	*bank = to_bank(*offset, internal);
> > +	*bit = GPIO_BIT(*offset, internal);
> >  }
> >  
> >  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> > @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> > aspeed_sgpio *gpio,
> >  	return 0;
> >  }
> >  
> > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > +	.max_ngpios = 128,
> > +	.pin_mask = GENMASK(10, 6),
> > +};
> > +
> > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> > +	.max_ngpios = 80,
> > +	.pin_mask = GENMASK(10, 6),
> > +};
> > +
> >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> >  	{ .compatible = "aspeed,ast2400-sgpio" },
> >  	{ .compatible = "aspeed,ast2500-sgpio" },
> 
> Add .data for these too.
> 

I was wondering if I can define a platform data for both ast2400 and
ast2500 as they have the same configurations.

For example:

static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
	.max_ngpios = 80,
	.pin_mask = GENMASK(9, 6),
};

static const struct of_device_id aspeed_sgpio_of_table[] = {
	{ .compatible = "aspeed,ast2400-sgpio", .data = ast2400_sgpio_pdata, },
	{ .compatible = "aspeed,ast2500-sgpio", .data = ast2400_sgpio_pdata, },

Thanks,
Steven

> > +	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> > &ast2600_sgpiom_128_pdata, },
> > +	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> > &ast2600_sgpiom_80_pdata, },
> >  	{}
> >  };
> >  
> > @@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
> >  
> >  static int __init aspeed_sgpio_probe(struct platform_device *pdev)
> >  {
> > +	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
> > +	const struct aspeed_sgpio_pdata *pdata;
> >  	struct aspeed_sgpio *gpio;
> > -	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
> > -	int rc;
> >  	unsigned long apb_freq;
> > +	int rc;
> >  
> >  	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> >  	if (!gpio)
> > @@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct 
> > platform_device *pdev)
> >  	if (IS_ERR(gpio->base))
> >  		return PTR_ERR(gpio->base);
> >  
> > +	pdata = device_get_match_data(&pdev->dev);
> > +	if (pdata) {
> > +		gpio->max_ngpios = pdata->max_ngpios;
> > +		pin_mask = pdata->pin_mask;
> > +	} else {
> > +		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > +		pin_mask = ASPEED_SGPIO_PINS_MASK;
> 
> Given the refactor I think the MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros are confusing and should be dropped.
> 
> Further, I think it would be better to just define these 'default' values in .data for the 2400 and 2500 compatibles and drop this if/else entirely.
> 
> > +	}
> > +
> >  	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
> >  	if (rc < 0) {
> >  		dev_err(&pdev->dev, "Could not read ngpios property\n");
> >  		return -EINVAL;
> > -	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
> > +	} else if (nr_gpios % 8) {
> > +		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
> > +			nr_gpios);
> > +		return -EINVAL;
> > +	} else if (nr_gpios > gpio->max_ngpios) {
> 
> I'd prefer this in a separate patch.
> 
> >  		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: 
> > %d\n",
> > -			MAX_NR_HW_SGPIO, nr_gpios);
> > +			gpio->max_ngpios, nr_gpios);
> >  		return -EINVAL;
> >  	}
> >  	gpio->n_sgpio = nr_gpios;
> > @@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct 
> > platform_device *pdev)
> >  	if (sgpio_clk_div > (1 << 16) - 1)
> >  		return -EINVAL;
> >  
> > -	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
> > -		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
> > -		  ASPEED_SGPIO_ENABLE,
> > -		  gpio->base + ASPEED_SGPIO_CTRL);
> > +	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;
> 
> Add a #define for the field starting at bit 6.
> 
> Andrew

Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Steven Lee]

The 06/08/2021 07:43, Andrew Jeffery wrote:
> 
> 
> On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins.
> > In the current driver, the maximum number of gpio pins of SoC is hardcoded
> > as 80 and the gpio pin count mask for GPIO Configuration register is
> > hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> > value to calculate the gpio offset.
> > The patch adds ast2600 compatibles and platform data that includes the
> > max number of gpio pins supported by ast2600 and gpio pin count mask for
> > GPIO Configuration register.
> > The patch also modifies some functions to pass aspeed_sgpio struct for
> > calculating gpio offset without using the hardcoded value.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
> >  1 file changed, 76 insertions(+), 34 deletions(-)
> > 
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index 64e54f8c30d2..8b893356f0ca 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -35,12 +35,18 @@
> >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> >  
> > +struct aspeed_sgpio_pdata {
> > +	const u32 pin_mask;
> > +	int max_ngpios;
> > +};
> > +
> >  struct aspeed_sgpio {
> >  	struct gpio_chip chip;
> >  	struct clk *pclk;
> >  	spinlock_t lock;
> >  	void __iomem *base;
> >  	int irq;
> > +	int max_ngpios;
> >  	int n_sgpio;
> >  };
> >  
> > @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> > aspeed_sgpio_banks[] = {
> >  		.val_regs = 0x0038,
> >  		.rdata_reg = 0x0078,
> >  		.irq_regs = 0x003C,
> > -		.names = { "I", "J" },
> > +		.names = { "I", "J", "K", "L" },
> > +	},
> > +	{
> > +		.val_regs = 0x0090,
> > +		.rdata_reg = 0x007C,
> > +		.irq_regs = 0x0094,
> > +		.names = { "M", "N", "O", "P" },
> >  	},
> >  };
> >  
> > @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
> >  	}
> >  }
> >  
> > -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> > -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> > -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> > +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
> 
> I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:
> 
> #define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)
> 
> There's another fix necessary here too - the x needs to be parenthesised:
> 
> #define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)
> 
> > +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> > +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
> 
> Again, put the context parameter first. And again we should add the parentheses around x in the expression.
> 
> >  
> > -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> > +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> > const struct aspeed_sgpio *gpio)
> >  {
> >  	unsigned int bank;
> >  
> > -	bank = GPIO_BANK(offset);
> > +	bank = GPIO_BANK(offset, gpio);
> >  
> >  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
> >  	return &aspeed_sgpio_banks[bank];
> > @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> > gpio_chip *gc,
> >  		unsigned long *valid_mask, unsigned int ngpios)
> >  {
> >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > +	int max_ngpios = sgpio->max_ngpios;
> >  	int n = sgpio->n_sgpio;
> > -	int c = SGPIO_OUTPUT_OFFSET - n;
> > +	int c = max_ngpios - n;
> >  
> > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > +	WARN_ON(ngpios < max_ngpios * 2);
> >  
> >  	/* input GPIOs in the lower range */
> >  	bitmap_set(valid_mask, 0, n);
> >  	bitmap_clear(valid_mask, n, c);
> >  
> > -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> > -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> > -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> > +	/* output GPIOS above max_ngpios */
> > +	bitmap_set(valid_mask, max_ngpios, n);
> > +	bitmap_clear(valid_mask, max_ngpios + n, c);
> >  
> >  	return 0;
> >  }
> > @@ -161,30 +174,30 @@ static void 
> > aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
> >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> >  	int n = sgpio->n_sgpio;
> >  
> > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
> >  
> >  	/* input GPIOs in the lower range */
> >  	bitmap_set(valid_mask, 0, n);
> >  	bitmap_clear(valid_mask, n, ngpios - n);
> >  }
> >  
> > -static bool aspeed_sgpio_is_input(unsigned int offset)
> > +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> > aspeed_sgpio *gpio)
> >  {
> > -	return offset < SGPIO_OUTPUT_OFFSET;
> > +	return offset < gpio->max_ngpios;
> >  }
> >  
> >  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
> >  {
> >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> >  	unsigned long flags;
> >  	enum aspeed_sgpio_reg reg;
> >  	int rc = 0;
> >  
> >  	spin_lock_irqsave(&gpio->lock, flags);
> >  
> > -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> > -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> > +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> > +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
> >  
> >  	spin_unlock_irqrestore(&gpio->lock, flags);
> >  
> > @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> > unsigned int offset)
> >  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> > int val)
> >  {
> >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> >  	void __iomem *addr_r, *addr_w;
> >  	u32 reg = 0;
> >  
> > -	if (aspeed_sgpio_is_input(offset))
> > +	if (aspeed_sgpio_is_input(offset, gpio))
> >  		return -EINVAL;
> >  
> >  	/* Since this is an output, read the cached value from rdata, then
> > @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> > unsigned int offset, int val)
> >  	reg = ioread32(addr_r);
> >  
> >  	if (val)
> > -		reg |= GPIO_BIT(offset);
> > +		reg |= GPIO_BIT(offset, gpio);
> >  	else
> > -		reg &= ~GPIO_BIT(offset);
> > +		reg &= ~GPIO_BIT(offset, gpio);
> >  
> >  	iowrite32(reg, addr_w);
> >  
> > @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> > unsigned int offset, int val)
> >  
> >  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
> >  {
> > -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > +
> > +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
> >  }
> >  
> >  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> > offset, int val)
> > @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> > *gc, unsigned int offset, int v
> >  
> >  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> > int offset)
> >  {
> > -	return !!aspeed_sgpio_is_input(offset);
> > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > +
> > +	return !!aspeed_sgpio_is_input(offset, gpio);
> >  }
> >  
> >  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> >  	WARN_ON(!internal);
> >  
> >  	*gpio = internal;
> > -	*bank = to_bank(*offset);
> > -	*bit = GPIO_BIT(*offset);
> > +	*bank = to_bank(*offset, internal);
> > +	*bit = GPIO_BIT(*offset, internal);
> >  }
> >  
> >  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> > @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> > aspeed_sgpio *gpio,
> >  	return 0;
> >  }
> >  
> > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > +	.max_ngpios = 128,
> > +	.pin_mask = GENMASK(10, 6),
> > +};
> > +
> > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> > +	.max_ngpios = 80,
> > +	.pin_mask = GENMASK(10, 6),
> > +};
> > +
> >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> >  	{ .compatible = "aspeed,ast2400-sgpio" },
> >  	{ .compatible = "aspeed,ast2500-sgpio" },
> 
> Add .data for these too.
> 

I was wondering if I can define a platform data for both ast2400 and
ast2500 as they have the same configurations.

For example:

static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
	.max_ngpios = 80,
	.pin_mask = GENMASK(9, 6),
};

static const struct of_device_id aspeed_sgpio_of_table[] = {
	{ .compatible = "aspeed,ast2400-sgpio", .data = ast2400_sgpio_pdata, },
	{ .compatible = "aspeed,ast2500-sgpio", .data = ast2400_sgpio_pdata, },

Thanks,
Steven

> > +	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> > &ast2600_sgpiom_128_pdata, },
> > +	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> > &ast2600_sgpiom_80_pdata, },
> >  	{}
> >  };
> >  
> > @@ -476,10 +505,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
> >  
> >  static int __init aspeed_sgpio_probe(struct platform_device *pdev)
> >  {
> > +	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
> > +	const struct aspeed_sgpio_pdata *pdata;
> >  	struct aspeed_sgpio *gpio;
> > -	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
> > -	int rc;
> >  	unsigned long apb_freq;
> > +	int rc;
> >  
> >  	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> >  	if (!gpio)
> > @@ -489,13 +519,26 @@ static int __init aspeed_sgpio_probe(struct 
> > platform_device *pdev)
> >  	if (IS_ERR(gpio->base))
> >  		return PTR_ERR(gpio->base);
> >  
> > +	pdata = device_get_match_data(&pdev->dev);
> > +	if (pdata) {
> > +		gpio->max_ngpios = pdata->max_ngpios;
> > +		pin_mask = pdata->pin_mask;
> > +	} else {
> > +		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > +		pin_mask = ASPEED_SGPIO_PINS_MASK;
> 
> Given the refactor I think the MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros are confusing and should be dropped.
> 
> Further, I think it would be better to just define these 'default' values in .data for the 2400 and 2500 compatibles and drop this if/else entirely.
> 
> > +	}
> > +
> >  	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
> >  	if (rc < 0) {
> >  		dev_err(&pdev->dev, "Could not read ngpios property\n");
> >  		return -EINVAL;
> > -	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
> > +	} else if (nr_gpios % 8) {
> > +		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
> > +			nr_gpios);
> > +		return -EINVAL;
> > +	} else if (nr_gpios > gpio->max_ngpios) {
> 
> I'd prefer this in a separate patch.
> 
> >  		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: 
> > %d\n",
> > -			MAX_NR_HW_SGPIO, nr_gpios);
> > +			gpio->max_ngpios, nr_gpios);
> >  		return -EINVAL;
> >  	}
> >  	gpio->n_sgpio = nr_gpios;
> > @@ -531,15 +574,14 @@ static int __init aspeed_sgpio_probe(struct 
> > platform_device *pdev)
> >  	if (sgpio_clk_div > (1 << 16) - 1)
> >  		return -EINVAL;
> >  
> > -	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
> > -		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
> > -		  ASPEED_SGPIO_ENABLE,
> > -		  gpio->base + ASPEED_SGPIO_CTRL);
> > +	gpio_cnt_regval = ((nr_gpios / 8) << 6) & pin_mask;
> 
> Add a #define for the field starting at bit 6.
> 
> Andrew

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Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Andrew Jeffery]

On Tue, 8 Jun 2021, at 12:20, Steven Lee wrote:
> The 06/08/2021 07:43, Andrew Jeffery wrote:
> > 
> > 
> > On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > > with 80 pins.
> > > In the current driver, the maximum number of gpio pins of SoC is hardcoded
> > > as 80 and the gpio pin count mask for GPIO Configuration register is
> > > hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> > > value to calculate the gpio offset.
> > > The patch adds ast2600 compatibles and platform data that includes the
> > > max number of gpio pins supported by ast2600 and gpio pin count mask for
> > > GPIO Configuration register.
> > > The patch also modifies some functions to pass aspeed_sgpio struct for
> > > calculating gpio offset without using the hardcoded value.
> > > 
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > >  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
> > >  1 file changed, 76 insertions(+), 34 deletions(-)
> > > 
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index 64e54f8c30d2..8b893356f0ca 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -35,12 +35,18 @@
> > >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> > >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> > >  
> > > +struct aspeed_sgpio_pdata {
> > > +	const u32 pin_mask;
> > > +	int max_ngpios;
> > > +};
> > > +
> > >  struct aspeed_sgpio {
> > >  	struct gpio_chip chip;
> > >  	struct clk *pclk;
> > >  	spinlock_t lock;
> > >  	void __iomem *base;
> > >  	int irq;
> > > +	int max_ngpios;
> > >  	int n_sgpio;
> > >  };
> > >  
> > > @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> > > aspeed_sgpio_banks[] = {
> > >  		.val_regs = 0x0038,
> > >  		.rdata_reg = 0x0078,
> > >  		.irq_regs = 0x003C,
> > > -		.names = { "I", "J" },
> > > +		.names = { "I", "J", "K", "L" },
> > > +	},
> > > +	{
> > > +		.val_regs = 0x0090,
> > > +		.rdata_reg = 0x007C,
> > > +		.irq_regs = 0x0094,
> > > +		.names = { "M", "N", "O", "P" },
> > >  	},
> > >  };
> > >  
> > > @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
> > >  	}
> > >  }
> > >  
> > > -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> > > -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> > > -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> > > +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
> > 
> > I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:
> > 
> > #define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)
> > 
> > There's another fix necessary here too - the x needs to be parenthesised:
> > 
> > #define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)
> > 
> > > +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> > > +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
> > 
> > Again, put the context parameter first. And again we should add the parentheses around x in the expression.
> > 
> > >  
> > > -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> > > +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> > > const struct aspeed_sgpio *gpio)
> > >  {
> > >  	unsigned int bank;
> > >  
> > > -	bank = GPIO_BANK(offset);
> > > +	bank = GPIO_BANK(offset, gpio);
> > >  
> > >  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
> > >  	return &aspeed_sgpio_banks[bank];
> > > @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> > > gpio_chip *gc,
> > >  		unsigned long *valid_mask, unsigned int ngpios)
> > >  {
> > >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > > +	int max_ngpios = sgpio->max_ngpios;
> > >  	int n = sgpio->n_sgpio;
> > > -	int c = SGPIO_OUTPUT_OFFSET - n;
> > > +	int c = max_ngpios - n;
> > >  
> > > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > > +	WARN_ON(ngpios < max_ngpios * 2);
> > >  
> > >  	/* input GPIOs in the lower range */
> > >  	bitmap_set(valid_mask, 0, n);
> > >  	bitmap_clear(valid_mask, n, c);
> > >  
> > > -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> > > -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> > > -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> > > +	/* output GPIOS above max_ngpios */
> > > +	bitmap_set(valid_mask, max_ngpios, n);
> > > +	bitmap_clear(valid_mask, max_ngpios + n, c);
> > >  
> > >  	return 0;
> > >  }
> > > @@ -161,30 +174,30 @@ static void 
> > > aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
> > >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > >  	int n = sgpio->n_sgpio;
> > >  
> > > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > > +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
> > >  
> > >  	/* input GPIOs in the lower range */
> > >  	bitmap_set(valid_mask, 0, n);
> > >  	bitmap_clear(valid_mask, n, ngpios - n);
> > >  }
> > >  
> > > -static bool aspeed_sgpio_is_input(unsigned int offset)
> > > +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> > > aspeed_sgpio *gpio)
> > >  {
> > > -	return offset < SGPIO_OUTPUT_OFFSET;
> > > +	return offset < gpio->max_ngpios;
> > >  }
> > >  
> > >  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
> > >  {
> > >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> > >  	unsigned long flags;
> > >  	enum aspeed_sgpio_reg reg;
> > >  	int rc = 0;
> > >  
> > >  	spin_lock_irqsave(&gpio->lock, flags);
> > >  
> > > -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> > > -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> > > +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> > > +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
> > >  
> > >  	spin_unlock_irqrestore(&gpio->lock, flags);
> > >  
> > > @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> > > unsigned int offset)
> > >  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> > > int val)
> > >  {
> > >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> > >  	void __iomem *addr_r, *addr_w;
> > >  	u32 reg = 0;
> > >  
> > > -	if (aspeed_sgpio_is_input(offset))
> > > +	if (aspeed_sgpio_is_input(offset, gpio))
> > >  		return -EINVAL;
> > >  
> > >  	/* Since this is an output, read the cached value from rdata, then
> > > @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> > > unsigned int offset, int val)
> > >  	reg = ioread32(addr_r);
> > >  
> > >  	if (val)
> > > -		reg |= GPIO_BIT(offset);
> > > +		reg |= GPIO_BIT(offset, gpio);
> > >  	else
> > > -		reg &= ~GPIO_BIT(offset);
> > > +		reg &= ~GPIO_BIT(offset, gpio);
> > >  
> > >  	iowrite32(reg, addr_w);
> > >  
> > > @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> > > unsigned int offset, int val)
> > >  
> > >  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
> > >  {
> > > -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> > > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > +
> > > +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
> > >  }
> > >  
> > >  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> > > offset, int val)
> > > @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> > > *gc, unsigned int offset, int v
> > >  
> > >  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> > > int offset)
> > >  {
> > > -	return !!aspeed_sgpio_is_input(offset);
> > > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > +
> > > +	return !!aspeed_sgpio_is_input(offset, gpio);
> > >  }
> > >  
> > >  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > > @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > >  	WARN_ON(!internal);
> > >  
> > >  	*gpio = internal;
> > > -	*bank = to_bank(*offset);
> > > -	*bit = GPIO_BIT(*offset);
> > > +	*bank = to_bank(*offset, internal);
> > > +	*bit = GPIO_BIT(*offset, internal);
> > >  }
> > >  
> > >  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> > > @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> > > aspeed_sgpio *gpio,
> > >  	return 0;
> > >  }
> > >  
> > > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > > +	.max_ngpios = 128,
> > > +	.pin_mask = GENMASK(10, 6),
> > > +};
> > > +
> > > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> > > +	.max_ngpios = 80,
> > > +	.pin_mask = GENMASK(10, 6),
> > > +};
> > > +
> > >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > >  	{ .compatible = "aspeed,ast2400-sgpio" },
> > >  	{ .compatible = "aspeed,ast2500-sgpio" },
> > 
> > Add .data for these too.
> > 
> 
> I was wondering if I can define a platform data for both ast2400 and
> ast2500 as they have the same configurations.
> 
> For example:
> 
> static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> 	.max_ngpios = 80,
> 	.pin_mask = GENMASK(9, 6),
> };
> 
> static const struct of_device_id aspeed_sgpio_of_table[] = {
> 	{ .compatible = "aspeed,ast2400-sgpio", .data = ast2400_sgpio_pdata, },
> 	{ .compatible = "aspeed,ast2500-sgpio", .data = ast2400_sgpio_pdata, },
> 

Yep, that's fine.

Cheers,

Andrew

Re: [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Andrew Jeffery]

On Tue, 8 Jun 2021, at 12:20, Steven Lee wrote:
> The 06/08/2021 07:43, Andrew Jeffery wrote:
> > 
> > 
> > On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > > with 80 pins.
> > > In the current driver, the maximum number of gpio pins of SoC is hardcoded
> > > as 80 and the gpio pin count mask for GPIO Configuration register is
> > > hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> > > value to calculate the gpio offset.
> > > The patch adds ast2600 compatibles and platform data that includes the
> > > max number of gpio pins supported by ast2600 and gpio pin count mask for
> > > GPIO Configuration register.
> > > The patch also modifies some functions to pass aspeed_sgpio struct for
> > > calculating gpio offset without using the hardcoded value.
> > > 
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > >  drivers/gpio/gpio-aspeed-sgpio.c | 110 +++++++++++++++++++++----------
> > >  1 file changed, 76 insertions(+), 34 deletions(-)
> > > 
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index 64e54f8c30d2..8b893356f0ca 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -35,12 +35,18 @@
> > >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> > >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> > >  
> > > +struct aspeed_sgpio_pdata {
> > > +	const u32 pin_mask;
> > > +	int max_ngpios;
> > > +};
> > > +
> > >  struct aspeed_sgpio {
> > >  	struct gpio_chip chip;
> > >  	struct clk *pclk;
> > >  	spinlock_t lock;
> > >  	void __iomem *base;
> > >  	int irq;
> > > +	int max_ngpios;
> > >  	int n_sgpio;
> > >  };
> > >  
> > > @@ -75,7 +81,13 @@ static const struct aspeed_sgpio_bank 
> > > aspeed_sgpio_banks[] = {
> > >  		.val_regs = 0x0038,
> > >  		.rdata_reg = 0x0078,
> > >  		.irq_regs = 0x003C,
> > > -		.names = { "I", "J" },
> > > +		.names = { "I", "J", "K", "L" },
> > > +	},
> > > +	{
> > > +		.val_regs = 0x0090,
> > > +		.rdata_reg = 0x007C,
> > > +		.irq_regs = 0x0094,
> > > +		.names = { "M", "N", "O", "P" },
> > >  	},
> > >  };
> > >  
> > > @@ -121,15 +133,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
> > >  	}
> > >  }
> > >  
> > > -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> > > -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> > > -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> > > +#define GPIO_BANK(x, gpio)    ((x % (gpio)->max_ngpios) >> 5)
> > 
> > I couldn't stop myself from commenting on this: The 'context' parameter should be first (by convention), so:
> > 
> > #define GPIO_BANK(gpio, x) ((x % (gpio)->max_ngpios) >> 5)
> > 
> > There's another fix necessary here too - the x needs to be parenthesised:
> > 
> > #define GPIO_BANK(gpio, x) (((x) % (gpio)->max_ngpios) >> 5)
> > 
> > > +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> > > +#define GPIO_BIT(x, gpio)     BIT(GPIO_OFFSET(x % (gpio)->max_ngpios))
> > 
> > Again, put the context parameter first. And again we should add the parentheses around x in the expression.
> > 
> > >  
> > > -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> > > +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> > > const struct aspeed_sgpio *gpio)
> > >  {
> > >  	unsigned int bank;
> > >  
> > > -	bank = GPIO_BANK(offset);
> > > +	bank = GPIO_BANK(offset, gpio);
> > >  
> > >  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
> > >  	return &aspeed_sgpio_banks[bank];
> > > @@ -139,18 +151,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> > > gpio_chip *gc,
> > >  		unsigned long *valid_mask, unsigned int ngpios)
> > >  {
> > >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > > +	int max_ngpios = sgpio->max_ngpios;
> > >  	int n = sgpio->n_sgpio;
> > > -	int c = SGPIO_OUTPUT_OFFSET - n;
> > > +	int c = max_ngpios - n;
> > >  
> > > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > > +	WARN_ON(ngpios < max_ngpios * 2);
> > >  
> > >  	/* input GPIOs in the lower range */
> > >  	bitmap_set(valid_mask, 0, n);
> > >  	bitmap_clear(valid_mask, n, c);
> > >  
> > > -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> > > -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> > > -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> > > +	/* output GPIOS above max_ngpios */
> > > +	bitmap_set(valid_mask, max_ngpios, n);
> > > +	bitmap_clear(valid_mask, max_ngpios + n, c);
> > >  
> > >  	return 0;
> > >  }
> > > @@ -161,30 +174,30 @@ static void 
> > > aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
> > >  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> > >  	int n = sgpio->n_sgpio;
> > >  
> > > -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> > > +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
> > >  
> > >  	/* input GPIOs in the lower range */
> > >  	bitmap_set(valid_mask, 0, n);
> > >  	bitmap_clear(valid_mask, n, ngpios - n);
> > >  }
> > >  
> > > -static bool aspeed_sgpio_is_input(unsigned int offset)
> > > +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> > > aspeed_sgpio *gpio)
> > >  {
> > > -	return offset < SGPIO_OUTPUT_OFFSET;
> > > +	return offset < gpio->max_ngpios;
> > >  }
> > >  
> > >  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
> > >  {
> > >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> > >  	unsigned long flags;
> > >  	enum aspeed_sgpio_reg reg;
> > >  	int rc = 0;
> > >  
> > >  	spin_lock_irqsave(&gpio->lock, flags);
> > >  
> > > -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> > > -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> > > +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> > > +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset, gpio));
> > >  
> > >  	spin_unlock_irqrestore(&gpio->lock, flags);
> > >  
> > > @@ -194,11 +207,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> > > unsigned int offset)
> > >  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> > > int val)
> > >  {
> > >  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> > > +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
> > >  	void __iomem *addr_r, *addr_w;
> > >  	u32 reg = 0;
> > >  
> > > -	if (aspeed_sgpio_is_input(offset))
> > > +	if (aspeed_sgpio_is_input(offset, gpio))
> > >  		return -EINVAL;
> > >  
> > >  	/* Since this is an output, read the cached value from rdata, then
> > > @@ -209,9 +222,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> > > unsigned int offset, int val)
> > >  	reg = ioread32(addr_r);
> > >  
> > >  	if (val)
> > > -		reg |= GPIO_BIT(offset);
> > > +		reg |= GPIO_BIT(offset, gpio);
> > >  	else
> > > -		reg &= ~GPIO_BIT(offset);
> > > +		reg &= ~GPIO_BIT(offset, gpio);
> > >  
> > >  	iowrite32(reg, addr_w);
> > >  
> > > @@ -232,7 +245,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> > > unsigned int offset, int val)
> > >  
> > >  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
> > >  {
> > > -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> > > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > +
> > > +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
> > >  }
> > >  
> > >  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> > > offset, int val)
> > > @@ -253,7 +268,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> > > *gc, unsigned int offset, int v
> > >  
> > >  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> > > int offset)
> > >  {
> > > -	return !!aspeed_sgpio_is_input(offset);
> > > +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> > > +
> > > +	return !!aspeed_sgpio_is_input(offset, gpio);
> > >  }
> > >  
> > >  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > > @@ -268,8 +285,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> > >  	WARN_ON(!internal);
> > >  
> > >  	*gpio = internal;
> > > -	*bank = to_bank(*offset);
> > > -	*bit = GPIO_BIT(*offset);
> > > +	*bank = to_bank(*offset, internal);
> > > +	*bit = GPIO_BIT(*offset, internal);
> > >  }
> > >  
> > >  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> > > @@ -466,9 +483,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> > > aspeed_sgpio *gpio,
> > >  	return 0;
> > >  }
> > >  
> > > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > > +	.max_ngpios = 128,
> > > +	.pin_mask = GENMASK(10, 6),
> > > +};
> > > +
> > > +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> > > +	.max_ngpios = 80,
> > > +	.pin_mask = GENMASK(10, 6),
> > > +};
> > > +
> > >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > >  	{ .compatible = "aspeed,ast2400-sgpio" },
> > >  	{ .compatible = "aspeed,ast2500-sgpio" },
> > 
> > Add .data for these too.
> > 
> 
> I was wondering if I can define a platform data for both ast2400 and
> ast2500 as they have the same configurations.
> 
> For example:
> 
> static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> 	.max_ngpios = 80,
> 	.pin_mask = GENMASK(9, 6),
> };
> 
> static const struct of_device_id aspeed_sgpio_of_table[] = {
> 	{ .compatible = "aspeed,ast2400-sgpio", .data = ast2400_sgpio_pdata, },
> 	{ .compatible = "aspeed,ast2500-sgpio", .data = ast2400_sgpio_pdata, },
> 

Yep, that's fine.

Cheers,

Andrew

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[PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function

[Steven Lee]

AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++---
 1 file changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 8b893356f0ca..08696f12ee1c 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -51,9 +51,10 @@ struct aspeed_sgpio {
 };
 
 struct aspeed_sgpio_bank {
-	uint16_t    val_regs;
-	uint16_t    rdata_reg;
-	uint16_t    irq_regs;
+	u16    val_regs;
+	u16    rdata_reg;
+	u16    irq_regs;
+	u16    tolerance_regs;
 	const char  names[4][3];
 };
 
@@ -69,24 +70,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0000,
 		.rdata_reg = 0x0070,
 		.irq_regs = 0x0004,
+		.tolerance_regs = 0x0018,
 		.names = { "A", "B", "C", "D" },
 	},
 	{
 		.val_regs = 0x001C,
 		.rdata_reg = 0x0074,
 		.irq_regs = 0x0020,
+		.tolerance_regs = 0x0034,
 		.names = { "E", "F", "G", "H" },
 	},
 	{
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
+		.tolerance_regs = 0x0050,
 		.names = { "I", "J", "K", "L" },
 	},
 	{
 		.val_regs = 0x0090,
 		.rdata_reg = 0x007C,
 		.irq_regs = 0x0094,
+		.tolerance_regs = 0x00A8,
 		.names = { "M", "N", "O", "P" },
 	},
 };
@@ -99,6 +104,7 @@ enum aspeed_sgpio_reg {
 	reg_irq_type1,
 	reg_irq_type2,
 	reg_irq_status,
+	reg_tolerance,
 };
 
 #define GPIO_VAL_VALUE      0x00
@@ -127,6 +133,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
 	case reg_irq_status:
 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+	case reg_tolerance:
+		return gpio->base + bank->tolerance_regs;
 	default:
 		/* acturally if code runs to here, it's an error case */
 		BUG();
@@ -483,6 +491,44 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+					unsigned int offset, bool enable)
+{
+	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+	unsigned long flags;
+	void __iomem *reg;
+	u32 val;
+
+	reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance);
+
+	spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(reg);
+
+	if (enable)
+		val |= GPIO_BIT(offset, gpio);
+	else
+		val &= ~GPIO_BIT(offset, gpio);
+
+	writel(val, reg);
+
+	spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+				   unsigned long config)
+{
+	unsigned long param = pinconf_to_config_param(config);
+	u32 arg = pinconf_to_config_argument(config);
+
+	if (param == PIN_CONFIG_PERSIST_STATE)
+		return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+
+	return -ENOTSUPP;
+}
+
 static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
 	.max_ngpios = 128,
 	.pin_mask = GENMASK(10, 6),
@@ -590,7 +636,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	gpio->chip.free = NULL;
 	gpio->chip.get = aspeed_sgpio_get;
 	gpio->chip.set = aspeed_sgpio_set;
-	gpio->chip.set_config = NULL;
+	gpio->chip.set_config = aspeed_sgpio_set_config;
 	gpio->chip.label = dev_name(&pdev->dev);
 	gpio->chip.base = -1;
 
-- 
2.17.1

[PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function

[Steven Lee]

AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++---
 1 file changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 8b893356f0ca..08696f12ee1c 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -51,9 +51,10 @@ struct aspeed_sgpio {
 };
 
 struct aspeed_sgpio_bank {
-	uint16_t    val_regs;
-	uint16_t    rdata_reg;
-	uint16_t    irq_regs;
+	u16    val_regs;
+	u16    rdata_reg;
+	u16    irq_regs;
+	u16    tolerance_regs;
 	const char  names[4][3];
 };
 
@@ -69,24 +70,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0000,
 		.rdata_reg = 0x0070,
 		.irq_regs = 0x0004,
+		.tolerance_regs = 0x0018,
 		.names = { "A", "B", "C", "D" },
 	},
 	{
 		.val_regs = 0x001C,
 		.rdata_reg = 0x0074,
 		.irq_regs = 0x0020,
+		.tolerance_regs = 0x0034,
 		.names = { "E", "F", "G", "H" },
 	},
 	{
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
+		.tolerance_regs = 0x0050,
 		.names = { "I", "J", "K", "L" },
 	},
 	{
 		.val_regs = 0x0090,
 		.rdata_reg = 0x007C,
 		.irq_regs = 0x0094,
+		.tolerance_regs = 0x00A8,
 		.names = { "M", "N", "O", "P" },
 	},
 };
@@ -99,6 +104,7 @@ enum aspeed_sgpio_reg {
 	reg_irq_type1,
 	reg_irq_type2,
 	reg_irq_status,
+	reg_tolerance,
 };
 
 #define GPIO_VAL_VALUE      0x00
@@ -127,6 +133,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
 	case reg_irq_status:
 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+	case reg_tolerance:
+		return gpio->base + bank->tolerance_regs;
 	default:
 		/* acturally if code runs to here, it's an error case */
 		BUG();
@@ -483,6 +491,44 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+					unsigned int offset, bool enable)
+{
+	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+	unsigned long flags;
+	void __iomem *reg;
+	u32 val;
+
+	reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance);
+
+	spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(reg);
+
+	if (enable)
+		val |= GPIO_BIT(offset, gpio);
+	else
+		val &= ~GPIO_BIT(offset, gpio);
+
+	writel(val, reg);
+
+	spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+				   unsigned long config)
+{
+	unsigned long param = pinconf_to_config_param(config);
+	u32 arg = pinconf_to_config_argument(config);
+
+	if (param == PIN_CONFIG_PERSIST_STATE)
+		return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+
+	return -ENOTSUPP;
+}
+
 static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
 	.max_ngpios = 128,
 	.pin_mask = GENMASK(10, 6),
@@ -590,7 +636,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	gpio->chip.free = NULL;
 	gpio->chip.get = aspeed_sgpio_get;
 	gpio->chip.set = aspeed_sgpio_set;
-	gpio->chip.set_config = NULL;
+	gpio->chip.set_config = aspeed_sgpio_set_config;
 	gpio->chip.label = dev_name(&pdev->dev);
 	gpio->chip.base = -1;
 
-- 
2.17.1


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Re: [PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST SoC supports *retain pin state* function when wdt reset.
> The patch adds set_config function for handling sgpio reset tolerance
> register.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> AST SoC supports *retain pin state* function when wdt reset.
> The patch adds set_config function for handling sgpio reset tolerance
> register.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

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[PATCH v4 6/7] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct

[Steven Lee]

The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 08696f12ee1c..b53dd1fa5849 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -42,6 +42,7 @@ struct aspeed_sgpio_pdata {
 
 struct aspeed_sgpio {
 	struct gpio_chip chip;
+	struct irq_chip intc;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
@@ -437,14 +438,6 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
-static struct irq_chip aspeed_sgpio_irqchip = {
-	.name       = "aspeed-sgpio",
-	.irq_ack    = aspeed_sgpio_irq_ack,
-	.irq_mask   = aspeed_sgpio_irq_mask,
-	.irq_unmask = aspeed_sgpio_irq_unmask,
-	.irq_set_type   = aspeed_sgpio_set_type,
-};
-
 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 				   struct platform_device *pdev)
 {
@@ -467,8 +460,14 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
 	}
 
+	gpio->intc.name = dev_name(&pdev->dev);
+	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
+	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
+	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
+	gpio->intc.irq_set_type = aspeed_sgpio_set_type;
+
 	irq = &gpio->chip.irq;
-	irq->chip = &aspeed_sgpio_irqchip;
+	irq->chip = &gpio->intc;
 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
-- 
2.17.1

[PATCH v4 6/7] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct

[Steven Lee]

The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 08696f12ee1c..b53dd1fa5849 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -42,6 +42,7 @@ struct aspeed_sgpio_pdata {
 
 struct aspeed_sgpio {
 	struct gpio_chip chip;
+	struct irq_chip intc;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
@@ -437,14 +438,6 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
-static struct irq_chip aspeed_sgpio_irqchip = {
-	.name       = "aspeed-sgpio",
-	.irq_ack    = aspeed_sgpio_irq_ack,
-	.irq_mask   = aspeed_sgpio_irq_mask,
-	.irq_unmask = aspeed_sgpio_irq_unmask,
-	.irq_set_type   = aspeed_sgpio_set_type,
-};
-
 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 				   struct platform_device *pdev)
 {
@@ -467,8 +460,14 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
 	}
 
+	gpio->intc.name = dev_name(&pdev->dev);
+	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
+	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
+	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
+	gpio->intc.irq_set_type = aspeed_sgpio_set_type;
+
 	irq = &gpio->chip.irq;
-	irq->chip = &aspeed_sgpio_irqchip;
+	irq->chip = &gpio->intc;
 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
-- 
2.17.1


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[PATCH v4 7/7] gpio: gpio-aspeed-sgpio: Use generic device property APIs

[Steven Lee]

Replace all of_property_read_u32() with device_property_read_u32().

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index b53dd1fa5849..da62e213916a 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -573,7 +573,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 		pin_mask = ASPEED_SGPIO_PINS_MASK;
 	}
 
-	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
@@ -588,7 +588,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	}
 	gpio->n_sgpio = nr_gpios;
 
-	rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read bus-frequency property\n");
 		return -EINVAL;
-- 
2.17.1

[PATCH v4 7/7] gpio: gpio-aspeed-sgpio: Use generic device property APIs

[Steven Lee]

Replace all of_property_read_u32() with device_property_read_u32().

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index b53dd1fa5849..da62e213916a 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -573,7 +573,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 		pin_mask = ASPEED_SGPIO_PINS_MASK;
 	}
 
-	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
@@ -588,7 +588,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	}
 	gpio->n_sgpio = nr_gpios;
 
-	rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read bus-frequency property\n");
 		return -EINVAL;
-- 
2.17.1


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Re: [PATCH v4 7/7] gpio: gpio-aspeed-sgpio: Use generic device property APIs

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> Replace all of_property_read_u32() with device_property_read_u32().
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Acked-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v4 7/7] gpio: gpio-aspeed-sgpio: Use generic device property APIs

[Andrew Jeffery]

On Mon, 7 Jun 2021, at 16:45, Steven Lee wrote:
> Replace all of_property_read_u32() with device_property_read_u32().
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Acked-by: Andrew Jeffery <andrew@aj.id.au>

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