* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
0 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-kernel
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Kukjin Kim, Russell King, Ben Dooks,
Mike Turquette, Daniel Lezcano, Thomas Gleixner, Heiko Stuebner,
Naour Romain, devicetree, linux-doc, linux-arm-kernel,
linux-samsung-soc, Tarek Dakhran, Tyrtov Vyacheslav, Dave.Martin,
nicolas.pitre, tomasz.figa
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exynos 5410.
Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
This patches is activating only the big cluster (all A15 cores)
EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15)
to run at the same time, will be released separately
Has been build on v3.13-rc3
Has been tested on Exynos 5410 reference board (exynos_defconfig)
Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre.
I hope, this is enough clean and hasn't any dependencies to go through
Samsung tree. Kukjin, what do you think about it?
Vyacheslav.
Changelog:
v5:
EDCS removed to separate patch.
In arch/arm/mach-exynos/Kconfig
1. Removed select ARM_CCI and MCPM.
In arch/arm/mach-exynos/platsmp.c
1. Added correct boot_reg for exynos5410.
In arch/arm/boot/dts/exynos5410.dtsi
1. Removed cortex-a7 cpu nodes and cci node.
v4:
In arch/arm/mach-exynos/edcs.c
1. Renamed all exynos_ prefixes to edcs_.
2. Reworked edcs_core_power_up/down functions.
3. Removed exynos_core_power_control function.
4. Added this_core_to_pcpu function.
5. Added core_power_state function which detects if cpu is being reset.
6. Replaced cache flush sequences with v7_exit_coherency_flush().
7. exynos_core_power_down moved to lock protected area.
8. edcs_power_down_finish implemented.
In Documentation/devicetree/bindings/clock/exynos5410-clock.txt
1. External clocks documented.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. oscclk node corrected according to ePAPR recommendation.
In arch/arm/boot/dts/exynos5410.dtsi
1. mct@101C0000 node renamed to timer@101C0000.
2. "interrupt-controller" line removed from mct node.
3. mct_map renamed to interrupt_map.
In arch/arm/mach-exynos/Kconfig
1. some cosmetic corrections.
In include/dt-bindings/clock/exynos5410.h
1. Unnecessary defines removed.
v3:
In drivers/clk/samsung/clk-exynos5410.c
1. Fixed rate clock "samsung,clock-oscclk" removed.
In arch/arm/boot/dts/exynos5410.dtsi
1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. Fixed rate oscclk clock added.
In arch/arm/mach-exynos/edcs.c
1. Added write memory barrier in exynos_core_power_control function.
2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed.
3. #define added for some magic constants.
4. Disabled the GIC CPU interface in exynos_power_down function.
v2:
In drivers/clk/samsung/clk-exynos5410.c
1. Clock driver converted to use preprocessor macros instead of enums.
Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
2. Unused spinlock removed.
3. Function exynos5410_clk_init defined as static.
Struct exynos5410_fixed_rate_ext_clks defined as static.
Struct exynos5410_mux_clks defined as static.
Struct exynos5410_div_clks defined as static.
Struct exynos5410_gate_clks defined as static.
4. Removed aliases.
5. Pll's magic register offsets defined as preprocessor macros.
6. Redundant check of device_node pointer removed.
In arch/arm/boot/dts/exynos5410.dtsi
1. dwmmcX nodes renamed to mmc.
dwmmc_X renamed to mmc_X.
dwmmc status="disabled" field added.
fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
2. Blank lines added where necessary.
3. cpu@ suffixes corrected.
4. edcs node removed.
5. Hexadecimal characters case corrected.
6. Clock IDs replaced with preprocessor macros.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. status = "okay" field added to mmc nodes.
In arch/arm/mach-exynos/edcs.c
1. "kfs_" prefix replaced with "edcs_"
2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
4. mcpm_sync_init() call added.
5. power management functions reworked.
Other
1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
ARM_CCI in arch/arm/mach-exynos/Kconfig.
3. edcs_status driver removed.
Tarek Dakhran (3):
ARM: EXYNOS: Add support for EXYNOS5410 SoC
clk: exynos5410: register clocks using common clock framework
ARM: dts: Add initial device tree support for EXYNOS5410
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++
arch/arm/boot/dts/exynos5410.dtsi | 145 +++++++++++++
arch/arm/mach-exynos/Kconfig | 10 +
arch/arm/mach-exynos/common.c | 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 32 +++
14 files changed, 587 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
--
1.8.1.5
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
0 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-arm-kernel
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exynos 5410.
Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
This patches is activating only the big cluster (all A15 cores)
EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15)
to run at the same time, will be released separately
Has been build on v3.13-rc3
Has been tested on Exynos 5410 reference board (exynos_defconfig)
Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre.
I hope, this is enough clean and hasn't any dependencies to go through
Samsung tree. Kukjin, what do you think about it?
Vyacheslav.
Changelog:
v5:
EDCS removed to separate patch.
In arch/arm/mach-exynos/Kconfig
1. Removed select ARM_CCI and MCPM.
In arch/arm/mach-exynos/platsmp.c
1. Added correct boot_reg for exynos5410.
In arch/arm/boot/dts/exynos5410.dtsi
1. Removed cortex-a7 cpu nodes and cci node.
v4:
In arch/arm/mach-exynos/edcs.c
1. Renamed all exynos_ prefixes to edcs_.
2. Reworked edcs_core_power_up/down functions.
3. Removed exynos_core_power_control function.
4. Added this_core_to_pcpu function.
5. Added core_power_state function which detects if cpu is being reset.
6. Replaced cache flush sequences with v7_exit_coherency_flush().
7. exynos_core_power_down moved to lock protected area.
8. edcs_power_down_finish implemented.
In Documentation/devicetree/bindings/clock/exynos5410-clock.txt
1. External clocks documented.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. oscclk node corrected according to ePAPR recommendation.
In arch/arm/boot/dts/exynos5410.dtsi
1. mct at 101C0000 node renamed to timer at 101C0000.
2. "interrupt-controller" line removed from mct node.
3. mct_map renamed to interrupt_map.
In arch/arm/mach-exynos/Kconfig
1. some cosmetic corrections.
In include/dt-bindings/clock/exynos5410.h
1. Unnecessary defines removed.
v3:
In drivers/clk/samsung/clk-exynos5410.c
1. Fixed rate clock "samsung,clock-oscclk" removed.
In arch/arm/boot/dts/exynos5410.dtsi
1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. Fixed rate oscclk clock added.
In arch/arm/mach-exynos/edcs.c
1. Added write memory barrier in exynos_core_power_control function.
2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed.
3. #define added for some magic constants.
4. Disabled the GIC CPU interface in exynos_power_down function.
v2:
In drivers/clk/samsung/clk-exynos5410.c
1. Clock driver converted to use preprocessor macros instead of enums.
Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
2. Unused spinlock removed.
3. Function exynos5410_clk_init defined as static.
Struct exynos5410_fixed_rate_ext_clks defined as static.
Struct exynos5410_mux_clks defined as static.
Struct exynos5410_div_clks defined as static.
Struct exynos5410_gate_clks defined as static.
4. Removed aliases.
5. Pll's magic register offsets defined as preprocessor macros.
6. Redundant check of device_node pointer removed.
In arch/arm/boot/dts/exynos5410.dtsi
1. dwmmcX nodes renamed to mmc.
dwmmc_X renamed to mmc_X.
dwmmc status="disabled" field added.
fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
2. Blank lines added where necessary.
3. cpu@ suffixes corrected.
4. edcs node removed.
5. Hexadecimal characters case corrected.
6. Clock IDs replaced with preprocessor macros.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. status = "okay" field added to mmc nodes.
In arch/arm/mach-exynos/edcs.c
1. "kfs_" prefix replaced with "edcs_"
2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
4. mcpm_sync_init() call added.
5. power management functions reworked.
Other
1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
ARM_CCI in arch/arm/mach-exynos/Kconfig.
3. edcs_status driver removed.
Tarek Dakhran (3):
ARM: EXYNOS: Add support for EXYNOS5410 SoC
clk: exynos5410: register clocks using common clock framework
ARM: dts: Add initial device tree support for EXYNOS5410
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++
arch/arm/boot/dts/exynos5410.dtsi | 145 +++++++++++++
arch/arm/mach-exynos/Kconfig | 10 +
arch/arm/mach-exynos/common.c | 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 32 +++
14 files changed, 587 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
--
1.8.1.5
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
2013-12-10 14:26 ` Vyacheslav Tyrtov
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
-1 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-kernel
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Kukjin Kim, Russell King, Ben Dooks,
Mike Turquette, Daniel Lezcano, Thomas Gleixner, Heiko Stuebner,
Naour Romain, devicetree, linux-doc, linux-arm-kernel,
linux-samsung-soc, Tarek Dakhran, Tyrtov Vyacheslav, Dave.Martin,
nicolas.pitre, tomasz.figa
From: Tarek Dakhran <t.dakhran@samsung.com>
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 10 ++++++++++
arch/arm/mach-exynos/common.c | 18 ++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 ++
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..1414bc6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 58b43e6..6506ce6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5410_SOC_ID 0xE5410000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410() is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c186786..31cac97 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -57,6 +57,9 @@
#define S3C_UART_OFFSET (0x400)
#endif
+#define S5P_VA_SYSRAM_NS_X(x) (S5P_VA_SYSRAM_NS + (x))
+#define EXYNOS5410_BOOT_REG S5P_VA_SYSRAM_NS_X(0x1c)
+
#include <plat/map-s3c.h>
#endif /* __ASM_PLAT_MAP_S5P_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v5 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
0 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 10 ++++++++++
arch/arm/mach-exynos/common.c | 18 ++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 ++
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..1414bc6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 58b43e6..6506ce6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5410_SOC_ID 0xE5410000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410() is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c186786..31cac97 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -57,6 +57,9 @@
#define S3C_UART_OFFSET (0x400)
#endif
+#define S5P_VA_SYSRAM_NS_X(x) (S5P_VA_SYSRAM_NS + (x))
+#define EXYNOS5410_BOOT_REG S5P_VA_SYSRAM_NS_X(0x1c)
+
#include <plat/map-s3c.h>
#endif /* __ASM_PLAT_MAP_S5P_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v5 2/3] clk: exynos5410: register clocks using common clock framework
2013-12-10 14:26 ` Vyacheslav Tyrtov
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
-1 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-kernel
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Kukjin Kim, Russell King, Ben Dooks,
Mike Turquette, Daniel Lezcano, Thomas Gleixner, Heiko Stuebner,
Naour Romain, devicetree, linux-doc, linux-arm-kernel,
linux-samsung-soc, Tarek Dakhran, Tyrtov Vyacheslav, Dave.Martin,
nicolas.pitre, tomasz.figa
From: Tarek Dakhran <t.dakhran@samsung.com>
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 0000000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 0000000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long exynos5410_clk_regs[] __initdata = {
+ SRC_CPU,
+ DIV_CPU0,
+ SRC_CPERI1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_FSYS,
+ SRC_PERIC0,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIC0,
+ GATE_BUS_FSYS0,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ SRC_CDREX,
+ SRC_KFC,
+ DIV_KFC0,
+};
+
+/* list of all parent clocks */
+PNAME(apll_p) = { "fin_pll", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+
+PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
+ "none", "none", "sclk_mpll_bpll",
+ "none", "none", "sclk_cpll" };
+
+static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
+ MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+ MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+ MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+ MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+ MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+ MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+ MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+ MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+ MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+ MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+
+ MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+ MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+ MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+
+ MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+ DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+ DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+ DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+ DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+ DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+ DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+ DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+ DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+ DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+ DIV_F(0, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+ DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+ GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+ GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+ GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+
+ GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+ exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
+ NULL, 0);
+
+ samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
+ reg_base);
+
+ samsung_clk_register_mux(exynos5410_mux_clks,
+ ARRAY_SIZE(exynos5410_mux_clks));
+ samsung_clk_register_div(exynos5410_div_clks,
+ ARRAY_SIZE(exynos5410_div_clks));
+ samsung_clk_register_gate(exynos5410_gate_clks,
+ ARRAY_SIZE(exynos5410_gate_clks));
+
+ pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000..3df181f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,32 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FOUT_APLL 1
+#define CLK_FOUT_CPLL 2
+#define CLK_FOUT_MPLL 3
+#define CLK_FOUT_BPLL 4
+#define CLK_FOUT_KPLL 5
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_MCT 315
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+
+#define CLK_NR_CLKS 512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v5 2/3] clk: exynos5410: register clocks using common clock framework
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
0 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 0000000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller at 0x10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 0000000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long exynos5410_clk_regs[] __initdata = {
+ SRC_CPU,
+ DIV_CPU0,
+ SRC_CPERI1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_FSYS,
+ SRC_PERIC0,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIC0,
+ GATE_BUS_FSYS0,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ SRC_CDREX,
+ SRC_KFC,
+ DIV_KFC0,
+};
+
+/* list of all parent clocks */
+PNAME(apll_p) = { "fin_pll", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+
+PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
+ "none", "none", "sclk_mpll_bpll",
+ "none", "none", "sclk_cpll" };
+
+static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
+ MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+ MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+ MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+ MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+ MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+ MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+ MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+ MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+ MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+ MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+
+ MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+ MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+ MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+
+ MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+ DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+ DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+ DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+ DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+ DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+ DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+ DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+ DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+ DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+ DIV_F(0, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+ DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+ GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+ GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+ GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+
+ GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+ exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
+ NULL, 0);
+
+ samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
+ reg_base);
+
+ samsung_clk_register_mux(exynos5410_mux_clks,
+ ARRAY_SIZE(exynos5410_mux_clks));
+ samsung_clk_register_div(exynos5410_div_clks,
+ ARRAY_SIZE(exynos5410_div_clks));
+ samsung_clk_register_gate(exynos5410_gate_clks,
+ ARRAY_SIZE(exynos5410_gate_clks));
+
+ pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000..3df181f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,32 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FOUT_APLL 1
+#define CLK_FOUT_CPLL 2
+#define CLK_FOUT_MPLL 3
+#define CLK_FOUT_BPLL 4
+#define CLK_FOUT_KPLL 5
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_MCT 315
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+
+#define CLK_NR_CLKS 512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v5 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
2013-12-10 14:26 ` Vyacheslav Tyrtov
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
-1 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-kernel
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Kukjin Kim, Russell King, Ben Dooks,
Mike Turquette, Daniel Lezcano, Thomas Gleixner, Heiko Stuebner,
Naour Romain, devicetree, linux-doc, linux-arm-kernel,
linux-samsung-soc, Tarek Dakhran, Tyrtov Vyacheslav, Dave.Martin,
nicolas.pitre, tomasz.figa
From: Tarek Dakhran <t.dakhran@samsung.com>
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++++++++++
arch/arm/boot/dts/exynos5410.dtsi | 145 ++++++++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 0000000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc@12200000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@12220000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 0000000..bf1b0cf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,145 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/exynos5410.h>
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1600000000>;
+ };
+ };
+
+ clock: clock-controller@10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+ timer@101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0xB00>;
+ interrupt-parent = <&interrupt_map>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
+ clocks = <&fin_pll>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ interrupt_map: interrupt-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &combiner 23 3>,
+ <1 &combiner 23 4>,
+ <2 &combiner 25 2>,
+ <3 &combiner 25 3>,
+ <4 &gic 0 120 0>,
+ <5 &gic 0 121 0>,
+ <6 &gic 0 122 0>,
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
+ };
+ };
+
+ mmc_0: mmc@12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12200000 0x1000>;
+ clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_1: mmc@12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12210000 0x1000>;
+ clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_2: mmc@12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12220000 0x1000>;
+ clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ serial@12C00000 {
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C10000 {
+ clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C20000 {
+ clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C30000 {
+ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v5 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
@ 2013-12-10 14:26 ` Vyacheslav Tyrtov
0 siblings, 0 replies; 18+ messages in thread
From: Vyacheslav Tyrtov @ 2013-12-10 14:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++++++++++
arch/arm/boot/dts/exynos5410.dtsi | 145 ++++++++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 0000000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc at 12200000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc at 12220000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 0000000..bf1b0cf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,145 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/exynos5410.h>
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1600000000>;
+ };
+ };
+
+ clock: clock-controller at 10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+ timer at 101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0xB00>;
+ interrupt-parent = <&interrupt_map>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
+ clocks = <&fin_pll>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ interrupt_map: interrupt-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &combiner 23 3>,
+ <1 &combiner 23 4>,
+ <2 &combiner 25 2>,
+ <3 &combiner 25 3>,
+ <4 &gic 0 120 0>,
+ <5 &gic 0 121 0>,
+ <6 &gic 0 122 0>,
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
+ };
+ };
+
+ mmc_0: mmc at 12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12200000 0x1000>;
+ clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_1: mmc at 12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12210000 0x1000>;
+ clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_2: mmc at 12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12220000 0x1000>;
+ clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ serial at 12C00000 {
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C10000 {
+ clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C20000 {
+ clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C30000 {
+ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
2013-12-10 14:26 ` Vyacheslav Tyrtov
(?)
@ 2013-12-10 16:40 ` Kevin Hilman
-1 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2013-12-10 16:40 UTC (permalink / raw)
To: Vyacheslav Tyrtov
Cc: linux-kernel, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Kukjin Kim,
Russell King, Ben Dooks, Mike Turquette, Daniel Lezcano,
Thomas Gleixner, Heiko Stuebner, Naour Romain, devicetree,
linux-doc, linux-arm-kernel, linux-samsung-soc, Tarek Dakhran,
Dave.Martin, nicolas.pitre, tomasz.figa
Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
>
> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
> This patches is activating only the big cluster (all A15 cores)
Testing this series on top of v3.13-rc3, plus a couple of other
necessary changes (which should've probably been noted in the changelog):
1) change CONFIG_NR_CPUS=8 in .config
2) add the exynos combiner patch from Chander:
[PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.045000] CPU0: update cpu_power 1024
[ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
[ 0.045000] CPU1: Booted secondary processor
[ 0.065000] CPU1: update cpu_power 1024
[ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 1.075000] CPU2: failed to boot: -38
[ 2.075000] CPU3: failed to boot: -38
[ 2.075000] Brought up 2 CPUs
[ 2.075000] SMP: Total of 2 processors activated.
[ 2.075000] CPU: All CPU(s) started in SVC mode.
Full boot log below.
Kevin
Connected to odroid-xu console [channel connected] (~$quit to exit)
(user:khilman) is already connected
(user:khilman) is already connected
~$hardreset
/ #
Command(odroid-xu console)> hardreset
(user:khilman) Reboot odroid-xu
.~;+wQ\bt.
U-Boot 2012.07-g3de3ad26283f (Nov 19 2013 - 13:47:04) for Exynos5410
CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
APLL = 900MHz, KPLL = 600MHz
MPLL = 532MHz, BPLL = 800MHz
DRAM: 2 GiB
WARNING: Caches not enabled
TrustZone Enabled BSP
BL1 version:
PMIC VER : 0, CHIP REV : 6
VDD MIF : 1.00000V
VDD ARM : 1.00000V
VDD INT : 1.00000V
VDD G3D : 1.00000V
VDD KFC : 1.00000V
Checking Boot Mode ... SDMMC
MMC: S5P_MSHC2: 0, S5P_MSHC0: 1
MMC Device 0: 7.4 GiB
MMC Device 1: [ERROR] response error : 00000006 cmd 8
[ERROR] response error : 00000006 cmd 55
[ERROR] response error : 00000006 cmd 2
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Press 'Enter' or 'Space' to stop autoboot: 3
\b\b\b 0
ODROID-XU #
ODROID-XU # version
version
U-Boot 2012.07-g3de3ad26283f (Nov 19 2013 - 13:47:04) for Exynos5410
arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.2-1ubuntu1) 4.7.2
GNU ld (GNU Binutils for Ubuntu) 2.22.90.20120919
ODROID-XU # setenv preboot usb start
setenv preboot usb start
ODROID-XU # setenv bootargs console=ttySAC2,115200n8 debug earlyprintk
setenv bootargs console=ttySAC2,115200n8 debug earlyprintk
ODROID-XU # if test -n ${initenv}; then run initenv; fi
if test -n ${initenv}; then run initenv; fi
ODROID-XU # if test -n ${preboot}; then run preboot; fi
if test -n ${preboot}; then run preboot; fi
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
scanning bus for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
ODROID-XU # setenv autoload no; setenv autoboot no
setenv autoload no; setenv autoboot no
ODROID-XU # dhcp
dhcp
Waiting for Ethernet connection... done.
BOOTP broadcast 1
DHCP client bound to address 192.168.1.187
ODROID-XU # setenv serverip 192.168.1.2
setenv serverip 192.168.1.2
ODROID-XU # if test -n ${netargs}; then run netargs; fi
if test -n ${netargs}; then run netargs; fi
ODROID-XU # tftp 0x40800000 tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage
tftp 0x40800000 tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.187
Filename 'tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage'.
Load address: 0x40800000
Loading: *\b#################################################################
#################################################################
##########################################################
done
Bytes transferred = 2745780 (29e5b4 hex)
ODROID-XU # tftp 0x42000000 buildroot.cpio.gz.uboot
tftp 0x42000000 buildroot.cpio.gz.uboot
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.187
Filename 'buildroot.cpio.gz.uboot'.
Load address: 0x42000000
Loading: *\b############################################
done
Bytes transferred = 639808 (9c340 hex)
ODROID-XU # printenv bootargs
printenv bootargs
bootargs=console=ttySAC2,115200n8 debug earlyprintk
ODROID-XU # bootm 0x40800000 0x42000000
bootm 0x40800000 0x42000000
## Booting kernel from Legacy Image at 40800000 ...
Image Name: Linux
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2745716 Bytes = 2.6 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 42000000 ...
Image Name:
Image Type: ARM Linux RAMDisk Image (uncompressed)
Data Size: 639744 Bytes = 624.8 KiB
Load Address: 81000000
Entry Point: 81000000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.13.0-rc3-linaro-00004-g0a685036323f (khilman@paris) (gcc version 4.7.2 (Ubuntu/Linaro 4.7.2-1ubuntu1) ) #4 SMP PREEMPT Tue Dec 10 08:35:04 PST 2013
[ 0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] Machine model: Samsung SMDK5410 board based on EXYNOS5410
[ 0.000000] NR_BANKS too low, ignoring high memory
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] CPU EXYNOS5410 (id 0xe5410023)
[ 0.000000] On node 0 totalpages: 521728
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 2572 pages used for memmap
[ 0.000000] HighMem zone: 327168 pages, LIFO batch:31
[ 0.000000] PERCPU: Embedded 7 pages/cpu @c0779000 s7424 r8192 d13056 u32768
[ 0.000000] pcpu-alloc: s7424 r8192 d13056 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520208
[ 0.000000] Kernel command line: console=ttySAC2,115200n8 debug earlyprintk
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 2063404K/2086912K available (3629K kernel code, 228K rwdata, 1120K rodata, 227K init, 268K bss, 23508K reserved, 1308672K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc04ab7b4 (4750 kB)
[ 0.000000] .init : 0xc04ac000 - 0xc04e4d00 ( 228 kB)
[ 0.000000] .data : 0xc04e6000 - 0xc051f0e0 ( 229 kB)
[ 0.000000] .bss : 0xc051f0ec - 0xc05623bc ( 269 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] sched_clock: 32 bits at 200 Hz, resolution 5000000ns, wraps every 10737418240000000ns
[ 0.000000] Console: colour dummy device 80x30
[ 0.045000] Calibrating delay loop... 1785.85 BogoMIPS (lpj=4464640)
[ 0.045000] pid_max: default: 32768 minimum: 301
[ 0.045000] Mount-cache hash table entries: 512
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.045000] CPU0: update cpu_power 1024
[ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
[ 0.045000] CPU1: Booted secondary processor
[ 0.065000] CPU1: update cpu_power 1024
[ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 1.075000] CPU2: failed to boot: -38
[ 2.075000] CPU3: failed to boot: -38
[ 2.075000] Brought up 2 CPUs
[ 2.075000] SMP: Total of 2 processors activated.
[ 2.075000] CPU: All CPU(s) started in SVC mode.
[ 2.075000] devtmpfs: initialized
[ 2.080000] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[ 2.080000] pinctrl core: initialized pinctrl subsystem
[ 2.080000] regulator-dummy: no parameters
[ 2.080000] NET: Registered protocol family 16
[ 2.080000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 2.085000] S3C Power Management, Copyright 2004 Simtec Electronics
[ 2.085000] EXYNOS: PMU not supported
[ 2.085000] EXYNOS: Initializing architecture
[ 2.100000] bio: create slab <bio-0> at 0
[ 2.100000] SCSI subsystem initialized
[ 2.100000] usbcore: registered new interface driver usbfs
[ 2.100000] usbcore: registered new interface driver hub
[ 2.100000] usbcore: registered new device driver usb
[ 2.105000] Switched to clocksource mct-frc
[ 2.120000] NET: Registered protocol family 2
[ 2.120000] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 2.120000] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[ 2.120000] TCP: Hash tables configured (established 8192 bind 8192)
[ 2.120000] TCP: reno registered
[ 2.120000] UDP hash table entries: 512 (order: 2, 24576 bytes)
[ 2.120000] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[ 2.125000] NET: Registered protocol family 1
[ 2.125000] Trying to unpack rootfs image as initramfs...
[ 2.170000] Freeing initrd memory: 620K (c2001000 - c209c000)
[ 2.175000] bounce pool size: 64 pages
[ 2.185000] ROMFS MTD (C) 2007 Red Hat, Inc.
[ 2.185000] msgmni has been set to 1475
[ 2.185000] io scheduler noop registered
[ 2.185000] io scheduler deadline registered
[ 2.185000] io scheduler cfq registered (default)
[ 2.280000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.285000] 12c00000.serial: ttySAC0 at MMIO 0x12c00000 (irq = 83, base_baud = 0) is a S3C6400/10
[ 2.285000] 12c10000.serial: ttySAC1 at MMIO 0x12c10000 (irq = 84, base_baud = 0) is a S3C6400/10
[ 2.285000] 12c20000.serial: ttySAC2 at MMIO 0x12c20000 (irq = 85, base_baud = 0) is a S3C6400/10
[ 2.780000] console [ttySAC2] enabled
[ 2.785000] 12c30000.serial: ttySAC3 at MMIO 0x12c30000 (irq = 86, base_baud = 0) is a S3C6400/10
[ 2.805000] brd: module loaded
[ 2.810000] loop: module loaded
[ 2.810000] usbcore: registered new interface driver asix
[ 2.815000] usbcore: registered new interface driver ax88179_178a
[ 2.825000] usbcore: registered new interface driver cdc_ether
[ 2.830000] usbcore: registered new interface driver r815x
[ 2.835000] usbcore: registered new interface driver smsc75xx
[ 2.840000] usbcore: registered new interface driver smsc95xx
[ 2.845000] usbcore: registered new interface driver net1080
[ 2.850000] usbcore: registered new interface driver cdc_subset
[ 2.855000] usbcore: registered new interface driver zaurus
[ 2.865000] usbcore: registered new interface driver cdc_ncm
[ 2.870000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 2.875000] usbcore: registered new interface driver usb-storage
[ 2.880000] mousedev: PS/2 mouse device common for all mice
[ 2.890000] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com
[ 2.895000] sdhci: Secure Digital Host Controller Interface driver
[ 2.900000] sdhci: Copyright(c) Pierre Ossman
[ 2.905000] Synopsys Designware Multimedia Card Interface Driver
[ 2.910000] dwmmc_exynos dwmmc0.0: invalid resource
[ 2.915000] dwmmc_exynos: probe of dwmmc0.0 failed with error -22
[ 2.920000] dwmmc_exynos dwmmc1.1: invalid resource
[ 2.925000] dwmmc_exynos: probe of dwmmc1.1 failed with error -22
[ 2.935000] dwmmc_exynos dwmmc2.2: invalid resource
[ 2.940000] dwmmc_exynos: probe of dwmmc2.2 failed with error -22
[ 2.945000] dwmmc_exynos 12200000.mmc: dummy supplies not allowed
[ 2.950000] dwmmc_exynos 12200000.mmc: no vmmc regulator found: -19
[ 2.955000] dwmmc_exynos 12200000.mmc: Using internal DMA controller.
[ 2.965000] dwmmc_exynos 12200000.mmc: Version ID is 241a
[ 2.970000] dwmmc_exynos 12200000.mmc: DW MMC controller at irq 107, 64 bit host data width, 128 deep fifo
[ 2.980000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc@12200000/slot@0[0]'
[ 3.015000] dwmmc_exynos 12200000.mmc: 1 slots initialized
[ 3.015000] dwmmc_exynos 12220000.mmc: dummy supplies not allowed
[ 3.025000] dwmmc_exynos 12220000.mmc: no vmmc regulator found: -19
[ 3.030000] dwmmc_exynos 12220000.mmc: Using internal DMA controller.
[ 3.035000] dwmmc_exynos 12220000.mmc: Version ID is 241a
[ 3.040000] dwmmc_exynos 12220000.mmc: DW MMC controller at irq 109, 64 bit host data width, 128 deep fifo
[ 3.050000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc@12220000/slot@0[0]'
[ 3.090000] dwmmc_exynos 12220000.mmc: 1 slots initialized
[ 3.095000] usbcore: registered new interface driver usbhid
[ 3.100000] usbhid: USB HID core driver
[ 3.100000] TCP: cubic registered
[ 3.105000] NET: Registered protocol family 17
[ 3.110000] NET: Registered protocol family 15
[ 3.115000] Registering SWP/SWPB emulation handler
[ 3.120000] /work/kernel/linaro/dev/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 3.130000] Freeing unused kernel memory: 224K (c04ac000 - c04e4000)
Starting logging: [ 3.155000] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
[ 3.165000] mmc1: new high speed SDHC card at address e624
OK
Initializing rand[ 3.170000] isa bounce pool size: 16 pages
om number gene[ 3.180000] mmcblk0: mmc1:e624 SU08G 7.40 GiB
rator... [ 3.185000] mmcblk0: p1 p2
[ 3.185000] random: dd urandom read with 13 bits of entropy available
done.
Starting network...
mount: mounting none on /sys/kernel/debug failed: No such file or directory
/bin/sh: can't access tty; job control turned off
/ # cat /proc/cmdline
cat /proc/cmdline
console=ttySAC2,115200n8 debug earlyprintk
/ # uname -r
uname -r
3.13.0-rc3-linaro-00004-g0a685036323f
/ # cat /proc/cpuinfo
cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 3 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc0f
CPU revision : 3
processor : 1
model name : ARMv7 Processor rev 3 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc0f
CPU revision : 3
Hardware : SAMSUNG EXYNOS5 (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
/ # ip -f inet -o addr
ip -f inet -o addr
1: lo inet 127.0.0.1/8 scope host lo\ valid_lft forever preferred_lft forever
/ # # PYBOOT: Time: 22.81 seconds.
# PYBOOT: Result: PASS
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-10 16:40 ` Kevin Hilman
0 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2013-12-10 16:40 UTC (permalink / raw)
To: Vyacheslav Tyrtov
Cc: linux-kernel, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Kukjin Kim,
Russell King, Ben Dooks, Mike Turquette, Daniel Lezcano,
Thomas Gleixner, Heiko Stuebner, Naour Romain, devicetree,
linux-doc, linux-arm-kernel, linux-samsung-soc, Tarek Dakhran,
Dave.Martin, nicolas.pitre, tomasz.figa
Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
>
> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
> This patches is activating only the big cluster (all A15 cores)
Testing this series on top of v3.13-rc3, plus a couple of other
necessary changes (which should've probably been noted in the changelog):
1) change CONFIG_NR_CPUS=8 in .config
2) add the exynos combiner patch from Chander:
[PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.045000] CPU0: update cpu_power 1024
[ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
[ 0.045000] CPU1: Booted secondary processor
[ 0.065000] CPU1: update cpu_power 1024
[ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 1.075000] CPU2: failed to boot: -38
[ 2.075000] CPU3: failed to boot: -38
[ 2.075000] Brought up 2 CPUs
[ 2.075000] SMP: Total of 2 processors activated.
[ 2.075000] CPU: All CPU(s) started in SVC mode.
Full boot log below.
Kevin
Connected to odroid-xu console [channel connected] (~$quit to exit)
(user:khilman) is already connected
(user:khilman) is already connected
~$hardreset
/ #
Command(odroid-xu console)> hardreset
(user:khilman) Reboot odroid-xu
.~;+wQ\bt.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-10 16:40 ` Kevin Hilman
0 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2013-12-10 16:40 UTC (permalink / raw)
To: linux-arm-kernel
Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
>
> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
> This patches is activating only the big cluster (all A15 cores)
Testing this series on top of v3.13-rc3, plus a couple of other
necessary changes (which should've probably been noted in the changelog):
1) change CONFIG_NR_CPUS=8 in .config
2) add the exynos combiner patch from Chander:
[PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.045000] CPU0: update cpu_power 1024
[ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
[ 0.045000] CPU1: Booted secondary processor
[ 0.065000] CPU1: update cpu_power 1024
[ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 1.075000] CPU2: failed to boot: -38
[ 2.075000] CPU3: failed to boot: -38
[ 2.075000] Brought up 2 CPUs
[ 2.075000] SMP: Total of 2 processors activated.
[ 2.075000] CPU: All CPU(s) started in SVC mode.
Full boot log below.
Kevin
Connected to odroid-xu console [channel connected] (~$quit to exit)
(user:khilman) is already connected
(user:khilman) is already connected
~$hardreset
/ #
Command(odroid-xu console)> hardreset
(user:khilman) Reboot odroid-xu
.~;+wQ\bt.\0t.\x04.\0.\0.\0.\0.\0.\0.\0.~.Reboot: odroid-xu ; phidget 1 3 : off, sleep, on
U-Boot 2012.07-g3de3ad26283f (Nov 19 2013 - 13:47:04) for Exynos5410
CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
APLL = 900MHz, KPLL = 600MHz
MPLL = 532MHz, BPLL = 800MHz
DRAM: 2 GiB
WARNING: Caches not enabled
TrustZone Enabled BSP
BL1 version:
PMIC VER : 0, CHIP REV : 6
VDD MIF : 1.00000V
VDD ARM : 1.00000V
VDD INT : 1.00000V
VDD G3D : 1.00000V
VDD KFC : 1.00000V
Checking Boot Mode ... SDMMC
MMC: S5P_MSHC2: 0, S5P_MSHC0: 1
MMC Device 0: 7.4 GiB
MMC Device 1: [ERROR] response error : 00000006 cmd 8
[ERROR] response error : 00000006 cmd 55
[ERROR] response error : 00000006 cmd 2
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Press 'Enter' or 'Space' to stop autoboot: 3
\b\b\b 0
ODROID-XU #
ODROID-XU # version
version
U-Boot 2012.07-g3de3ad26283f (Nov 19 2013 - 13:47:04) for Exynos5410
arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.2-1ubuntu1) 4.7.2
GNU ld (GNU Binutils for Ubuntu) 2.22.90.20120919
ODROID-XU # setenv preboot usb start
setenv preboot usb start
ODROID-XU # setenv bootargs console=ttySAC2,115200n8 debug earlyprintk
setenv bootargs console=ttySAC2,115200n8 debug earlyprintk
ODROID-XU # if test -n ${initenv}; then run initenv; fi
if test -n ${initenv}; then run initenv; fi
ODROID-XU # if test -n ${preboot}; then run preboot; fi
if test -n ${preboot}; then run preboot; fi
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
scanning bus for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
ODROID-XU # setenv autoload no; setenv autoboot no
setenv autoload no; setenv autoboot no
ODROID-XU # dhcp
dhcp
Waiting for Ethernet connection... done.
BOOTP broadcast 1
DHCP client bound to address 192.168.1.187
ODROID-XU # setenv serverip 192.168.1.2
setenv serverip 192.168.1.2
ODROID-XU # if test -n ${netargs}; then run netargs; fi
if test -n ${netargs}; then run netargs; fi
ODROID-XU # tftp 0x40800000 tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage
tftp 0x40800000 tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.187
Filename 'tmp/odroid-xu-erdIn8/tmp9D1Cmd-uImage'.
Load address: 0x40800000
Loading: *\b#################################################################
#################################################################
##########################################################
done
Bytes transferred = 2745780 (29e5b4 hex)
ODROID-XU # tftp 0x42000000 buildroot.cpio.gz.uboot
tftp 0x42000000 buildroot.cpio.gz.uboot
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.187
Filename 'buildroot.cpio.gz.uboot'.
Load address: 0x42000000
Loading: *\b############################################
done
Bytes transferred = 639808 (9c340 hex)
ODROID-XU # printenv bootargs
printenv bootargs
bootargs=console=ttySAC2,115200n8 debug earlyprintk
ODROID-XU # bootm 0x40800000 0x42000000
bootm 0x40800000 0x42000000
## Booting kernel from Legacy Image at 40800000 ...
Image Name: Linux
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2745716 Bytes = 2.6 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 42000000 ...
Image Name:
Image Type: ARM Linux RAMDisk Image (uncompressed)
Data Size: 639744 Bytes = 624.8 KiB
Load Address: 81000000
Entry Point: 81000000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.13.0-rc3-linaro-00004-g0a685036323f (khilman at paris) (gcc version 4.7.2 (Ubuntu/Linaro 4.7.2-1ubuntu1) ) #4 SMP PREEMPT Tue Dec 10 08:35:04 PST 2013
[ 0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] Machine model: Samsung SMDK5410 board based on EXYNOS5410
[ 0.000000] NR_BANKS too low, ignoring high memory
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] CPU EXYNOS5410 (id 0xe5410023)
[ 0.000000] On node 0 totalpages: 521728
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 2572 pages used for memmap
[ 0.000000] HighMem zone: 327168 pages, LIFO batch:31
[ 0.000000] PERCPU: Embedded 7 pages/cpu @c0779000 s7424 r8192 d13056 u32768
[ 0.000000] pcpu-alloc: s7424 r8192 d13056 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520208
[ 0.000000] Kernel command line: console=ttySAC2,115200n8 debug earlyprintk
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 2063404K/2086912K available (3629K kernel code, 228K rwdata, 1120K rodata, 227K init, 268K bss, 23508K reserved, 1308672K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc04ab7b4 (4750 kB)
[ 0.000000] .init : 0xc04ac000 - 0xc04e4d00 ( 228 kB)
[ 0.000000] .data : 0xc04e6000 - 0xc051f0e0 ( 229 kB)
[ 0.000000] .bss : 0xc051f0ec - 0xc05623bc ( 269 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] sched_clock: 32 bits at 200 Hz, resolution 5000000ns, wraps every 10737418240000000ns
[ 0.000000] Console: colour dummy device 80x30
[ 0.045000] Calibrating delay loop... 1785.85 BogoMIPS (lpj=4464640)
[ 0.045000] pid_max: default: 32768 minimum: 301
[ 0.045000] Mount-cache hash table entries: 512
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.045000] CPU0: update cpu_power 1024
[ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
[ 0.045000] CPU1: Booted secondary processor
[ 0.065000] CPU1: update cpu_power 1024
[ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 1.075000] CPU2: failed to boot: -38
[ 2.075000] CPU3: failed to boot: -38
[ 2.075000] Brought up 2 CPUs
[ 2.075000] SMP: Total of 2 processors activated.
[ 2.075000] CPU: All CPU(s) started in SVC mode.
[ 2.075000] devtmpfs: initialized
[ 2.080000] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[ 2.080000] pinctrl core: initialized pinctrl subsystem
[ 2.080000] regulator-dummy: no parameters
[ 2.080000] NET: Registered protocol family 16
[ 2.080000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 2.085000] S3C Power Management, Copyright 2004 Simtec Electronics
[ 2.085000] EXYNOS: PMU not supported
[ 2.085000] EXYNOS: Initializing architecture
[ 2.100000] bio: create slab <bio-0> at 0
[ 2.100000] SCSI subsystem initialized
[ 2.100000] usbcore: registered new interface driver usbfs
[ 2.100000] usbcore: registered new interface driver hub
[ 2.100000] usbcore: registered new device driver usb
[ 2.105000] Switched to clocksource mct-frc
[ 2.120000] NET: Registered protocol family 2
[ 2.120000] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 2.120000] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[ 2.120000] TCP: Hash tables configured (established 8192 bind 8192)
[ 2.120000] TCP: reno registered
[ 2.120000] UDP hash table entries: 512 (order: 2, 24576 bytes)
[ 2.120000] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[ 2.125000] NET: Registered protocol family 1
[ 2.125000] Trying to unpack rootfs image as initramfs...
[ 2.170000] Freeing initrd memory: 620K (c2001000 - c209c000)
[ 2.175000] bounce pool size: 64 pages
[ 2.185000] ROMFS MTD (C) 2007 Red Hat, Inc.
[ 2.185000] msgmni has been set to 1475
[ 2.185000] io scheduler noop registered
[ 2.185000] io scheduler deadline registered
[ 2.185000] io scheduler cfq registered (default)
[ 2.280000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.285000] 12c00000.serial: ttySAC0 at MMIO 0x12c00000 (irq = 83, base_baud = 0) is a S3C6400/10
[ 2.285000] 12c10000.serial: ttySAC1 at MMIO 0x12c10000 (irq = 84, base_baud = 0) is a S3C6400/10
[ 2.285000] 12c20000.serial: ttySAC2 at MMIO 0x12c20000 (irq = 85, base_baud = 0) is a S3C6400/10
[ 2.780000] console [ttySAC2] enabled
[ 2.785000] 12c30000.serial: ttySAC3 at MMIO 0x12c30000 (irq = 86, base_baud = 0) is a S3C6400/10
[ 2.805000] brd: module loaded
[ 2.810000] loop: module loaded
[ 2.810000] usbcore: registered new interface driver asix
[ 2.815000] usbcore: registered new interface driver ax88179_178a
[ 2.825000] usbcore: registered new interface driver cdc_ether
[ 2.830000] usbcore: registered new interface driver r815x
[ 2.835000] usbcore: registered new interface driver smsc75xx
[ 2.840000] usbcore: registered new interface driver smsc95xx
[ 2.845000] usbcore: registered new interface driver net1080
[ 2.850000] usbcore: registered new interface driver cdc_subset
[ 2.855000] usbcore: registered new interface driver zaurus
[ 2.865000] usbcore: registered new interface driver cdc_ncm
[ 2.870000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 2.875000] usbcore: registered new interface driver usb-storage
[ 2.880000] mousedev: PS/2 mouse device common for all mice
[ 2.890000] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel at redhat.com
[ 2.895000] sdhci: Secure Digital Host Controller Interface driver
[ 2.900000] sdhci: Copyright(c) Pierre Ossman
[ 2.905000] Synopsys Designware Multimedia Card Interface Driver
[ 2.910000] dwmmc_exynos dwmmc0.0: invalid resource
[ 2.915000] dwmmc_exynos: probe of dwmmc0.0 failed with error -22
[ 2.920000] dwmmc_exynos dwmmc1.1: invalid resource
[ 2.925000] dwmmc_exynos: probe of dwmmc1.1 failed with error -22
[ 2.935000] dwmmc_exynos dwmmc2.2: invalid resource
[ 2.940000] dwmmc_exynos: probe of dwmmc2.2 failed with error -22
[ 2.945000] dwmmc_exynos 12200000.mmc: dummy supplies not allowed
[ 2.950000] dwmmc_exynos 12200000.mmc: no vmmc regulator found: -19
[ 2.955000] dwmmc_exynos 12200000.mmc: Using internal DMA controller.
[ 2.965000] dwmmc_exynos 12200000.mmc: Version ID is 241a
[ 2.970000] dwmmc_exynos 12200000.mmc: DW MMC controller at irq 107, 64 bit host data width, 128 deep fifo
[ 2.980000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc at 12200000/slot at 0[0]'
[ 3.015000] dwmmc_exynos 12200000.mmc: 1 slots initialized
[ 3.015000] dwmmc_exynos 12220000.mmc: dummy supplies not allowed
[ 3.025000] dwmmc_exynos 12220000.mmc: no vmmc regulator found: -19
[ 3.030000] dwmmc_exynos 12220000.mmc: Using internal DMA controller.
[ 3.035000] dwmmc_exynos 12220000.mmc: Version ID is 241a
[ 3.040000] dwmmc_exynos 12220000.mmc: DW MMC controller at irq 109, 64 bit host data width, 128 deep fifo
[ 3.050000] of_get_named_gpiod_flags: can't parse gpios property of node '/mmc at 12220000/slot at 0[0]'
[ 3.090000] dwmmc_exynos 12220000.mmc: 1 slots initialized
[ 3.095000] usbcore: registered new interface driver usbhid
[ 3.100000] usbhid: USB HID core driver
[ 3.100000] TCP: cubic registered
[ 3.105000] NET: Registered protocol family 17
[ 3.110000] NET: Registered protocol family 15
[ 3.115000] Registering SWP/SWPB emulation handler
[ 3.120000] /work/kernel/linaro/dev/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 3.130000] Freeing unused kernel memory: 224K (c04ac000 - c04e4000)
Starting logging: [ 3.155000] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
[ 3.165000] mmc1: new high speed SDHC card at address e624
OK
Initializing rand[ 3.170000] isa bounce pool size: 16 pages
om number gene[ 3.180000] mmcblk0: mmc1:e624 SU08G 7.40 GiB
rator... [ 3.185000] mmcblk0: p1 p2
[ 3.185000] random: dd urandom read with 13 bits of entropy available
done.
Starting network...
mount: mounting none on /sys/kernel/debug failed: No such file or directory
/bin/sh: can't access tty; job control turned off
/ # cat /proc/cmdline
cat /proc/cmdline
console=ttySAC2,115200n8 debug earlyprintk
/ # uname -r
uname -r
3.13.0-rc3-linaro-00004-g0a685036323f
/ # cat /proc/cpuinfo
cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 3 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc0f
CPU revision : 3
processor : 1
model name : ARMv7 Processor rev 3 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc0f
CPU revision : 3
Hardware : SAMSUNG EXYNOS5 (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
/ # ip -f inet -o addr
ip -f inet -o addr
1: lo inet 127.0.0.1/8 scope host lo\ valid_lft forever preferred_lft forever
/ # # PYBOOT: Time: 22.81 seconds.
# PYBOOT: Result: PASS
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
2013-12-10 16:40 ` Kevin Hilman
(?)
@ 2013-12-11 9:56 ` Tarek Dakhran
-1 siblings, 0 replies; 18+ messages in thread
From: Tarek Dakhran @ 2013-12-11 9:56 UTC (permalink / raw)
To: Kevin Hilman, Vyacheslav Tyrtov
Cc: linux-kernel, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Kukjin Kim,
Russell King, Ben Dooks, Mike Turquette, Daniel Lezcano,
Thomas Gleixner, Heiko Stuebner, Naour Romain, devicetree,
linux-doc, linux-arm-kernel, linux-samsung-soc, Dave.Martin,
nicolas.pitre, tomasz.figa
On 12/10/2013 08:40 PM, Kevin Hilman wrote:
> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>
>> The series of patches represent support of Exynos 5410 SoC
>>
>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>
>> Patches add new platform description, support of clock controller and device
>> tree for Exynos 5410.
>>
>> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
>> This patches is activating only the big cluster (all A15 cores)
> Testing this series on top of v3.13-rc3, plus a couple of other
> necessary changes (which should've probably been noted in the changelog):
>
> 1) change CONFIG_NR_CPUS=8 in .config
> 2) add the exynos combiner patch from Chander:
> [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
>
> I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
>
> [ 0.045000] CPU: Testing write buffer coherency: ok
> [ 0.045000] CPU0: update cpu_power 1024
> [ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
> [ 0.045000] CPU1: Booted secondary processor
> [ 0.065000] CPU1: update cpu_power 1024
> [ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 1.075000] CPU2: failed to boot: -38
> [ 2.075000] CPU3: failed to boot: -38
> [ 2.075000] Brought up 2 CPUs
> [ 2.075000] SMP: Total of 2 processors activated.
> [ 2.075000] CPU: All CPU(s) started in SVC mode.
>
Hi Kevin,
EDCS(exynos dual cluster support) moved to separate patch now.
This patches introduce only base SoC support (2xA15).
Patches tested on samsung smdk5410 board.
Next version of EDCS patches will be available soon.
They allow power on and boot all 8 cores.
Best regards,
Tarek Dakhran.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-11 9:56 ` Tarek Dakhran
0 siblings, 0 replies; 18+ messages in thread
From: Tarek Dakhran @ 2013-12-11 9:56 UTC (permalink / raw)
To: Kevin Hilman, Vyacheslav Tyrtov
Cc: Mark Rutland, nicolas.pitre, Daniel Lezcano, Heiko Stuebner,
linux-doc, tomasz.figa, Naour Romain, Kukjin Kim, Russell King,
Stephen Warren, Dave.Martin, devicetree, Pawel Moll,
Ian Campbell, Rob Herring, linux-samsung-soc, Ben Dooks,
Mike Turquette, Thomas Gleixner, linux-arm-kernel, linux-kernel,
Rob Landley
On 12/10/2013 08:40 PM, Kevin Hilman wrote:
> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>
>> The series of patches represent support of Exynos 5410 SoC
>>
>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>
>> Patches add new platform description, support of clock controller and device
>> tree for Exynos 5410.
>>
>> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
>> This patches is activating only the big cluster (all A15 cores)
> Testing this series on top of v3.13-rc3, plus a couple of other
> necessary changes (which should've probably been noted in the changelog):
>
> 1) change CONFIG_NR_CPUS=8 in .config
> 2) add the exynos combiner patch from Chander:
> [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
>
> I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
>
> [ 0.045000] CPU: Testing write buffer coherency: ok
> [ 0.045000] CPU0: update cpu_power 1024
> [ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
> [ 0.045000] CPU1: Booted secondary processor
> [ 0.065000] CPU1: update cpu_power 1024
> [ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 1.075000] CPU2: failed to boot: -38
> [ 2.075000] CPU3: failed to boot: -38
> [ 2.075000] Brought up 2 CPUs
> [ 2.075000] SMP: Total of 2 processors activated.
> [ 2.075000] CPU: All CPU(s) started in SVC mode.
>
Hi Kevin,
EDCS(exynos dual cluster support) moved to separate patch now.
This patches introduce only base SoC support (2xA15).
Patches tested on samsung smdk5410 board.
Next version of EDCS patches will be available soon.
They allow power on and boot all 8 cores.
Best regards,
Tarek Dakhran.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-11 9:56 ` Tarek Dakhran
0 siblings, 0 replies; 18+ messages in thread
From: Tarek Dakhran @ 2013-12-11 9:56 UTC (permalink / raw)
To: linux-arm-kernel
On 12/10/2013 08:40 PM, Kevin Hilman wrote:
> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>
>> The series of patches represent support of Exynos 5410 SoC
>>
>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>
>> Patches add new platform description, support of clock controller and device
>> tree for Exynos 5410.
>>
>> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
>> This patches is activating only the big cluster (all A15 cores)
> Testing this series on top of v3.13-rc3, plus a couple of other
> necessary changes (which should've probably been noted in the changelog):
>
> 1) change CONFIG_NR_CPUS=8 in .config
> 2) add the exynos combiner patch from Chander:
> [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
>
> I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
>
> [ 0.045000] CPU: Testing write buffer coherency: ok
> [ 0.045000] CPU0: update cpu_power 1024
> [ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
> [ 0.045000] CPU1: Booted secondary processor
> [ 0.065000] CPU1: update cpu_power 1024
> [ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 1.075000] CPU2: failed to boot: -38
> [ 2.075000] CPU3: failed to boot: -38
> [ 2.075000] Brought up 2 CPUs
> [ 2.075000] SMP: Total of 2 processors activated.
> [ 2.075000] CPU: All CPU(s) started in SVC mode.
>
Hi Kevin,
EDCS(exynos dual cluster support) moved to separate patch now.
This patches introduce only base SoC support (2xA15).
Patches tested on samsung smdk5410 board.
Next version of EDCS patches will be available soon.
They allow power on and boot all 8 cores.
Best regards,
Tarek Dakhran.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
2013-12-10 14:26 ` Vyacheslav Tyrtov
@ 2013-12-11 22:29 ` Kukjin Kim
-1 siblings, 0 replies; 18+ messages in thread
From: Kukjin Kim @ 2013-12-11 22:29 UTC (permalink / raw)
To: Vyacheslav Tyrtov
Cc: linux-kernel, Mark Rutland, nicolas.pitre, Daniel Lezcano,
Heiko Stuebner, linux-doc, tomasz.figa, Naour Romain,
Tarek Dakhran, Kukjin Kim, Russell King, Stephen Warren,
Dave.Martin, devicetree, Pawel Moll, Ian Campbell, Rob Herring,
linux-samsung-soc, Ben Dooks, Mike Turquette, Thomas Gleixner,
linux-arm-kernel, Rob Landley
On 12/10/13 23:26, Vyacheslav Tyrtov wrote:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
>
> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
> This patches is activating only the big cluster (all A15 cores)
>
> EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15)
> to run at the same time, will be released separately
>
> Has been build on v3.13-rc3
> Has been tested on Exynos 5410 reference board (exynos_defconfig)
>
> Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre.
> I hope, this is enough clean and hasn't any dependencies to go through
> Samsung tree. Kukjin, what do you think about it?
>
OK, looks good and I've applied.
Thanks,
Kukjin
> Vyacheslav.
>
>
> Changelog:
>
> v5:
> EDCS removed to separate patch.
>
> In arch/arm/mach-exynos/Kconfig
> 1. Removed select ARM_CCI and MCPM.
> In arch/arm/mach-exynos/platsmp.c
> 1. Added correct boot_reg for exynos5410.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. Removed cortex-a7 cpu nodes and cci node.
>
> v4:
> In arch/arm/mach-exynos/edcs.c
> 1. Renamed all exynos_ prefixes to edcs_.
> 2. Reworked edcs_core_power_up/down functions.
> 3. Removed exynos_core_power_control function.
> 4. Added this_core_to_pcpu function.
> 5. Added core_power_state function which detects if cpu is being reset.
> 6. Replaced cache flush sequences with v7_exit_coherency_flush().
> 7. exynos_core_power_down moved to lock protected area.
> 8. edcs_power_down_finish implemented.
> In Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> 1. External clocks documented.
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. oscclk node corrected according to ePAPR recommendation.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. mct@101C0000 node renamed to timer@101C0000.
> 2. "interrupt-controller" line removed from mct node.
> 3. mct_map renamed to interrupt_map.
> In arch/arm/mach-exynos/Kconfig
> 1. some cosmetic corrections.
> In include/dt-bindings/clock/exynos5410.h
> 1. Unnecessary defines removed.
>
> v3:
> In drivers/clk/samsung/clk-exynos5410.c
> 1. Fixed rate clock "samsung,clock-oscclk" removed.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk.
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. Fixed rate oscclk clock added.
> In arch/arm/mach-exynos/edcs.c
> 1. Added write memory barrier in exynos_core_power_control function.
> 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed.
> 3. #define added for some magic constants.
> 4. Disabled the GIC CPU interface in exynos_power_down function.
>
> v2:
> In drivers/clk/samsung/clk-exynos5410.c
> 1. Clock driver converted to use preprocessor macros instead of enums.
> Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
> 2. Unused spinlock removed.
> 3. Function exynos5410_clk_init defined as static.
> Struct exynos5410_fixed_rate_ext_clks defined as static.
> Struct exynos5410_mux_clks defined as static.
> Struct exynos5410_div_clks defined as static.
> Struct exynos5410_gate_clks defined as static.
> 4. Removed aliases.
> 5. Pll's magic register offsets defined as preprocessor macros.
> 6. Redundant check of device_node pointer removed.
>
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. dwmmcX nodes renamed to mmc.
> dwmmc_X renamed to mmc_X.
> dwmmc status="disabled" field added.
> fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
> 2. Blank lines added where necessary.
> 3. cpu@ suffixes corrected.
> 4. edcs node removed.
> 5. Hexadecimal characters case corrected.
> 6. Clock IDs replaced with preprocessor macros.
>
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. status = "okay" field added to mmc nodes.
>
> In arch/arm/mach-exynos/edcs.c
> 1. "kfs_" prefix replaced with "edcs_"
> 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
> 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
> 4. mcpm_sync_init() call added.
> 5. power management functions reworked.
>
> Other
> 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
> 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
> ARM_CCI in arch/arm/mach-exynos/Kconfig.
> 3. edcs_status driver removed.
>
> Tarek Dakhran (3):
> ARM: EXYNOS: Add support for EXYNOS5410 SoC
> clk: exynos5410: register clocks using common clock framework
> ARM: dts: Add initial device tree support for EXYNOS5410
>
> .../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++
> arch/arm/boot/dts/exynos5410.dtsi | 145 +++++++++++++
> arch/arm/mach-exynos/Kconfig | 10 +
> arch/arm/mach-exynos/common.c | 18 ++
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
> arch/arm/mach-exynos/platsmp.c | 2 +
> arch/arm/plat-samsung/include/plat/cpu.h | 8 +
> arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5410.h | 32 +++
> 14 files changed, 587 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
> create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-11 22:29 ` Kukjin Kim
0 siblings, 0 replies; 18+ messages in thread
From: Kukjin Kim @ 2013-12-11 22:29 UTC (permalink / raw)
To: linux-arm-kernel
On 12/10/13 23:26, Vyacheslav Tyrtov wrote:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
>
> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
> This patches is activating only the big cluster (all A15 cores)
>
> EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15)
> to run at the same time, will be released separately
>
> Has been build on v3.13-rc3
> Has been tested on Exynos 5410 reference board (exynos_defconfig)
>
> Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre.
> I hope, this is enough clean and hasn't any dependencies to go through
> Samsung tree. Kukjin, what do you think about it?
>
OK, looks good and I've applied.
Thanks,
Kukjin
> Vyacheslav.
>
>
> Changelog:
>
> v5:
> EDCS removed to separate patch.
>
> In arch/arm/mach-exynos/Kconfig
> 1. Removed select ARM_CCI and MCPM.
> In arch/arm/mach-exynos/platsmp.c
> 1. Added correct boot_reg for exynos5410.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. Removed cortex-a7 cpu nodes and cci node.
>
> v4:
> In arch/arm/mach-exynos/edcs.c
> 1. Renamed all exynos_ prefixes to edcs_.
> 2. Reworked edcs_core_power_up/down functions.
> 3. Removed exynos_core_power_control function.
> 4. Added this_core_to_pcpu function.
> 5. Added core_power_state function which detects if cpu is being reset.
> 6. Replaced cache flush sequences with v7_exit_coherency_flush().
> 7. exynos_core_power_down moved to lock protected area.
> 8. edcs_power_down_finish implemented.
> In Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> 1. External clocks documented.
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. oscclk node corrected according to ePAPR recommendation.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. mct at 101C0000 node renamed to timer at 101C0000.
> 2. "interrupt-controller" line removed from mct node.
> 3. mct_map renamed to interrupt_map.
> In arch/arm/mach-exynos/Kconfig
> 1. some cosmetic corrections.
> In include/dt-bindings/clock/exynos5410.h
> 1. Unnecessary defines removed.
>
> v3:
> In drivers/clk/samsung/clk-exynos5410.c
> 1. Fixed rate clock "samsung,clock-oscclk" removed.
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk.
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. Fixed rate oscclk clock added.
> In arch/arm/mach-exynos/edcs.c
> 1. Added write memory barrier in exynos_core_power_control function.
> 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed.
> 3. #define added for some magic constants.
> 4. Disabled the GIC CPU interface in exynos_power_down function.
>
> v2:
> In drivers/clk/samsung/clk-exynos5410.c
> 1. Clock driver converted to use preprocessor macros instead of enums.
> Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
> 2. Unused spinlock removed.
> 3. Function exynos5410_clk_init defined as static.
> Struct exynos5410_fixed_rate_ext_clks defined as static.
> Struct exynos5410_mux_clks defined as static.
> Struct exynos5410_div_clks defined as static.
> Struct exynos5410_gate_clks defined as static.
> 4. Removed aliases.
> 5. Pll's magic register offsets defined as preprocessor macros.
> 6. Redundant check of device_node pointer removed.
>
> In arch/arm/boot/dts/exynos5410.dtsi
> 1. dwmmcX nodes renamed to mmc.
> dwmmc_X renamed to mmc_X.
> dwmmc status="disabled" field added.
> fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
> 2. Blank lines added where necessary.
> 3. cpu@ suffixes corrected.
> 4. edcs node removed.
> 5. Hexadecimal characters case corrected.
> 6. Clock IDs replaced with preprocessor macros.
>
> In arch/arm/boot/dts/exynos5410-smdk5410.dts
> 1. status = "okay" field added to mmc nodes.
>
> In arch/arm/mach-exynos/edcs.c
> 1. "kfs_" prefix replaced with "edcs_"
> 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
> 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
> 4. mcpm_sync_init() call added.
> 5. power management functions reworked.
>
> Other
> 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
> 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
> ARM_CCI in arch/arm/mach-exynos/Kconfig.
> 3. edcs_status driver removed.
>
> Tarek Dakhran (3):
> ARM: EXYNOS: Add support for EXYNOS5410 SoC
> clk: exynos5410: register clocks using common clock framework
> ARM: dts: Add initial device tree support for EXYNOS5410
>
> .../devicetree/bindings/clock/exynos5410-clock.txt | 54 +++++
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++++++
> arch/arm/boot/dts/exynos5410.dtsi | 145 +++++++++++++
> arch/arm/mach-exynos/Kconfig | 10 +
> arch/arm/mach-exynos/common.c | 18 ++
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
> arch/arm/mach-exynos/platsmp.c | 2 +
> arch/arm/plat-samsung/include/plat/cpu.h | 8 +
> arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 239 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5410.h | 32 +++
> 14 files changed, 587 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
> create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v5 0/3] Exynos 5410 support
2013-12-11 9:56 ` Tarek Dakhran
@ 2013-12-13 0:32 ` Kevin Hilman
-1 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2013-12-13 0:32 UTC (permalink / raw)
To: Tarek Dakhran
Cc: Vyacheslav Tyrtov, linux-kernel, Rob Herring, Pawel Moll,
Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley,
Kukjin Kim, Russell King, Ben Dooks, Mike Turquette,
Daniel Lezcano, Thomas Gleixner, Heiko Stuebner, Naour Romain,
devicetree, linux-doc, linux-arm-kernel, linux-samsung-soc,
Dave.Martin, nicolas.pitre, tomasz.figa
Tarek Dakhran <t.dakhran@samsung.com> writes:
> On 12/10/2013 08:40 PM, Kevin Hilman wrote:
>> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>>
>>> The series of patches represent support of Exynos 5410 SoC
>>>
>>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>>
>>> Patches add new platform description, support of clock controller and device
>>> tree for Exynos 5410.
>>>
>>> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
>>> This patches is activating only the big cluster (all A15 cores)
>> Testing this series on top of v3.13-rc3, plus a couple of other
>> necessary changes (which should've probably been noted in the changelog):
>>
>> 1) change CONFIG_NR_CPUS=8 in .config
>> 2) add the exynos combiner patch from Chander:
>> [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
>>
>> I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
>>
>> [ 0.045000] CPU: Testing write buffer coherency: ok
>> [ 0.045000] CPU0: update cpu_power 1024
>> [ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
>> [ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
>> [ 0.045000] CPU1: Booted secondary processor
>> [ 0.065000] CPU1: update cpu_power 1024
>> [ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
>> [ 1.075000] CPU2: failed to boot: -38
>> [ 2.075000] CPU3: failed to boot: -38
>> [ 2.075000] Brought up 2 CPUs
>> [ 2.075000] SMP: Total of 2 processors activated.
>> [ 2.075000] CPU: All CPU(s) started in SVC mode.
>>
> Hi Kevin,
>
> EDCS(exynos dual cluster support) moved to separate patch now.
> This patches introduce only base SoC support (2xA15).
Thanks for the clarification
I thought there were 4 A15s, and the changelog mentioned this patch
enabled "all A15s".
Kevin
> Patches tested on samsung smdk5410 board.
>
> Next version of EDCS patches will be available soon.
> They allow power on and boot all 8 cores.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 0/3] Exynos 5410 support
@ 2013-12-13 0:32 ` Kevin Hilman
0 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2013-12-13 0:32 UTC (permalink / raw)
To: linux-arm-kernel
Tarek Dakhran <t.dakhran@samsung.com> writes:
> On 12/10/2013 08:40 PM, Kevin Hilman wrote:
>> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>>
>>> The series of patches represent support of Exynos 5410 SoC
>>>
>>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
>>>
>>> Patches add new platform description, support of clock controller and device
>>> tree for Exynos 5410.
>>>
>>> Dual cluster support for Exynos 5410 (EDCS) has been removed from this series
>>> This patches is activating only the big cluster (all A15 cores)
>> Testing this series on top of v3.13-rc3, plus a couple of other
>> necessary changes (which should've probably been noted in the changelog):
>>
>> 1) change CONFIG_NR_CPUS=8 in .config
>> 2) add the exynos combiner patch from Chander:
>> [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value
>>
>> I'm still only seeing 2 out of 4 cores come up on my odroid-xu:
>>
>> [ 0.045000] CPU: Testing write buffer coherency: ok
>> [ 0.045000] CPU0: update cpu_power 1024
>> [ 0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
>> [ 0.045000] Setting up static identity map for 0x403717d8 - 0x40371830
>> [ 0.045000] CPU1: Booted secondary processor
>> [ 0.065000] CPU1: update cpu_power 1024
>> [ 0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
>> [ 1.075000] CPU2: failed to boot: -38
>> [ 2.075000] CPU3: failed to boot: -38
>> [ 2.075000] Brought up 2 CPUs
>> [ 2.075000] SMP: Total of 2 processors activated.
>> [ 2.075000] CPU: All CPU(s) started in SVC mode.
>>
> Hi Kevin,
>
> EDCS(exynos dual cluster support) moved to separate patch now.
> This patches introduce only base SoC support (2xA15).
Thanks for the clarification
I thought there were 4 A15s, and the changelog mentioned this patch
enabled "all A15s".
Kevin
> Patches tested on samsung smdk5410 board.
>
> Next version of EDCS patches will be available soon.
> They allow power on and boot all 8 cores.
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2013-12-13 0:32 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-10 14:26 [PATCH v5 0/3] Exynos 5410 support Vyacheslav Tyrtov
2013-12-10 14:26 ` Vyacheslav Tyrtov
2013-12-10 14:26 ` [PATCH v5 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
2013-12-10 14:26 ` Vyacheslav Tyrtov
2013-12-10 14:26 ` [PATCH v5 2/3] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
2013-12-10 14:26 ` Vyacheslav Tyrtov
2013-12-10 14:26 ` [PATCH v5 3/3] ARM: dts: Add initial device tree support for EXYNOS5410 Vyacheslav Tyrtov
2013-12-10 14:26 ` Vyacheslav Tyrtov
2013-12-10 16:40 ` [PATCH v5 0/3] Exynos 5410 support Kevin Hilman
2013-12-10 16:40 ` Kevin Hilman
2013-12-10 16:40 ` Kevin Hilman
2013-12-11 9:56 ` Tarek Dakhran
2013-12-11 9:56 ` Tarek Dakhran
2013-12-11 9:56 ` Tarek Dakhran
2013-12-13 0:32 ` Kevin Hilman
2013-12-13 0:32 ` Kevin Hilman
2013-12-11 22:29 ` Kukjin Kim
2013-12-11 22:29 ` Kukjin Kim
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