* [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8
@ 2013-12-09 15:46 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
` (17 more replies)
0 siblings, 18 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The QEMU emulation models for Power7 and Power8 are still missing some
of the base instructions that were introduced in Power ISA 2.06 and
even a few that were introduced prior to that.
This patch series gets these models caught up with respect to the
base 2.06 ISA. That is, the Book I and Book II instructions for
the branch, fixed point and floating point units will be completed
with this series. Decimal floating point is not addressed in this
series, nor are the base ISA 2.07 changes for the Power8 model.
In some cases, existing instructions are re-implemented using common
macros, thus eliminating some redundant code. The patch series
eliminates almost half as much code as it adds.
Additionally, some bugs in the common floating point library (softfloat)
are fixed.
Tom Musta (18):
target-ppc: Add Flag for Power ISA V2.06
target-ppc: Add ISA2.06 bpermd Instruction
target-ppc: Add ISA2.06 divdeu[o] Instructions
target-ppc: Add ISA2.06 divde[o] Instructions
target-ppc: Add ISA 2.06 divwe[u][o] Instructions
target-ppc: Add ISA2.06 lbarx, lharx Instructions
target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
target-ppc: Add ISA2.06 Float to Integer Instructions
softfloat: Fix Handling of Small Negatives in float64_to_uint64
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Fix float64_to_uint32
softfloat: Fix float64_to_uint32_round_to_zero
target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
target-ppc: Fix and enable fri[mnpz]
target-ppc: Add ISA 2.06 ftdiv Instruction
target-ppc: Add ISA 2.06 ftsqrt
target-ppc: Enable frsqrtes on Power7 and Power8
target-ppc: Add ISA2.06 lfiwzx Instruction
fpu/softfloat.c | 73 +++++------
target-ppc/cpu.h | 4 +-
target-ppc/fpu_helper.c | 248 ++++++++++++++++++---------------
target-ppc/helper.h | 13 ++
target-ppc/int_helper.c | 111 +++++++++++++++
target-ppc/translate.c | 318 +++++++++++++++++++++++++++++++++----------
target-ppc/translate_init.c | 10 +-
7 files changed, 547 insertions(+), 230 deletions(-)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
@ 2013-12-09 15:46 ` Tom Musta
2013-12-18 22:02 ` Scott Wood
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
` (16 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds a flag for base instruction additions to Power ISA
2.06B. The flag will be used to identify/select basic Book I and
Book II instructions that were newly added in that revision of the
architecture. The flag will not be used for VSX or Altivec.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/cpu.h | 4 +++-
target-ppc/translate_init.c | 6 ++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0abc848..fe3aace 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1877,9 +1877,11 @@ enum {
PPC2_ISA205 = 0x0000000000000020ULL,
/* VSX additions in ISA 2.07 */
PPC2_VSX207 = 0x0000000000000040ULL,
+ /* Book I 2.06B PowerPC specification (base instructions) */
+ PPC2_ISA206 = 0x0000000000000080ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
- PPC2_ISA205 | PPC2_VSX207)
+ PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e14ab63..491e56c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
+ PPC2_ISA206;
pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_ISA206;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
@ 2013-12-09 15:46 ` Tom Musta
2013-12-10 0:01 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
` (15 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 20 ++++++++++++++++++++
target-ppc/translate.c | 10 ++++++++++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6250eba..1ec9c65 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_3(bpermd, i64, env, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
#endif
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index e50bdd2..c140a0d 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t)
}
#endif
+#if defined(TARGET_PPC64)
+
+uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb)
+{
+ int i;
+ uint64_t ra = 0;
+
+ for (i = 0; i < 8; i++) {
+ int index = (rs & (0xFFul) << (i*8)) >> (i*8);
+ if (index < 64) {
+ if (rb & (1ul << (63-index))) {
+ ra |= (1<<i);
+ }
+ }
+ }
+ return ra;
+}
+
+#endif
+
target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
{
target_ulong mask = 0xff;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1f7e499..0d39de2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1525,6 +1525,15 @@ static void gen_prtyd(DisasContext *ctx)
#endif
#if defined(TARGET_PPC64)
+/* bpermd */
+static void gen_bpermd(DisasContext *ctx)
+{
+ gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], cpu_env,
+ cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+}
+#endif
+
+#if defined(TARGET_PPC64)
/* extsw & extsw. */
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -9322,6 +9331,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_ISA206),
#endif
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-10 0:05 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
` (14 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used, providing a
repeated difference algorithm.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 20 ++++++++++++++++++++
3 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1ec9c65..3eff4df 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -31,6 +31,7 @@ DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_3(mulldo, i64, env, i64, i64)
+DEF_HELPER_4(divdeu, i64, env, i64, i64, i32)
#endif
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index c140a0d..94a54d2 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -41,6 +41,53 @@ uint64_t helper_mulldo(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
}
#endif
+#if defined(TARGET_PPC64)
+
+static void _divide_u64_extended(uint64_t ra, uint64_t rb, uint64_t *quotient, int *overflow)
+{
+ int i;
+ uint64_t carry = 0;
+
+ *quotient = 0;
+ *overflow = 0;
+
+ if ((ra >= rb) || (rb == 0)) {
+ *overflow = 1;
+ return;
+ }
+
+ for (i = 0; i <= 64; i++) {
+ *quotient = (*quotient) << 1;
+ if ((rb <= ra) || carry) {
+ *quotient |= 1;
+ ra -= rb;
+ }
+ carry = ra & 0x8000000000000000ul;
+ ra <<= 1;
+ }
+}
+
+uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe)
+{
+ uint64_t rt = 0;
+ int overflow = 0;
+
+ _divide_u64_extended(ra, rb, &rt, &overflow);
+
+ if (oe) {
+ if (unlikely(overflow)) {
+ env->so = env->ov = 1;
+ } else {
+ env->ov = 0;
+ }
+ }
+
+ return rt;
+}
+
+#endif
+
+
target_ulong helper_cntlzw(target_ulong t)
{
return clz32(t);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0d39de2..7a51c6d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1032,6 +1032,23 @@ GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
/* divw divw. divwo divwo. */
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
+
+/* divdeu[o][.] */
+#define GEN_DIVDE(name, hlpr, compute_ov) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0 = tcg_const_i32(compute_ov); \
+ gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
+ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
+ tcg_temp_free_i32(t0); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
+ } \
+}
+
+GEN_DIVDE(divdeu, divdeu, 0);
+GEN_DIVDE(divdeuo, divdeu, 1);
+
#endif
/* mulhw mulhw. */
@@ -9594,6 +9611,9 @@ GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
+GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206),
+
#undef GEN_INT_ARITH_MUL_HELPER
#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (2 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
` (13 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 4 ++++
3 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3eff4df..4359009 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -32,6 +32,7 @@ DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_3(mulldo, i64, env, i64, i64)
DEF_HELPER_4(divdeu, i64, env, i64, i64, i32)
+DEF_HELPER_4(divde, i64, env, i64, i64, i32)
#endif
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 94a54d2..bd41d4b 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -85,6 +85,50 @@ uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe)
return rt;
}
+uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32_t oe)
+{
+ int64_t rt = 0;
+ int64_t ra = (int64_t)rau;
+ int64_t rb = (int64_t)rbu;
+ int overflow = 0;
+
+ int sgna = (ra < 0) ? 1 : 0;
+ int sgnb = (rb < 0) ? 1 : 0;
+
+ if (sgna) {
+ ra = 0 - ra;
+ }
+
+ if (sgnb) {
+ rb = 0 - rb;
+ }
+
+ _divide_u64_extended(ra, rb, (uint64_t *)&rt, &overflow);
+
+ if (sgna ^ sgnb) {
+ rt = 0 - rt;
+ }
+
+ if (oe) {
+
+ if (overflow == 0) {
+ int sgnt = (rt < 0) ? 1 : 0;
+ if (sgnt ^ (sgna ^ sgnb)) {
+ overflow = 1;
+ rt = 0; /* undefined */
+ }
+ }
+
+ if (unlikely(overflow)) {
+ env->so = env->ov = 1;
+ } else {
+ env->ov = 0;
+ }
+ }
+
+ return rt;
+}
+
#endif
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7a51c6d..b274a15 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1048,6 +1048,8 @@ static void gen_##name(DisasContext *ctx) \
GEN_DIVDE(divdeu, divdeu, 0);
GEN_DIVDE(divdeuo, divdeu, 1);
+GEN_DIVDE(divde, divde, 0);
+GEN_DIVDE(divdeo, divde, 1);
#endif
@@ -9613,6 +9615,8 @@ GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
#undef GEN_INT_ARITH_MUL_HELPER
#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (3 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-10 0:26 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
` (12 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b274a15..afab0cf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -984,6 +984,76 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
/* divw divw. divwo divwo. */
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
+
+#define GEN_DIVWE(op, signed, compute_ov) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ /* Need to use local temps because of the branches */ \
+ TCGv ra = tcg_temp_local_new(); \
+ TCGv rb = tcg_temp_local_new(); \
+ int lbl_ov = gen_new_label(); \
+ int lbl_rc = gen_new_label(); \
+ \
+ \
+ if (signed) { \
+ /* divide by zero ? */ \
+ tcg_gen_ext32s_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ /* check for MIN div -1 */ \
+ int l3 = gen_new_label(); \
+ tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
+ gen_set_label(l3); \
+ tcg_gen_div_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ /* does the result fit in 32 bits? */ \
+ tcg_gen_brcondi_i64(TCG_COND_LT, cpu_gpr[rD(ctx->opcode)], INT32_MIN, \
+ lbl_ov); \
+ tcg_gen_brcondi_i64(TCG_COND_GT, cpu_gpr[rD(ctx->opcode)], INT32_MAX, \
+ lbl_ov); \
+ } else { /* unsigned */ \
+ /* divide by zero ? */ \
+ tcg_gen_ext32u_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ /* is ra[32:63] > rb[32:63] ? */ \
+ tcg_gen_ext32u_i64(ra, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_brcond_i64(TCG_COND_GTU, ra, rb, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ tcg_gen_divu_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ } \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 0); \
+ } \
+ tcg_gen_br(lbl_rc); \
+ \
+ gen_set_label(lbl_ov); /* overflow handling */ \
+ \
+ if (signed) { \
+ tcg_gen_sari_i64(cpu_gpr[rD(ctx->opcode)], ra, 63); \
+ } else { \
+ tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
+ } \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 1); \
+ tcg_gen_movi_tl(cpu_so, 1); \
+ } \
+ \
+ gen_set_label(lbl_rc); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
+ } \
+ \
+ tcg_temp_free(ra); \
+ tcg_temp_free(rb); \
+}
+
+GEN_DIVWE(divweu, 0, 0);
+GEN_DIVWE(divweuo, 0, 1);
+GEN_DIVWE(divwe, 1, 0);
+GEN_DIVWE(divweo, 1, 1);
+
#if defined(TARGET_PPC64)
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -9603,6 +9673,10 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
+GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206),
#if defined(TARGET_PPC64)
#undef GEN_INT_ARITH_DIVD
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (4 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-10 0:31 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
` (11 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the byte and halfword variations of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a common macro is provided and the
existing implementations of lwarx and ldarx are re-implemented using
this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 50 +++++++++++++++++++++++------------------------
1 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index afab0cf..23b82f9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3222,21 +3222,29 @@ static void gen_isync(DisasContext *ctx)
gen_stop_exception(ctx);
}
-/* lwarx */
-static void gen_lwarx(DisasContext *ctx)
-{
- TCGv t0;
- TCGv gpr = cpu_gpr[rD(ctx->opcode)];
- gen_set_access_type(ctx, ACCESS_RES);
- t0 = tcg_temp_local_new();
- gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x03);
- gen_qemu_ld32u(ctx, gpr, t0);
- tcg_gen_mov_tl(cpu_reserve, t0);
- tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
- tcg_temp_free(t0);
+#define LARX(name, len, loadop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv t0; \
+ TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
+ gen_set_access_type(ctx, ACCESS_RES); \
+ t0 = tcg_temp_local_new(); \
+ gen_addr_reg_index(ctx, t0); \
+ if ((len) > 1) { \
+ gen_check_align(ctx, t0, (len)-1); \
+ } \
+ gen_qemu_##loadop(ctx, gpr, t0); \
+ tcg_gen_mov_tl(cpu_reserve, t0); \
+ tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
+ tcg_temp_free(t0); \
}
+/* lwarx */
+LARX(lbarx, 1, ld8u);
+LARX(lharx, 1, ld16u);
+LARX(lwarx, 4, ld32u);
+
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store (DisasContext *ctx, TCGv EA,
int reg, int size)
@@ -3283,19 +3291,7 @@ static void gen_stwcx_(DisasContext *ctx)
#if defined(TARGET_PPC64)
/* ldarx */
-static void gen_ldarx(DisasContext *ctx)
-{
- TCGv t0;
- TCGv gpr = cpu_gpr[rD(ctx->opcode)];
- gen_set_access_type(ctx, ACCESS_RES);
- t0 = tcg_temp_local_new();
- gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x07);
- gen_qemu_ld64(ctx, gpr, t0);
- tcg_gen_mov_tl(cpu_reserve, t0);
- tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
- tcg_temp_free(t0);
-}
+LARX(ldarx, 8, ld64);
/* stdcx. */
static void gen_stdcx_(DisasContext *ctx)
@@ -9465,6 +9461,8 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
+GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (5 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-10 0:41 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
` (10 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are re-implemented using this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 93 ++++++++++++++++++++++-------------------------
1 files changed, 44 insertions(+), 49 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 23b82f9..29c5dc1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3246,7 +3246,7 @@ LARX(lwarx, 4, ld32u);
#if defined(CONFIG_USER_ONLY)
-static void gen_conditional_store (DisasContext *ctx, TCGv EA,
+static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int size)
{
TCGv t0 = tcg_temp_new();
@@ -3261,62 +3261,55 @@ static void gen_conditional_store (DisasContext *ctx, TCGv EA,
gen_exception(ctx, POWERPC_EXCP_STCX);
ctx->exception = save_exception;
}
-#endif
-
-/* stwcx. */
-static void gen_stwcx_(DisasContext *ctx)
-{
- TCGv t0;
- gen_set_access_type(ctx, ACCESS_RES);
- t0 = tcg_temp_local_new();
- gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x03);
-#if defined(CONFIG_USER_ONLY)
- gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
-#else
- {
- int l1;
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
- gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_reserve, -1);
- }
-#endif
- tcg_temp_free(t0);
+#define STCX(name, len, storeop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv t0; \
+ gen_set_access_type(ctx, ACCESS_RES); \
+ t0 = tcg_temp_local_new(); \
+ gen_addr_reg_index(ctx, t0); \
+ if ((len) > 1) { \
+ gen_check_align(ctx, t0, (len)-1); \
+ } \
+ gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
+ tcg_temp_free(t0); \
}
+#else
+#define STCX(name, len, storeop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv t0; \
+ gen_set_access_type(ctx, ACCESS_RES); \
+ t0 = tcg_temp_local_new(); \
+ gen_addr_reg_index(ctx, t0); \
+ gen_check_align(ctx, t0, (len)-1); \
+ { \
+ int l1; \
+ \
+ tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); \
+ l1 = gen_new_label(); \
+ tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); \
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); \
+ gen_qemu_##storeop(ctx, cpu_gpr[rS(ctx->opcode)], t0); \
+ gen_set_label(l1); \
+ tcg_gen_movi_tl(cpu_reserve, -1); \
+ } \
+ tcg_temp_free(t0); \
+}
+#endif
+
+STCX(stbcx_, 1, st8);
+STCX(sthcx_, 2, st16);
+STCX(stwcx_, 4, st32);
+
#if defined(TARGET_PPC64)
/* ldarx */
LARX(ldarx, 8, ld64);
/* stdcx. */
-static void gen_stdcx_(DisasContext *ctx)
-{
- TCGv t0;
- gen_set_access_type(ctx, ACCESS_RES);
- t0 = tcg_temp_local_new();
- gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x07);
-#if defined(CONFIG_USER_ONLY)
- gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
-#else
- {
- int l1;
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
- gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_reserve, -1);
- }
-#endif
- tcg_temp_free(t0);
-}
+STCX(stdcx_, 8, st64);
#endif /* defined(TARGET_PPC64) */
/* sync */
@@ -9464,6 +9457,8 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
+GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (6 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
` (9 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu)
- Floating Convert to Integer Word Unsigned with Round Toward
Zero (fctiwuz)
- Floating Convert to Integer Doubleword Unsigned (fctidu)
- Floating Convert to Integer Doubleword Unsigned with Round
Toward Zero (fctiduz)
A common macro is developed to eliminate repetitive code. Existing instructions
are also re-implemented to use this macro (fctiw, fctiwz, fctid, fctidz), thus
eliminating copy/paste code.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 122 +++++++++++++----------------------------------
target-ppc/helper.h | 4 ++
target-ppc/translate.c | 12 +++++
3 files changed, 50 insertions(+), 88 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 5bc8659..4c3cca7 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -600,55 +600,41 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
return farg1.ll;
}
-/* fctiw - fctiw. */
-uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int32(farg.d, &env->fp_status);
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750
- */
- farg.ll |= 0xFFF80000ULL << 32;
- }
- return farg.ll;
-}
-
-/* fctiwz - fctiwz. */
-uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
- farg.ll = arg;
+#define FPU_FCTI(op, cvt, nanval) \
+uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
+{ \
+ CPU_DoubleU farg; \
+ \
+ farg.ll = arg; \
+ farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
+ \
+ if (unlikely(env->fp_status.float_exception_flags)) { \
+ if (float64_is_any_nan(arg)) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
+ if (float64_is_signaling_nan(arg)) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
+ } \
+ farg.ll = nanval; \
+ } else if (env->fp_status.float_exception_flags & \
+ float_flag_invalid) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
+ } \
+ helper_float_check_status(env); \
+ } \
+ return farg.ll; \
+ }
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750
- */
- farg.ll |= 0xFFF80000ULL << 32;
- }
- return farg.ll;
-}
+FPU_FCTI(fctiw, int32, 0x80000000)
+FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000)
+FPU_FCTI(fctiwu, uint32, 0x00000000)
+FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000)
+#if defined(TARGET_PPC64)
+FPU_FCTI(fctid, int64, 0x8000000000000000)
+FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000)
+FPU_FCTI(fctidu, uint64, 0x0000000000000000)
+FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000)
+#endif
#if defined(TARGET_PPC64)
/* fcfid - fcfid. */
@@ -660,47 +646,7 @@ uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
return farg.ll;
}
-/* fctid - fctid. */
-uint64_t helper_fctid(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int64(farg.d, &env->fp_status);
- }
- return farg.ll;
-}
-
-/* fctidz - fctidz. */
-uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
- }
- return farg.ll;
-}
#endif
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4359009..4518da0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -64,11 +64,15 @@ DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
DEF_HELPER_2(fctiw, i64, env, i64)
+DEF_HELPER_2(fctiwu, i64, env, i64)
DEF_HELPER_2(fctiwz, i64, env, i64)
+DEF_HELPER_2(fctiwuz, i64, env, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_2(fcfid, i64, env, i64)
DEF_HELPER_2(fctid, i64, env, i64)
+DEF_HELPER_2(fctidu, i64, env, i64)
DEF_HELPER_2(fctidz, i64, env, i64)
+DEF_HELPER_2(fctiduz, i64, env, i64)
#endif
DEF_HELPER_2(frsp, i64, env, i64)
DEF_HELPER_2(frin, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 29c5dc1..55da80a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2267,8 +2267,12 @@ GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
/*** Floating-Point round & convert ***/
/* fctiw */
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
+/* fctiwu */
+GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_ISA206);
/* fctiwz */
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
+/* fctiwuz */
+GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_ISA206);
/* frsp */
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
#if defined(TARGET_PPC64)
@@ -2276,8 +2280,12 @@ GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
/* fctid */
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
+/* fctidu */
+GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_ISA206);
/* fctidz */
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
+/* fctidu */
+GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_ISA206);
#endif
/* frin */
@@ -9793,12 +9801,16 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
#if defined(TARGET_PPC64)
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
+GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
+GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
#endif
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (7 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-13 0:13 ` Peter Maydell
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
` (8 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The float64_to_uint64 routine exits early for all negative numbers.
While the integer result is always correctly returned as 0, the
exception flags are also always set to float_flag_invalid. This
is incorrect for those cases where a small negative number (-1 < x < 0)
rounds to zero. In such a case, the flag should be reported as
inexact.
The following patch allows these small numbers to flow through the
rounding and packing code.
Some interesting test patterns are:
(1) BC6AEEBA7F390215 / -0x1.aeeba7f390215p-57, round to nearest
even should round up to zero (inexact)
(2) A66A44F252C9AAAC /-0x1.a44f252c9aaacp-409 round up should round
up to zero (inexact)
(3) B4692F3AFFAF2716 / -0x1.92f3affaf2716p-185 round down should
be invalid.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
fpu/softfloat.c | 41 +++++++++++++++++++++--------------------
1 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index cb03dca..3d7a8ff 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -161,7 +161,6 @@ static int32 roundAndPackInt32( flag zSign, uint64_t absZ STATUS_PARAM)
| exception is raised and the largest positive or negative integer is
| returned.
*----------------------------------------------------------------------------*/
-
static int64 roundAndPackInt64( flag zSign, uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
{
int8 roundingMode;
@@ -213,20 +212,24 @@ static int64 roundAndPackInt64( flag zSign, uint64_t absZ0, uint64_t absZ1 STATU
| exception is raised and the largest unsigned integer is returned.
*----------------------------------------------------------------------------*/
-static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
+static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
+ uint64_t absZ1 STATUS_PARAM)
{
int8 roundingMode;
flag roundNearestEven, increment;
- int64_t z;
roundingMode = STATUS(float_rounding_mode);
roundNearestEven = (roundingMode == float_round_nearest_even);
- increment = ((int64_t) absZ1 < 0);
+ increment = ((int64_t)absZ1 < 0);
if (!roundNearestEven) {
if (roundingMode == float_round_to_zero) {
increment = 0;
- } else {
- increment = (roundingMode == float_round_up) && absZ1;
+ } else if (absZ1) {
+ if (zSign) {
+ increment = (roundingMode == float_round_down) && absZ1;
+ } else {
+ increment = (roundingMode == float_round_up) && absZ1;
+ }
}
}
if (increment) {
@@ -237,11 +240,16 @@ static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
}
absZ0 &= ~(((uint64_t)(absZ1<<1) == 0) & roundNearestEven);
}
- z = absZ0;
+
+ if (zSign && absZ0) {
+ float_raise(float_flag_invalid STATUS_VAR);
+ return 0;
+ }
+
if (absZ1) {
STATUS(float_exception_flags) |= float_flag_inexact;
}
- return z;
+ return absZ0;
}
/*----------------------------------------------------------------------------
@@ -1590,7 +1598,7 @@ uint64 float32_to_uint64(float32 a STATUS_PARAM)
aSig64 = aSig;
aSig64 <<= 40;
shift64ExtraRightJamming(aSig64, 0, shiftCount, &aSig64, &aSigExtra);
- return roundAndPackUint64(aSig64, aSigExtra STATUS_VAR);
+ return roundAndPackUint64(aSign, aSig64, aSigExtra STATUS_VAR);
}
/*----------------------------------------------------------------------------
@@ -6643,12 +6651,8 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
aSig = extractFloat64Frac(a);
aExp = extractFloat64Exp(a);
aSign = extractFloat64Sign(a);
- if (aSign) {
- if (aExp) {
- float_raise(float_flag_invalid STATUS_VAR);
- } else if (aSig) { /* negative denormalized */
- float_raise(float_flag_inexact STATUS_VAR);
- }
+ if (aSign && (aExp > 1022)) {
+ float_raise(float_flag_invalid STATUS_VAR);
return 0;
}
if (aExp) {
@@ -6657,10 +6661,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
shiftCount = 0x433 - aExp;
if (shiftCount <= 0) {
if (0x43E < aExp) {
- if ((aSig != LIT64(0x0010000000000000)) ||
- (aExp == 0x7FF)) {
- float_raise(float_flag_invalid STATUS_VAR);
- }
+ float_raise(float_flag_invalid STATUS_VAR);
return LIT64(0xFFFFFFFFFFFFFFFF);
}
aSigExtra = 0;
@@ -6668,7 +6669,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
} else {
shift64ExtraRightJamming(aSig, 0, shiftCount, &aSig, &aSigExtra);
}
- return roundAndPackUint64(aSig, aSigExtra STATUS_VAR);
+ return roundAndPackUint64(aSign, aSig, aSigExtra STATUS_VAR);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (8 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
` (7 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4AEC29 / 0x1.97351ff4aec29p+103
currently produces 8000000000000000 instead of FFFFFFFFFFFFFFFF.
This patch re-implements the routine to temporarily force the
rounding mode and use the float64_to_uint64 routine.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
fpu/softfloat.c | 12 +++++-------
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3d7a8ff..1003e59 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6675,13 +6675,11 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM)
{
- int64_t v;
-
- v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
- v += float64_val(a);
- v = float64_to_int64_round_to_zero(make_float64(v) STATUS_VAR);
-
- return v - INT64_MIN;
+ signed char current_rounding_mode = STATUS(float_rounding_mode);
+ set_float_rounding_mode(float_round_to_zero STATUS_VAR);
+ int64_t v = float64_to_uint64(a STATUS_VAR);
+ set_float_rounding_mode(current_rounding_mode STATUS_VAR);
+ return v;
}
#define COMPARE(s, nan_exp) \
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (9 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
` (6 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The float64_to_uint32 has several flaws:
- for numbers between 2**32 and 2**64, the inexact exception flag
may get incorrectly set. In this case, only the invalid flag
should be set.
test pattern: 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
- for numbers between 2**63 and 2**64, incorrect results may
be produced:
test pattern: 43EAAF73F1F0B8BD / 0x1.aaf73f1f0b8bdp+63
This patch re-implements float64_to_uint32 to re-use the
float64_to_uint64 routine (instead of float64_to_int64). For the
saturation case, the inexact bit is explicitly cleared before raising
the invalid flag.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
fpu/softfloat.c | 10 ++++------
1 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 1003e59..6a8b6f5 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6578,15 +6578,13 @@ uint_fast16_t float32_to_uint16_round_to_zero(float32 a STATUS_PARAM)
uint32 float64_to_uint32( float64 a STATUS_PARAM )
{
- int64_t v;
+ uint64_t v;
uint32 res;
- v = float64_to_int64(a STATUS_VAR);
- if (v < 0) {
- res = 0;
- float_raise( float_flag_invalid STATUS_VAR);
- } else if (v > 0xffffffff) {
+ v = float64_to_uint64(a STATUS_VAR);
+ if (v > 0xffffffff) {
res = 0xffffffff;
+ STATUS(float_exception_flags) &= ~float_flag_inexact;
float_raise( float_flag_invalid STATUS_VAR);
} else {
res = v;
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (10 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
` (5 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The float64_to_uint32_round_to_zero routine is incorrect.
For example, the following test pattern:
425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
will erroneously set the inexact flag.
This patch re-implements the routine to temporarily force the
rounding mode and use the float64_to_uint32 routine.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
fpu/softfloat.c | 10 ++++------
1 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 6a8b6f5..052c202 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6594,15 +6594,13 @@ uint32 float64_to_uint32( float64 a STATUS_PARAM )
uint32 float64_to_uint32_round_to_zero( float64 a STATUS_PARAM )
{
- int64_t v;
+ uint64_t v;
uint32 res;
- v = float64_to_int64_round_to_zero(a STATUS_VAR);
- if (v < 0) {
- res = 0;
- float_raise( float_flag_invalid STATUS_VAR);
- } else if (v > 0xffffffff) {
+ v = float64_to_uint64_round_to_zero(a STATUS_VAR);
+ if (v > 0xffffffff) {
res = 0xffffffff;
+ STATUS(float_exception_flags) &= ~float_flag_inexact;
float_raise( float_flag_invalid STATUS_VAR);
} else {
res = v;
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (11 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
` (4 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06. A common macro is provided to
eliminated redudant code, and the existing fcfid instruction is
re-implemented to use this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 23 ++++++++++++++++-------
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 9 +++++++++
3 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 4c3cca7..5521fc2 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -637,16 +637,25 @@ FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000)
#endif
#if defined(TARGET_PPC64)
-/* fcfid - fcfid. */
-uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.d = int64_to_float64(arg, &env->fp_status);
- return farg.ll;
-}
-
+#define FPU_FCFI(op, cvtr, is_single) \
+uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
+{ \
+ CPU_DoubleU farg; \
+ \
+ farg.d = cvtr(arg, &env->fp_status); \
+ \
+ if (is_single) { \
+ farg.d = helper_frsp(env, farg.d); \
+ } \
+ helper_float_check_status(env); \
+ return farg.ll; \
+}
+
+FPU_FCFI(fcfid, int64_to_float64, 0)
+FPU_FCFI(fcfids, int64_to_float64, 1)
+FPU_FCFI(fcfidu, uint64_to_float64, 0)
+FPU_FCFI(fcfidus, uint64_to_float64, 1)
#endif
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4518da0..19b2f6b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -69,6 +69,9 @@ DEF_HELPER_2(fctiwz, i64, env, i64)
DEF_HELPER_2(fctiwuz, i64, env, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_2(fcfid, i64, env, i64)
+DEF_HELPER_2(fcfidu, i64, env, i64)
+DEF_HELPER_2(fcfids, i64, env, i64)
+DEF_HELPER_2(fcfidus, i64, env, i64)
DEF_HELPER_2(fctid, i64, env, i64)
DEF_HELPER_2(fctidu, i64, env, i64)
DEF_HELPER_2(fctidz, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 55da80a..793a781 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2278,6 +2278,12 @@ GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
#if defined(TARGET_PPC64)
/* fcfid */
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
+/* fcfids */
+GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_ISA206);
+/* fcfidu */
+GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_ISA206);
+/* fcfidus */
+GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_ISA206);
/* fctid */
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
/* fctidu */
@@ -9807,6 +9813,9 @@ GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
#if defined(TARGET_PPC64)
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
+GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz]
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (12 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
` (3 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 12 ++++++------
target-ppc/translate_init.c | 2 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 5521fc2..1fb3d15 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -668,18 +668,18 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ farg.ll = float64_default_nan | 0x0008000000000000ul;
} else {
set_float_rounding_mode(rounding_mode, &env->fp_status);
farg.ll = float64_round_to_int(farg.d, &env->fp_status);
/* Restore rounding mode from FPSCR */
fpscr_set_rounding_mode(env);
+
+ /* fri* does not set FPSCR[XX] */
+ env->fp_status.float_exception_flags &= ~float_flag_inexact;
}
+ helper_float_check_status(env);
return farg.ll;
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 491e56c..7bb9bbc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7228,6 +7228,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7265,6 +7266,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (13 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
` (2 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 56 ++++++++++++++++++++++++++++++++++++++--------
target-ppc/helper.h | 2 +
target-ppc/translate.c | 17 ++++++++++++++
3 files changed, 65 insertions(+), 10 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1fb3d15..4977618 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -50,6 +50,16 @@ static inline int isden(float64 d)
return ((u.ll >> 52) & 0x7FF) == 0;
}
+static inline int ppc_float32_get_unbiased_exp(float32 f)
+{
+ return ((f >> 23) & 0xFF) - 127;
+}
+
+static inline int ppc_float64_get_unbiased_exp(float64 f)
+{
+ return ((f >> 52) & 0x7FF) - 1023;
+}
+
uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
{
CPU_DoubleU farg;
@@ -988,6 +998,42 @@ uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
}
}
+void helper_ftdiv(CPUPPCState *env, uint32_t bf, uint64_t fra, uint64_t frb)
+{
+ int fe_flag = 0;
+ int fg_flag = 0;
+
+ if (unlikely(float64_is_infinity(fra) ||
+ float64_is_infinity(frb) ||
+ float64_is_zero(frb))) {
+ fe_flag = 1;
+ fg_flag = 1;
+ } else {
+ int e_a = ppc_float64_get_unbiased_exp(fra);
+ int e_b = ppc_float64_get_unbiased_exp(frb);
+
+ if (unlikely(float64_is_any_nan(fra) ||
+ float64_is_any_nan(frb))) {
+ fe_flag = 1;
+ } else if ((e_b <= -1022) || (e_b >= 1021)) {
+ fe_flag = 1;
+ } else if (!float64_is_zero(fra) &&
+ (((e_a - e_b) >= 1023) ||
+ ((e_a - e_b) <= -1021) ||
+ (e_a <= -970))) {
+ fe_flag = 1;
+ }
+
+ if (unlikely(float64_is_zero_or_denormal(frb))) {
+ /* XB is not zero because of the above check and */
+ /* so must be denormalized. */
+ fg_flag = 1;
+ }
+ }
+
+ env->crf[bf] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+}
+
void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint32_t crfD)
{
@@ -2016,16 +2062,6 @@ VSX_RSQRTE(xsrsqrtesp, 1, float64, f64, 1, 1)
VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0, 0)
VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0, 0)
-static inline int ppc_float32_get_unbiased_exp(float32 f)
-{
- return ((f >> 23) & 0xFF) - 127;
-}
-
-static inline int ppc_float64_get_unbiased_exp(float64 f)
-{
- return ((f >> 52) & 0x7FF) - 1023;
-}
-
/* VSX_TDIV - VSX floating point test for divide
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 19b2f6b..5f5d3f6 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -97,6 +97,8 @@ DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
+DEF_HELPER_4(ftdiv, void, env, i32, i64, i64)
+
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
#define dh_is_signed_avr dh_is_signed_ptr
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 793a781..2362c12 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2303,6 +2303,22 @@ GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
/* frim */
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
+static void gen_ftdiv(DisasContext *ctx)
+{
+ TCGv_i32 bf;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ /* NIP cannot be restored if the memory exception comes from an helper */
+ gen_update_nip(ctx, ctx->nip - 4);
+ bf = tcg_const_i32(crfD(ctx->opcode));
+ gen_helper_ftdiv(cpu_env, bf, cpu_fpr[rA(ctx->opcode)],
+ cpu_fpr[rB(ctx->opcode)]);
+}
+
+
+
/*** Floating-Point compare ***/
/* fcmpo */
@@ -9806,6 +9822,7 @@ GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
+GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (14 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 31 +++++++++++++++++++++++++++++++
target-ppc/helper.h | 1 +
target-ppc/translate.c | 14 ++++++++++++++
3 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 4977618..74f43fa 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1034,6 +1034,37 @@ void helper_ftdiv(CPUPPCState *env, uint32_t bf, uint64_t fra, uint64_t frb)
env->crf[bf] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
}
+void helper_ftsqrt(CPUPPCState *env, uint32_t bf, uint64_t frb)
+{
+ int fe_flag = 0;
+ int fg_flag = 0;
+
+ if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
+ fe_flag = 1;
+ fg_flag = 1;
+ } else {
+ int e_b = ppc_float64_get_unbiased_exp(frb);
+
+ if (unlikely(float64_is_any_nan(frb))) {
+ fe_flag = 1;
+ } else if (unlikely(float64_is_zero(frb))) {
+ fe_flag = 1;
+ } else if (unlikely(float64_is_neg(frb))) {
+ fe_flag = 1;
+ } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
+ fe_flag = 1;
+ }
+
+ if (unlikely(float64_is_zero_or_denormal(frb))) {
+ /* XB is not zero because of the above check and */
+ /* therefore must be denormalized. */
+ fg_flag = 1;
+ }
+ }
+
+ env->crf[bf] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+}
+
void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint32_t crfD)
{
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5f5d3f6..ccf5711 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -98,6 +98,7 @@ DEF_HELPER_2(frsqrte, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
DEF_HELPER_4(ftdiv, void, env, i32, i64, i64)
+DEF_HELPER_3(ftsqrt, void, env, i32, i64)
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2362c12..eb1c49a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2317,6 +2317,19 @@ static void gen_ftdiv(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
}
+static void gen_ftsqrt(DisasContext *ctx)
+{
+ TCGv_i32 bf;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ /* NIP cannot be restored if the memory exception comes from an helper */
+ gen_update_nip(ctx, ctx->nip - 4);
+ bf = tcg_const_i32(crfD(ctx->opcode));
+ gen_helper_ftsqrt(cpu_env, bf, cpu_fpr[rB(ctx->opcode)]);
+}
+
/*** Floating-Point compare ***/
@@ -9823,6 +9836,7 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (15 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes
in the P7 and P8 machines.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate_init.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7bb9bbc..ec65bf4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7227,6 +7227,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
PPC_FLOAT_STFIWX |
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
@@ -7265,6 +7266,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
PPC_FLOAT_STFIWX |
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
` (16 preceding siblings ...)
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
@ 2013-12-09 15:47 ` Tom Musta
17 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-09 15:47 UTC (permalink / raw)
To: qemu-devel; +Cc: Tom Musta, qemu-ppc
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index eb1c49a..4148ba9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3529,6 +3529,20 @@ static void gen_lfiwax(DisasContext *ctx)
tcg_temp_free(t0);
}
+/* lfiwzx */
+static void gen_lfiwzx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32u(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_temp_free(EA);
+}
/*** Floating-point store ***/
#define GEN_STF(name, stop, opc, type) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -9942,6 +9956,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x00000001, PPC_NONE, PPC2_ISA206),
GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
--
1.7.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
@ 2013-12-10 0:01 ` Richard Henderson
2013-12-10 17:47 ` Tom Musta
0 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 0:01 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/09/2013 07:46 AM, Tom Musta wrote:
> + for (i = 0; i < 8; i++) {
> + int index = (rs & (0xFFul) << (i*8)) >> (i*8);
This is a silly expression. Better as
int index = (rs >> (i * 8)) & 0xff;
> + ra |= (1<<i);
Unnecessary parens, and missing spaces around the operator.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
@ 2013-12-10 0:05 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 0:05 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/09/2013 07:47 AM, Tom Musta wrote:
> This patch adds the Divide Doubleword Extended Unsigned
> instructions. This instruction requires dividing a 128-bit
> value by a 64 bit value. Since 128 bit integer division is
> not supported in TCG, a helper is used, providing a
> repeated difference algorithm.
It's long past time we provided this generically.
There's a (slightly) better algorithm than this in target-i386/int_helper.c.
Extra points for stealing the (much) better algorithm from gcc's libgcc2.c.
This ought to go in "host-utils.h" next to mul[us]64.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
@ 2013-12-10 0:26 ` Richard Henderson
2013-12-10 17:58 ` Tom Musta
0 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 0:26 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/09/2013 07:47 AM, Tom Musta wrote:
> + /* does the result fit in 32 bits? */ \
> + tcg_gen_brcondi_i64(TCG_COND_LT, cpu_gpr[rD(ctx->opcode)], INT32_MIN, \
> + lbl_ov); \
> + tcg_gen_brcondi_i64(TCG_COND_GT, cpu_gpr[rD(ctx->opcode)], INT32_MAX, \
> + lbl_ov); \
Better with an extend and single brcond.
> + tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
> + /* check for MIN div -1 */ \
> + int l3 = gen_new_label(); \
> + tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
> + tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
The second test can never be true, since ra has 32 zero bits.
Thus the first test is also pointless.
> + gen_set_label(lbl_ov); /* overflow handling */ \
> + \
> + if (signed) { \
> + tcg_gen_sari_i64(cpu_gpr[rD(ctx->opcode)], ra, 63); \
> + } else { \
> + tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
> + } \
Divide by zero from the signed case reads an uninitialized ra here. While it's
true that the result is undefined, I don't think we want to expose
uninitialized reads to the TCG optimizer.
Although... what is that sari for anyway? The result is undefined in the
non-div-by-zero overflow case as well. We might as well use 0, or even
0xdeadbeef, all the time, no?
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
@ 2013-12-10 0:31 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 0:31 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/09/2013 07:47 AM, Tom Musta wrote:
> +LARX(lharx, 1, ld16u);
2
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
@ 2013-12-10 0:41 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 0:41 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/09/2013 07:47 AM, Tom Musta wrote:
> -static void gen_conditional_store (DisasContext *ctx, TCGv EA,
> +static void gen_conditional_store(DisasContext *ctx, TCGv EA,
> int reg, int size)
If you're going to make random changes to the formatting, fix it all -- the
indentation on the next line is now wrong.
> + gen_qemu_##storeop(ctx, cpu_gpr[rS(ctx->opcode)], t0); \
I meant to mention this for l*arx too, but please use the new ldst opcodes.
That'll save me having to make the change here in the next couple of weeks.
Also, surely better to implement gen_conditional_store !USER, instead of
duplicating the STCX macro.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction
2013-12-10 0:01 ` Richard Henderson
@ 2013-12-10 17:47 ` Tom Musta
0 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-10 17:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-ppc
On 12/9/2013 6:01 PM, Richard Henderson wrote:
> On 12/09/2013 07:46 AM, Tom Musta wrote:
>> + for (i = 0; i < 8; i++) {
>> + int index = (rs & (0xFFul) << (i*8)) >> (i*8);
>
> This is a silly expression. Better as
>
> int index = (rs >> (i * 8)) & 0xff;
>
>> + ra |= (1<<i);
>
> Unnecessary parens, and missing spaces around the operator.
Thanks, as always, for reviewing. I concur with most of the comments ...
will respond only to those that I either disagree with or have further
questions.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
2013-12-10 0:26 ` Richard Henderson
@ 2013-12-10 17:58 ` Tom Musta
2013-12-10 18:30 ` Richard Henderson
0 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-10 17:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-ppc
On 12/9/2013 6:26 PM, Richard Henderson wrote:
>> + tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
>> + /* check for MIN div -1 */ \
>> + int l3 = gen_new_label(); \
>> + tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
>> + tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
>
> The second test can never be true, since ra has 32 zero bits.
> Thus the first test is also pointless.
Hmm. Consider the case where GPR[RA] = 0xUUUUUUUU_80000000 (U=don't care) and
GPR[RB] = 0xUUUUUUUU_FFFFFFFF. Without these checks, I do not believe overflow
will be properly detected.
>
>> + gen_set_label(lbl_ov); /* overflow handling */ \
>> + \
>> + if (signed) { \
>> + tcg_gen_sari_i64(cpu_gpr[rD(ctx->opcode)], ra, 63); \
>> + } else { \
>> + tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
>> + } \
>
> Divide by zero from the signed case reads an uninitialized ra here. While it's
> true that the result is undefined, I don't think we want to expose
> uninitialized reads to the TCG optimizer.
>
> Although... what is that sari for anyway? The result is undefined in the
> non-div-by-zero overflow case as well. We might as well use 0, or even
> 0xdeadbeef, all the time, no?
I don't disagree with the comment. I was being consistent with existing code for
divw/divd. I suspect whomever wrote this was trying to match the hardware's
implementation. But 0 is certainly a perfectly good undefined value and would
simplify the code.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
2013-12-10 17:58 ` Tom Musta
@ 2013-12-10 18:30 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2013-12-10 18:30 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc
On 12/10/2013 09:58 AM, Tom Musta wrote:
>> > The second test can never be true, since ra has 32 zero bits.
>> > Thus the first test is also pointless.
> Hmm. Consider the case where GPR[RA] = 0xUUUUUUUU_80000000 (U=don't care) and
> GPR[RB] = 0xUUUUUUUU_FFFFFFFF. Without these checks, I do not believe overflow
> will be properly detected.
>
Hmm. I'm not sure what I was thinking here. Ignore all that.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
@ 2013-12-13 0:13 ` Peter Maydell
2013-12-16 15:20 ` Tom Musta
0 siblings, 1 reply; 37+ messages in thread
From: Peter Maydell @ 2013-12-13 0:13 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, QEMU Developers
On 9 December 2013 15:47, Tom Musta <tommusta@gmail.com> wrote:
> The float64_to_uint64 routine exits early for all negative numbers.
> While the integer result is always correctly returned as 0, the
> exception flags are also always set to float_flag_invalid. This
> is incorrect for those cases where a small negative number (-1 < x < 0)
> rounds to zero. In such a case, the flag should be reported as
> inexact.
> -static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
> +static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
> + uint64_t absZ1 STATUS_PARAM)
This function isn't in the copy of fpu/softfloat.c that's in master,
unless I'm confused. Does this series depend on something else?
thanks
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64
2013-12-13 0:13 ` Peter Maydell
@ 2013-12-16 15:20 ` Tom Musta
2013-12-16 15:24 ` Peter Maydell
0 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-16 15:20 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 12/12/2013 6:13 PM, Peter Maydell wrote:
> On 9 December 2013 15:47, Tom Musta <tommusta@gmail.com> wrote:
>> The float64_to_uint64 routine exits early for all negative numbers.
>> While the integer result is always correctly returned as 0, the
>> exception flags are also always set to float_flag_invalid. This
>> is incorrect for those cases where a small negative number (-1 < x < 0)
>> rounds to zero. In such a case, the flag should be reported as
>> inexact.
>
>> -static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
>> +static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
>> + uint64_t absZ1 STATUS_PARAM)
>
> This function isn't in the copy of fpu/softfloat.c that's in master,
> unless I'm confused. Does this series depend on something else?
>
> thanks
> -- PMM
>
Peter: Yes, it does. See http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg00045.html and specifically patch 1/19.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64
2013-12-16 15:20 ` Tom Musta
@ 2013-12-16 15:24 ` Peter Maydell
2013-12-16 15:26 ` Tom Musta
0 siblings, 1 reply; 37+ messages in thread
From: Peter Maydell @ 2013-12-16 15:24 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, QEMU Developers
On 16 December 2013 15:20, Tom Musta <tommusta@gmail.com> wrote:
> On 12/12/2013 6:13 PM, Peter Maydell wrote:
>> This function isn't in the copy of fpu/softfloat.c that's in master,
>> unless I'm confused. Does this series depend on something else?
> Peter: Yes, it does. See
> http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg00045.html
> and specifically patch 1/19.
OK. Please could you fold this bugfix directly into that patch?
It's very hard to review "this is broken and then this thing
fixes it", especially if the two patches are in different
series -- much easier to just have one patch which implements
the fixed version.
thanks
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64
2013-12-16 15:24 ` Peter Maydell
@ 2013-12-16 15:26 ` Tom Musta
0 siblings, 0 replies; 37+ messages in thread
From: Tom Musta @ 2013-12-16 15:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 12/16/2013 9:24 AM, Peter Maydell wrote:
> On 16 December 2013 15:20, Tom Musta <tommusta@gmail.com> wrote:
>> On 12/12/2013 6:13 PM, Peter Maydell wrote:
>>> This function isn't in the copy of fpu/softfloat.c that's in master,
>>> unless I'm confused. Does this series depend on something else?
>
>
>> Peter: Yes, it does. See
>> http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg00045.html
>> and specifically patch 1/19.
>
> OK. Please could you fold this bugfix directly into that patch?
> It's very hard to review "this is broken and then this thing
> fixes it", especially if the two patches are in different
> series -- much easier to just have one patch which implements
> the fixed version.
>
> thanks
> -- PMM
>
Yes, I will do that. Thanks, Peter.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
@ 2013-12-18 22:02 ` Scott Wood
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
0 siblings, 1 reply; 37+ messages in thread
From: Scott Wood @ 2013-12-18 22:02 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
> This patch adds a flag for base instruction additions to Power ISA
> 2.06B. The flag will be used to identify/select basic Book I and
> Book II instructions that were newly added in that revision of the
> architecture. The flag will not be used for VSX or Altivec.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/cpu.h | 4 +++-
> target-ppc/translate_init.c | 6 ++++--
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 0abc848..fe3aace 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1877,9 +1877,11 @@ enum {
> PPC2_ISA205 = 0x0000000000000020ULL,
> /* VSX additions in ISA 2.07 */
> PPC2_VSX207 = 0x0000000000000040ULL,
> + /* Book I 2.06B PowerPC specification (base instructions) */
> + PPC2_ISA206 = 0x0000000000000080ULL,
>
> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
> - PPC2_ISA205 | PPC2_VSX207)
> + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
> };
>
> /*****************************************************************************/
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e14ab63..491e56c 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> PPC_64B | PPC_ALTIVEC |
> PPC_SEGMENT_64B | PPC_SLBI |
> PPC_POPCNTB | PPC_POPCNTWD;
> - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
> + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
> + PPC2_ISA206;
> pcc->msr_mask = 0x800000000284FF37ULL;
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
> @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> PPC_64B | PPC_ALTIVEC |
> PPC_SEGMENT_64B | PPC_SLBI |
> PPC_POPCNTB | PPC_POPCNTWD;
> - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> + PPC2_ISA206;
> pcc->msr_mask = 0x800000000284FF36ULL;
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
e500mc/e5500 are also ISA 2.06 (minus some of these new instructions,
but not all of them -- better to emulate instructions that don't exist
than to not emulate instructions that do exist).
-Scott
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-18 22:02 ` Scott Wood
@ 2013-12-18 22:09 ` Alexander Graf
2013-12-18 22:11 ` Scott Wood
0 siblings, 1 reply; 37+ messages in thread
From: Alexander Graf @ 2013-12-18 22:09 UTC (permalink / raw)
To: Scott Wood; +Cc: Tom Musta, qemu-ppc, QEMU Developers
On 18.12.2013, at 23:02, Scott Wood <scottwood@freescale.com> wrote:
> On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
>> This patch adds a flag for base instruction additions to Power ISA
>> 2.06B. The flag will be used to identify/select basic Book I and
>> Book II instructions that were newly added in that revision of the
>> architecture. The flag will not be used for VSX or Altivec.
>>
>> Signed-off-by: Tom Musta <tommusta@gmail.com>
>> ---
>> target-ppc/cpu.h | 4 +++-
>> target-ppc/translate_init.c | 6 ++++--
>> 2 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 0abc848..fe3aace 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1877,9 +1877,11 @@ enum {
>> PPC2_ISA205 = 0x0000000000000020ULL,
>> /* VSX additions in ISA 2.07 */
>> PPC2_VSX207 = 0x0000000000000040ULL,
>> + /* Book I 2.06B PowerPC specification (base instructions) */
>> + PPC2_ISA206 = 0x0000000000000080ULL,
>>
>> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
>> - PPC2_ISA205 | PPC2_VSX207)
>> + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
>> };
>>
>> /*****************************************************************************/
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index e14ab63..491e56c 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>> PPC_64B | PPC_ALTIVEC |
>> PPC_SEGMENT_64B | PPC_SLBI |
>> PPC_POPCNTB | PPC_POPCNTWD;
>> - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
>> + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
>> + PPC2_ISA206;
>> pcc->msr_mask = 0x800000000284FF37ULL;
>> pcc->mmu_model = POWERPC_MMU_2_06;
>> #if defined(CONFIG_SOFTMMU)
>> @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>> PPC_64B | PPC_ALTIVEC |
>> PPC_SEGMENT_64B | PPC_SLBI |
>> PPC_POPCNTB | PPC_POPCNTWD;
>> - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
>> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
>> + PPC2_ISA206;
>> pcc->msr_mask = 0x800000000284FF36ULL;
>> pcc->mmu_model = POWERPC_MMU_2_06;
>> #if defined(CONFIG_SOFTMMU)
>
> e500mc/e5500 are also ISA 2.06 (minus some of these new instructions,
> but not all of them -- better to emulate instructions that don't exist
> than to not emulate instructions that do exist).
Well, that's what the nice categories in the ISA are there for, no? They should tell us quite explicitly which instructions are available in embedded and which are not.
Tom, please model the flags accordingly so that we keep instructions that are not a common subset between 2.06 e500 and 2.06 POWER as a separate flag that we can set exclusively on the POWER CPUs.
Alex
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
@ 2013-12-18 22:11 ` Scott Wood
2013-12-18 22:37 ` Alexander Graf
0 siblings, 1 reply; 37+ messages in thread
From: Scott Wood @ 2013-12-18 22:11 UTC (permalink / raw)
To: Alexander Graf; +Cc: Tom Musta, qemu-ppc, QEMU Developers
On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
> On 18.12.2013, at 23:02, Scott Wood <scottwood@freescale.com> wrote:
>
> > On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
> >> This patch adds a flag for base instruction additions to Power ISA
> >> 2.06B. The flag will be used to identify/select basic Book I and
> >> Book II instructions that were newly added in that revision of the
> >> architecture. The flag will not be used for VSX or Altivec.
> >>
> >> Signed-off-by: Tom Musta <tommusta@gmail.com>
> >> ---
> >> target-ppc/cpu.h | 4 +++-
> >> target-ppc/translate_init.c | 6 ++++--
> >> 2 files changed, 7 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> >> index 0abc848..fe3aace 100644
> >> --- a/target-ppc/cpu.h
> >> +++ b/target-ppc/cpu.h
> >> @@ -1877,9 +1877,11 @@ enum {
> >> PPC2_ISA205 = 0x0000000000000020ULL,
> >> /* VSX additions in ISA 2.07 */
> >> PPC2_VSX207 = 0x0000000000000040ULL,
> >> + /* Book I 2.06B PowerPC specification (base instructions) */
> >> + PPC2_ISA206 = 0x0000000000000080ULL,
> >>
> >> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
> >> - PPC2_ISA205 | PPC2_VSX207)
> >> + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
> >> };
> >>
> >> /*****************************************************************************/
> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >> index e14ab63..491e56c 100644
> >> --- a/target-ppc/translate_init.c
> >> +++ b/target-ppc/translate_init.c
> >> @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> >> PPC_64B | PPC_ALTIVEC |
> >> PPC_SEGMENT_64B | PPC_SLBI |
> >> PPC_POPCNTB | PPC_POPCNTWD;
> >> - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
> >> + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
> >> + PPC2_ISA206;
> >> pcc->msr_mask = 0x800000000284FF37ULL;
> >> pcc->mmu_model = POWERPC_MMU_2_06;
> >> #if defined(CONFIG_SOFTMMU)
> >> @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >> PPC_64B | PPC_ALTIVEC |
> >> PPC_SEGMENT_64B | PPC_SLBI |
> >> PPC_POPCNTB | PPC_POPCNTWD;
> >> - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
> >> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> >> + PPC2_ISA206;
> >> pcc->msr_mask = 0x800000000284FF36ULL;
> >> pcc->mmu_model = POWERPC_MMU_2_06;
> >> #if defined(CONFIG_SOFTMMU)
> >
> > e500mc/e5500 are also ISA 2.06 (minus some of these new instructions,
> > but not all of them -- better to emulate instructions that don't exist
> > than to not emulate instructions that do exist).
>
> Well, that's what the nice categories in the ISA are there for, no?
> They should tell us quite explicitly which instructions are available
> in embedded and which are not.
They should, but they don't. In the core reference manual for e500mc
and derivatives, it lists the ISA categories supported... and then has a
table that says "oh, except for these instructions".
-Scott
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-18 22:11 ` Scott Wood
@ 2013-12-18 22:37 ` Alexander Graf
2013-12-19 15:35 ` Tom Musta
0 siblings, 1 reply; 37+ messages in thread
From: Alexander Graf @ 2013-12-18 22:37 UTC (permalink / raw)
To: Scott Wood; +Cc: Tom Musta, qemu-ppc, QEMU Developers
> Am 18.12.2013 um 23:11 schrieb Scott Wood <scottwood@freescale.com>:
>
>> On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
>>> On 18.12.2013, at 23:02, Scott Wood <scottwood@freescale.com> wrote:
>>>
>>>> On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
>>>> This patch adds a flag for base instruction additions to Power ISA
>>>> 2.06B. The flag will be used to identify/select basic Book I and
>>>> Book II instructions that were newly added in that revision of the
>>>> architecture. The flag will not be used for VSX or Altivec.
>>>>
>>>> Signed-off-by: Tom Musta <tommusta@gmail.com>
>>>> ---
>>>> target-ppc/cpu.h | 4 +++-
>>>> target-ppc/translate_init.c | 6 ++++--
>>>> 2 files changed, 7 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>>>> index 0abc848..fe3aace 100644
>>>> --- a/target-ppc/cpu.h
>>>> +++ b/target-ppc/cpu.h
>>>> @@ -1877,9 +1877,11 @@ enum {
>>>> PPC2_ISA205 = 0x0000000000000020ULL,
>>>> /* VSX additions in ISA 2.07 */
>>>> PPC2_VSX207 = 0x0000000000000040ULL,
>>>> + /* Book I 2.06B PowerPC specification (base instructions) */
>>>> + PPC2_ISA206 = 0x0000000000000080ULL,
>>>>
>>>> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
>>>> - PPC2_ISA205 | PPC2_VSX207)
>>>> + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
>>>> };
>>>>
>>>> /*****************************************************************************/
>>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>>> index e14ab63..491e56c 100644
>>>> --- a/target-ppc/translate_init.c
>>>> +++ b/target-ppc/translate_init.c
>>>> @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>>>> PPC_64B | PPC_ALTIVEC |
>>>> PPC_SEGMENT_64B | PPC_SLBI |
>>>> PPC_POPCNTB | PPC_POPCNTWD;
>>>> - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
>>>> + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
>>>> + PPC2_ISA206;
>>>> pcc->msr_mask = 0x800000000284FF37ULL;
>>>> pcc->mmu_model = POWERPC_MMU_2_06;
>>>> #if defined(CONFIG_SOFTMMU)
>>>> @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>>> PPC_64B | PPC_ALTIVEC |
>>>> PPC_SEGMENT_64B | PPC_SLBI |
>>>> PPC_POPCNTB | PPC_POPCNTWD;
>>>> - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
>>>> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
>>>> + PPC2_ISA206;
>>>> pcc->msr_mask = 0x800000000284FF36ULL;
>>>> pcc->mmu_model = POWERPC_MMU_2_06;
>>>> #if defined(CONFIG_SOFTMMU)
>>>
>>> e500mc/e5500 are also ISA 2.06 (minus some of these new instructions,
>>> but not all of them -- better to emulate instructions that don't exist
>>> than to not emulate instructions that do exist).
>>
>> Well, that's what the nice categories in the ISA are there for, no?
>> They should tell us quite explicitly which instructions are available
>> in embedded and which are not.
>
> They should, but they don't. In the core reference manual for e500mc
> and derivatives, it lists the ISA categories supported... and then has a
> table that says "oh, except for these instructions".
Hooray :). Can we please split the feature bit nevertheless?
Alex
>
> -Scott
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-18 22:37 ` Alexander Graf
@ 2013-12-19 15:35 ` Tom Musta
2013-12-19 17:17 ` Scott Wood
0 siblings, 1 reply; 37+ messages in thread
From: Tom Musta @ 2013-12-19 15:35 UTC (permalink / raw)
To: Alexander Graf, Scott Wood; +Cc: qemu-ppc, QEMU Developers
On 12/18/2013 4:37 PM, Alexander Graf wrote:
>
>
>> Am 18.12.2013 um 23:11 schrieb Scott Wood <scottwood@freescale.com>:
>>
>>> On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
>>>> On 18.12.2013, at 23:02, Scott Wood <scottwood@freescale.com> wrote:
>>>>
>>>>> On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
>>>>> This patch adds a flag for base instruction additions to Power ISA
>>>>> 2.06B. The flag will be used to identify/select basic Book I and
>>>>> Book II instructions that were newly added in that revision of the
>>>>> architecture. The flag will not be used for VSX or Altivec.
>>>>>
>>>>> Signed-off-by: Tom Musta <tommusta@gmail.com>
>>>>> ---
>>>>> target-ppc/cpu.h | 4 +++-
>>>>> target-ppc/translate_init.c | 6 ++++--
>>>>> 2 files changed, 7 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>>>>> index 0abc848..fe3aace 100644
>>>>> --- a/target-ppc/cpu.h
>>>>> +++ b/target-ppc/cpu.h
>>>>> @@ -1877,9 +1877,11 @@ enum {
>>>>> PPC2_ISA205 = 0x0000000000000020ULL,
>>>>> /* VSX additions in ISA 2.07 */
>>>>> PPC2_VSX207 = 0x0000000000000040ULL,
>>>>> + /* Book I 2.06B PowerPC specification (base instructions) */
>>>>> + PPC2_ISA206 = 0x0000000000000080ULL,
>>>>>
>>>>> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
>>>>> - PPC2_ISA205 | PPC2_VSX207)
>>>>> + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
>>>>> };
>>>>>
>>>>> /*****************************************************************************/
>>>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>>>> index e14ab63..491e56c 100644
>>>>> --- a/target-ppc/translate_init.c
>>>>> +++ b/target-ppc/translate_init.c
>>>>> @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>>>>> PPC_64B | PPC_ALTIVEC |
>>>>> PPC_SEGMENT_64B | PPC_SLBI |
>>>>> PPC_POPCNTB | PPC_POPCNTWD;
>>>>> - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
>>>>> + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
>>>>> + PPC2_ISA206;
>>>>> pcc->msr_mask = 0x800000000284FF37ULL;
>>>>> pcc->mmu_model = POWERPC_MMU_2_06;
>>>>> #if defined(CONFIG_SOFTMMU)
>>>>> @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>>>> PPC_64B | PPC_ALTIVEC |
>>>>> PPC_SEGMENT_64B | PPC_SLBI |
>>>>> PPC_POPCNTB | PPC_POPCNTWD;
>>>>> - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
>>>>> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
>>>>> + PPC2_ISA206;
>>>>> pcc->msr_mask = 0x800000000284FF36ULL;
>>>>> pcc->mmu_model = POWERPC_MMU_2_06;
>>>>> #if defined(CONFIG_SOFTMMU)
>>>>
>>>> e500mc/e5500 are also ISA 2.06 (minus some of these new instructions,
>>>> but not all of them -- better to emulate instructions that don't exist
>>>> than to not emulate instructions that do exist).
>>>
>>> Well, that's what the nice categories in the ISA are there for, no?
>>> They should tell us quite explicitly which instructions are available
>>> in embedded and which are not.
>>
>> They should, but they don't. In the core reference manual for e500mc
>> and derivatives, it lists the ISA categories supported... and then has a
>> table that says "oh, except for these instructions".
>
> Hooray :). Can we please split the feature bit nevertheless?
>
> Alex
>
>>
>> -Scott
>>
>>
It turns out that all of the instructions added in this series are *not* implemented
in e500mc. So the patch, as is, is correct for e500mc as well as P7/P8.
The problem with this patch series seems to be that previously implemented ISA2.06
instructions were given their own flags (e.g. PPC_POPCNTWD). But this series attempted
to use a single flag for all of base ISA 2.06.
Based on Alex's suggestion, I propose that I re-implement, eliminating PPC2_ISA206 and
replacing it with the following new flags:
- PPC2_PERMUTE_206 (bpermd)
- PPC2_DIV_EXT_206 (div[wd]e[u])
- PPC2_ATOMIC_206 (l[bh]arx, st[bh]cx.)
- PPC2_FP_CVT_206 (fcfid*, fcti[dw]u[z], lfiwzx)
- PPC2_FP_TEST_206 (ftdiv, ftsqrt)
Comments?
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
2013-12-19 15:35 ` Tom Musta
@ 2013-12-19 17:17 ` Scott Wood
0 siblings, 0 replies; 37+ messages in thread
From: Scott Wood @ 2013-12-19 17:17 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, Alexander Graf, QEMU Developers
On Thu, 2013-12-19 at 09:35 -0600, Tom Musta wrote:
> It turns out that all of the instructions added in this series are *not* implemented
> in e500mc. So the patch, as is, is correct for e500mc as well as P7/P8.
That may be true for e500mc (for some reason it didn't look that way
when I checked yesterday), but e5500 supports bpermd.
e6500 (not in QEMU yet, but hopefully added soon) additionally supports
lbarx/lharx/stbcx./sthcx.
> The problem with this patch series seems to be that previously implemented ISA2.06
> instructions were given their own flags (e.g. PPC_POPCNTWD). But this series attempted
> to use a single flag for all of base ISA 2.06.
>
> Based on Alex's suggestion, I propose that I re-implement, eliminating PPC2_ISA206 and
> replacing it with the following new flags:
>
> - PPC2_PERMUTE_206 (bpermd)
> - PPC2_DIV_EXT_206 (div[wd]e[u])
> - PPC2_ATOMIC_206 (l[bh]arx, st[bh]cx.)
> - PPC2_FP_CVT_206 (fcfid*, fcti[dw]u[z], lfiwzx)
> - PPC2_FP_TEST_206 (ftdiv, ftsqrt)
>
> Comments?
Sounds good.
-Scott
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2013-12-19 17:18 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-18 22:02 ` Scott Wood
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-18 22:11 ` Scott Wood
2013-12-18 22:37 ` Alexander Graf
2013-12-19 15:35 ` Tom Musta
2013-12-19 17:17 ` Scott Wood
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-10 0:01 ` Richard Henderson
2013-12-10 17:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-10 0:05 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
2013-12-10 0:26 ` Richard Henderson
2013-12-10 17:58 ` Tom Musta
2013-12-10 18:30 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-10 0:31 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-10 0:41 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
2013-12-13 0:13 ` Peter Maydell
2013-12-16 15:20 ` Tom Musta
2013-12-16 15:24 ` Peter Maydell
2013-12-16 15:26 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
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