From: "Jan Beulich" <JBeulich@suse.com>
To: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Cc: jinsong.liu@intel.com, boris.ostrovsky@oracle.com,
chegger@amazon.de, suravee.suthikulpanit@amd.com,
xen-devel@lists.xen.org
Subject: Re: [PATCH V4.1] mcheck, vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs
Date: Thu, 13 Feb 2014 08:38:05 +0000 [thread overview]
Message-ID: <52FC927D020000780011BF0A@nat28.tlf.novell.com> (raw)
In-Reply-To: <1392247608-6960-1-git-send-email-aravind.gopalakrishnan@amd.com>
>>> On 13.02.14 at 00:26, Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> wrote:
> --- a/xen/arch/x86/cpu/mcheck/vmce.c
> +++ b/xen/arch/x86/cpu/mcheck/vmce.c
> @@ -107,7 +107,8 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
>
> *val = 0;
>
> - switch ( msr & (MSR_IA32_MC0_CTL | 3) )
> + /* Allow only first 3 MC banks into switch() */
> + switch ( msr & (-MSR_IA32_MC0_CTL | 3) )
> {
> case MSR_IA32_MC0_CTL:
> /* stick all 1's to MCi_CTL */
I'm confused: You now add a comment as if the mask was including
bit 4, which it doesn't. What am I missing?
Also, please get used to mention (commonly at the bottom of the
commit message, after a --- separator) what changed compared to
the previous iteration.
Jan
next prev parent reply other threads:[~2014-02-13 8:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-12 23:26 [PATCH V4.1] mcheck, vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs Aravind Gopalakrishnan
2014-02-13 8:38 ` Jan Beulich [this message]
2014-02-13 17:27 ` Aravind Gopalakrishnan
2014-02-13 18:24 ` Aravind Gopalakrishnan
2014-02-14 8:28 ` Jan Beulich
2014-02-16 14:47 ` Liu, Jinsong
2014-02-18 4:25 ` Liu, Jinsong
2014-02-18 9:41 ` Jan Beulich
2014-02-18 10:52 ` Liu, Jinsong
2014-02-18 11:02 ` Jan Beulich
2014-02-18 11:42 ` Liu, Jinsong
2014-02-18 12:36 ` Jan Beulich
2014-02-18 12:42 ` Liu, Jinsong
2014-02-18 16:23 ` Aravind Gopalakrishnan
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