From: Steven Price <steven.price@arm.com> To: Robin Murphy <robin.murphy@arm.com>, will@kernel.org Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 08/10] iommu/io-pgtable-arm: Rationalise TTBRn handling Date: Mon, 28 Oct 2019 15:09:24 +0000 [thread overview] Message-ID: <5324d888-857a-b07c-439c-4ae4ea3a9784@arm.com> (raw) In-Reply-To: <74ada0e6c488a2310206a553eb108cc28fd52457.1572024120.git.robin.murphy@arm.com> On 25/10/2019 19:08, Robin Murphy wrote: > TTBR1 values have so far been redundant since no users implement any > support for split address spaces. Crucially, though, one of the main > reasons for wanting to do so is to be able to manage each half entirely > independently, e.g. context-switching one set of mappings without > disturbing the other. Thus it seems unlikely that tying two tables > together in a single io_pgtable_cfg would ever be particularly desirable > or useful. > > Streamline the configs to just a single conceptual TTBR value > representing the allocated table. This paves the way for future users to > support split address spaces by simply allocating a table and dealing > with the detailed TTBRn logistics themselves. > > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > --- > drivers/iommu/arm-smmu-v3.c | 2 +- > drivers/iommu/arm-smmu.c | 9 ++++----- > drivers/iommu/io-pgtable-arm-v7s.c | 16 +++++++--------- > drivers/iommu/io-pgtable-arm.c | 5 ++--- > drivers/iommu/ipmmu-vmsa.c | 2 +- > drivers/iommu/msm_iommu.c | 4 ++-- > drivers/iommu/mtk_iommu.c | 4 ++-- > drivers/iommu/qcom_iommu.c | 3 +-- > include/linux/io-pgtable.h | 4 ++-- > 9 files changed, 22 insertions(+), 27 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 3f20e548f1ec..da31e607698f 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -2170,7 +2170,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > } > > cfg->cd.asid = (u16)asid; > - cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; > return 0; > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 2bc3e93b11e6..a249e4e49ead 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -534,13 +534,12 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > /* TTBRs */ > if (stage1) { > if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { > - cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; > - cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; > + cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; > + cb->ttbr[1] = 0; > } else { > - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid); > - cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; > - cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid); > + cb->ttbr[1] = FIELD_PREP(TTBRn_ASID, cfg->asid); > } > } else { > cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index 7c3bd2c3cdca..4d2c1e7f67c4 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -822,15 +822,13 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > /* Ensure the empty pgd is visible before any actual TTBR write */ > wmb(); > > - /* TTBRs */ > - cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | > - ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS | > - (cfg->coherent_walk ? > - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | > - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : > - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | > - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); > - cfg->arm_v7s_cfg.ttbr[1] = 0; > + /* TTBR */ > + cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | > + (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS | > + ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | > + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : > + (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | > + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); ARM_V7S_TTBR_NOS seems to have sneaked into the cfg->coherent_walk condition here - which you haven't mentioned in the commit log, so it doesn't look like it should be in this commit. Steve > return &data->iop; > > out_free_data: > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c > index 1795df8f7a51..bc0841040ebe 100644 > --- a/drivers/iommu/io-pgtable-arm.c > +++ b/drivers/iommu/io-pgtable-arm.c > @@ -872,9 +872,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) > /* Ensure the empty pgd is visible before any actual TTBR write */ > wmb(); > > - /* TTBRs */ > - cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); > - cfg->arm_lpae_s1_cfg.ttbr[1] = 0; > + /* TTBR */ > + cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); > return &data->iop; > > out_free_data: > diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c > index e4da6efbda49..4fe0ff3216ce 100644 > --- a/drivers/iommu/ipmmu-vmsa.c > +++ b/drivers/iommu/ipmmu-vmsa.c > @@ -416,7 +416,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) > u32 tmp; > > /* TTBR0 */ > - ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; > + ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; > ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); > ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); > > diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c > index be99d408cf35..9ceec140fa67 100644 > --- a/drivers/iommu/msm_iommu.c > +++ b/drivers/iommu/msm_iommu.c > @@ -279,8 +279,8 @@ static void __program_context(void __iomem *base, int ctx, > SET_V2PCFG(base, ctx, 0x3); > > SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); > - SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); > - SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); > + SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); > + SET_TTBR1(base, ctx, 0); > > /* Set prrr and nmrr */ > SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 67a483c1a935..ef0b36eeb83d 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -392,7 +392,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, > /* Update the pgtable base address register of the M4U HW */ > if (!data->m4u_dom) { > data->m4u_dom = dom; > - writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, > + writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, > data->base + REG_MMU_PT_BASE_ADDR); > } > > @@ -797,7 +797,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); > writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); > if (m4u_dom) > - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, > + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, > base + REG_MMU_PT_BASE_ADDR); > return 0; > } > diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c > index 66e9b40e9275..9a57eb6c253c 100644 > --- a/drivers/iommu/qcom_iommu.c > +++ b/drivers/iommu/qcom_iommu.c > @@ -269,10 +269,9 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, > > /* TTBRs */ > iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > - pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | > + pgtbl_cfg.arm_lpae_s1_cfg.ttbr | > FIELD_PREP(TTBRn_ASID, ctx->asid)); > iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, > - pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | > FIELD_PREP(TTBRn_ASID, ctx->asid)); > > /* TCR */ > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index ee21eedafe98..53bca5343f52 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -100,7 +100,7 @@ struct io_pgtable_cfg { > /* Low-level data specific to the table format */ > union { > struct { > - u64 ttbr[2]; > + u64 ttbr; > u64 tcr; > u64 mair; > } arm_lpae_s1_cfg; > @@ -111,7 +111,7 @@ struct io_pgtable_cfg { > } arm_lpae_s2_cfg; > > struct { > - u32 ttbr[2]; > + u32 ttbr; > u32 tcr; > u32 nmrr; > u32 prrr; > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Steven Price <steven.price@arm.com> To: Robin Murphy <robin.murphy@arm.com>, will@kernel.org Cc: iommu@lists.linux-foundation.org, jcrouse@codeaurora.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 08/10] iommu/io-pgtable-arm: Rationalise TTBRn handling Date: Mon, 28 Oct 2019 15:09:24 +0000 [thread overview] Message-ID: <5324d888-857a-b07c-439c-4ae4ea3a9784@arm.com> (raw) In-Reply-To: <74ada0e6c488a2310206a553eb108cc28fd52457.1572024120.git.robin.murphy@arm.com> On 25/10/2019 19:08, Robin Murphy wrote: > TTBR1 values have so far been redundant since no users implement any > support for split address spaces. Crucially, though, one of the main > reasons for wanting to do so is to be able to manage each half entirely > independently, e.g. context-switching one set of mappings without > disturbing the other. Thus it seems unlikely that tying two tables > together in a single io_pgtable_cfg would ever be particularly desirable > or useful. > > Streamline the configs to just a single conceptual TTBR value > representing the allocated table. This paves the way for future users to > support split address spaces by simply allocating a table and dealing > with the detailed TTBRn logistics themselves. > > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > --- > drivers/iommu/arm-smmu-v3.c | 2 +- > drivers/iommu/arm-smmu.c | 9 ++++----- > drivers/iommu/io-pgtable-arm-v7s.c | 16 +++++++--------- > drivers/iommu/io-pgtable-arm.c | 5 ++--- > drivers/iommu/ipmmu-vmsa.c | 2 +- > drivers/iommu/msm_iommu.c | 4 ++-- > drivers/iommu/mtk_iommu.c | 4 ++-- > drivers/iommu/qcom_iommu.c | 3 +-- > include/linux/io-pgtable.h | 4 ++-- > 9 files changed, 22 insertions(+), 27 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 3f20e548f1ec..da31e607698f 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -2170,7 +2170,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > } > > cfg->cd.asid = (u16)asid; > - cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; > return 0; > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 2bc3e93b11e6..a249e4e49ead 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -534,13 +534,12 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > /* TTBRs */ > if (stage1) { > if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { > - cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; > - cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; > + cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; > + cb->ttbr[1] = 0; > } else { > - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid); > - cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; > - cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid); > + cb->ttbr[1] = FIELD_PREP(TTBRn_ASID, cfg->asid); > } > } else { > cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index 7c3bd2c3cdca..4d2c1e7f67c4 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -822,15 +822,13 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > /* Ensure the empty pgd is visible before any actual TTBR write */ > wmb(); > > - /* TTBRs */ > - cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | > - ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS | > - (cfg->coherent_walk ? > - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | > - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : > - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | > - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); > - cfg->arm_v7s_cfg.ttbr[1] = 0; > + /* TTBR */ > + cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | > + (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS | > + ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | > + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : > + (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | > + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); ARM_V7S_TTBR_NOS seems to have sneaked into the cfg->coherent_walk condition here - which you haven't mentioned in the commit log, so it doesn't look like it should be in this commit. Steve > return &data->iop; > > out_free_data: > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c > index 1795df8f7a51..bc0841040ebe 100644 > --- a/drivers/iommu/io-pgtable-arm.c > +++ b/drivers/iommu/io-pgtable-arm.c > @@ -872,9 +872,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) > /* Ensure the empty pgd is visible before any actual TTBR write */ > wmb(); > > - /* TTBRs */ > - cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); > - cfg->arm_lpae_s1_cfg.ttbr[1] = 0; > + /* TTBR */ > + cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); > return &data->iop; > > out_free_data: > diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c > index e4da6efbda49..4fe0ff3216ce 100644 > --- a/drivers/iommu/ipmmu-vmsa.c > +++ b/drivers/iommu/ipmmu-vmsa.c > @@ -416,7 +416,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) > u32 tmp; > > /* TTBR0 */ > - ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; > + ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; > ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); > ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); > > diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c > index be99d408cf35..9ceec140fa67 100644 > --- a/drivers/iommu/msm_iommu.c > +++ b/drivers/iommu/msm_iommu.c > @@ -279,8 +279,8 @@ static void __program_context(void __iomem *base, int ctx, > SET_V2PCFG(base, ctx, 0x3); > > SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); > - SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); > - SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); > + SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); > + SET_TTBR1(base, ctx, 0); > > /* Set prrr and nmrr */ > SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 67a483c1a935..ef0b36eeb83d 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -392,7 +392,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, > /* Update the pgtable base address register of the M4U HW */ > if (!data->m4u_dom) { > data->m4u_dom = dom; > - writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, > + writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, > data->base + REG_MMU_PT_BASE_ADDR); > } > > @@ -797,7 +797,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); > writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); > if (m4u_dom) > - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, > + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, > base + REG_MMU_PT_BASE_ADDR); > return 0; > } > diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c > index 66e9b40e9275..9a57eb6c253c 100644 > --- a/drivers/iommu/qcom_iommu.c > +++ b/drivers/iommu/qcom_iommu.c > @@ -269,10 +269,9 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, > > /* TTBRs */ > iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > - pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | > + pgtbl_cfg.arm_lpae_s1_cfg.ttbr | > FIELD_PREP(TTBRn_ASID, ctx->asid)); > iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, > - pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | > FIELD_PREP(TTBRn_ASID, ctx->asid)); > > /* TCR */ > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index ee21eedafe98..53bca5343f52 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -100,7 +100,7 @@ struct io_pgtable_cfg { > /* Low-level data specific to the table format */ > union { > struct { > - u64 ttbr[2]; > + u64 ttbr; > u64 tcr; > u64 mair; > } arm_lpae_s1_cfg; > @@ -111,7 +111,7 @@ struct io_pgtable_cfg { > } arm_lpae_s2_cfg; > > struct { > - u32 ttbr[2]; > + u32 ttbr; > u32 tcr; > u32 nmrr; > u32 prrr; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-28 15:09 UTC|newest] Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-25 18:08 [PATCH v2 00/10] iommu/io-pgtable: Cleanup and prep for split tables Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 01/10] iommu/io-pgtable: Make selftest gubbins consistently __init Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 02/10] iommu/io-pgtable-arm: Rationalise size check Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 03/10] iommu/io-pgtable-arm: Simplify bounds checks Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 04/10] iommu/io-pgtable-arm: Simplify start level lookup Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 05/10] iommu/io-pgtable-arm: Simplify PGD size handling Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-25 18:08 ` [PATCH v2 06/10] iommu/io-pgtable-arm: Simplify level indexing Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-11-04 18:17 ` Will Deacon 2019-11-04 18:17 ` Will Deacon 2019-11-04 18:36 ` Robin Murphy 2019-11-04 18:36 ` Robin Murphy 2019-11-04 19:20 ` Will Deacon 2019-11-04 19:20 ` Will Deacon 2019-10-25 18:08 ` [PATCH v2 07/10] iommu/io-pgtable-arm: Rationalise MAIR handling Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-11-04 18:20 ` Will Deacon 2019-11-04 18:20 ` Will Deacon 2019-11-04 18:43 ` Robin Murphy 2019-11-04 18:43 ` Robin Murphy 2019-11-04 19:20 ` Will Deacon 2019-11-04 19:20 ` Will Deacon 2019-11-04 19:57 ` Will Deacon 2019-11-04 19:57 ` Will Deacon 2019-10-25 18:08 ` [PATCH v2 08/10] iommu/io-pgtable-arm: Rationalise TTBRn handling Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-10-28 15:09 ` Steven Price [this message] 2019-10-28 15:09 ` Steven Price 2019-10-28 18:51 ` Robin Murphy 2019-10-28 18:51 ` Robin Murphy 2019-11-04 18:36 ` Will Deacon 2019-11-04 18:36 ` Will Deacon 2019-11-04 19:12 ` Robin Murphy 2019-11-04 19:12 ` Robin Murphy 2019-11-22 22:40 ` Jordan Crouse 2019-11-22 22:40 ` Jordan Crouse 2019-10-25 18:08 ` [PATCH v2 09/10] iommu/io-pgtable-arm: Rationalise TCR handling Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-11-04 19:14 ` Will Deacon 2019-11-04 19:14 ` Will Deacon 2019-11-04 23:27 ` Jordan Crouse 2019-11-04 23:27 ` Jordan Crouse 2019-11-20 15:11 ` Will Deacon 2019-11-22 15:51 ` Robin Murphy 2019-11-22 15:51 ` Robin Murphy 2019-11-25 7:58 ` Will Deacon 2019-11-25 7:58 ` Will Deacon 2019-11-22 22:03 ` Jordan Crouse 2019-11-22 22:03 ` Jordan Crouse 2019-10-25 18:08 ` [PATCH v2 10/10] iommu/io-pgtable-arm: Prepare for TTBR1 usage Robin Murphy 2019-10-25 18:08 ` Robin Murphy 2019-11-04 23:40 ` Jordan Crouse 2019-11-04 23:40 ` Jordan Crouse 2019-11-20 19:18 ` Will Deacon 2019-11-20 19:18 ` Will Deacon 2019-11-22 22:03 ` Jordan Crouse 2019-11-22 22:03 ` Jordan Crouse 2019-11-04 19:22 ` [PATCH v2 00/10] iommu/io-pgtable: Cleanup and prep for split tables Will Deacon 2019-11-04 19:22 ` Will Deacon 2019-11-04 20:20 ` Will Deacon 2019-11-04 20:20 ` Will Deacon 2020-01-10 15:09 ` Will Deacon 2020-01-10 15:09 ` Will Deacon
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