* [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup
@ 2014-03-21 18:28 Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 01/13] ARM: tegra: pinctrl: remove func_safe Stephen Warren
` (12 more replies)
0 siblings, 13 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This series:
a) Removes some unused cruft from the Tegra pinmux drivers.
b) Creates a single implementation of the Tegra pinmux API thus removing
a lot of duplicate code.
c) Auto-generates the Tegra30/114/124 pinmux data from the same data
source used to auto-generate the Linux kernel pinmux drivers. This
ensures that the two SW stacks are consistent. The data source has
also been validated against the TRM, and some issues in the existing
U-Boot data tables are fixed due to this.
(a) and (b) together remove over 1700 lines of code!
So far, I haven't looked at the content of the per-board pinmux config
tables in detail; I've just fixed issues in the drivers. I will be
validating the board configurations next, and will send patches to fix
any issues I find in those too.
Stephen Warren (13):
ARM: tegra: pinctrl: remove func_safe
ARM: tegra: pinctrl: remove vddio
ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
ARM: tegra: prototype pinmux_init() in board.h
ARM: tegra: use apb_misc.h in more places
ARM: tegra: pinctrl: remove duplication
ARM: tegra: reduce public pinmux API
ARM: tegra: pinmux naming consistency fixes
ARM: tegra: use clrsetbits_le32 in pinmux driver
ARM: tegra: Tegra20 pinmux cleanup
ARM: tegra: Tegra30 pinmux cleanup
ARM: tegra: Tegra114 pinmux cleanup
ARM: tegra: Tegra124 pinmux cleanup
arch/arm/cpu/arm720t/tegra-common/spl.c | 6 +-
arch/arm/cpu/arm720t/tegra114/cpu.c | 4 +-
arch/arm/cpu/arm720t/tegra124/cpu.c | 4 +-
arch/arm/cpu/tegra-common/Makefile | 6 +-
arch/arm/cpu/tegra-common/pinmux-common.c | 420 +++++++++
arch/arm/cpu/tegra114-common/funcmux.c | 32 +-
arch/arm/cpu/tegra114-common/pinmux.c | 895 +++++--------------
arch/arm/cpu/tegra124-common/funcmux.c | 38 +-
arch/arm/cpu/tegra124-common/pinmux.c | 898 +++++--------------
arch/arm/cpu/tegra20-common/emc.c | 2 +-
arch/arm/cpu/tegra20-common/funcmux.c | 185 ++--
arch/arm/cpu/tegra20-common/pinmux.c | 416 +++------
arch/arm/cpu/tegra20-common/warmboot.c | 8 +-
arch/arm/cpu/tegra20-common/warmboot_avp.c | 6 +-
arch/arm/cpu/tegra30-common/funcmux.c | 20 +-
arch/arm/cpu/tegra30-common/pinmux.c | 948 ++++++--------------
.../asm/{arch-tegra20 => arch-tegra}/apb_misc.h | 2 +
arch/arm/include/asm/arch-tegra/board.h | 1 +
arch/arm/include/asm/arch-tegra/pinmux.h | 185 ++++
arch/arm/include/asm/arch-tegra114/pinmux.h | 828 ++++++------------
arch/arm/include/asm/arch-tegra124/pinmux.h | 858 +++++++-----------
arch/arm/include/asm/arch-tegra20/pinmux.h | 380 +++-----
arch/arm/include/asm/arch-tegra30/pinmux.h | 955 ++++++++-------------
.../common/pinmux-config-tamonten-ng.h | 492 +++++------
board/avionic-design/common/tamonten-ng.c | 12 +-
board/avionic-design/common/tamonten.c | 4 +-
board/compal/paz00/paz00.c | 22 +-
board/compulab/trimslice/trimslice.c | 4 +-
board/nvidia/cardhu/cardhu.c | 6 +-
board/nvidia/cardhu/pinmux-config-cardhu.h | 498 +++++------
board/nvidia/common/board.c | 8 +-
board/nvidia/dalmore/dalmore.c | 9 +-
board/nvidia/dalmore/pinmux-config-dalmore.h | 388 ++++-----
board/nvidia/harmony/harmony.c | 18 +-
board/nvidia/seaboard/seaboard.c | 6 +-
board/nvidia/venice2/pinmux-config-venice2.h | 360 ++++----
board/nvidia/venice2/venice2.c | 15 +-
.../colibri_t20-common/colibri_t20-common.c | 8 +-
board/toradex/colibri_t20_iris/colibri_t20_iris.c | 4 +-
drivers/spi/tegra20_sflash.c | 6 +-
drivers/video/tegra.c | 4 +-
41 files changed, 3615 insertions(+), 5346 deletions(-)
create mode 100644 arch/arm/cpu/tegra-common/pinmux-common.c
rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h (87%)
create mode 100644 arch/arm/include/asm/arch-tegra/pinmux.h
--
1.8.1.5
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 01/13] ARM: tegra: pinctrl: remove func_safe
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 02/13] ARM: tegra: pinctrl: remove vddio Stephen Warren
` (11 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
v2: No change.
---
arch/arm/cpu/tegra114-common/pinmux.c | 6 ------
arch/arm/cpu/tegra124-common/pinmux.c | 6 ------
arch/arm/cpu/tegra20-common/pinmux.c | 2 --
arch/arm/cpu/tegra30-common/pinmux.c | 6 ------
arch/arm/include/asm/arch-tegra114/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra124/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra20/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra30/pinmux.h | 1 -
8 files changed, 24 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 4983a05090a2..7bf494c49a4d 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -62,7 +61,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -396,10 +394,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
if (func & PMUX_FUNC_RSVD1) {
mux = func & 0x3;
} else {
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index a4ab4eae408f..b1ac59e5b3c9 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -15,7 +15,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -387,10 +385,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
if (func & PMUX_FUNC_RSVD1) {
mux = func & 0x3;
} else {
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index a65e9915194e..1f04d9c7ff7d 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -259,7 +259,6 @@ enum pmux_pullid {
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id;
@@ -294,7 +293,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_ ## f_safe, \
.ctl_id = mux, \
.pull_id = pupd \
}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index eecf0580bc90..6fd424981c23 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -61,7 +60,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -381,10 +379,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
if (func & PMUX_FUNC_RSVD1) {
mux = func & 0x3;
} else {
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 9c22c08b6e30..edf1a89ce111 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -367,7 +367,6 @@ enum pmux_func {
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
- PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_INVALID = 0x4000,
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 9662e2b8aa53..f51f44a54a24 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -374,7 +374,6 @@ enum pmux_func {
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
- PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_INVALID = 0x4000,
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 05925df861da..3374d9c40f12 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -227,7 +227,6 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
- PMUX_FUNC_SAFE,
/* These don't have a name, but can be used in the table */
PMUX_FUNC_RSVD1,
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index a9e1b462c4a1..ff2511e8774f 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -438,7 +438,6 @@ enum pmux_func {
PMUX_FUNC_CPU_PWR_REQ,
PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_CLK_32K_IN,
- PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 02/13] ARM: tegra: pinctrl: remove vddio
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 01/13] ARM: tegra: pinctrl: remove func_safe Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 03/13] ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20 Stephen Warren
` (10 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
v2: No change.
---
arch/arm/cpu/tegra114-common/pinmux.c | 2 --
arch/arm/cpu/tegra124-common/pinmux.c | 2 --
arch/arm/cpu/tegra20-common/pinmux.c | 2 --
arch/arm/cpu/tegra30-common/pinmux.c | 2 --
arch/arm/include/asm/arch-tegra114/pinmux.h | 21 ---------------------
arch/arm/include/asm/arch-tegra124/pinmux.h | 21 ---------------------
arch/arm/include/asm/arch-tegra20/pinmux.h | 15 ---------------
arch/arm/include/asm/arch-tegra30/pinmux.h | 21 ---------------------
8 files changed, 86 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 7bf494c49a4d..e83a29f43a5f 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index b1ac59e5b3c9..921dd2119b10 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -15,7 +15,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 1f04d9c7ff7d..40301e13c29d 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -259,7 +259,6 @@ enum pmux_pullid {
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id;
};
@@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 6fd424981c23..8eca0dd65485 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index edf1a89ce111..93d2ca525cec 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index f51f44a54a24..2042f1f7e5a3 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -458,27 +458,6 @@ enum pmux_pin_rcv_sel {
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 3374d9c40f12..2bfaf53d349d 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -257,21 +257,6 @@ enum pmux_tristate {
PMUX_TRI_TRISTATE = 1,
};
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
-
- PMUX_VDDIO_NONE
-};
-
enum {
PMUX_TRISTATE_REGS = 4,
PMUX_MUX_REGS = 7,
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index ff2511e8774f..0704e4d4d4a1 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -509,27 +509,6 @@ enum pmux_pin_ioreset {
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 03/13] ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 01/13] ARM: tegra: pinctrl: remove func_safe Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 02/13] ARM: tegra: pinctrl: remove vddio Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 04/13] ARM: tegra: prototype pinmux_init() in board.h Stephen Warren
` (9 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
For consistency with other SoCs, modify Tegra20's enum pmux_func to:
* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0;
this will be assumed by pinmux_set_func() in a future patch.
Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
v2: No change.
---
arch/arm/cpu/tegra20-common/pinmux.c | 4 +++-
arch/arm/include/asm/arch-tegra20/pinmux.h | 17 +++++++----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 40301e13c29d..14467f01f547 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -307,7 +307,9 @@ struct tegra_pingroup_desc {
/* A pin group number which is not used */
#define PIN_RESERVED \
- PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
+ PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
+
+#define PMUX_FUNC_RSVD ((enum pmux_func)-1)
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 2bfaf53d349d..1980201ce8cc 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -228,21 +228,18 @@ enum pmux_func {
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
- /* These don't have a name, but can be used in the table */
- PMUX_FUNC_RSVD1,
- PMUX_FUNC_RSVD2,
- PMUX_FUNC_RSVD3,
- PMUX_FUNC_RSVD4,
- PMUX_FUNC_RSVD, /* Not valid and should not be used */
-
PMUX_FUNC_COUNT,
- PMUX_FUNC_NONE = -1,
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
};
/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
- (func) != PMUX_FUNC_RSVD)
+#define pmux_func_isvalid(func) \
+ ((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) ||\
+ (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 04/13] ARM: tegra: prototype pinmux_init() in board.h
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (2 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 03/13] ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20 Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places Stephen Warren
` (8 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
pinmux_init() is a board-level function, not a pinmux driver function.
Move the prototype to a board header rather than the driver header.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
v2: No change.
---
arch/arm/include/asm/arch-tegra/board.h | 1 +
arch/arm/include/asm/arch-tegra114/pinmux.h | 3 ---
arch/arm/include/asm/arch-tegra124/pinmux.h | 3 ---
arch/arm/include/asm/arch-tegra30/pinmux.h | 3 ---
board/nvidia/common/board.c | 8 ++++++--
5 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 0e698644a0a1..ff773646cbec 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -24,6 +24,7 @@ void gpio_early_init(void); /* overrideable GPIO config */
* an empty stub function will be called.
*/
+void pinmux_init(void); /* overrideable general pinmux setup */
void pin_mux_usb(void); /* overrideable USB pinmux setup */
void pin_mux_spi(void); /* overrideable SPI pinmux setup */
void pin_mux_nand(void); /* overrideable NAND pinmux setup */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 93d2ca525cec..a06b24f412ee 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -580,9 +580,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 2042f1f7e5a3..900cf4462264 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -584,9 +584,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 0704e4d4d4a1..1449f53b333e 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -632,9 +632,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 3b18e28cc4fe..d3d7bbd19598 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -48,6 +48,12 @@ const struct tegra_sysinfo sysinfo = {
CONFIG_TEGRA_BOARD_STRING
};
+void __pinmux_init(void)
+{
+}
+
+void pinmux_init(void) __attribute__((weak, alias("__pinmux_init")));
+
void __pin_mux_usb(void)
{
}
@@ -176,9 +182,7 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
int board_early_init_f(void)
{
-#if !defined(CONFIG_TEGRA20)
pinmux_init();
-#endif
board_init_uart_f();
/* Initialize periph GPIOs */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (3 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 04/13] ARM: tegra: prototype pinmux_init() in board.h Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:17 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication Stephen Warren
` (7 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
Tegra's "APB misc" register region contains various miscellaneous
registers and the Tegra pinmux registers. Some code that touches the
misc registers currently uses struct pmux_tri_ctlr, which is intended to
be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
which is intended to be a definition of the miscellaneous registers.
Convert all such code to use struct apb_misc_pp_ctrl, since struct
pmux_tri_ctlr goes away in the next patch.
This requires adding a missing field definition to struct
apb_misc_pp_ctrl, and moving the header into a more common location.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
V2: New patch
---
arch/arm/cpu/arm720t/tegra-common/spl.c | 6 ++++--
arch/arm/cpu/tegra20-common/emc.c | 2 +-
arch/arm/cpu/tegra20-common/warmboot.c | 8 +++++---
arch/arm/cpu/tegra20-common/warmboot_avp.c | 6 ++++--
arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h | 2 ++
5 files changed, 16 insertions(+), 8 deletions(-)
rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h (87%)
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
index 5171a8f907a1..3479541020b4 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -13,16 +13,18 @@
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h>
#include "cpu.h"
void spl_board_init(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */
- writel(0xC0, &pmt->pmt_cfg_ctl);
+ writel(0xC0, &apb_misc->cfg_ctl);
board_init_uart_f();
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c
index 934e39595586..ed2462ab0fa6 100644
--- a/arch/arm/cpu/tegra20-common/emc.c
+++ b/arch/arm/cpu/tegra20-common/emc.c
@@ -8,7 +8,7 @@
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
-#include <asm/arch/apb_misc.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/tegra.h>
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 8beba53fc357..5fdc4bbb5007 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -15,6 +15,7 @@
#include <asm/arch/sdram_param.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/fuse.h>
@@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void)
{
u32 ram_code;
struct sdram_params sdram;
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
@@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void)
union fbio_spare_reg fbio_spare;
/* get ram code that is used as index to array sdram_params in BCT */
- ram_code = (readl(&pmt->pmt_strap_opt_a) >>
- STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+ ram_code = (readl(&apb_misc->strapping_opt_a) >>
+ STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
memcpy(&sdram,
(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
sizeof(sdram));
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c
index b910f7844bb6..27ce5f480f54 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -12,6 +12,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/warmboot.h>
@@ -21,7 +22,8 @@
void wb_start(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
@@ -33,7 +35,7 @@ void wb_start(void)
u32 reg;
/* enable JTAG & TBE */
- writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
+ writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */
asm volatile (
diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h
similarity index 87%
rename from arch/arm/include/asm/arch-tegra20/apb_misc.h
rename to arch/arm/include/asm/arch-tegra/apb_misc.h
index f314f5acc38e..a5bc092ffdc1 100644
--- a/arch/arm/include/asm/arch-tegra20/apb_misc.h
+++ b/arch/arm/include/asm/arch-tegra/apb_misc.h
@@ -11,6 +11,8 @@
struct apb_misc_pp_ctlr {
u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+ u32 reserved1[6]; /* 0x0c .. 0x20 */
+ u32 cfg_ctl; /* 0x24 */
};
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (4 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:23 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 07/13] ARM: tegra: reduce public pinmux API Stephen Warren
` (6 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
duplication by creating pinmux-common.c for all the identical code.
This leaves:
* arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
the various pins/pin groups, drive groups, and mux functions.
* arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
stating which pin groups support which mux functions.
The code in pinmux-common.c is semantically identical to that in the
various original pinmux.c, but had some consistency and cleanup fixes
applied during migration.
I removed the definition of struct pmux_tri_ctlr, since this is different
between SoCs (especially Tegra20 vs all others), and it's much simpler to
deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
and warmboot_avp.c needed updates due to this, since they previously
hijacked this struct to encode the location of some non-pinmux registers.
Now, that code simply calculates these register addresses directly using
simple and obvious math. I like this method better irrespective of the
pinmux code cleanup anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Made tegra*_pingroups[] static, since they don't need to be public.
---
arch/arm/cpu/tegra-common/Makefile | 6 +-
arch/arm/cpu/tegra-common/pinmux-common.c | 507 ++++++++++++++++++++++++++++
arch/arm/cpu/tegra114-common/pinmux.c | 430 +----------------------
arch/arm/cpu/tegra124-common/pinmux.c | 429 +----------------------
arch/arm/cpu/tegra20-common/pinmux.c | 124 +------
arch/arm/cpu/tegra30-common/pinmux.c | 400 +---------------------
arch/arm/include/asm/arch-tegra/pinmux.h | 189 +++++++++++
arch/arm/include/asm/arch-tegra114/pinmux.h | 219 +-----------
arch/arm/include/asm/arch-tegra124/pinmux.h | 216 +-----------
arch/arm/include/asm/arch-tegra20/pinmux.h | 85 +----
arch/arm/include/asm/arch-tegra30/pinmux.h | 199 +----------
11 files changed, 732 insertions(+), 2072 deletions(-)
create mode 100644 arch/arm/cpu/tegra-common/pinmux-common.c
create mode 100644 arch/arm/include/asm/arch-tegra/pinmux.h
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 34d57349afb5..892556e64451 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -7,6 +7,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += ap.o
+obj-y += board.o
+obj-y += cache.o
+obj-y += clock.o
obj-y += lowlevel_init.o
-obj-y += ap.o board.o clock.o cache.o
+obj-y += pinmux-common.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
new file mode 100644
index 000000000000..10f68ba98b52
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+ ((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) || \
+ (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) \
+ (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
+
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+ (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) \
+ (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) \
+ (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) \
+ (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+ (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
+ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
+
+#if defined(CONFIG_TEGRA20)
+
+#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
+#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
+
+#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
+#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
+
+#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
+#define TRI_SHIFT(grp) ((grp) % 32)
+
+#else
+
+#define REG(pin) _R(0x3000 + ((pin) * 4))
+
+#define MUX_REG(pin) REG(pin)
+#define MUX_SHIFT(pin) 0
+
+#define PULL_REG(pin) REG(pin)
+#define PULL_SHIFT(pin) 2
+
+#define TRI_REG(pin) REG(pin)
+#define TRI_SHIFT(pin) 4
+
+#endif /* CONFIG_TEGRA20 */
+
+#define DRV_REG(group) _R(0x868 + ((group) * 4))
+
+#define IO_SHIFT 5
+#define OD_SHIFT 6
+#define LOCK_SHIFT 7
+#define IO_RESET_SHIFT 8
+#define RCV_SEL_SHIFT 9
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ u32 *reg = MUX_REG(pin);
+ int i, mux = -1;
+ u32 val;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ val = readl(reg);
+ val &= ~(3 << MUX_SHIFT(pin));
+ val |= (mux << MUX_SHIFT(pin));
+ writel(val, reg);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ u32 *reg = PULL_REG(pin);
+ u32 val;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ val = readl(reg);
+ val &= ~(3 << PULL_SHIFT(pin));
+ val |= (pupd << PULL_SHIFT(pin));
+ writel(val, reg);
+}
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+{
+ u32 *reg = TRI_REG(pin);
+ u32 val;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_tristate_isvalid(tri));
+
+ val = readl(reg);
+ if (tri == PMUX_TRI_TRISTATE)
+ val |= (1 << TRI_SHIFT(pin));
+ else
+ val &= ~(1 << TRI_SHIFT(pin));
+ writel(val, reg);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
+}
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (io == PMUX_PIN_NONE)
+ return;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ val = readl(reg);
+ if (io == PMUX_PIN_INPUT)
+ val |= (io & 1) << IO_SHIFT;
+ else
+ val &= ~(1 << IO_SHIFT);
+ writel(val, reg);
+}
+
+static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ val = readl(reg);
+ if (lock == PMUX_PIN_LOCK_ENABLE) {
+ val |= (1 << LOCK_SHIFT);
+ } else {
+ if (val & (1 << LOCK_SHIFT))
+ printf("%s: Cannot clear LOCK bit!\n", __func__);
+ val &= ~(1 << LOCK_SHIFT);
+ }
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ val = readl(reg);
+ if (od == PMUX_PIN_OD_ENABLE)
+ val |= (1 << OD_SHIFT);
+ else
+ val &= ~(1 << OD_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ val = readl(reg);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ val |= (1 << IO_RESET_SHIFT);
+ else
+ val &= ~(1 << IO_RESET_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
+ enum pmux_pin_rcv_sel rcv_sel)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+ return;
+
+ /* Error check on pin and rcv_sel */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+ val = readl(reg);
+ if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+ val |= (1 << RCV_SEL_SHIFT);
+ else
+ val &= ~(1 << RCV_SEL_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+void pinmux_config_pingroup(const struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+ pinmux_set_rcv_sel(pin, config->rcv_sel);
+#endif
+#endif
+}
+
+void pinmux_config_table(const struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
+
+#ifdef TEGRA_PMX_HAS_PADGRPS
+
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+#define pmux_pad_slw_isvalid(slw) \
+ (((slw) >= PGRP_SLWF_MIN) && ((slw) <= PGRP_SLWF_MAX))
+
+#define pmux_pad_drv_isvalid(drv) \
+ (((drv) >= PGRP_DRVUP_MIN) && ((drv) <= PGRP_DRVUP_MAX))
+
+#define pmux_pad_lpmd_isvalid(lpm) \
+ (((lpm) >= PGRP_LPMD_X8) && ((lpm) <= PGRP_LPMD_X))
+
+#define pmux_pad_schmt_isvalid(schmt) \
+ (((schmt) >= PGRP_SCHMT_DISABLE) && ((schmt) <= PGRP_SCHMT_ENABLE))
+
+#define pmux_pad_hsm_isvalid(hsm) \
+ (((hsm) >= PGRP_HSM_DISABLE) && ((hsm) <= PGRP_HSM_ENABLE))
+
+#define HSM_SHIFT 2
+#define SCHMT_SHIFT 3
+#define LPMD_SHIFT 4
+#define LPMD_MASK (3 << LPMD_SHIFT)
+#define DRVDN_SHIFT 12
+#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
+#define DRVUP_SHIFT 20
+#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
+#define SLWR_SHIFT 28
+#define SLWR_MASK (3 << SLWR_SHIFT)
+#define SLWF_SHIFT 30
+#define SLWF_MASK (3 << SLWF_SHIFT)
+
+static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ val = readl(reg);
+ val &= ~SLWF_MASK;
+ val |= (slwf << SLWF_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_drvdn_slwr(enum pdrive_pingrp grp, int slwr)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ val = readl(reg);
+ val &= ~SLWR_MASK;
+ val |= (slwr << SLWR_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_drvup(enum pdrive_pingrp grp, int drvup)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ val = readl(reg);
+ val &= ~DRVUP_MASK;
+ val |= (drvup << DRVUP_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_drvdn(enum pdrive_pingrp grp, int drvdn)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ val = readl(reg);
+ val &= ~DRVDN_MASK;
+ val |= (drvdn << DRVDN_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_lpmd(enum pdrive_pingrp grp, enum pgrp_lpmd lpmd)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PGRP_LPMD_NONE)
+ return;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_lpmd_isvalid(lpmd));
+
+ val = readl(reg);
+ val &= ~LPMD_MASK;
+ val |= (lpmd << LPMD_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_schmt(enum pdrive_pingrp grp, enum pgrp_schmt schmt)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PGRP_SCHMT_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_schmt_isvalid(schmt));
+
+ val = readl(reg);
+ if (schmt == PGRP_SCHMT_ENABLE)
+ val |= (1 << SCHMT_SHIFT);
+ else
+ val &= ~(1 << SCHMT_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padgrp_set_hsm(enum pdrive_pingrp grp, enum pgrp_hsm hsm)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PGRP_HSM_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(grp));
+ assert(pmux_pad_hsm_isvalid(hsm));
+
+ val = readl(reg);
+ if (hsm == PGRP_HSM_ENABLE)
+ val |= (1 << HSM_SHIFT);
+ else
+ val &= ~(1 << HSM_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void padctrl_config_pingroup(const struct padctrl_config *config)
+{
+ enum pdrive_pingrp grp = config->padgrp;
+
+ padgrp_set_drvup_slwf(grp, config->slwf);
+ padgrp_set_drvdn_slwr(grp, config->slwr);
+ padgrp_set_drvup(grp, config->drvup);
+ padgrp_set_drvdn(grp, config->drvdn);
+ padgrp_set_lpmd(grp, config->lpmd);
+ padgrp_set_schmt(grp, config->schmt);
+ padgrp_set_hsm(grp, config->hsm);
+}
+
+void padgrp_config_table(const struct padctrl_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ padctrl_config_pingroup(&config[i]);
+}
+#endif /* TEGRA_PMX_HAS_PADGRPS */
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index e83a29f43a5f..5076717592eb 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -18,38 +18,8 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-#define PMUX_RCV_SEL_SHIFT 9
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
@@ -59,7 +29,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .io = PMUX_PIN_ ## iod, \
}
/* Input and output pins */
@@ -72,7 +41,7 @@ struct tegra_pingroup_desc {
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+static const struct tegra_pingroup_desc tegra114_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -334,399 +303,4 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved by t114: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE)
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return 0;
-
- reg = readl(pin_rcv_sel);
- reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
- writel(reg, pin_rcv_sel);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PGRP_SCHMT_NONE)
- return 0;
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PGRP_HSM_NONE)
- return 0;
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index 921dd2119b10..137f3de96be0 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -9,38 +9,8 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-#define PMUX_RCV_SEL_SHIFT 9
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
@@ -50,7 +20,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .io = PMUX_PIN_ ## iod, \
}
/* Input and output pins */
@@ -63,7 +32,7 @@ struct tegra_pingroup_desc {
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+static const struct tegra_pingroup_desc tegra124_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -325,398 +294,4 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE) {
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- } else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return 0;
-
- reg = readl(pin_rcv_sel);
- reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
- writel(reg, pin_rcv_sel);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PGRP_SCHMT_NONE)
- return 0;
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PGRP_HSM_NONE)
- return 0;
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 14467f01f547..9e34c8bec075 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -8,10 +8,8 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-
/*
* This defines the order of the pin mux control bits in the registers. For
* some reason there is no correspendence between the tristate, pin mux and
@@ -256,32 +254,6 @@ enum pmux_pullid {
PUCTL_NONE = -1
};
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_ctlid ctl_id;
- enum pmux_pullid pull_id;
-};
-
-
-/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
-#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
-
-/* Mask value for a tristate (within TRISTATE_REG(id)) */
-#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
-
-/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
-#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
-
-/* Converts a PUCTL id to a shift position */
-#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
-
-/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
-#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
-
-/* Converts a MUXCTL id to a shift position */
-#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
-
/* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
{ \
@@ -309,9 +281,9 @@ struct tegra_pingroup_desc {
#define PIN_RESERVED \
PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
-#define PMUX_FUNC_RSVD ((enum pmux_func)-1)
+#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+static const struct tegra_pingroup_desc tegra20_pingroups[] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
@@ -462,94 +434,4 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
- u32 reg;
-
- reg = readl(tri);
- if (enable)
- reg |= TRISTATE_MASK(pin);
- else
- reg &= ~TRISTATE_MASK(pin);
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
- u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
- u32 mask_bit;
- u32 reg;
- mask_bit = PULL_SHIFT(pull_id);
-
- reg = readl(pull);
- reg &= ~(0x3 << mask_bit);
- reg |= pupd << mask_bit;
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
- u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
- u32 mask_bit;
- int i, mux = -1;
- u32 reg;
-
- assert(pmux_func_isvalid(func));
-
- /* Handle special values */
- if (func >= PMUX_FUNC_RSVD1) {
- mux = (func - PMUX_FUNC_RSVD1) & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- mask_bit = MUXCTL_SHIFT(mux_id);
- reg = readl(muxctl);
- reg &= ~(0x3 << mask_bit);
- reg |= mux << mask_bit;
- writel(reg, muxctl);
-}
-
-void pinmux_config_pingroup(const struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
-}
-
-void pinmux_config_table(const struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
+const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 8eca0dd65485..a12b0767f2c1 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -18,39 +18,10 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
.funcs = { \
PMUX_FUNC_ ## f0, \
@@ -58,7 +29,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .io = PMUX_PIN_ ## iod, \
}
/* Input and output pins */
@@ -67,7 +37,7 @@ struct tegra_pingroup_desc {
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -319,368 +289,4 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE)
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
- int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad,
- enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra30_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
new file mode 100644
index 000000000000..e97fffdcf87b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
+};
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+ enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
+ /* VIL/VIH receivers */
+#endif
+#endif
+};
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(const struct pingroup_config *config);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(const struct pingroup_config *config, int len);
+
+#ifdef TEGRA_PMX_HAS_PADGRPS
+
+#define PGRP_SLWF_MIN 0
+#define PGRP_SLWF_MAX 3
+#define PGRP_SLWF_NONE -1
+
+#define PGRP_SLWR_MIN 0
+#define PGRP_SLWR_MAX 3
+#define PGRP_SLWR_NONE -1
+
+#define PGRP_DRVUP_MIN 0
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVUP_NONE -1
+
+#define PGRP_DRVDN_MIN 0
+#define PGRP_DRVDN_MAX 127
+#define PGRP_DRVDN_NONE -1
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+ PGRP_LPMD_X8 = 0,
+ PGRP_LPMD_X4,
+ PGRP_LPMD_X2,
+ PGRP_LPMD_X,
+ PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+ PGRP_SCHMT_DISABLE = 0,
+ PGRP_SCHMT_ENABLE = 1,
+ PGRP_SCHMT_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+ PGRP_HSM_DISABLE = 0,
+ PGRP_HSM_ENABLE = 1,
+ PGRP_HSM_NONE = -1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+ enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+ int slwf; /* falling edge slew */
+ int slwr; /* rising edge slew */
+ int drvup; /* pull-up drive strength */
+ int drvdn; /* pull-down drive strength */
+ enum pgrp_lpmd lpmd; /* low-power mode selection */
+ enum pgrp_schmt schmt; /* schmidt enable */
+ enum pgrp_hsm hsm; /* high-speed mode enable */
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void padgrp_config_table(const struct padctrl_config *config, int len);
+
+#endif /* TEGRA_PMX_HAS_PADGRPS */
+
+struct tegra_pingroup_desc {
+ enum pmux_func funcs[4];
+#if defined(CONFIG_TEGRA20)
+ u32 ctl_id;
+ u32 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct tegra_pingroup_desc *tegra_soc_pingroups;
+
+#endif /* _TEGRA_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index a06b24f412ee..00ef5423547d 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -367,7 +367,7 @@ enum pmux_func {
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
- PMUX_FUNC_MAX,
+ PMUX_FUNC_COUNT,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
@@ -376,216 +376,9 @@ enum pmux_func {
PMUX_FUNC_RSVD4 = 0x8003,
};
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_PADGRPS
+#include <asm/arch-tegra/pinmux.h>
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
-};
-
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
-
-#endif /* _TEGRA114_PINMUX_H_ */
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 900cf4462264..2c6f0d8e60fc 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -374,7 +374,7 @@ enum pmux_func {
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
- PMUX_FUNC_MAX,
+ PMUX_FUNC_COUNT,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
@@ -383,213 +383,9 @@ enum pmux_func {
PMUX_FUNC_RSVD4 = 0x8003,
};
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
- (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_PADGRPS
+#include <asm/arch-tegra/pinmux.h>
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && \
- ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* Tegra124 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
-};
-
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
-
-#endif /* _TEGRA124_PINMUX_H_ */
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 1980201ce8cc..5517c0783da2 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _PINMUX_H_
-#define _PINMUX_H_
+#ifndef _TEGRA20_PINMUX_H_
+#define _TEGRA20_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
@@ -236,83 +236,6 @@ enum pmux_func {
PMUX_FUNC_RSVD4 = 0x8003,
};
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- ((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) ||\
- (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+#include <asm/arch-tegra/pinmux.h>
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-
-enum {
- PMUX_TRISTATE_REGS = 4,
- PMUX_MUX_REGS = 7,
- PMUX_PULL_REGS = 5,
-};
-
-/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
-
- uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
- uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
- uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
-};
-
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(const struct pingroup_config *config);
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/**
- * Configuure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(const struct pingroup_config *config, int len);
-
-#endif /* PINMUX_H */
+#endif /* _TEGRA20_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 1449f53b333e..e10df76342bb 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -439,7 +439,7 @@ enum pmux_func {
PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_CLK_32K_IN,
- PMUX_FUNC_MAX,
+ PMUX_FUNC_COUNT,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
@@ -447,197 +447,8 @@ enum pmux_func {
PMUX_FUNC_RSVD4 = 0x8003,
};
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_PADGRPS
+#include <asm/arch-tegra/pinmux.h>
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t30 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
-};
-
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
-
-#endif /* _TEGRA30_PINMUX_H_ */
+#endif /* _TEGRA30_PINMUX_H_ */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 07/13] ARM: tegra: reduce public pinmux API
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (5 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes Stephen Warren
` (5 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
Remove a few unused functions from the pinmux header. They aren't
currently used, and removing them prevents any new usage from appearing.
This will ease moving to just pinmux_config_table() and
padgrp_config_table() in the future.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
V2: No change.
---
arch/arm/cpu/tegra-common/pinmux-common.c | 4 ++--
arch/arm/include/asm/arch-tegra/pinmux.h | 6 ------
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
index 10f68ba98b52..51ba6eecdfab 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -131,7 +131,7 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
writel(val, reg);
}
-void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
{
u32 *reg = TRI_REG(pin);
u32 val;
@@ -275,7 +275,7 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-void pinmux_config_pingroup(const struct pingroup_config *config)
+static void pinmux_config_pingroup(const struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index e97fffdcf87b..b8d21c1bf92f 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -86,9 +86,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
@@ -100,9 +97,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin);
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(const struct pingroup_config *config);
-
/**
* Configure a list of pin groups
*
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (6 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 07/13] ARM: tegra: reduce public pinmux API Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:24 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver Stephen Warren
` (4 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
compiles. A separate per-SoC change will be made immediately following,
in order to keep individual patch size down.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
V2: No change.
---
arch/arm/cpu/tegra-common/pinmux-common.c | 122 +++++++++++----------
arch/arm/cpu/tegra114-common/pinmux.c | 4 +-
arch/arm/cpu/tegra124-common/pinmux.c | 4 +-
arch/arm/cpu/tegra20-common/funcmux.c | 6 +-
arch/arm/cpu/tegra20-common/pinmux.c | 4 +-
arch/arm/cpu/tegra30-common/pinmux.c | 4 +-
arch/arm/include/asm/arch-tegra/pinmux.h | 88 +++++++--------
arch/arm/include/asm/arch-tegra114/pinmux.h | 8 +-
arch/arm/include/asm/arch-tegra124/pinmux.h | 8 +-
arch/arm/include/asm/arch-tegra20/pinmux.h | 2 +-
arch/arm/include/asm/arch-tegra30/pinmux.h | 8 +-
.../common/pinmux-config-tamonten-ng.h | 30 ++---
board/avionic-design/common/tamonten-ng.c | 12 +-
board/nvidia/cardhu/cardhu.c | 6 +-
board/nvidia/cardhu/pinmux-config-cardhu.h | 30 ++---
board/nvidia/dalmore/dalmore.c | 9 +-
board/nvidia/dalmore/pinmux-config-dalmore.h | 40 +++----
board/nvidia/venice2/pinmux-config-venice2.h | 40 +++----
board/nvidia/venice2/venice2.c | 15 +--
19 files changed, 223 insertions(+), 217 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
index 51ba6eecdfab..32a46d53f068 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -10,7 +10,7 @@
#include <asm/arch/pinmux.h>
/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) \
@@ -275,9 +275,9 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-static void pinmux_config_pingroup(const struct pingroup_config *config)
+static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
- enum pmux_pingrp pin = config->pingroup;
+ enum pmux_pingrp pin = config->pingrp;
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
@@ -293,32 +293,33 @@ static void pinmux_config_pingroup(const struct pingroup_config *config)
#endif
}
-void pinmux_config_table(const struct pingroup_config *config, int len)
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len)
{
int i;
for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
+ pinmux_config_pingrp(&config[i]);
}
-#ifdef TEGRA_PMX_HAS_PADGRPS
+#ifdef TEGRA_PMX_HAS_DRVGRPS
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
-#define pmux_pad_slw_isvalid(slw) \
- (((slw) >= PGRP_SLWF_MIN) && ((slw) <= PGRP_SLWF_MAX))
+#define pmux_slw_isvalid(slw) \
+ (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
-#define pmux_pad_drv_isvalid(drv) \
- (((drv) >= PGRP_DRVUP_MIN) && ((drv) <= PGRP_DRVUP_MAX))
+#define pmux_drv_isvalid(drv) \
+ (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
-#define pmux_pad_lpmd_isvalid(lpm) \
- (((lpm) >= PGRP_LPMD_X8) && ((lpm) <= PGRP_LPMD_X))
+#define pmux_lpmd_isvalid(lpm) \
+ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
-#define pmux_pad_schmt_isvalid(schmt) \
- (((schmt) >= PGRP_SCHMT_DISABLE) && ((schmt) <= PGRP_SCHMT_ENABLE))
+#define pmux_schmt_isvalid(schmt) \
+ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
-#define pmux_pad_hsm_isvalid(hsm) \
- (((hsm) >= PGRP_HSM_DISABLE) && ((hsm) <= PGRP_HSM_ENABLE))
+#define pmux_hsm_isvalid(hsm) \
+ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#define HSM_SHIFT 2
#define SCHMT_SHIFT 3
@@ -333,18 +334,18 @@ void pinmux_config_table(const struct pingroup_config *config, int len)
#define SLWF_SHIFT 30
#define SLWF_MASK (3 << SLWF_SHIFT)
-static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
+static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
+ if (slwf == PMUX_SLWF_NONE)
return;
/* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_slw_isvalid(slwf));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_slw_isvalid(slwf));
val = readl(reg);
val &= ~SLWF_MASK;
@@ -354,18 +355,18 @@ static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
return;
}
-static void padgrp_set_drvdn_slwr(enum pdrive_pingrp grp, int slwr)
+static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
+ if (slwr == PMUX_SLWR_NONE)
return;
/* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_slw_isvalid(slwr));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_slw_isvalid(slwr));
val = readl(reg);
val &= ~SLWR_MASK;
@@ -375,18 +376,18 @@ static void padgrp_set_drvdn_slwr(enum pdrive_pingrp grp, int slwr)
return;
}
-static void padgrp_set_drvup(enum pdrive_pingrp grp, int drvup)
+static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
+ if (drvup == PMUX_DRVUP_NONE)
return;
/* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_drv_isvalid(drvup));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_drv_isvalid(drvup));
val = readl(reg);
val &= ~DRVUP_MASK;
@@ -396,18 +397,18 @@ static void padgrp_set_drvup(enum pdrive_pingrp grp, int drvup)
return;
}
-static void padgrp_set_drvdn(enum pdrive_pingrp grp, int drvdn)
+static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
+ if (drvdn == PMUX_DRVDN_NONE)
return;
/* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_drv_isvalid(drvdn));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_drv_isvalid(drvdn));
val = readl(reg);
val &= ~DRVDN_MASK;
@@ -417,18 +418,18 @@ static void padgrp_set_drvdn(enum pdrive_pingrp grp, int drvdn)
return;
}
-static void padgrp_set_lpmd(enum pdrive_pingrp grp, enum pgrp_lpmd lpmd)
+static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
+ if (lpmd == PMUX_LPMD_NONE)
return;
/* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_lpmd_isvalid(lpmd));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_lpmd_isvalid(lpmd));
val = readl(reg);
val &= ~LPMD_MASK;
@@ -438,21 +439,21 @@ static void padgrp_set_lpmd(enum pdrive_pingrp grp, enum pgrp_lpmd lpmd)
return;
}
-static void padgrp_set_schmt(enum pdrive_pingrp grp, enum pgrp_schmt schmt)
+static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (schmt == PGRP_SCHMT_NONE)
+ if (schmt == PMUX_SCHMT_NONE)
return;
/* Error check pad */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_schmt_isvalid(schmt));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_schmt_isvalid(schmt));
val = readl(reg);
- if (schmt == PGRP_SCHMT_ENABLE)
+ if (schmt == PMUX_SCHMT_ENABLE)
val |= (1 << SCHMT_SHIFT);
else
val &= ~(1 << SCHMT_SHIFT);
@@ -461,21 +462,21 @@ static void padgrp_set_schmt(enum pdrive_pingrp grp, enum pgrp_schmt schmt)
return;
}
-static void padgrp_set_hsm(enum pdrive_pingrp grp, enum pgrp_hsm hsm)
+static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
- if (hsm == PGRP_HSM_NONE)
+ if (hsm == PMUX_HSM_NONE)
return;
/* Error check pad */
- assert(pmux_padgrp_isvalid(grp));
- assert(pmux_pad_hsm_isvalid(hsm));
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_hsm_isvalid(hsm));
val = readl(reg);
- if (hsm == PGRP_HSM_ENABLE)
+ if (hsm == PMUX_HSM_ENABLE)
val |= (1 << HSM_SHIFT);
else
val &= ~(1 << HSM_SHIFT);
@@ -484,24 +485,25 @@ static void padgrp_set_hsm(enum pdrive_pingrp grp, enum pgrp_hsm hsm)
return;
}
-static void padctrl_config_pingroup(const struct padctrl_config *config)
+static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
{
- enum pdrive_pingrp grp = config->padgrp;
-
- padgrp_set_drvup_slwf(grp, config->slwf);
- padgrp_set_drvdn_slwr(grp, config->slwr);
- padgrp_set_drvup(grp, config->drvup);
- padgrp_set_drvdn(grp, config->drvdn);
- padgrp_set_lpmd(grp, config->lpmd);
- padgrp_set_schmt(grp, config->schmt);
- padgrp_set_hsm(grp, config->hsm);
+ enum pmux_drvgrp grp = config->drvgrp;
+
+ pinmux_set_drvup_slwf(grp, config->slwf);
+ pinmux_set_drvdn_slwr(grp, config->slwr);
+ pinmux_set_drvup(grp, config->drvup);
+ pinmux_set_drvdn(grp, config->drvdn);
+ pinmux_set_lpmd(grp, config->lpmd);
+ pinmux_set_schmt(grp, config->schmt);
+ pinmux_set_hsm(grp, config->hsm);
}
-void padgrp_config_table(const struct padctrl_config *config, int len)
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+ int len)
{
int i;
for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
+ pinmux_config_drvgrp(&config[i]);
}
-#endif /* TEGRA_PMX_HAS_PADGRPS */
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 5076717592eb..5d3d4d52e8a1 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -41,7 +41,7 @@
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
-static const struct tegra_pingroup_desc tegra114_pingroups[PINGRP_COUNT] = {
+static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -303,4 +303,4 @@ static const struct tegra_pingroup_desc tegra114_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved by t114: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
-const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra114_pingroups;
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index 137f3de96be0..a2385653055c 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -32,7 +32,7 @@
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
-static const struct tegra_pingroup_desc tegra124_pingroups[PINGRP_COUNT] = {
+static const struct pmux_pingrp_desc tegra124_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -294,4 +294,4 @@ static const struct tegra_pingroup_desc tegra124_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
-const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra124_pingroups;
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c
index 1931908199d1..8ae28672499a 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -16,7 +16,7 @@
#define PINMUX(grp, mux, pupd, tri) \
{PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
-static const struct pingroup_config disp1_default[] = {
+static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
PINMUX(LHP0, DISPA, NORMAL, NORMAL),
PINMUX(LHP1, DISPA, NORMAL, NORMAL),
@@ -275,8 +275,8 @@ int funcmux_select(enum periph_id id, int config)
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
}
- pinmux_config_table(disp1_default,
- ARRAY_SIZE(disp1_default));
+ pinmux_config_pingrp_table(disp1_default,
+ ARRAY_SIZE(disp1_default));
}
break;
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 9e34c8bec075..4c8999500641 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -283,7 +283,7 @@ enum pmux_pullid {
#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
-static const struct tegra_pingroup_desc tegra20_pingroups[] = {
+static const struct pmux_pingrp_desc tegra20_pingroups[] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
@@ -434,4 +434,4 @@ static const struct tegra_pingroup_desc tegra20_pingroups[] = {
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
};
-const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra20_pingroups;
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index a12b0767f2c1..f1d199321aca 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -37,7 +37,7 @@
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
+static const struct pmux_pingrp_desc tegra30_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@@ -289,4 +289,4 @@ static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
};
-const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra30_pingroups;
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index b8d21c1bf92f..80b804694aee 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -63,16 +63,16 @@ enum pmux_pin_rcv_sel {
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
+struct pmux_pingrp_config {
+ enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */
+ enum pmux_func func; /* function to assign PMUX_FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
#ifdef TEGRA_PMX_HAS_RCV_SEL
enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
/* VIL/VIH receivers */
@@ -103,61 +103,62 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
* @param config List of config items
* @param len Number of config items in list
*/
-void pinmux_config_table(const struct pingroup_config *config, int len);
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len);
-#ifdef TEGRA_PMX_HAS_PADGRPS
+#ifdef TEGRA_PMX_HAS_DRVGRPS
-#define PGRP_SLWF_MIN 0
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWF_NONE -1
+#define PMUX_SLWF_MIN 0
+#define PMUX_SLWF_MAX 3
+#define PMUX_SLWF_NONE -1
-#define PGRP_SLWR_MIN 0
-#define PGRP_SLWR_MAX 3
-#define PGRP_SLWR_NONE -1
+#define PMUX_SLWR_MIN 0
+#define PMUX_SLWR_MAX 3
+#define PMUX_SLWR_NONE -1
-#define PGRP_DRVUP_MIN 0
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVUP_NONE -1
+#define PMUX_DRVUP_MIN 0
+#define PMUX_DRVUP_MAX 127
+#define PMUX_DRVUP_NONE -1
-#define PGRP_DRVDN_MIN 0
-#define PGRP_DRVDN_MAX 127
-#define PGRP_DRVDN_NONE -1
+#define PMUX_DRVDN_MIN 0
+#define PMUX_DRVDN_MAX 127
+#define PMUX_DRVDN_NONE -1
/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
+enum pmux_lpmd {
+ PMUX_LPMD_X8 = 0,
+ PMUX_LPMD_X4,
+ PMUX_LPMD_X2,
+ PMUX_LPMD_X,
+ PMUX_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
- PGRP_SCHMT_NONE = -1,
+enum pmux_schmt {
+ PMUX_SCHMT_DISABLE = 0,
+ PMUX_SCHMT_ENABLE = 1,
+ PMUX_SCHMT_NONE = -1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
- PGRP_HSM_NONE = -1,
+enum pmux_hsm {
+ PMUX_HSM_DISABLE = 0,
+ PMUX_HSM_ENABLE = 1,
+ PMUX_HSM_NONE = -1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+struct pmux_drvgrp_config {
+ enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */
int slwf; /* falling edge slew */
int slwr; /* rising edge slew */
int drvup; /* pull-up drive strength */
int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
+ enum pmux_lpmd lpmd; /* low-power mode selection */
+ enum pmux_schmt schmt; /* schmidt enable */
+ enum pmux_hsm hsm; /* high-speed mode enable */
};
/**
@@ -166,11 +167,12 @@ struct padctrl_config {
* @param config List of config items
* @param len Number of config items in list
*/
-void padgrp_config_table(const struct padctrl_config *config, int len);
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+ int len);
-#endif /* TEGRA_PMX_HAS_PADGRPS */
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
-struct tegra_pingroup_desc {
+struct pmux_pingrp_desc {
enum pmux_func funcs[4];
#if defined(CONFIG_TEGRA20)
u32 ctl_id;
@@ -178,6 +180,6 @@ struct tegra_pingroup_desc {
#endif /* CONFIG_TEGRA20 */
};
-extern const struct tegra_pingroup_desc *tegra_soc_pingroups;
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
#endif /* _TEGRA_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 00ef5423547d..070745933503 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -202,10 +202,10 @@ enum pmux_pingrp {
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
- PINGRP_COUNT,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
+enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@@ -244,7 +244,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+ PMUX_DRVGRP_COUNT,
};
/*
@@ -378,7 +378,7 @@ enum pmux_func {
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_PADGRPS
+#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 2c6f0d8e60fc..b37590671202 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -209,10 +209,10 @@ enum pmux_pingrp {
PINGRP_USB_VBUS_EN2,
PINGRP_GPIO_PFF2,
PINGRP_DP_HPD, /* last reg offset = 0x3430 */
- PINGRP_COUNT,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
+enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@@ -251,7 +251,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+ PMUX_DRVGRP_COUNT,
};
/*
@@ -385,7 +385,7 @@ enum pmux_func {
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_PADGRPS
+#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 5517c0783da2..328a3e3224d5 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -159,7 +159,7 @@ enum pmux_pingrp {
PINGRP_XM2C,
PINGRP_XM2D,
- PINGRP_COUNT,
+ PMUX_PINGRP_COUNT,
};
/*
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index e10df76342bb..0112e3574736 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -275,10 +275,10 @@ enum pmux_pingrp {
PINGRP_PEX_L2_RST_N,
PINGRP_PEX_L2_CLKREQ_N,
PINGRP_HDMI_CEC, /* offset 0x33e0 */
- PINGRP_COUNT,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
+enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@@ -320,7 +320,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_GPV,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_COUNT,
+ PMUX_DRVGRP_COUNT,
};
/*
@@ -448,7 +448,7 @@ enum pmux_func {
};
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_PADGRPS
+#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
index 39df73138a41..69515d210612 100644
--- a/board/avionic-design/common/pinmux-config-tamonten-ng.h
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -8,9 +8,9 @@
#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
#define _PINMUX_CONFIG_TAMONTEN_NG_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -20,9 +20,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -32,9 +32,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -44,19 +44,19 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tamonten_ng_pinmux_common[] = {
+static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
@@ -277,7 +277,7 @@ static struct pingroup_config tamonten_ng_pinmux_common[] = {
DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
/* UART1 - NC */
DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
@@ -377,8 +377,8 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
};
-static struct padctrl_config tamonten_ng_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
index 9d395c676e07..5870b95afbf8 100644
--- a/board/avionic-design/common/tamonten-ng.c
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -28,14 +28,14 @@
void pinmux_init(void)
{
- pinmux_config_table(tamonten_ng_pinmux_common,
- ARRAY_SIZE(tamonten_ng_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
- ARRAY_SIZE(unused_pins_lowpower));
+ pinmux_config_pingrp_table(tamonten_ng_pinmux_common,
+ ARRAY_SIZE(tamonten_ng_pinmux_common));
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(tamonten_ng_padctrl,
- ARRAY_SIZE(tamonten_ng_padctrl));
+ pinmux_config_drvgrp_table(tamonten_ng_padctrl,
+ ARRAY_SIZE(tamonten_ng_padctrl));
}
void gpio_early_init(void)
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index 47e7abedf114..cc0e5e130fda 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -20,14 +20,14 @@
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra3_pinmux_common,
+ pinmux_config_pingrp_table(tegra3_pinmux_common,
ARRAY_SIZE(tegra3_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
+ pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
+ pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
index 51d2b9425c90..c230dac1361e 100644
--- a/board/nvidia/cardhu/pinmux-config-cardhu.h
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -17,9 +17,9 @@
#ifndef _PINMUX_CONFIG_CARDHU_H_
#define _PINMUX_CONFIG_CARDHU_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -29,9 +29,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -41,9 +41,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -53,19 +53,19 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra3_pinmux_common[] = {
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
@@ -316,7 +316,7 @@ static struct pingroup_config tegra3_pinmux_common[] = {
LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
};
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
@@ -338,8 +338,8 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
};
-static struct padctrl_config cardhu_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config cardhu_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
index 2c23a29db78a..f2d05afac791 100644
--- a/board/nvidia/dalmore/dalmore.c
+++ b/board/nvidia/dalmore/dalmore.c
@@ -29,17 +29,18 @@
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra114_pinmux_set_nontristate,
+ pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
ARRAY_SIZE(tegra114_pinmux_set_nontristate));
- pinmux_config_table(tegra114_pinmux_common,
+ pinmux_config_pingrp_table(tegra114_pinmux_common,
ARRAY_SIZE(tegra114_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
+ pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl));
+ pinmux_config_drvgrp_table(dalmore_padctrl,
+ ARRAY_SIZE(dalmore_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 9dcd5e42af10..6069fb6c02c8 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -17,9 +17,9 @@
#ifndef _PINMUX_CONFIG_DALMORE_H_
#define _PINMUX_CONFIG_DALMORE_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -29,9 +29,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -41,9 +41,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -53,9 +53,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -65,9 +65,9 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -79,19 +79,19 @@
#define USB_PINMUX CEC_PINMUX
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra114_pinmux_common[] = {
+static struct pmux_pingrp_config tegra114_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
@@ -286,13 +286,13 @@ static struct pingroup_config tegra114_pinmux_common[] = {
DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
-static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
+static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT),
@@ -362,8 +362,8 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
};
-static struct padctrl_config dalmore_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config dalmore_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index b3d68d589a95..51cd4bfcb6cc 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -8,9 +8,9 @@
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -20,9 +20,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -32,9 +32,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -44,9 +44,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -56,9 +56,9 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -70,19 +70,19 @@
#define USB_PINMUX CEC_PINMUX
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra124_pinmux_common[] = {
+static struct pmux_pingrp_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
@@ -286,12 +286,12 @@ static struct pingroup_config tegra124_pinmux_common[] = {
DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
-static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
+static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
@@ -331,8 +331,8 @@ static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
-static struct padctrl_config venice2_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config venice2_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
index 1ed2fd788ec1..15082c419507 100644
--- a/board/nvidia/venice2/venice2.c
+++ b/board/nvidia/venice2/venice2.c
@@ -19,15 +19,16 @@
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra124_pinmux_set_nontristate,
- ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+ pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
+ ARRAY_SIZE(tegra124_pinmux_set_nontristate));
- pinmux_config_table(tegra124_pinmux_common,
- ARRAY_SIZE(tegra124_pinmux_common));
+ pinmux_config_pingrp_table(tegra124_pinmux_common,
+ ARRAY_SIZE(tegra124_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
- ARRAY_SIZE(unused_pins_lowpower));
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+ pinmux_config_drvgrp_table(venice2_padctrl,
+ ARRAY_SIZE(venice2_padctrl));
}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (7 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:27 ` Simon Glass
2014-03-25 17:26 ` Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup Stephen Warren
` (3 subsequent siblings)
12 siblings, 2 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This removes a bunch of open-coded register IO, masking, and shifting.
I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
except that keeping it a separate commit allows easier bisection of any
issues that are introduced by this patch. I also wrote this patch on top
of the series, and pushing it any lower in the series results in some
conflicts I didn't feel like fixing.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
V2: New patch.
---
arch/arm/cpu/tegra-common/pinmux-common.c | 135 +++++-------------------------
1 file changed, 23 insertions(+), 112 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
index 32a46d53f068..7f7d4a87a4aa 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -87,11 +87,15 @@
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
+static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
+{
+ clrsetbits_le32(reg, mask << shift, val << shift);
+}
+
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
u32 *reg = MUX_REG(pin);
int i, mux = -1;
- u32 val;
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
@@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
}
assert(mux != -1);
- val = readl(reg);
- val &= ~(3 << MUX_SHIFT(pin));
- val |= (mux << MUX_SHIFT(pin));
- writel(val, reg);
+ update_field(reg, 3, MUX_SHIFT(pin), mux);
}
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
{
u32 *reg = PULL_REG(pin);
- u32 val;
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
- val = readl(reg);
- val &= ~(3 << PULL_SHIFT(pin));
- val |= (pupd << PULL_SHIFT(pin));
- writel(val, reg);
+ update_field(reg, 3, PULL_SHIFT(pin), pupd);
}
static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
{
u32 *reg = TRI_REG(pin);
- u32 val;
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_tristate_isvalid(tri));
- val = readl(reg);
- if (tri == PMUX_TRI_TRISTATE)
- val |= (1 << TRI_SHIFT(pin));
- else
- val &= ~(1 << TRI_SHIFT(pin));
- writel(val, reg);
+ update_field(reg, 1, TRI_SHIFT(pin), tri == PMUX_TRI_TRISTATE);
}
void pinmux_tristate_enable(enum pmux_pingrp pin)
@@ -162,7 +153,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
u32 *reg = REG(pin);
- u32 val;
if (io == PMUX_PIN_NONE)
return;
@@ -171,18 +161,12 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
- val = readl(reg);
- if (io == PMUX_PIN_INPUT)
- val |= (io & 1) << IO_SHIFT;
- else
- val &= ~(1 << IO_SHIFT);
- writel(val, reg);
+ update_field(reg, 1, IO_SHIFT, io == PMUX_PIN_INPUT);
}
static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
u32 *reg = REG(pin);
- u32 val;
if (lock == PMUX_PIN_LOCK_DEFAULT)
return;
@@ -191,23 +175,18 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
- val = readl(reg);
- if (lock == PMUX_PIN_LOCK_ENABLE) {
- val |= (1 << LOCK_SHIFT);
- } else {
+ if (lock == PMUX_PIN_LOCK_DISABLE) {
+ u32 val = readl(reg);
if (val & (1 << LOCK_SHIFT))
printf("%s: Cannot clear LOCK bit!\n", __func__);
- val &= ~(1 << LOCK_SHIFT);
}
- writel(val, reg);
- return;
+ update_field(reg, 1, LOCK_SHIFT, lock == PMUX_PIN_LOCK_ENABLE);
}
static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
u32 *reg = REG(pin);
- u32 val;
if (od == PMUX_PIN_OD_DEFAULT)
return;
@@ -216,21 +195,13 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_od_isvalid(od));
- val = readl(reg);
- if (od == PMUX_PIN_OD_ENABLE)
- val |= (1 << OD_SHIFT);
- else
- val &= ~(1 << OD_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, 1, OD_SHIFT, od == PMUX_PIN_OD_ENABLE);
}
static void pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
u32 *reg = REG(pin);
- u32 val;
if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
return;
@@ -239,14 +210,8 @@ static void pinmux_set_ioreset(enum pmux_pingrp pin,
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_ioreset_isvalid(ioreset));
- val = readl(reg);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- val |= (1 << IO_RESET_SHIFT);
- else
- val &= ~(1 << IO_RESET_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, 1, IO_RESET_SHIFT,
+ ioreset == PMUX_PIN_IO_RESET_ENABLE);
}
#ifdef TEGRA_PMX_HAS_RCV_SEL
@@ -254,7 +219,6 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
enum pmux_pin_rcv_sel rcv_sel)
{
u32 *reg = REG(pin);
- u32 val;
if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
return;
@@ -263,14 +227,7 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
- val = readl(reg);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- val |= (1 << RCV_SEL_SHIFT);
- else
- val &= ~(1 << RCV_SEL_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, 1, RCV_SEL_SHIFT, rcv_sel == PMUX_PIN_RCV_SEL_HIGH);
}
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
@@ -337,7 +294,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwf == PMUX_SLWF_NONE)
@@ -347,18 +303,12 @@ static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwf));
- val = readl(reg);
- val &= ~SLWF_MASK;
- val |= (slwf << SLWF_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, SLWF_MASK, SLWF_SHIFT, slwf);
}
static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwr == PMUX_SLWR_NONE)
@@ -368,18 +318,12 @@ static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwr));
- val = readl(reg);
- val &= ~SLWR_MASK;
- val |= (slwr << SLWR_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, SLWR_MASK, SLWR_SHIFT, slwr);
}
static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvup == PMUX_DRVUP_NONE)
@@ -389,18 +333,12 @@ static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvup));
- val = readl(reg);
- val &= ~DRVUP_MASK;
- val |= (drvup << DRVUP_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, DRVUP_MASK, DRVUP_SHIFT, drvup);
}
static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PMUX_DRVDN_NONE)
@@ -410,18 +348,12 @@ static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvdn));
- val = readl(reg);
- val &= ~DRVDN_MASK;
- val |= (drvdn << DRVDN_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, DRVDN_MASK, DRVDN_SHIFT, drvdn);
}
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PMUX_LPMD_NONE)
@@ -431,18 +363,12 @@ static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_lpmd_isvalid(lpmd));
- val = readl(reg);
- val &= ~LPMD_MASK;
- val |= (lpmd << LPMD_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, LPMD_MASK, LPMD_SHIFT, lpmd);
}
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (schmt == PMUX_SCHMT_NONE)
@@ -452,20 +378,12 @@ static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_schmt_isvalid(schmt));
- val = readl(reg);
- if (schmt == PMUX_SCHMT_ENABLE)
- val |= (1 << SCHMT_SHIFT);
- else
- val &= ~(1 << SCHMT_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, 1, SCHMT_SHIFT, schmt == PMUX_SCHMT_ENABLE);
}
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
- u32 val;
/* NONE means unspecified/do not change/use POR value */
if (hsm == PMUX_HSM_NONE)
@@ -475,14 +393,7 @@ static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_hsm_isvalid(hsm));
- val = readl(reg);
- if (hsm == PMUX_HSM_ENABLE)
- val |= (1 << HSM_SHIFT);
- else
- val &= ~(1 << HSM_SHIFT);
- writel(val, reg);
-
- return;
+ update_field(reg, 1, HSM_SHIFT, hsm == PMUX_HSM_ENABLE);
}
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (8 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:29 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 " Stephen Warren
` (2 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.
The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
V2: No change.
---
arch/arm/cpu/tegra20-common/funcmux.c | 179 ++++++-------
arch/arm/cpu/tegra20-common/pinmux.c | 288 ++++++++++-----------
arch/arm/include/asm/arch-tegra20/pinmux.h | 266 ++++++++++---------
board/avionic-design/common/tamonten.c | 4 +-
board/compal/paz00/paz00.c | 22 +-
board/compulab/trimslice/trimslice.c | 4 +-
board/nvidia/harmony/harmony.c | 18 +-
board/nvidia/seaboard/seaboard.c | 6 +-
.../colibri_t20-common/colibri_t20-common.c | 8 +-
board/toradex/colibri_t20_iris/colibri_t20_iris.c | 4 +-
drivers/spi/tegra20_sflash.c | 6 +-
drivers/video/tegra.c | 4 +-
12 files changed, 397 insertions(+), 412 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c
index 8ae28672499a..0df4a0738de4 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -14,7 +14,7 @@
* The PINMUX macro is used to set up pinmux tables.
*/
#define PINMUX(grp, mux, pupd, tri) \
- {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+ {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
@@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
- pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_IRRX);
- pinmux_tristate_disable(PINGRP_IRTX);
+ pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_IRRX);
+ pinmux_tristate_disable(PMUX_PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
- pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_UAA);
- pinmux_tristate_disable(PINGRP_UAB);
+ pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
}
@@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config)
* state the group to avoid driving any signal onto it
* until we know what's connected.
*/
- pinmux_tristate_enable(PINGRP_SDB);
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_tristate_enable(PMUX_PINGRP_SDB);
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
}
break;
case PERIPH_ID_UART2:
if (config == FUNCMUX_UART2_UAD) {
- pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
- pinmux_tristate_disable(PINGRP_UAD);
+ pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
+ pinmux_tristate_disable(PMUX_PINGRP_UAD);
}
break;
case PERIPH_ID_UART4:
if (config == FUNCMUX_UART4_GMC) {
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
- pinmux_tristate_disable(PINGRP_GMC);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
+ pinmux_tristate_disable(PMUX_PINGRP_GMC);
}
break;
case PERIPH_ID_DVC_I2C:
/* there is only one selection, pinmux_config is ignored */
if (config == FUNCMUX_DVC_I2CP) {
- pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PINGRP_I2CP);
+ pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
+ pinmux_tristate_disable(PMUX_PINGRP_I2CP);
}
break;
case PERIPH_ID_I2C1:
/* support pinmux_config of 0 for now, */
if (config == FUNCMUX_I2C1_RM) {
- pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PINGRP_RM);
+ pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
+ pinmux_tristate_disable(PMUX_PINGRP_RM);
}
break;
case PERIPH_ID_I2C2: /* I2C2 */
switch (config) {
case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
- pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
+ pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
/* PTA to HDMI */
- pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
- pinmux_tristate_disable(PINGRP_DDC);
+ pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
+ pinmux_tristate_disable(PMUX_PINGRP_DDC);
break;
case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
- pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
+ pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
/* set DDC_SEL to RSVDx (RSVD2 works for now) */
- pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
- pinmux_tristate_disable(PINGRP_PTA);
+ pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
+ pinmux_tristate_disable(PMUX_PINGRP_PTA);
bad_config = 0;
break;
}
@@ -131,50 +131,50 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_I2C3: /* I2C3 */
/* support pinmux_config of 0 for now */
if (config == FUNCMUX_I2C3_DTF) {
- pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
- pinmux_tristate_disable(PINGRP_DTF);
+ pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
+ pinmux_tristate_disable(PMUX_PINGRP_DTF);
}
break;
case PERIPH_ID_SDMMC1:
if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
}
break;
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
- pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
- pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+ pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
+ pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
- pinmux_tristate_disable(PINGRP_DTA);
- pinmux_tristate_disable(PINGRP_DTD);
+ pinmux_tristate_disable(PMUX_PINGRP_DTA);
+ pinmux_tristate_disable(PMUX_PINGRP_DTD);
}
break;
case PERIPH_ID_SDMMC3:
switch (config) {
case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
- pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PINGRP_SLXA);
- pinmux_tristate_disable(PINGRP_SLXC);
- pinmux_tristate_disable(PINGRP_SLXD);
- pinmux_tristate_disable(PINGRP_SLXK);
+ pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+ pinmux_tristate_disable(PMUX_PINGRP_SLXA);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXC);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXD);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXK);
/* fall through */
case FUNCMUX_SDMMC3_SDB_4BIT:
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
- pinmux_tristate_disable(PINGRP_SDB);
- pinmux_tristate_disable(PINGRP_SDC);
- pinmux_tristate_disable(PINGRP_SDD);
+ pinmux_tristate_disable(PMUX_PINGRP_SDB);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
+ pinmux_tristate_disable(PMUX_PINGRP_SDD);
bad_config = 0;
break;
}
@@ -183,24 +183,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_SDMMC4:
switch (config) {
case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
- pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATC);
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
break;
case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
- pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_GME);
+ pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+ pinmux_tristate_disable(PMUX_PINGRP_GME);
/* fall through */
case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
- pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATB);
- pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMA);
bad_config = 0;
break;
}
@@ -208,9 +208,10 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_KBC:
if (config == FUNCMUX_DEFAULT) {
- enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
- PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
- PINGRP_KBCF};
+ enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
+ PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
+ PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
+ PMUX_PINGRP_KBCF};
int i;
for (i = 0; i < ARRAY_SIZE(grp); i++) {
@@ -223,44 +224,44 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_USB2:
if (config == FUNCMUX_USB2_ULPI) {
- pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
- pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
- pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
- pinmux_tristate_disable(PINGRP_UAA);
- pinmux_tristate_disable(PINGRP_UAB);
- pinmux_tristate_disable(PINGRP_UDA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAB);
+ pinmux_tristate_disable(PMUX_PINGRP_UDA);
}
break;
case PERIPH_ID_SPI1:
if (config == FUNCMUX_SPI1_GMC_GMD) {
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
- pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
- pinmux_tristate_disable(PINGRP_GMC);
- pinmux_tristate_disable(PINGRP_GMD);
+ pinmux_tristate_disable(PMUX_PINGRP_GMC);
+ pinmux_tristate_disable(PMUX_PINGRP_GMD);
}
break;
case PERIPH_ID_NDFLASH:
switch (config) {
case FUNCMUX_NDFLASH_ATC:
- pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
break;
case FUNCMUX_NDFLASH_KBC_8_BIT:
- pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
-
- pinmux_tristate_disable(PINGRP_KBCA);
- pinmux_tristate_disable(PINGRP_KBCC);
- pinmux_tristate_disable(PINGRP_KBCD);
- pinmux_tristate_disable(PINGRP_KBCE);
- pinmux_tristate_disable(PINGRP_KBCF);
+ pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
+
+ pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCD);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCE);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCF);
bad_config = 0;
break;
@@ -270,7 +271,7 @@ int funcmux_select(enum periph_id id, int config)
if (config == FUNCMUX_DEFAULT) {
int i;
- for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+ for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
pinmux_set_func(i, PMUX_FUNC_DISPA);
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 4c8999500641..e484f991bf81 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -255,183 +255,171 @@ enum pmux_pullid {
};
/* Convenient macro for defining pin group properties */
-#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
+#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
{ \
.funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
}, \
.ctl_id = mux, \
.pull_id = pupd \
}
/* A normal pin group where the mux name and pull-up name match */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
- PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
- MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
+#define PIN(pingrp, f0, f1, f2, f3) \
+ PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
/* A pin group where the pull-up name doesn't have a 1-1 mapping */
-#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
- PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
- MUXCTL_ ## pg_name, PUCTL_ ## pupd)
+#define PINP(pingrp, f0, f1, f2, f3, pupd) \
+ PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
/* A pin group number which is not used */
#define PIN_RESERVED \
- PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
+ PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
-#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
+#define DRVGRP(drvgrp) \
+ PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
static const struct pmux_pingrp_desc tegra20_pingroups[] = {
- PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
- PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
- PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
- PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
- PLLC_OUT1),
- PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
-
- PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
- PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
- PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
- PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
- PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
- PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
- PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
- PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
-
- PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
- GPSLXAU),
- PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
- PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
- PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
- PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
- PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
- PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
- PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
-
- PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
- PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
- PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
- PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
- PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
- PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
- PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
- PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
-
- PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
- PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
- PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
+ PIN(ATA, IDE, NAND, GMI, RSVD4),
+ PIN(ATB, IDE, NAND, GMI, SDIO4),
+ PIN(ATC, IDE, NAND, GMI, SDIO4),
+ PIN(ATD, IDE, NAND, GMI, SDIO4),
+ PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
+ PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
+ PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
+ PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
+
+ PIN(DAP2, DAP2, TWC, RSVD3, GMI),
+ PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
+ PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
+ PIN(DTB, RSVD1, RSVD2, VI, SPI1),
+ PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
+ PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
+ PIN(DTE, RSVD1, RSVD2, VI, SPI1),
+
+ PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
+ PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
+ PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
+ PIN(IRTX, UARTA, UARTB, GMI, SPI4),
+ PIN(IRRX, UARTA, UARTB, GMI, SPI4),
+ PIN(KBCB, KBC, NAND, SDIO2, MIO),
+ PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
+ PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
+
+ PIN(PTA, I2C2, HDMI, GMI, RSVD4),
+ PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
+ PIN(KBCE, KBC, NAND, OWR, RSVD4),
+ PIN(KBCF, KBC, NAND, TRACE, MIO),
+ PIN(GMA, UARTE, SPI3, GMI, SDIO4),
+ PIN(GMC, UARTD, SPI4, GMI, SFLASH),
+ PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
+ PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
+
+ PIN(GME, RSVD1, DAP5, GMI, SDIO4),
+ PIN(SDC, PWM, TWC, SDIO3, SPI3),
+ PIN(SDD, UARTA, PWM, SDIO3, SPI3),
PIN_RESERVED,
- PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
- PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
- PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
- PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
-
- PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
- PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
- PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
- PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
- PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
-
- PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
- PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
- PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
- PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
- PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
- PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
- PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
- PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
+ PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
+ PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
+ PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
+ PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
+
+ PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
+ PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
+ PIN(SPIA, SPI1, SPI2, SPI3, GMI),
+ PIN(SPIB, SPI1, SPI2, SPI3, GMI),
+ PIN(SPIC, SPI1, SPI2, SPI3, GMI),
+ PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
+
+ PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
+ PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
+ PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
+ PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
+ PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UCB, UARTC, PWM, GMI, RSVD4),
PIN_RESERVED,
- PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
- PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
+ PIN(ATE, IDE, NAND, GMI, RSVD4),
+ PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
PIN_RESERVED,
PIN_RESERVED,
- PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
- PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
- PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
+ PIN(GMB, IDE, NAND, GMI, GMI_INT),
+ PIN(GMD, RSVD1, NAND, GMI, SFLASH),
+ PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
/* 64 */
- PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
-
- PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
-
- PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
- PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
- PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
- PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
- PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
- PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
- PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
-
- PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
- PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
- PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
- PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
- PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
- PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
+ PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
+
+ PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
+
+ PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
+ PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
+ PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
+ PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
+ PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
+ PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
+ PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
+
+ PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
+ PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
+ PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
+ PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
+ PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
+ PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
/* 96 */
- PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
- PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
- PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
- PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
- PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
-
- PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
+ PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
+ PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
+ PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
+ PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
+ PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
+
+ PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PIN_RESERVED,
- PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
- PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
- PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
- PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
- PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
- PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
+ PIN(KBCD, KBC, NAND, SDIO2, MIO),
+ PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(DTF, I2C3, RSVD2, VI, RSVD4),
+ PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
+ PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
+ PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
/* these pin groups only have pullup and pull down control */
- PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
+ DRVGRP(CK32),
+ DRVGRP(DDRC),
+ DRVGRP(PMCA),
+ DRVGRP(PMCB),
+ DRVGRP(PMCC),
+ DRVGRP(PMCD),
+ DRVGRP(PMCE),
+ DRVGRP(XM2C),
+ DRVGRP(XM2D),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 328a3e3224d5..d7802d967597 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -18,147 +18,145 @@
*/
enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
- PINGRP_ATA,
- PINGRP_ATB,
- PINGRP_ATC,
- PINGRP_ATD,
- PINGRP_CDEV1,
- PINGRP_CDEV2,
- PINGRP_CSUS,
- PINGRP_DAP1,
-
- PINGRP_DAP2,
- PINGRP_DAP3,
- PINGRP_DAP4,
- PINGRP_DTA,
- PINGRP_DTB,
- PINGRP_DTC,
- PINGRP_DTD,
- PINGRP_DTE,
-
- PINGRP_GPU,
- PINGRP_GPV,
- PINGRP_I2CP,
- PINGRP_IRTX,
- PINGRP_IRRX,
- PINGRP_KBCB,
- PINGRP_KBCA,
- PINGRP_PMC,
-
- PINGRP_PTA,
- PINGRP_RM,
- PINGRP_KBCE,
- PINGRP_KBCF,
- PINGRP_GMA,
- PINGRP_GMC,
- PINGRP_SDIO1,
- PINGRP_OWC,
+ PMUX_PINGRP_ATA,
+ PMUX_PINGRP_ATB,
+ PMUX_PINGRP_ATC,
+ PMUX_PINGRP_ATD,
+ PMUX_PINGRP_CDEV1,
+ PMUX_PINGRP_CDEV2,
+ PMUX_PINGRP_CSUS,
+ PMUX_PINGRP_DAP1,
+
+ PMUX_PINGRP_DAP2,
+ PMUX_PINGRP_DAP3,
+ PMUX_PINGRP_DAP4,
+ PMUX_PINGRP_DTA,
+ PMUX_PINGRP_DTB,
+ PMUX_PINGRP_DTC,
+ PMUX_PINGRP_DTD,
+ PMUX_PINGRP_DTE,
+
+ PMUX_PINGRP_GPU,
+ PMUX_PINGRP_GPV,
+ PMUX_PINGRP_I2CP,
+ PMUX_PINGRP_IRTX,
+ PMUX_PINGRP_IRRX,
+ PMUX_PINGRP_KBCB,
+ PMUX_PINGRP_KBCA,
+ PMUX_PINGRP_PMC,
+
+ PMUX_PINGRP_PTA,
+ PMUX_PINGRP_RM,
+ PMUX_PINGRP_KBCE,
+ PMUX_PINGRP_KBCF,
+ PMUX_PINGRP_GMA,
+ PMUX_PINGRP_GMC,
+ PMUX_PINGRP_SDIO1,
+ PMUX_PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
- PINGRP_GME,
- PINGRP_SDC,
- PINGRP_SDD,
- PINGRP_RESERVED0,
- PINGRP_SLXA,
- PINGRP_SLXC,
- PINGRP_SLXD,
- PINGRP_SLXK,
-
- PINGRP_SPDI,
- PINGRP_SPDO,
- PINGRP_SPIA,
- PINGRP_SPIB,
- PINGRP_SPIC,
- PINGRP_SPID,
- PINGRP_SPIE,
- PINGRP_SPIF,
-
- PINGRP_SPIG,
- PINGRP_SPIH,
- PINGRP_UAA,
- PINGRP_UAB,
- PINGRP_UAC,
- PINGRP_UAD,
- PINGRP_UCA,
- PINGRP_UCB,
-
- PINGRP_RESERVED1,
- PINGRP_ATE,
- PINGRP_KBCC,
- PINGRP_RESERVED2,
- PINGRP_RESERVED3,
- PINGRP_GMB,
- PINGRP_GMD,
- PINGRP_DDC,
+ PMUX_PINGRP_GME,
+ PMUX_PINGRP_SDC,
+ PMUX_PINGRP_SDD,
+ PMUX_PINGRP_RESERVED0,
+ PMUX_PINGRP_SLXA,
+ PMUX_PINGRP_SLXC,
+ PMUX_PINGRP_SLXD,
+ PMUX_PINGRP_SLXK,
+
+ PMUX_PINGRP_SPDI,
+ PMUX_PINGRP_SPDO,
+ PMUX_PINGRP_SPIA,
+ PMUX_PINGRP_SPIB,
+ PMUX_PINGRP_SPIC,
+ PMUX_PINGRP_SPID,
+ PMUX_PINGRP_SPIE,
+ PMUX_PINGRP_SPIF,
+
+ PMUX_PINGRP_SPIG,
+ PMUX_PINGRP_SPIH,
+ PMUX_PINGRP_UAA,
+ PMUX_PINGRP_UAB,
+ PMUX_PINGRP_UAC,
+ PMUX_PINGRP_UAD,
+ PMUX_PINGRP_UCA,
+ PMUX_PINGRP_UCB,
+
+ PMUX_PINGRP_RESERVED1,
+ PMUX_PINGRP_ATE,
+ PMUX_PINGRP_KBCC,
+ PMUX_PINGRP_RESERVED2,
+ PMUX_PINGRP_RESERVED3,
+ PMUX_PINGRP_GMB,
+ PMUX_PINGRP_GMD,
+ PMUX_PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
- PINGRP_LD0,
- PINGRP_LD1,
- PINGRP_LD2,
- PINGRP_LD3,
- PINGRP_LD4,
- PINGRP_LD5,
- PINGRP_LD6,
- PINGRP_LD7,
-
- PINGRP_LD8,
- PINGRP_LD9,
- PINGRP_LD10,
- PINGRP_LD11,
- PINGRP_LD12,
- PINGRP_LD13,
- PINGRP_LD14,
- PINGRP_LD15,
-
- PINGRP_LD16,
- PINGRP_LD17,
- PINGRP_LHP0,
- PINGRP_LHP1,
- PINGRP_LHP2,
- PINGRP_LVP0,
- PINGRP_LVP1,
- PINGRP_HDINT,
-
- PINGRP_LM0,
- PINGRP_LM1,
- PINGRP_LVS,
- PINGRP_LSC0,
- PINGRP_LSC1,
- PINGRP_LSCK,
- PINGRP_LDC,
- PINGRP_LCSN,
+ PMUX_PINGRP_LD0,
+ PMUX_PINGRP_LD1,
+ PMUX_PINGRP_LD2,
+ PMUX_PINGRP_LD3,
+ PMUX_PINGRP_LD4,
+ PMUX_PINGRP_LD5,
+ PMUX_PINGRP_LD6,
+ PMUX_PINGRP_LD7,
+
+ PMUX_PINGRP_LD8,
+ PMUX_PINGRP_LD9,
+ PMUX_PINGRP_LD10,
+ PMUX_PINGRP_LD11,
+ PMUX_PINGRP_LD12,
+ PMUX_PINGRP_LD13,
+ PMUX_PINGRP_LD14,
+ PMUX_PINGRP_LD15,
+
+ PMUX_PINGRP_LD16,
+ PMUX_PINGRP_LD17,
+ PMUX_PINGRP_LHP0,
+ PMUX_PINGRP_LHP1,
+ PMUX_PINGRP_LHP2,
+ PMUX_PINGRP_LVP0,
+ PMUX_PINGRP_LVP1,
+ PMUX_PINGRP_HDINT,
+
+ PMUX_PINGRP_LM0,
+ PMUX_PINGRP_LM1,
+ PMUX_PINGRP_LVS,
+ PMUX_PINGRP_LSC0,
+ PMUX_PINGRP_LSC1,
+ PMUX_PINGRP_LSCK,
+ PMUX_PINGRP_LDC,
+ PMUX_PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
- PINGRP_LSPI,
- PINGRP_LSDA,
- PINGRP_LSDI,
- PINGRP_LPW0,
- PINGRP_LPW1,
- PINGRP_LPW2,
- PINGRP_LDI,
- PINGRP_LHS,
-
- PINGRP_LPP,
- PINGRP_RESERVED4,
- PINGRP_KBCD,
- PINGRP_GPU7,
- PINGRP_DTF,
- PINGRP_UDA,
- PINGRP_CRTP,
- PINGRP_SDB,
+ PMUX_PINGRP_LSPI,
+ PMUX_PINGRP_LSDA,
+ PMUX_PINGRP_LSDI,
+ PMUX_PINGRP_LPW0,
+ PMUX_PINGRP_LPW1,
+ PMUX_PINGRP_LPW2,
+ PMUX_PINGRP_LDI,
+ PMUX_PINGRP_LHS,
+
+ PMUX_PINGRP_LPP,
+ PMUX_PINGRP_RESERVED4,
+ PMUX_PINGRP_KBCD,
+ PMUX_PINGRP_GPU7,
+ PMUX_PINGRP_DTF,
+ PMUX_PINGRP_UDA,
+ PMUX_PINGRP_CRTP,
+ PMUX_PINGRP_SDB,
/* these pin groups only have pullup and pull down control */
- PINGRP_FIRST_NO_MUX,
- PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
- PINGRP_DDRC,
- PINGRP_PMCA,
- PINGRP_PMCB,
- PINGRP_PMCC,
- PINGRP_PMCD,
- PINGRP_PMCE,
- PINGRP_XM2C,
- PINGRP_XM2D,
-
+ PMUX_PINGRP_CK32,
+ PMUX_PINGRP_DDRC,
+ PMUX_PINGRP_PMCA,
+ PMUX_PINGRP_PMCB,
+ PMUX_PINGRP_PMCC,
+ PMUX_PINGRP_PMCD,
+ PMUX_PINGRP_PMCE,
+ PMUX_PINGRP_XM2C,
+ PMUX_PINGRP_XM2D,
PMUX_PINGRP_COUNT,
};
@@ -227,9 +225,7 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
-
PMUX_FUNC_COUNT,
-
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 177d185ea8d8..9c8677943ad3 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -37,8 +37,8 @@ void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
/* for write-protect GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* for CD GPIO PH2 */
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
}
#endif
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index d6e5c3740e5f..462ab05556c8 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -28,23 +28,23 @@
void pin_mux_mmc(void)
{
/* SDMMC4: config 3, x8 on 2nd set of pins */
- pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATB);
- pinmux_tristate_disable(PINGRP_GMA);
- pinmux_tristate_disable(PINGRP_GME);
+ pinmux_tristate_disable(PMUX_PINGRP_ATB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMA);
+ pinmux_tristate_disable(PMUX_PINGRP_GME);
/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
/* For power GPIO PV1 */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* For CD GPIO PV5 */
- pinmux_tristate_disable(PINGRP_GPV);
+ pinmux_tristate_disable(PMUX_PINGRP_GPV);
}
#endif
@@ -55,6 +55,6 @@ void pin_mux_display(void)
debug("init display pinmux\n");
/* EN_VDD_PANEL GPIO A4 */
- pinmux_tristate_disable(PINGRP_DAP2);
+ pinmux_tristate_disable(PMUX_PINGRP_DAP2);
}
#endif
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index ef949303a680..723293fef35a 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -20,7 +20,7 @@ void pin_mux_usb(void)
* USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
* in the current device tree.
*/
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_spi(void)
@@ -38,5 +38,5 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
/* For CD GPIO PP1 */
- pinmux_tristate_disable(PINGRP_DAP3);
+ pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index b74c21934754..c892a25751f9 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -25,28 +25,28 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
/* For power GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PH2 */
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
/* For power GPIO PT3 */
- pinmux_tristate_disable(PINGRP_DTB);
+ pinmux_tristate_disable(PMUX_PINGRP_DTB);
/* For CD GPIO PI5 */
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
- pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
- pinmux_tristate_disable(PINGRP_CDEV2);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* USB2 PHY reset GPIO */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_display(void)
{
- pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PINGRP_SDC);
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
}
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index ef4e481c75f1..ce2db40f9ebf 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -37,14 +37,14 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
/* For power GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PI5 */
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
- pinmux_tristate_disable(PINGRP_SLXK);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXK);
}
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c
index 823d0de5e42a..58a9916f0ade 100644
--- a/board/toradex/colibri_t20-common/colibri_t20-common.c
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.c
@@ -18,12 +18,12 @@ void colibri_t20_common_pin_mux_usb(void)
/* module internal USB bus to connect ethernet chipset */
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
/* ULPI reference clock output */
- pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
- pinmux_tristate_disable(PINGRP_CDEV2);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* PHY reset GPIO */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* VBus GPIO */
- pinmux_tristate_disable(PINGRP_DTE);
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
}
#endif
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
index f5f0475b893d..49c74f34f1e8 100644
--- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c
+++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -19,7 +19,7 @@ void pin_mux_usb(void)
colibri_t20_common_pin_mux_usb();
/* USB 1 aka Tegra USB port 3 VBus*/
- pinmux_tristate_disable(PINGRP_SPIG);
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif
@@ -31,6 +31,6 @@ void pin_mux_usb(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
- pinmux_tristate_disable(PINGRP_GMB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
}
#endif
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 603c024bcc16..b5d561be3410 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -208,9 +208,9 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
* SPI pins on Tegra20 are muxed - change pinmux later due to UART
* issue.
*/
- pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
- pinmux_tristate_disable(PINGRP_LSPI);
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
+ pinmux_tristate_disable(PMUX_PINGRP_LSPI);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
return 0;
}
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index c047e6e785df..57cb0074e277 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -229,8 +229,8 @@ static int handle_stage(const void *blob)
break;
case STAGE_PWM:
/* Enable PWM@15/16 high, 32768 Hz with divider 1 */
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
break;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 pinmux cleanup
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (9 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup Stephen Warren
@ 2014-03-21 18:28 ` Stephen Warren
2014-03-25 2:30 ` Simon Glass
2014-03-21 18:29 ` [U-Boot] [PATCH V2 12/13] ARM: tegra: Tegra114 " Stephen Warren
2014-03-21 18:29 ` [U-Boot] [PATCH V2 13/13] ARM: tegra: Tegra124 " Stephen Warren
12 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:28 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra30_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted one entry in
pinmux-config-cardhu.h due to this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Fixed indentation of tegra30_pingroups[]
---
arch/arm/cpu/tegra30-common/funcmux.c | 20 +-
arch/arm/cpu/tegra30-common/pinmux.c | 542 ++++++++-------
arch/arm/include/asm/arch-tegra30/pinmux.h | 725 ++++++++++-----------
.../common/pinmux-config-tamonten-ng.h | 470 ++++++-------
board/nvidia/cardhu/pinmux-config-cardhu.h | 476 +++++++-------
5 files changed, 1082 insertions(+), 1151 deletions(-)
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
index e24c57efbdd3..409335ce1d1f 100644
--- a/arch/arm/cpu/tegra30-common/funcmux.c
+++ b/arch/arm/cpu/tegra30-common/funcmux.c
@@ -29,14 +29,18 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_ULPI:
- pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_ULPI_DATA0);
- pinmux_tristate_disable(PINGRP_ULPI_DATA1);
- pinmux_tristate_disable(PINGRP_ULPI_DATA2);
- pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
break;
}
break;
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index f1d199321aca..7eb05743b4bc 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -1,292 +1,276 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra30 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+#define PIN_RESERVED {}
-static const struct pmux_pingrp_desc tegra30_pingroups[PMUX_PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
- PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
- PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
- PINI(VI_MCLK, VI, VI, VI, VI, VI),
- PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
- PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
- PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
- PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
- PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
- PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
- PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
- PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
- PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
- PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
- PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
- PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
- PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
- PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
- PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
- PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
- PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
- PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
- PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
- PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
- PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
+static const struct pmux_pingrp_desc tegra30_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(PV2, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
+ PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4),
+ PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4),
+ PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4),
+ PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3),
+ PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4),
+ PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4),
+ PIN(PU0, OWR, UARTA, GMI, RSVD4),
+ PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU3, PWM0, UARTA, GMI, RSVD4),
+ PIN(PU4, PWM1, UARTA, GMI, RSVD4),
+ PIN(PU5, PWM2, UARTA, GMI, RSVD4),
+ PIN(PU6, PWM3, UARTA, GMI, RSVD4),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
+ PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
+ PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA),
+ PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT),
+ PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4),
+ PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4),
+ PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4),
+ PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4),
+ PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT),
+ PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV),
+ PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV),
+ PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4),
+ PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4),
+ PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4),
+ PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4),
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID),
+ PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR),
+ PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST),
+ PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST),
+ PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO),
+ PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO),
+ PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4),
+ PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, CEC, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2),
+ PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4),
+ PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2),
+ PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI),
+ PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4),
+ PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1),
+ PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1),
+ PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3),
+ PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2),
+ PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
+ PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 0112e3574736..3fed194339dd 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -1,446 +1,389 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA30_PINMUX_H_
#define _TEGRA30_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_GPIO_PV2,
- PINGRP_GPIO_PV3,
- PINGRP_CLK2_OUT,
- PINGRP_CLK2_REQ,
- PINGRP_LCD_PWR1,
- PINGRP_LCD_PWR2,
- PINGRP_LCD_SDIN,
- PINGRP_LCD_SDOUT,
- PINGRP_LCD_WR_N,
- PINGRP_LCD_CS0_N,
- PINGRP_LCD_DC0,
- PINGRP_LCD_SCK,
- PINGRP_LCD_PWR0,
- PINGRP_LCD_PCLK,
- PINGRP_LCD_DE,
- PINGRP_LCD_HSYNC,
- PINGRP_LCD_VSYNC,
- PINGRP_LCD_D0,
- PINGRP_LCD_D1,
- PINGRP_LCD_D2,
- PINGRP_LCD_D3,
- PINGRP_LCD_D4,
- PINGRP_LCD_D5,
- PINGRP_LCD_D6,
- PINGRP_LCD_D7,
- PINGRP_LCD_D8,
- PINGRP_LCD_D9,
- PINGRP_LCD_D10,
- PINGRP_LCD_D11,
- PINGRP_LCD_D12,
- PINGRP_LCD_D13,
- PINGRP_LCD_D14,
- PINGRP_LCD_D15,
- PINGRP_LCD_D16,
- PINGRP_LCD_D17,
- PINGRP_LCD_D18,
- PINGRP_LCD_D19,
- PINGRP_LCD_D20,
- PINGRP_LCD_D21,
- PINGRP_LCD_D22,
- PINGRP_LCD_D23,
- PINGRP_LCD_CS1_N,
- PINGRP_LCD_M1,
- PINGRP_LCD_DC1,
- PINGRP_HDMI_INT,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_CRT_HSYNC,
- PINGRP_CRT_VSYNC,
- PINGRP_VI_D0,
- PINGRP_VI_D1,
- PINGRP_VI_D2,
- PINGRP_VI_D3,
- PINGRP_VI_D4,
- PINGRP_VI_D5,
- PINGRP_VI_D6,
- PINGRP_VI_D7,
- PINGRP_VI_D8,
- PINGRP_VI_D9,
- PINGRP_VI_D10,
- PINGRP_VI_D11,
- PINGRP_VI_PCLK,
- PINGRP_VI_MCLK,
- PINGRP_VI_VSYNC,
- PINGRP_VI_HSYNC,
- PINGRP_UART2_RXD,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_SDMMC4_RST_N,
- PINGRP_CAM_MCLK,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_SPI2_MOSI,
- PINGRP_SPI2_MISO,
- PINGRP_SPI2_CS0_N,
- PINGRP_SPI2_SCK,
- PINGRP_SPI1_MOSI,
- PINGRP_SPI1_SCK,
- PINGRP_SPI1_CS0_N,
- PINGRP_SPI1_MISO,
- PINGRP_SPI2_CS1_N,
- PINGRP_SPI2_CS2_N,
- PINGRP_SDMMC3_CLK,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_SDMMC3_DAT4,
- PINGRP_SDMMC3_DAT5,
- PINGRP_SDMMC3_DAT6,
- PINGRP_SDMMC3_DAT7,
- PINGRP_PEX_L0_PRSNT_N,
- PINGRP_PEX_L0_RST_N,
- PINGRP_PEX_L0_CLKREQ_N,
- PINGRP_PEX_WAKE_N,
- PINGRP_PEX_L1_PRSNT_N,
- PINGRP_PEX_L1_RST_N,
- PINGRP_PEX_L1_CLKREQ_N,
- PINGRP_PEX_L2_PRSNT_N,
- PINGRP_PEX_L2_RST_N,
- PINGRP_PEX_L2_CLKREQ_N,
- PINGRP_HDMI_CEC, /* offset 0x33e0 */
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_PV2,
+ PMUX_PINGRP_PV3,
+ PMUX_PINGRP_CLK2_OUT_PW5,
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_LCD_PWR1_PC1,
+ PMUX_PINGRP_LCD_PWR2_PC6,
+ PMUX_PINGRP_LCD_SDIN_PZ2,
+ PMUX_PINGRP_LCD_SDOUT_PN5,
+ PMUX_PINGRP_LCD_WR_N_PZ3,
+ PMUX_PINGRP_LCD_CS0_N_PN4,
+ PMUX_PINGRP_LCD_DC0_PN6,
+ PMUX_PINGRP_LCD_SCK_PZ4,
+ PMUX_PINGRP_LCD_PWR0_PB2,
+ PMUX_PINGRP_LCD_PCLK_PB3,
+ PMUX_PINGRP_LCD_DE_PJ1,
+ PMUX_PINGRP_LCD_HSYNC_PJ3,
+ PMUX_PINGRP_LCD_VSYNC_PJ4,
+ PMUX_PINGRP_LCD_D0_PE0,
+ PMUX_PINGRP_LCD_D1_PE1,
+ PMUX_PINGRP_LCD_D2_PE2,
+ PMUX_PINGRP_LCD_D3_PE3,
+ PMUX_PINGRP_LCD_D4_PE4,
+ PMUX_PINGRP_LCD_D5_PE5,
+ PMUX_PINGRP_LCD_D6_PE6,
+ PMUX_PINGRP_LCD_D7_PE7,
+ PMUX_PINGRP_LCD_D8_PF0,
+ PMUX_PINGRP_LCD_D9_PF1,
+ PMUX_PINGRP_LCD_D10_PF2,
+ PMUX_PINGRP_LCD_D11_PF3,
+ PMUX_PINGRP_LCD_D12_PF4,
+ PMUX_PINGRP_LCD_D13_PF5,
+ PMUX_PINGRP_LCD_D14_PF6,
+ PMUX_PINGRP_LCD_D15_PF7,
+ PMUX_PINGRP_LCD_D16_PM0,
+ PMUX_PINGRP_LCD_D17_PM1,
+ PMUX_PINGRP_LCD_D18_PM2,
+ PMUX_PINGRP_LCD_D19_PM3,
+ PMUX_PINGRP_LCD_D20_PM4,
+ PMUX_PINGRP_LCD_D21_PM5,
+ PMUX_PINGRP_LCD_D22_PM6,
+ PMUX_PINGRP_LCD_D23_PM7,
+ PMUX_PINGRP_LCD_CS1_N_PW0,
+ PMUX_PINGRP_LCD_M1_PW1,
+ PMUX_PINGRP_LCD_DC1_PD2,
+ PMUX_PINGRP_HDMI_INT_PN7,
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_CRT_HSYNC_PV6,
+ PMUX_PINGRP_CRT_VSYNC_PV7,
+ PMUX_PINGRP_VI_D0_PT4,
+ PMUX_PINGRP_VI_D1_PD5,
+ PMUX_PINGRP_VI_D2_PL0,
+ PMUX_PINGRP_VI_D3_PL1,
+ PMUX_PINGRP_VI_D4_PL2,
+ PMUX_PINGRP_VI_D5_PL3,
+ PMUX_PINGRP_VI_D6_PL4,
+ PMUX_PINGRP_VI_D7_PL5,
+ PMUX_PINGRP_VI_D8_PL6,
+ PMUX_PINGRP_VI_D9_PL7,
+ PMUX_PINGRP_VI_D10_PT2,
+ PMUX_PINGRP_VI_D11_PT3,
+ PMUX_PINGRP_VI_PCLK_PT0,
+ PMUX_PINGRP_VI_MCLK_PT1,
+ PMUX_PINGRP_VI_VSYNC_PD6,
+ PMUX_PINGRP_VI_HSYNC_PD7,
+ PMUX_PINGRP_UART2_RXD_PC3,
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_PI2,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_SDMMC4_RST_N_PCC3,
+ PMUX_PINGRP_CAM_MCLK_PCC0,
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK_PU7,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_SPI2_MOSI_PX0,
+ PMUX_PINGRP_SPI2_MISO_PX1,
+ PMUX_PINGRP_SPI2_CS0_N_PX3,
+ PMUX_PINGRP_SPI2_SCK_PX2,
+ PMUX_PINGRP_SPI1_MOSI_PX4,
+ PMUX_PINGRP_SPI1_SCK_PX5,
+ PMUX_PINGRP_SPI1_CS0_N_PX6,
+ PMUX_PINGRP_SPI1_MISO_PX7,
+ PMUX_PINGRP_SPI2_CS1_N_PW2,
+ PMUX_PINGRP_SPI2_CS2_N_PW3,
+ PMUX_PINGRP_SDMMC3_CLK_PA6,
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_SDMMC3_DAT4_PD1,
+ PMUX_PINGRP_SDMMC3_DAT5_PD0,
+ PMUX_PINGRP_SDMMC3_DAT6_PD3,
+ PMUX_PINGRP_SDMMC3_DAT7_PD4,
+ PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1,
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5,
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
+ PMUX_PINGRP_PEX_L2_RST_N_PCC6,
+ PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
+ PMUX_PINGRP_HDMI_CEC_PEE3,
PMUX_PINGRP_COUNT,
};
enum pmux_drvgrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_CSUS,
- PDRIVE_PINGROUP_DAP1,
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_LCD1,
- PDRIVE_PINGROUP_LCD2,
- PDRIVE_PINGROUP_SDIO2,
- PDRIVE_PINGROUP_SDIO3,
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
- PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
- PDRIVE_PINGROUP_DDC,
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GMB,
- PDRIVE_PINGROUP_GMC,
- PDRIVE_PINGROUP_GMD,
- PDRIVE_PINGROUP_GME,
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_GPV,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_CSUS,
+ PMUX_DRVGRP_DAP1,
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_LCD1,
+ PMUX_DRVGRP_LCD2,
+ PMUX_DRVGRP_SDIO2,
+ PMUX_DRVGRP_SDIO3,
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_VI1,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_CRT = (0x90 / 4),
+ PMUX_DRVGRP_DDC,
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GMB,
+ PMUX_DRVGRP_GMC,
+ PMUX_DRVGRP_GMD,
+ PMUX_DRVGRP_GME,
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK_12M_OUT,
+ PMUX_FUNC_CLK_32K_IN,
+ PMUX_FUNC_CORE_PWR_REQ,
+ PMUX_FUNC_CPU_PWR_REQ,
PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HDCP,
PMUX_FUNC_HDMI,
+ PMUX_FUNC_HSI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_INVALID,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
+ PMUX_FUNC_NAND_ALT,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_RTCK,
+ PMUX_FUNC_SATA,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TEST,
PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- PMUX_FUNC_BLINK,
- PMUX_FUNC_CEC,
- PMUX_FUNC_CLK12,
- PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
- PMUX_FUNC_DEV3,
- PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
- PMUX_FUNC_EXTPERIPH1,
- PMUX_FUNC_EXTPERIPH2,
- PMUX_FUNC_EXTPERIPH3,
- PMUX_FUNC_GMI_ALT,
- PMUX_FUNC_HDA,
- PMUX_FUNC_HSI,
- PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
- PMUX_FUNC_I2CPWR,
- PMUX_FUNC_I2S0,
- PMUX_FUNC_I2S1,
- PMUX_FUNC_I2S2,
- PMUX_FUNC_I2S3,
- PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
- PMUX_FUNC_PWM0,
- PMUX_FUNC_PWM1,
- PMUX_FUNC_PWM2,
- PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
- PMUX_FUNC_SPI5,
- PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- PMUX_FUNC_CLK_12M_OUT,
- PMUX_FUNC_HDCP,
- PMUX_FUNC_TEST,
- PMUX_FUNC_CORE_PWR_REQ,
- PMUX_FUNC_CPU_PWR_REQ,
- PMUX_FUNC_PWR_INT_N,
- PMUX_FUNC_CLK_32K_IN,
-
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
PMUX_FUNC_COUNT,
-
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
index 69515d210612..00634f17aa93 100644
--- a/board/avionic-design/common/pinmux-config-tamonten-ng.h
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -10,7 +10,7 @@
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -22,7 +22,7 @@
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -34,7 +34,7 @@
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -46,7 +46,7 @@
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
@@ -58,323 +58,323 @@
static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, RSVD1, UP, NORMAL, INPUT),
/* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C4 pinmux */
- I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* Power I2C pinmux */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* UART1 */
- DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
/* UART2 */
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
/* UART3 */
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
/* UART4 */
- DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
/* DAP */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
/* I2S1 */
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* SPDIF */
- DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
/* I2S2 */
- DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
/* DAP4 */
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* Tamonten GPIO */
- DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT),
/* LCD */
- DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
/* BT656 */
- LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
/* GPIOs */
- DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT),
/* LCD BL */
- DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT),
/* SPI4 */
- DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
/* Video input GPIO */
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT),
/* Sensor GPIO */
- DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT),
/* JTAG */
- DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
/* Power controls */
- DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT),
/* SPI1 */
- DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
/* PMU */
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/* PCI */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/* HDMI */
- DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
};
static struct pmux_pingrp_config unused_pins_lowpower[] = {
/* UART1 - NC */
- DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
/* UART2 - NC */
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
/* DAP - NC */
- DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, NORMAL, INPUT),
/* DAP4 - NC */
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
/* Tamonten GPIO - NC */
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
/* BT656 - NC */
- LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
/* GPIO - NC */
- DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT),
/* Video input - NC */
- DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, RSVD1, NORMAL, NORMAL, INPUT),
/* KBC keys - NC */
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
/* PMU - NC */
- DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT),
/* Power rails GPIO - NC */
- DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, RSVD1, NORMAL, NORMAL, INPUT),
/* Others - NC */
- DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
};
static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
index c230dac1361e..255e4cd82bd5 100644
--- a/board/nvidia/cardhu/pinmux-config-cardhu.h
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -19,7 +19,7 @@
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -31,7 +31,7 @@
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -43,7 +43,7 @@
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -55,7 +55,7 @@
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
@@ -67,275 +67,275 @@
static struct pmux_pingrp_config tegra3_pinmux_common[] = {
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
/* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C4 pinmux */
- I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* Power I2C pinmux */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
- DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
- DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
- DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
/* KBC keys */
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
/* GPIOs */
/* SDMMC1 CD gpio */
- DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
/* SDMMC1 WP gpio */
- LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
/* Touch panel GPIO */
/* Touch IRQ */
- DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
/* Touch RESET */
- DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
/* Power rails GPIO */
- DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
- LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
};
static struct pmux_pingrp_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
};
static struct pmux_drvgrp_config cardhu_padctrl[] = {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 12/13] ARM: tegra: Tegra114 pinmux cleanup
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (10 preceding siblings ...)
2014-03-21 18:28 ` [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 " Stephen Warren
@ 2014-03-21 18:29 ` Stephen Warren
2014-03-21 18:29 ` [U-Boot] [PATCH V2 13/13] ARM: tegra: Tegra124 " Stephen Warren
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:29 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Fixed indentation of tegra114_pingroups[]
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 4 +-
arch/arm/cpu/tegra114-common/funcmux.c | 32 +-
arch/arm/cpu/tegra114-common/pinmux.c | 459 +++++++++++----------
arch/arm/include/asm/arch-tegra114/pinmux.h | 578 ++++++++++++---------------
board/nvidia/dalmore/pinmux-config-dalmore.h | 360 ++++++++---------
5 files changed, 680 insertions(+), 753 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index d10b96a1d45a..5ed3bb9d9aba 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void)
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
- pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
/*
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c
index 5af755034d6d..52441c71e653 100644
--- a/arch/arm/cpu/tegra114-common/funcmux.c
+++ b/arch/arm/cpu/tegra114-common/funcmux.c
@@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GMI:
- pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
-
- pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PINGRP_GMI_A16);
- pinmux_tristate_disable(PINGRP_GMI_A17);
- pinmux_tristate_disable(PINGRP_GMI_A18);
- pinmux_tristate_disable(PINGRP_GMI_A19);
+ pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
break;
}
break;
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 5d3d4d52e8a1..3e5acb93ce28 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -1,77 +1,59 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra114 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
-static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra114_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(PV0, USB, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3068 */
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
PIN_RESERVED,
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
@@ -110,11 +92,11 @@ static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
+ /* Offset 0x3110 */
+ PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
- PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
@@ -132,175 +114,180 @@ static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
- PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
- PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
- PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
- PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
- PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
- PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
- PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3280 */
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
- PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
- PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
- PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
- PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
- PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
- PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
- PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
- PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
- PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
- PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
- PIN_RESERVED,
- PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
- PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
- PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
- PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
- PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
- PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
- PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
- PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3404 */
- PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ /* Offset 0x3164 */
+ PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4),
+ PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA),
+ PIN(PU0, OWR, UARTA, RSVD3, RSVD4),
+ PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4),
+ PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4),
+ PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU6, PWM3, UARTA, USB, DISPLAYB),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE),
+ PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
+ PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
+ PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
+ PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
+ PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
+ PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
+ PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
+ PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2),
+ PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV),
+ PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS),
+ PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS),
+ PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB),
+ PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4),
+ PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4),
+ PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV),
+ PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV),
+ PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT),
+ PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE),
+ PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE),
+ PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE),
+ PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC),
+ PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3284 */
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB),
+ PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB),
+ PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+ PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x32fc */
+ PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL),
+ PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL),
+ PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
+ PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
+ PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4),
+ PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
+ PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
+ PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4),
+ PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4),
+ PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4),
+ PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4),
+ PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4),
+ PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4),
+ PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2),
+ PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3390 */
+ PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
+ PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
+ PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
+ PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33e0 */
+ PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC),
+ PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
+ PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
+ PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
+ PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
+ PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
+ PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4),
+ PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 070745933503..0df69e3ab34b 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -1,375 +1,311 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA114_PINMUX_H_
#define _TEGRA114_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_P_PJ3,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
PMUX_PINGRP_COUNT,
};
enum pmux_drvgrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3,
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4,
+ PMUX_DRVGRP_AO0,
PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_NAND,
PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
PMUX_FUNC_COUNT,
-
- PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 6069fb6c02c8..891ac07dd903 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -19,7 +19,7 @@
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -31,7 +31,7 @@
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -43,7 +43,7 @@
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -55,7 +55,7 @@
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -67,7 +67,7 @@
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -81,7 +81,7 @@
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
@@ -93,142 +93,142 @@
static struct pmux_pingrp_config tegra114_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
- DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* VI pinmux */
- VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* VI_ALT1 pinmux */
- VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* VGP4 pinmux */
- VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux */
- DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 pinmux */
- DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SOC pinmux */
- DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT),
/* EXTPERIPH2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
- DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
/*Audio Codec*/
- DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux */
- DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* SYSCLK pinmux */
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
@@ -249,117 +249,117 @@ static struct pmux_pingrp_config tegra114_pinmux_common[] = {
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB pinmux */
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
/* IRDA pinmux */
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
/* UARTC pinmux */
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
/* OWR pinmux */
- DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
/* CEC pinmux */
- CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 pinmux */
- DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
- DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
- USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* nct */
- DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT),
};
static struct pmux_pingrp_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
- DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
};
static struct pmux_drvgrp_config dalmore_padctrl[] = {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 13/13] ARM: tegra: Tegra124 pinmux cleanup
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
` (11 preceding siblings ...)
2014-03-21 18:29 ` [U-Boot] [PATCH V2 12/13] ARM: tegra: Tegra114 " Stephen Warren
@ 2014-03-21 18:29 ` Stephen Warren
12 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-21 18:29 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra124_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
There are differences in the set of drive groups. I have validated this
against the TRM. There are differences order of pin definitions in
pinmux.c; these previously had significant mismatches with the correct
order:-( I adjusted a few entries in pinmux-config-venice2.h since the
set of legal functions for some pins was updated to match the TRM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Fixed indentation of tegra124_pingroups[].
---
arch/arm/cpu/arm720t/tegra124/cpu.c | 4 +-
arch/arm/cpu/tegra124-common/funcmux.c | 38 +-
arch/arm/cpu/tegra124-common/pinmux.c | 463 ++++++++++----------
arch/arm/include/asm/arch-tegra124/pinmux.h | 611 ++++++++++++---------------
board/nvidia/venice2/pinmux-config-venice2.h | 334 +++++++--------
5 files changed, 706 insertions(+), 744 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index 97f5928bd7da..6ff6aeb5463a 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -26,8 +26,8 @@ static void enable_cpu_power_rail(void)
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
- pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
pmic_enable_cpu_vdd();
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
index d19fda06c55c..cced787e6b6d 100644
--- a/arch/arm/cpu/tegra124-common/funcmux.c
+++ b/arch/arm/cpu/tegra124-common/funcmux.c
@@ -20,20 +20,20 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
- pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
- pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
- pinmux_tristate_disable(PINGRP_GPIO_PJ7);
- pinmux_tristate_disable(PINGRP_GPIO_PB0);
- pinmux_tristate_disable(PINGRP_GPIO_PB1);
- pinmux_tristate_disable(PINGRP_GPIO_PK7);
+ pinmux_tristate_disable(PMUX_PINGRP_PJ7);
+ pinmux_tristate_disable(PMUX_PINGRP_PB0);
+ pinmux_tristate_disable(PMUX_PINGRP_PB1);
+ pinmux_tristate_disable(PMUX_PINGRP_PK7);
break;
}
break;
@@ -41,14 +41,16 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_KBC:
- pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_FUNC_UARTA);
- pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
- pinmux_tristate_disable(PINGRP_KB_ROW9);
- pinmux_tristate_disable(PINGRP_KB_ROW10);
+ pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
+ pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
break;
}
break;
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index a2385653055c..c6685eaae1e9 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -1,68 +1,59 @@
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra124 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
-static const struct pmux_pingrp_desc tegra124_pingroups[PMUX_PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra124_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4),
+ PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB),
+ PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3068 */
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
PIN_RESERVED,
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
@@ -101,11 +92,11 @@ static const struct pmux_pingrp_desc tegra124_pingroups[PMUX_PINGRP_COUNT] = {
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
+ /* Offset 0x3110 */
+ PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
- PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
@@ -123,175 +114,193 @@ static const struct pmux_pingrp_desc tegra124_pingroups[PMUX_PINGRP_COUNT] = {
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
- PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
- PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
- PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
- PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
- PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
- PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
- PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3280 */
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
- PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
- PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
- PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
- PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
- PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
- PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
- PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
- PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
- PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
- PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
- PIN_RESERVED,
- PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
- PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
- PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
- PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
- PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
- PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
- PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
- PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3404 */
- PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ /* Offset 0x3164 */
+ PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4),
+ PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI),
+ PIN(PU0, OWR, UARTA, GMI, RSVD4),
+ PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU3, PWM0, UARTA, GMI, DISPLAYB),
+ PIN(PU4, PWM1, UARTA, GMI, DISPLAYB),
+ PIN(PU5, PWM2, UARTA, GMI, DISPLAYB),
+ PIN(PU6, PWM3, UARTA, RSVD3, GMI),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT),
+ PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PI7, RSVD1, TRACE, GMI, DTV),
+ PIN(PK0, RSVD1, SDMMC3, GMI, SOC),
+ PIN(PK1, SDMMC2, TRACE, GMI, RSVD4),
+ PIN(PJ0, RSVD1, RSVD2, GMI, USB),
+ PIN(PJ2, RSVD1, RSVD2, GMI, SOC),
+ PIN(PK3, SDMMC2, TRACE, GMI, CCLA),
+ PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT),
+ PIN(PK2, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI3, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2),
+ PIN(PG0, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PG1, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PG2, RSVD1, TRACE, GMI, RSVD4),
+ PIN(PG3, RSVD1, TRACE, GMI, RSVD4),
+ PIN(PG4, RSVD1, TMDS, GMI, SPI4),
+ PIN(PG5, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PG6, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PG7, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PH0, PWM0, TRACE, GMI, DTV),
+ PIN(PH1, PWM1, TMDS, GMI, DISPLAYA),
+ PIN(PH2, PWM2, TMDS, GMI, CLDVFS),
+ PIN(PH3, PWM3, SPI4, GMI, CLDVFS),
+ PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PH6, SDMMC2, TRACE, GMI, DTV),
+ PIN(PH7, SDMMC2, TRACE, GMI, DTV),
+ PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT),
+ PIN(PB0, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PB1, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PK7, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PI0, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI1, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI2, SDMMC2, TRACE, GMI, RSVD4),
+ PIN(PI4, SPI4, TRACE, GMI, DISPLAYA),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4),
+ PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3284 */
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2),
+ PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2),
+ PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2),
+ PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2),
+ PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
+ PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB),
+ PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+ PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA),
+ PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA),
+ PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4),
+ PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
+ PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
+ PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD),
+ PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD),
+ PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3324 */
+ PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4),
+ PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3),
+ PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4),
+ PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4),
+ PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4),
+ PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4),
+ PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4),
+ PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2),
+ PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI),
+ PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3390 */
+ PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
+ PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
+ PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
+ PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33bc */
+ PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x33cc */
+ PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33e0 */
+ PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
+ PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
+ PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
+ PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
+ PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
+ PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC),
+ PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC),
+ PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4),
+ PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3430 */
+ PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index b37590671202..70254b5c731e 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -1,382 +1,333 @@
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_PINMUX_H_
#define _TEGRA124_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
- PINGRP_GPIO_PC7, /* offset 0x31c0 */
- PINGRP_GPIO_PI5,
- PINGRP_GPIO_PI7,
- PINGRP_GPIO_PK0,
- PINGRP_GPIO_PK1,
- PINGRP_GPIO_PJ0,
- PINGRP_GPIO_PJ2,
- PINGRP_GPIO_PK3,
- PINGRP_GPIO_PK4,
- PINGRP_GPIO_PK2,
- PINGRP_GPIO_PI3,
- PINGRP_GPIO_PI6,
- PINGRP_GPIO_PG0,
- PINGRP_GPIO_PG1,
- PINGRP_GPIO_PG2,
- PINGRP_GPIO_PG3,
- PINGRP_GPIO_PG4,
- PINGRP_GPIO_PG5,
- PINGRP_GPIO_PG6,
- PINGRP_GPIO_PG7,
- PINGRP_GPIO_PH0,
- PINGRP_GPIO_PH1,
- PINGRP_GPIO_PH2,
- PINGRP_GPIO_PH3,
- PINGRP_GPIO_PH4,
- PINGRP_GPIO_PH5,
- PINGRP_GPIO_PH6,
- PINGRP_GPIO_PH7,
- PINGRP_GPIO_PJ7,
- PINGRP_GPIO_PB0,
- PINGRP_GPIO_PB1,
- PINGRP_GPIO_PK7,
- PINGRP_GPIO_PI0,
- PINGRP_GPIO_PI1,
- PINGRP_GPIO_PI2,
- PINGRP_GPIO_PI4, /* offset 0x324c */
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0, /* offset 0x32fc */
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
- PINGRP_PEX_L0_CLKREQ,
- PINGRP_PEX_WAKE,
- PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
- PINGRP_PEX_L1_CLKREQ,
- PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0,
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_GMI_CLK_LB,
- PINGRP_RESET_OUT_N,
- PINGRP_KB_ROW16, /* offset 0x340c */
- PINGRP_KB_ROW17,
- PINGRP_USB_VBUS_EN2,
- PINGRP_GPIO_PFF2,
- PINGRP_DP_HPD, /* last reg offset = 0x3430 */
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_PC7,
+ PMUX_PINGRP_PI5,
+ PMUX_PINGRP_PI7,
+ PMUX_PINGRP_PK0,
+ PMUX_PINGRP_PK1,
+ PMUX_PINGRP_PJ0,
+ PMUX_PINGRP_PJ2,
+ PMUX_PINGRP_PK3,
+ PMUX_PINGRP_PK4,
+ PMUX_PINGRP_PK2,
+ PMUX_PINGRP_PI3,
+ PMUX_PINGRP_PI6,
+ PMUX_PINGRP_PG0,
+ PMUX_PINGRP_PG1,
+ PMUX_PINGRP_PG2,
+ PMUX_PINGRP_PG3,
+ PMUX_PINGRP_PG4,
+ PMUX_PINGRP_PG5,
+ PMUX_PINGRP_PG6,
+ PMUX_PINGRP_PG7,
+ PMUX_PINGRP_PH0,
+ PMUX_PINGRP_PH1,
+ PMUX_PINGRP_PH2,
+ PMUX_PINGRP_PH3,
+ PMUX_PINGRP_PH4,
+ PMUX_PINGRP_PH5,
+ PMUX_PINGRP_PH6,
+ PMUX_PINGRP_PH7,
+ PMUX_PINGRP_PJ7,
+ PMUX_PINGRP_PB0,
+ PMUX_PINGRP_PB1,
+ PMUX_PINGRP_PK7,
+ PMUX_PINGRP_PI0,
+ PMUX_PINGRP_PI1,
+ PMUX_PINGRP_PI2,
+ PMUX_PINGRP_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+ PMUX_PINGRP_DAP_MCLK1_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
+ PMUX_PINGRP_KB_ROW16_PT0,
+ PMUX_PINGRP_KB_ROW17_PT1,
+ PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+ PMUX_PINGRP_PFF2,
+ PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
PMUX_PINGRP_COUNT,
};
enum pmux_drvgrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3 = (0x140 / 4),
+ PMUX_DRVGRP_AO0 = (0x148 / 4),
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+ PMUX_DRVGRP_AO4,
PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
+ PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DP,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PE,
+ PMUX_FUNC_PE0,
+ PMUX_FUNC_PE1,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
PMUX_FUNC_SATA,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_SYS,
+ PMUX_FUNC_TMDS,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_VIMCLK2,
+ PMUX_FUNC_VIMCLK2_ALT,
PMUX_FUNC_COUNT,
-
- PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index 51cd4bfcb6cc..2f79ec75237e 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -10,7 +10,7 @@
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -22,7 +22,7 @@
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -34,7 +34,7 @@
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -46,7 +46,7 @@
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingrp = PINGRP_##_pingrp, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@@ -56,23 +56,23 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define USB_PINMUX CEC_PINMUX
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
@@ -84,122 +84,122 @@
static struct pmux_pingrp_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
- DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
/* EC KBC/SPI */
- DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
- DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 (Winbond 'boot ROM') */
- DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT),
/* Touch IRQ */
- DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
- DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
- DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
/* Misc */
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
- DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
@@ -220,115 +220,115 @@ static struct pmux_pingrp_config tegra124_pinmux_common[] = {
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB, GPS */
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
/* UARTC (WIFI/BT) */
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
/* CEC pinmux */
- CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 (HDMI_DDC) pinmux */
- DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
- DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
- USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* Unused, marked SNN_ on schematic, TRISTATE 'em */
- DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT),
};
static struct pmux_pingrp_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
- DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
/* EN_VDD_BL */
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
/* MODEM */
- DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
/* BOOT_SEL0-3 */
- DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
/* TS_SHDN_L */
- DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
static struct pmux_drvgrp_config venice2_padctrl[] = {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places
2014-03-21 18:28 ` [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places Stephen Warren
@ 2014-03-25 2:17 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:17 UTC (permalink / raw)
To: u-boot
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra's "APB misc" register region contains various miscellaneous
> registers and the Tegra pinmux registers. Some code that touches the
> misc registers currently uses struct pmux_tri_ctlr, which is intended to
> be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
> which is intended to be a definition of the miscellaneous registers.
> Convert all such code to use struct apb_misc_pp_ctrl, since struct
> pmux_tri_ctlr goes away in the next patch.
>
> This requires adding a missing field definition to struct
> apb_misc_pp_ctrl, and moving the header into a more common location.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication
2014-03-21 18:28 ` [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication Stephen Warren
@ 2014-03-25 2:23 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:23 UTC (permalink / raw)
To: u-boot
Hi Stephen,
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
> duplication by creating pinmux-common.c for all the identical code.
>
> This leaves:
> * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
> the various pins/pin groups, drive groups, and mux functions.
> * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
> stating which pin groups support which mux functions.
>
> The code in pinmux-common.c is semantically identical to that in the
> various original pinmux.c, but had some consistency and cleanup fixes
> applied during migration.
>
> I removed the definition of struct pmux_tri_ctlr, since this is different
> between SoCs (especially Tegra20 vs all others), and it's much simpler to
> deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
> and warmboot_avp.c needed updates due to this, since they previously
> hijacked this struct to encode the location of some non-pinmux registers.
> Now, that code simply calculates these register addresses directly using
> simple and obvious math. I like this method better irrespective of the
> pinmux code cleanup anyway.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
IMO it would be better for the #defines to go in the relevant header
(e.g. T20/T30) rather than having #ifdef TEGRA20 in this file. But OK.
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes
2014-03-21 18:28 ` [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes Stephen Warren
@ 2014-03-25 2:24 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:24 UTC (permalink / raw)
To: u-boot
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Clean up the naming of pinmux-related objects:
> * Refer to drive groups rather than pad groups to match the Linux kernel.
> * Ensure all pinmux API types are prefixed with pmux_, values (defines)
> are prefixed with PMUX_, and functions prefixed with pinmux_.
> * Modify a few type names to make their content clearer.
> * Minimal changes to SoC-specific .h/.c files are made so the code still
> compiles. A separate per-SoC change will be made immediately following,
> in order to keep individual patch size down.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-21 18:28 ` [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver Stephen Warren
@ 2014-03-25 2:27 ` Simon Glass
2014-03-25 15:54 ` Stephen Warren
2014-03-25 17:26 ` Stephen Warren
1 sibling, 1 reply; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:27 UTC (permalink / raw)
To: u-boot
Hi Stephen,
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This removes a bunch of open-coded register IO, masking, and shifting.
> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> except that keeping it a separate commit allows easier bisection of any
> issues that are introduced by this patch. I also wrote this patch on top
> of the series, and pushing it any lower in the series results in some
> conflicts I didn't feel like fixing.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
But see comment below.
> ---
> V2: New patch.
> ---
> arch/arm/cpu/tegra-common/pinmux-common.c | 135 +++++-------------------------
> 1 file changed, 23 insertions(+), 112 deletions(-)
>
> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
> index 32a46d53f068..7f7d4a87a4aa 100644
> --- a/arch/arm/cpu/tegra-common/pinmux-common.c
> +++ b/arch/arm/cpu/tegra-common/pinmux-common.c
> @@ -87,11 +87,15 @@
> #define IO_RESET_SHIFT 8
> #define RCV_SEL_SHIFT 9
>
> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
> +{
> + clrsetbits_le32(reg, mask << shift, val << shift);
I wonder if it would be better to write this out explicitly in each site.
> +}
> +
> void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
> {
> u32 *reg = MUX_REG(pin);
> int i, mux = -1;
> - u32 val;
>
> /* Error check on pin and func */
> assert(pmux_pingrp_isvalid(pin));
> @@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
> }
> assert(mux != -1);
>
> - val = readl(reg);
> - val &= ~(3 << MUX_SHIFT(pin));
> - val |= (mux << MUX_SHIFT(pin));
> - writel(val, reg);
> + update_field(reg, 3, MUX_SHIFT(pin), mux);
Because here you are obscuring the shift - the parameter order is by
no means obvious.
Or perhaps update_reg_mask_shift_val()?
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup
2014-03-21 18:28 ` [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup Stephen Warren
@ 2014-03-25 2:29 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:29 UTC (permalink / raw)
To: u-boot
Hi Stephen,
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This renames all the Tegra20 pinmux pins and functions so they have a
> prefix which matches the type name.
>
> The entries in tegra20_pingroups[] are all updated to remove the columns
> which are no longer used.
>
> All affected code is updated to match.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
I see you have removed the 'safe' parameter - I guess that is what you mean.
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 pinmux cleanup
2014-03-21 18:28 ` [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 " Stephen Warren
@ 2014-03-25 2:30 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2014-03-25 2:30 UTC (permalink / raw)
To: u-boot
On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This renames all the pinmux pins, drive groups, and functions so they
> have a prefix which matches the type name. These lists are also auto-
> generated using scripts that were also used to generate the kernel
> pinctrl drivers. This ensures that the lists are consistent between the
> two.
>
> The entries in tegra30_pingroups[] are all updated to remove the columns
> which are no longer used.
>
> All affected code is updated to match.
>
> This introduces a few changes to pin/group/function naming and the set of
> available functions for each pin. The new values now exactly match the
> TRM; the chip documentation. I adjusted one entry in
> pinmux-config-cardhu.h due to this.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 2:27 ` Simon Glass
@ 2014-03-25 15:54 ` Stephen Warren
2014-03-25 16:04 ` Simon Glass
2014-03-25 16:51 ` Wolfgang Denk
0 siblings, 2 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-25 15:54 UTC (permalink / raw)
To: u-boot
On 03/24/2014 08:27 PM, Simon Glass wrote:
> Hi Stephen,
>
> On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> This removes a bunch of open-coded register IO, masking, and shifting.
>> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
>> except that keeping it a separate commit allows easier bisection of any
>> issues that are introduced by this patch. I also wrote this patch on top
>> of the series, and pushing it any lower in the series results in some
>> conflicts I didn't feel like fixing.
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> But see comment below.
>> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
>> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
>> +{
>> + clrsetbits_le32(reg, mask << shift, val << shift);
>
> I wonder if it would be better to write this out explicitly in each site.
>
>> +}
>> +
>> void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>> {
>> u32 *reg = MUX_REG(pin);
>> int i, mux = -1;
>> - u32 val;
>>
>> /* Error check on pin and func */
>> assert(pmux_pingrp_isvalid(pin));
>> @@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>> }
>> assert(mux != -1);
>>
>> - val = readl(reg);
>> - val &= ~(3 << MUX_SHIFT(pin));
>> - val |= (mux << MUX_SHIFT(pin));
>> - writel(val, reg);
>> + update_field(reg, 3, MUX_SHIFT(pin), mux);
>
> Because here you are obscuring the shift - the parameter order is by
> no means obvious.
Well, for pretty much no function is it obvious from the function name
what the parameter order is; it's just one of those things you memorize
or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.
> Or perhaps update_reg_mask_shift_val()?
Still, I can rename the function if you want; it certainly does make it
obvious. It's rather a long name though, but I guess wrapping the
parameters isn't too bad.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 15:54 ` Stephen Warren
@ 2014-03-25 16:04 ` Simon Glass
2014-03-25 16:28 ` Stephen Warren
2014-03-25 16:51 ` Wolfgang Denk
1 sibling, 1 reply; 28+ messages in thread
From: Simon Glass @ 2014-03-25 16:04 UTC (permalink / raw)
To: u-boot
Hi Stephen,
On 25 March 2014 08:54, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 03/24/2014 08:27 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> From: Stephen Warren <swarren@nvidia.com>
>>>
>>> This removes a bunch of open-coded register IO, masking, and shifting.
>>> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
>>> except that keeping it a separate commit allows easier bisection of any
>>> issues that are introduced by this patch. I also wrote this patch on top
>>> of the series, and pushing it any lower in the series results in some
>>> conflicts I didn't feel like fixing.
>>>
>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>> But see comment below.
>
>>> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
>
>>> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
>>> +{
>>> + clrsetbits_le32(reg, mask << shift, val << shift);
>>
>> I wonder if it would be better to write this out explicitly in each site.
>>
>>> +}
>>> +
>>> void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>>> {
>>> u32 *reg = MUX_REG(pin);
>>> int i, mux = -1;
>>> - u32 val;
>>>
>>> /* Error check on pin and func */
>>> assert(pmux_pingrp_isvalid(pin));
>>> @@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>>> }
>>> assert(mux != -1);
>>>
>>> - val = readl(reg);
>>> - val &= ~(3 << MUX_SHIFT(pin));
>>> - val |= (mux << MUX_SHIFT(pin));
>>> - writel(val, reg);
>>> + update_field(reg, 3, MUX_SHIFT(pin), mux);
>>
>> Because here you are obscuring the shift - the parameter order is by
>> no means obvious.
>
> Well, for pretty much no function is it obvious from the function name
> what the parameter order is; it's just one of those things you memorize
> or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.
Well that at least indicates that the clr mask comes before set.
>
>> Or perhaps update_reg_mask_shift_val()?
>
> Still, I can rename the function if you want; it certainly does make it
> obvious. It's rather a long name though, but I guess wrapping the
> parameters isn't too bad.
I'll leave it to you, it's just a thought.
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 16:04 ` Simon Glass
@ 2014-03-25 16:28 ` Stephen Warren
0 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2014-03-25 16:28 UTC (permalink / raw)
To: u-boot
On 03/25/2014 10:04 AM, Simon Glass wrote:
> On 25 March 2014 08:54, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 03/24/2014 08:27 PM, Simon Glass wrote:
>>> On 21 March 2014 11:28, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> This removes a bunch of open-coded register IO, masking, and shifting.
>>>> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
>>>> except that keeping it a separate commit allows easier bisection of any
>>>> issues that are introduced by this patch. I also wrote this patch on top
>>>> of the series, and pushing it any lower in the series results in some
>>>> conflicts I didn't feel like fixing.
>>>>
>>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>
>>> But see comment below.
>>
>>>> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
>>
>>>> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
>>>> +{
>>>> + clrsetbits_le32(reg, mask << shift, val << shift);
>>>
>>> I wonder if it would be better to write this out explicitly in each site.
...
>>>> + update_field(reg, 3, MUX_SHIFT(pin), mux);
>>>
>>> Because here you are obscuring the shift - the parameter order is by
>>> no means obvious.
>>
>> Well, for pretty much no function is it obvious from the function name
>> what the parameter order is; it's just one of those things you memorize
>> or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.
>
> Well that at least indicates that the clr mask comes before set.
>
>>
>>> Or perhaps update_reg_mask_shift_val()?
>>
>> Still, I can rename the function if you want; it certainly does make it
>> obvious. It's rather a long name though, but I guess wrapping the
>> parameters isn't too bad.
>
> I'll leave it to you, it's just a thought.
Well, the wrapping didn't work out to badly, so I posted V3 including
this rename.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 15:54 ` Stephen Warren
2014-03-25 16:04 ` Simon Glass
@ 2014-03-25 16:51 ` Wolfgang Denk
2014-03-25 16:55 ` Stephen Warren
1 sibling, 1 reply; 28+ messages in thread
From: Wolfgang Denk @ 2014-03-25 16:51 UTC (permalink / raw)
To: u-boot
Dear Stephen Warren,
In message <5331A6B6.8090805@wwwdotorg.org> you wrote:
>
> > Or perhaps update_reg_mask_shift_val()?
>
> Still, I can rename the function if you want; it certainly does make it
> obvious. It's rather a long name though, but I guess wrapping the
> parameters isn't too bad.
Please do not invent new bit manipulation functions. Just use the
standard I/O accessors. And whenever possible, please remove pre-
existing functions.
I've just recently sent patches to get rid of such "inventions" that
resulted in undefined code.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Faith: not *wanting* to know what is true." - Friedrich Nietzsche
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 16:51 ` Wolfgang Denk
@ 2014-03-25 16:55 ` Stephen Warren
2014-03-25 17:03 ` Wolfgang Denk
0 siblings, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-25 16:55 UTC (permalink / raw)
To: u-boot
On 03/25/2014 10:51 AM, Wolfgang Denk wrote:
> Dear Stephen Warren,
>
> In message <5331A6B6.8090805@wwwdotorg.org> you wrote:
>>
>>> Or perhaps update_reg_mask_shift_val()?
>>
>> Still, I can rename the function if you want; it certainly does make it
>> obvious. It's rather a long name though, but I guess wrapping the
>> parameters isn't too bad.
>
> Please do not invent new bit manipulation functions. Just use the
> standard I/O accessors. And whenever possible, please remove pre-
> existing functions.
>
> I've just recently sent patches to get rid of such "inventions" that
> resulted in undefined code.
That's not what this code is doing. The existing IO accessors are used;
it's just removing duplication from the parameters passed to the
existing functions (the shift needs to be written out twice).
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 16:55 ` Stephen Warren
@ 2014-03-25 17:03 ` Wolfgang Denk
0 siblings, 0 replies; 28+ messages in thread
From: Wolfgang Denk @ 2014-03-25 17:03 UTC (permalink / raw)
To: u-boot
Dear Stephen Warren,
In message <5331B4E4.5090101@wwwdotorg.org> you wrote:
>
> > Please do not invent new bit manipulation functions. Just use the
> > standard I/O accessors. And whenever possible, please remove pre-
> > existing functions.
> >
> > I've just recently sent patches to get rid of such "inventions" that
> > resulted in undefined code.
>
> That's not what this code is doing. The existing IO accessors are used;
> it's just removing duplication from the parameters passed to the
> existing functions (the shift needs to be written out twice).
Yes, I've seen that. You can save a little typ[ing this way. But you
have to type it only once, and then maintain it forever. And the
helper function obscures what is happening, which is bad. It makes
the code more difficult to read and understand and maintain,
especially when the shift count is not easily recognizable - at least I
cannot really read what PULL_SHIFT(pin) decodes to.
Please make the code simple to read, use existing standard functions.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
An armed society is a polite society.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-21 18:28 ` [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver Stephen Warren
2014-03-25 2:27 ` Simon Glass
@ 2014-03-25 17:26 ` Stephen Warren
2014-03-25 19:11 ` Wolfgang Denk
1 sibling, 1 reply; 28+ messages in thread
From: Stephen Warren @ 2014-03-25 17:26 UTC (permalink / raw)
To: u-boot
On 03/21/2014 12:28 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This removes a bunch of open-coded register IO, masking, and shifting.
> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> except that keeping it a separate commit allows easier bisection of any
> issues that are introduced by this patch. I also wrote this patch on top
> of the series, and pushing it any lower in the series results in some
> conflicts I didn't feel like fixing.
Tom, when applying this series, please just drop this patch. Also,
ignore V3 of this patch. Thanks.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver
2014-03-25 17:26 ` Stephen Warren
@ 2014-03-25 19:11 ` Wolfgang Denk
0 siblings, 0 replies; 28+ messages in thread
From: Wolfgang Denk @ 2014-03-25 19:11 UTC (permalink / raw)
To: u-boot
Dear Tom,
In message <5331BC48.7020807@wwwdotorg.org> Stephen Warren wrote:
> On 03/21/2014 12:28 PM, Stephen Warren wrote:
> > From: Stephen Warren <swarren@nvidia.com>
> >
> > This removes a bunch of open-coded register IO, masking, and shifting.
> > I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> > except that keeping it a separate commit allows easier bisection of any
> > issues that are introduced by this patch. I also wrote this patch on top
> > of the series, and pushing it any lower in the series results in some
> > conflicts I didn't feel like fixing.
>
> Tom, when applying this series, please just drop this patch. Also,
> ignore V3 of this patch. Thanks.
Alternatively, please consider patch V4 which I just posted.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
One essential to success is that you desire be an all-obsessing one,
your thoughts and aims be co-ordinated, and your energy be concentra-
ted and applied without letup.
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2014-03-25 19:11 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-03-21 18:28 [U-Boot] [PATCH V2 00/13] ARM: tegra: pinmux driver cleanup Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 01/13] ARM: tegra: pinctrl: remove func_safe Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 02/13] ARM: tegra: pinctrl: remove vddio Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 03/13] ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20 Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 04/13] ARM: tegra: prototype pinmux_init() in board.h Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 05/13] ARM: tegra: use apb_misc.h in more places Stephen Warren
2014-03-25 2:17 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 06/13] ARM: tegra: pinctrl: remove duplication Stephen Warren
2014-03-25 2:23 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 07/13] ARM: tegra: reduce public pinmux API Stephen Warren
2014-03-21 18:28 ` [U-Boot] [PATCH V2 08/13] ARM: tegra: pinmux naming consistency fixes Stephen Warren
2014-03-25 2:24 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver Stephen Warren
2014-03-25 2:27 ` Simon Glass
2014-03-25 15:54 ` Stephen Warren
2014-03-25 16:04 ` Simon Glass
2014-03-25 16:28 ` Stephen Warren
2014-03-25 16:51 ` Wolfgang Denk
2014-03-25 16:55 ` Stephen Warren
2014-03-25 17:03 ` Wolfgang Denk
2014-03-25 17:26 ` Stephen Warren
2014-03-25 19:11 ` Wolfgang Denk
2014-03-21 18:28 ` [U-Boot] [PATCH V2 10/13] ARM: tegra: Tegra20 pinmux cleanup Stephen Warren
2014-03-25 2:29 ` Simon Glass
2014-03-21 18:28 ` [U-Boot] [PATCH V2 11/13] ARM: tegra: Tegra30 " Stephen Warren
2014-03-25 2:30 ` Simon Glass
2014-03-21 18:29 ` [U-Boot] [PATCH V2 12/13] ARM: tegra: Tegra114 " Stephen Warren
2014-03-21 18:29 ` [U-Boot] [PATCH V2 13/13] ARM: tegra: Tegra124 " Stephen Warren
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