[Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Anton Blanchard]

Add MSR_LE to the msr_mask for POWER8.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
 target-ppc/translate_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7f53c33..a82c8f9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7175,7 +7175,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
                         PPC2_ISA205 | PPC2_ISA207S;
-    pcc->msr_mask = 0x800000000284FF36ULL;
+    pcc->msr_mask = 0x800000000284FF37ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-- 
1.8.3.2

[Qemu-devel] [PATCH 2/6] target-ppc: POWER8 supports isel

[Anton Blanchard]

POWER8 supports isel, so enable it in QEMU.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
 target-ppc/translate_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a82c8f9..4fda0fd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7157,7 +7157,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
     pcc->init_proc = init_proc_POWER8;
     pcc->check_pow = check_pow_nocheck;
-    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
                        PPC_FLOAT_FRSQRTES |
-- 
1.8.3.2

[Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit

[Anton Blanchard]

Without MSR_VSX we die early during a Linux boot.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
 target-ppc/translate_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4fda0fd..87c00a1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7118,7 +7118,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
                         PPC2_FP_TST_ISA206;
-    pcc->msr_mask = 0x800000000204FF37ULL;
+    pcc->msr_mask = 0x800000000284FF37ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-- 
1.8.3.2

[Qemu-devel] [PATCH 4/6] target-ppc: MSR_POW not supported on POWER7/7+/8

[Anton Blanchard]

Remove MSR_POW from the msr_mask for POWER7/7+/8.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
 target-ppc/translate_init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 87c00a1..d07e186 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7075,7 +7075,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
                         PPC2_FP_TST_ISA206;
-    pcc->msr_mask = 0x800000000284FF37ULL;
+    pcc->msr_mask = 0x800000000280FF37ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7118,7 +7118,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
                         PPC2_FP_TST_ISA206;
-    pcc->msr_mask = 0x800000000284FF37ULL;
+    pcc->msr_mask = 0x800000000280FF37ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7175,7 +7175,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
                         PPC2_ISA205 | PPC2_ISA207S;
-    pcc->msr_mask = 0x800000000284FF37ULL;
+    pcc->msr_mask = 0x800000000280FF37ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-- 
1.8.3.2

[Qemu-devel] [PATCH 5/6] target-ppc: Fix Book3S PMU SPRs

[Anton Blanchard]

Most of the PMU SPRs were wrong on Book3S.

Signed-off-by: Anton Blanchard <anton@samba.org>
---
 target-ppc/cpu.h            |  29 ++++++++-
 target-ppc/translate_init.c | 139 +++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 153 insertions(+), 15 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2719c08..7082041 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1452,54 +1452,81 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_MI_CTR        (0x300)
 #define SPR_PERF1             (0x301)
 #define SPR_RCPU_MI_RBA1      (0x301)
+#define SPR_BOOK3S_UMMCR2     (0x301)
 #define SPR_PERF2             (0x302)
 #define SPR_RCPU_MI_RBA2      (0x302)
 #define SPR_MPC_MI_AP         (0x302)
-#define SPR_MMCRA             (0x302)
+#define SPR_BOOK3S_UMMCRA     (0x302)
 #define SPR_PERF3             (0x303)
 #define SPR_RCPU_MI_RBA3      (0x303)
 #define SPR_MPC_MI_EPN        (0x303)
+#define SPR_BOOK3S_UPMC1      (0x303)
 #define SPR_PERF4             (0x304)
+#define SPR_BOOK3S_UPMC2      (0x304)
 #define SPR_PERF5             (0x305)
 #define SPR_MPC_MI_TWC        (0x305)
+#define SPR_BOOK3S_UPMC3      (0x305)
 #define SPR_PERF6             (0x306)
 #define SPR_MPC_MI_RPN        (0x306)
+#define SPR_BOOK3S_UPMC4      (0x306)
 #define SPR_PERF7             (0x307)
+#define SPR_BOOK3S_UPMC5      (0x307)
 #define SPR_PERF8             (0x308)
 #define SPR_RCPU_L2U_RBA0     (0x308)
 #define SPR_MPC_MD_CTR        (0x308)
+#define SPR_BOOK3S_UPMC6      (0x308)
 #define SPR_PERF9             (0x309)
 #define SPR_RCPU_L2U_RBA1     (0x309)
 #define SPR_MPC_MD_CASID      (0x309)
+#define SPR_BOOK3S_UPMC7      (0x309)
 #define SPR_PERFA             (0x30A)
 #define SPR_RCPU_L2U_RBA2     (0x30A)
 #define SPR_MPC_MD_AP         (0x30A)
+#define SPR_BOOK3S_UPMC8      (0x30A)
 #define SPR_PERFB             (0x30B)
 #define SPR_RCPU_L2U_RBA3     (0x30B)
 #define SPR_MPC_MD_EPN        (0x30B)
+#define SPR_BOOK3S_UMMCR0     (0x30B)
 #define SPR_PERFC             (0x30C)
 #define SPR_MPC_MD_TWB        (0x30C)
+#define SPR_BOOK3S_USIAR      (0x30C)
 #define SPR_PERFD             (0x30D)
 #define SPR_MPC_MD_TWC        (0x30D)
+#define SPR_BOOK3S_USDAR      (0x30D)
 #define SPR_PERFE             (0x30E)
 #define SPR_MPC_MD_RPN        (0x30E)
+#define SPR_BOOK3S_UMMCR1     (0x30E)
 #define SPR_PERFF             (0x30F)
 #define SPR_MPC_MD_TW         (0x30F)
 #define SPR_UPERF0            (0x310)
 #define SPR_UPERF1            (0x311)
+#define SPR_BOOK3S_MMCR2      (0x311)
 #define SPR_UPERF2            (0x312)
+#define SPR_BOOK3S_MMCRA      (0x312)
 #define SPR_UPERF3            (0x313)
+#define SPR_BOOK3S_PMC1       (0x313)
 #define SPR_UPERF4            (0x314)
+#define SPR_BOOK3S_PMC2       (0x314)
 #define SPR_UPERF5            (0x315)
+#define SPR_BOOK3S_PMC3       (0x315)
 #define SPR_UPERF6            (0x316)
+#define SPR_BOOK3S_PMC4       (0x316)
 #define SPR_UPERF7            (0x317)
+#define SPR_BOOK3S_PMC5       (0x317)
 #define SPR_UPERF8            (0x318)
+#define SPR_BOOK3S_PMC6       (0x318)
 #define SPR_UPERF9            (0x319)
+#define SPR_BOOK3S_PMC7       (0x319)
 #define SPR_UPERFA            (0x31A)
+#define SPR_BOOK3S_PMC8       (0x31A)
 #define SPR_UPERFB            (0x31B)
+#define SPR_BOOK3S_MMCR0      (0x31B)
 #define SPR_UPERFC            (0x31C)
+#define SPR_BOOK3S_SIAR       (0x31C)
 #define SPR_UPERFD            (0x31D)
+#define SPR_BOOK3S_SDAR       (0x31D)
 #define SPR_UPERFE            (0x31E)
+#define SPR_BOOK3S_MMCR1      (0x31E)
 #define SPR_UPERFF            (0x31F)
 #define SPR_RCPU_MI_RA0       (0x320)
 #define SPR_MPC_MI_DBCAM      (0x320)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d07e186..273e37d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6629,10 +6629,128 @@ static int check_pow_970 (CPUPPCState *env)
     return 0;
 }
 
+/* SPR common to all book3s implementations */
+static void gen_spr_book3s (CPUPPCState *env)
+{
+    /* Breakpoints */
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_DABR, "DABR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_DABR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IABR, "IABR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+
+    /* Performance monitors */
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_MMCR0, "MMCR0",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCR0, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_MMCR1, "MMCR1",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCR1, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC1, "PMC1",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC1, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC2, "PMC2",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC2, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC3, "PMC3",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC3, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC4, "PMC4",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC4, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC5, "PMC5",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC5, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC6, "PMC6",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC6, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     KVM_REG_PPC_SIAR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     KVM_REG_PPC_SDAR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UMMCR0, "UMMCR0",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UMMCR1, "UMMCR1",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC1, "UPMC1",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC2, "UPMC2",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC3, "UPMC3",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC4, "UPMC4",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC5, "UPMC5",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC6, "UPMC6",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_USIAR, "USIAR",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_USDAR, "USDAR",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+}
+
 static void init_proc_970 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6712,7 +6830,7 @@ static int check_pow_970FX (CPUPPCState *env)
 static void init_proc_970FX (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6804,7 +6922,7 @@ static int check_pow_970MP (CPUPPCState *env)
 static void init_proc_970MP (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6882,7 +7000,7 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
 static void init_proc_power5plus(CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6972,7 +7090,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
 static void init_proc_POWER7 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Processor identification */
@@ -6998,18 +7116,11 @@ static void init_proc_POWER7 (CPUPPCState *env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_DSCR, 0x00000000);
-    spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+    spr_register_kvm(env, SPR_BOOK3S_MMCRA, "SPR_MMCRA",
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_MMCRA, 0x00000000);
-    spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
-                     SPR_NOACCESS, SPR_NOACCESS,
-                     &spr_read_generic, &spr_write_generic,
-                     KVM_REG_PPC_PMC5, 0x00000000);
-    spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
-                     SPR_NOACCESS, SPR_NOACCESS,
-                     &spr_read_generic, &spr_write_generic,
-                     KVM_REG_PPC_PMC6, 0x00000000);
+
 #endif /* !CONFIG_USER_ONLY */
     gen_spr_amr(env);
     /* XXX : not implemented */
-- 
1.8.3.2

Re: [Qemu-devel] [Qemu-ppc] [PATCH 5/6] target-ppc: Fix Book3S PMU SPRs

[Alexander Graf]

On 25.03.14 03:40, Anton Blanchard wrote:
> Most of the PMU SPRs were wrong on Book3S.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>   target-ppc/cpu.h            |  29 ++++++++-
>   target-ppc/translate_init.c | 139 +++++++++++++++++++++++++++++++++++++++-----
>   2 files changed, 153 insertions(+), 15 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 2719c08..7082041 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1452,54 +1452,81 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>   #define SPR_MPC_MI_CTR        (0x300)
>   #define SPR_PERF1             (0x301)
>   #define SPR_RCPU_MI_RBA1      (0x301)
> +#define SPR_BOOK3S_UMMCR2     (0x301)
>   #define SPR_PERF2             (0x302)
>   #define SPR_RCPU_MI_RBA2      (0x302)
>   #define SPR_MPC_MI_AP         (0x302)
> -#define SPR_MMCRA             (0x302)
> +#define SPR_BOOK3S_UMMCRA     (0x302)
>   #define SPR_PERF3             (0x303)
>   #define SPR_RCPU_MI_RBA3      (0x303)
>   #define SPR_MPC_MI_EPN        (0x303)
> +#define SPR_BOOK3S_UPMC1      (0x303)
>   #define SPR_PERF4             (0x304)
> +#define SPR_BOOK3S_UPMC2      (0x304)
>   #define SPR_PERF5             (0x305)
>   #define SPR_MPC_MI_TWC        (0x305)
> +#define SPR_BOOK3S_UPMC3      (0x305)
>   #define SPR_PERF6             (0x306)
>   #define SPR_MPC_MI_RPN        (0x306)
> +#define SPR_BOOK3S_UPMC4      (0x306)
>   #define SPR_PERF7             (0x307)
> +#define SPR_BOOK3S_UPMC5      (0x307)
>   #define SPR_PERF8             (0x308)
>   #define SPR_RCPU_L2U_RBA0     (0x308)
>   #define SPR_MPC_MD_CTR        (0x308)
> +#define SPR_BOOK3S_UPMC6      (0x308)
>   #define SPR_PERF9             (0x309)
>   #define SPR_RCPU_L2U_RBA1     (0x309)
>   #define SPR_MPC_MD_CASID      (0x309)
> +#define SPR_BOOK3S_UPMC7      (0x309)
>   #define SPR_PERFA             (0x30A)
>   #define SPR_RCPU_L2U_RBA2     (0x30A)
>   #define SPR_MPC_MD_AP         (0x30A)
> +#define SPR_BOOK3S_UPMC8      (0x30A)
>   #define SPR_PERFB             (0x30B)
>   #define SPR_RCPU_L2U_RBA3     (0x30B)
>   #define SPR_MPC_MD_EPN        (0x30B)
> +#define SPR_BOOK3S_UMMCR0     (0x30B)
>   #define SPR_PERFC             (0x30C)
>   #define SPR_MPC_MD_TWB        (0x30C)
> +#define SPR_BOOK3S_USIAR      (0x30C)
>   #define SPR_PERFD             (0x30D)
>   #define SPR_MPC_MD_TWC        (0x30D)
> +#define SPR_BOOK3S_USDAR      (0x30D)
>   #define SPR_PERFE             (0x30E)
>   #define SPR_MPC_MD_RPN        (0x30E)
> +#define SPR_BOOK3S_UMMCR1     (0x30E)
>   #define SPR_PERFF             (0x30F)
>   #define SPR_MPC_MD_TW         (0x30F)
>   #define SPR_UPERF0            (0x310)
>   #define SPR_UPERF1            (0x311)
> +#define SPR_BOOK3S_MMCR2      (0x311)
>   #define SPR_UPERF2            (0x312)
> +#define SPR_BOOK3S_MMCRA      (0x312)
>   #define SPR_UPERF3            (0x313)
> +#define SPR_BOOK3S_PMC1       (0x313)
>   #define SPR_UPERF4            (0x314)
> +#define SPR_BOOK3S_PMC2       (0x314)
>   #define SPR_UPERF5            (0x315)
> +#define SPR_BOOK3S_PMC3       (0x315)
>   #define SPR_UPERF6            (0x316)
> +#define SPR_BOOK3S_PMC4       (0x316)
>   #define SPR_UPERF7            (0x317)
> +#define SPR_BOOK3S_PMC5       (0x317)
>   #define SPR_UPERF8            (0x318)
> +#define SPR_BOOK3S_PMC6       (0x318)
>   #define SPR_UPERF9            (0x319)
> +#define SPR_BOOK3S_PMC7       (0x319)
>   #define SPR_UPERFA            (0x31A)
> +#define SPR_BOOK3S_PMC8       (0x31A)
>   #define SPR_UPERFB            (0x31B)
> +#define SPR_BOOK3S_MMCR0      (0x31B)
>   #define SPR_UPERFC            (0x31C)
> +#define SPR_BOOK3S_SIAR       (0x31C)
>   #define SPR_UPERFD            (0x31D)
> +#define SPR_BOOK3S_SDAR       (0x31D)
>   #define SPR_UPERFE            (0x31E)
> +#define SPR_BOOK3S_MMCR1      (0x31E)
>   #define SPR_UPERFF            (0x31F)
>   #define SPR_RCPU_MI_RA0       (0x320)
>   #define SPR_MPC_MI_DBCAM      (0x320)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index d07e186..273e37d 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -6629,10 +6629,128 @@ static int check_pow_970 (CPUPPCState *env)
>       return 0;
>   }
>   
> +/* SPR common to all book3s implementations */
> +static void gen_spr_book3s (CPUPPCState *env)

Book3s or Book3s_64? We usually refer to 750+ as book3s as well - and 
depending on who you ask some 60x ones too :).

So I'd prefer if we name (and give the comment) slightly more specific. 
Something like "SPRs common to all ISA 2.x book3s implementations" for 
example. Then it's clear what we're talking about.

Otherwise seems to make a lot of sense.


Alex

[Qemu-devel] [PATCH 6/6] target-ppc: Add PMC7/8 to 970

[Anton Blanchard]

970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
it 3 times, and simplify the existing code.

Signed-off-by: Anton Blanchard <anton@samba.org>
---
 target-ppc/translate_init.c | 89 ++++++++++++++++++++-------------------------
 1 file changed, 39 insertions(+), 50 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 273e37d..50b2603 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6747,12 +6747,13 @@ static void gen_spr_book3s (CPUPPCState *env)
                  0x00000000);
 }
 
-static void init_proc_970 (CPUPPCState *env)
+static void gen_spr_970 (CPUPPCState *env)
 {
-    gen_spr_ne_601(env);
-    gen_spr_book3s(env);
-    /* Time base */
-    gen_tbl(env);
+    spr_register(env, SPR_HIOR, "SPR_HIOR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_hior, &spr_write_hior,
+                 0x00000000);
+
     /* Hardware implementation registers */
     /* XXX : not implemented */
     spr_register(env, SPR_HID0, "HID0",
@@ -6769,13 +6770,40 @@ static void init_proc_970 (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_generic,
                  POWERPC970_HID5_INIT);
+
+    /* Performance monitors */
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC7, "PMC7",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC7, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC8, "PMC8",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC8, 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC7, "UPMC7",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC8, "UPMC8",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+}
+
+static void init_proc_970 (CPUPPCState *env)
+{
+    gen_spr_ne_601(env);
+    gen_spr_book3s(env);
+    gen_spr_970(env);
+    /* Time base */
+    gen_tbl(env);
     /* Memory management */
     /* XXX: not correct */
     gen_low_BATs(env);
-    spr_register(env, SPR_HIOR, "SPR_HIOR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_hior, &spr_write_hior,
-                 0x00000000);
 #if !defined(CONFIG_USER_ONLY)
     env->slb_nr = 32;
 #endif
@@ -6831,31 +6859,12 @@ static void init_proc_970FX (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
     gen_spr_book3s(env);
+    gen_spr_970(env);
     /* Time base */
     gen_tbl(env);
-    /* Hardware implementation registers */
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID0, "HID0",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_clear,
-                 0x60000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID1, "HID1",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_970_HID5, "HID5",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 POWERPC970_HID5_INIT);
     /* Memory management */
     /* XXX: not correct */
     gen_low_BATs(env);
-    spr_register(env, SPR_HIOR, "SPR_HIOR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_hior, &spr_write_hior,
-                 0x00000000);
     spr_register(env, SPR_CTRL, "SPR_CTRL",
                  SPR_NOACCESS, SPR_NOACCESS,
                  SPR_NOACCESS, &spr_write_generic,
@@ -6923,32 +6932,12 @@ static void init_proc_970MP (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
     gen_spr_book3s(env);
+    gen_spr_970(env);
     /* Time base */
     gen_tbl(env);
-    /* Hardware implementation registers */
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID0, "HID0",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_clear,
-                 0x60000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID1, "HID1",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_970_HID5, "HID5",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 POWERPC970_HID5_INIT);
-    /* XXX : not implemented */
     /* Memory management */
     /* XXX: not correct */
     gen_low_BATs(env);
-    spr_register(env, SPR_HIOR, "SPR_HIOR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_hior, &spr_write_hior,
-                 0x00000000);
     /* Logical partitionning */
     spr_register_kvm(env, SPR_LPCR, "LPCR",
                      SPR_NOACCESS, SPR_NOACCESS,
-- 
1.8.3.2

Re: [Qemu-devel] [Qemu-ppc] [PATCH 6/6] target-ppc: Add PMC7/8 to 970

[Alexey Kardashevskiy]

On 03/25/2014 01:40 PM, Anton Blanchard wrote:
> 970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
> it 3 times, and simplify the existing code.
> 
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>  target-ppc/translate_init.c | 89 ++++++++++++++++++++-------------------------
>  1 file changed, 39 insertions(+), 50 deletions(-)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 273e37d..50b2603 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -6747,12 +6747,13 @@ static void gen_spr_book3s (CPUPPCState *env)
>                   0x00000000);
>  }
>  
> -static void init_proc_970 (CPUPPCState *env)
> +static void gen_spr_970 (CPUPPCState *env)
>  {
> -    gen_spr_ne_601(env);
> -    gen_spr_book3s(env);
> -    /* Time base */
> -    gen_tbl(env);
> +    spr_register(env, SPR_HIOR, "SPR_HIOR",


+    spr_register(env, SPR_HIOR, "HIOR",

Can we please not add SPR_ in string name? Thanks.



> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_hior, &spr_write_hior,
> +                 0x00000000);
> +
>      /* Hardware implementation registers */
>      /* XXX : not implemented */
>      spr_register(env, SPR_HID0, "HID0",
> @@ -6769,13 +6770,40 @@ static void init_proc_970 (CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_generic,
>                   POWERPC970_HID5_INIT);
> +
> +    /* Performance monitors */
> +    /* XXX : not implemented */
> +    spr_register_kvm(env, SPR_BOOK3S_PMC7, "PMC7",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_PMC7, 0x00000000);
> +    /* XXX : not implemented */
> +    spr_register_kvm(env, SPR_BOOK3S_PMC8, "PMC8",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_PMC8, 0x00000000);
> +    /* XXX : not implemented */
> +    spr_register(env, SPR_BOOK3S_UPMC7, "UPMC7",
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 0x00000000);
> +    /* XXX : not implemented */
> +    spr_register(env, SPR_BOOK3S_UPMC8, "UPMC8",
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 0x00000000);
> +}
> +
> +static void init_proc_970 (CPUPPCState *env)
> +{
> +    gen_spr_ne_601(env);
> +    gen_spr_book3s(env);
> +    gen_spr_970(env);
> +    /* Time base */
> +    gen_tbl(env);
>      /* Memory management */
>      /* XXX: not correct */
>      gen_low_BATs(env);
> -    spr_register(env, SPR_HIOR, "SPR_HIOR",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_hior, &spr_write_hior,
> -                 0x00000000);
>  #if !defined(CONFIG_USER_ONLY)
>      env->slb_nr = 32;
>  #endif
> @@ -6831,31 +6859,12 @@ static void init_proc_970FX (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
>      gen_spr_book3s(env);
> +    gen_spr_970(env);
>      /* Time base */
>      gen_tbl(env);
> -    /* Hardware implementation registers */
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID0, "HID0",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_clear,
> -                 0x60000000);
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID1, "HID1",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_970_HID5, "HID5",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 POWERPC970_HID5_INIT);
>      /* Memory management */
>      /* XXX: not correct */
>      gen_low_BATs(env);
> -    spr_register(env, SPR_HIOR, "SPR_HIOR",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_hior, &spr_write_hior,
> -                 0x00000000);
>      spr_register(env, SPR_CTRL, "SPR_CTRL",
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   SPR_NOACCESS, &spr_write_generic,
> @@ -6923,32 +6932,12 @@ static void init_proc_970MP (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
>      gen_spr_book3s(env);
> +    gen_spr_970(env);
>      /* Time base */
>      gen_tbl(env);
> -    /* Hardware implementation registers */
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID0, "HID0",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_clear,
> -                 0x60000000);
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID1, "HID1",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_970_HID5, "HID5",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 POWERPC970_HID5_INIT);
> -    /* XXX : not implemented */
>      /* Memory management */
>      /* XXX: not correct */
>      gen_low_BATs(env);
> -    spr_register(env, SPR_HIOR, "SPR_HIOR",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_hior, &spr_write_hior,
> -                 0x00000000);
>      /* Logical partitionning */
>      spr_register_kvm(env, SPR_LPCR, "LPCR",
>                       SPR_NOACCESS, SPR_NOACCESS,
> 


-- 
Alexey

Re: [Qemu-devel] [Qemu-ppc] [PATCH 6/6] target-ppc: Add PMC7/8 to 970

[Andreas Färber]

Am 27.03.2014 14:03, schrieb Alexey Kardashevskiy:
> On 03/25/2014 01:40 PM, Anton Blanchard wrote:
>> 970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
>> it 3 times, and simplify the existing code.
>>
>> Signed-off-by: Anton Blanchard <anton@samba.org>
>> ---
>>  target-ppc/translate_init.c | 89 ++++++++++++++++++++-------------------------
>>  1 file changed, 39 insertions(+), 50 deletions(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 273e37d..50b2603 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -6747,12 +6747,13 @@ static void gen_spr_book3s (CPUPPCState *env)
>>                   0x00000000);
>>  }
>>  
>> -static void init_proc_970 (CPUPPCState *env)
>> +static void gen_spr_970 (CPUPPCState *env)
>>  {
>> -    gen_spr_ne_601(env);
>> -    gen_spr_book3s(env);
>> -    /* Time base */
>> -    gen_tbl(env);
>> +    spr_register(env, SPR_HIOR, "SPR_HIOR",
> 
> 
> +    spr_register(env, SPR_HIOR, "HIOR",
> 
> Can we please not add SPR_ in string name? Thanks.

As far I see, this is only being moved around, not added here.

If this is not user ABI, feel free to first drop it, then move it.
Similarly, adding the new ones in a third step would make review and
bisection easier.

Regards,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [Qemu-ppc] [PATCH 6/6] target-ppc: Add PMC7/8 to 970

[Alexander Graf]

On 25.03.14 03:40, Anton Blanchard wrote:
> 970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
> it 3 times, and simplify the existing code.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>

Don't you think we could just combine 970, 970FX and 970MP into the same 
class?


Alex

Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Alex Bennée]

Anton Blanchard <anton@samba.org> writes:

> Add MSR_LE to the msr_mask for POWER8.
>
<snip>
> -    pcc->msr_mask = 0x800000000284FF36ULL;
> +    pcc->msr_mask = 0x800000000284FF37ULL;
<snip>

Should we be adding some #define's for the various bit positions on this
mask? Looking at the current code it looks like a big ream of magic
numbers.

Cheers,

-- 
Alex Bennée

Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Andreas Färber]

Am 25.03.2014 08:29, schrieb Alex Bennée:
> 
> Anton Blanchard <anton@samba.org> writes:
> 
>> Add MSR_LE to the msr_mask for POWER8.
>>
> <snip>
>> -    pcc->msr_mask = 0x800000000284FF36ULL;
>> +    pcc->msr_mask = 0x800000000284FF37ULL;
> <snip>
> 
> Should we be adding some #define's for the various bit positions on this
> mask? Looking at the current code it looks like a big ream of magic
> numbers.

In general I concur that defines would be nice, however for 2.0 that's
too risky for me as temporary maintainer and I'm not sure if these
values are being pieced together by contributors or whether this is
coming directly from the manual?

The other issue has been that adding a new family, even after the
initial round of cleanups, still requires a chunk of code to be copied,
which seems prone to forgetting little bits on the new one, then maybe
fixing up the original template but not the derived models, etc.

Cheers,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Tom Musta]

On 3/27/2014 9:58 AM, Andreas Färber wrote:
> Am 25.03.2014 08:29, schrieb Alex Bennée:
>>
>> Anton Blanchard <anton@samba.org> writes:
>>
>>> Add MSR_LE to the msr_mask for POWER8.
>>>
>> <snip>
>>> -    pcc->msr_mask = 0x800000000284FF36ULL;
>>> +    pcc->msr_mask = 0x800000000284FF37ULL;
>> <snip>
>>
>> Should we be adding some #define's for the various bit positions on this
>> mask? Looking at the current code it looks like a big ream of magic
>> numbers.
> 
> In general I concur that defines would be nice, however for 2.0 that's
> too risky for me as temporary maintainer and I'm not sure if these
> values are being pieced together by contributors or whether this is
> coming directly from the manual?

There are defines in target-ppc/cpu.h that identify the bit position.  So
something like this could/should be done (in 2.1):

    pcc->msr_mask =
        (1ULL << MSR_SF) |
        (1ULL << MSR_TAG) |
        (1ULL << MSR_ISF) |
        (1ULL << MSR_DR /* MISSING */ ) |
        (1ULL << MSR_IR /* MISSING */ ) |
        (1ULL << MSR_FE1 /* MISSING */ ) |
        (1ULL << MSR_BE /* MISSING */ ) |
        (1ULL << MSR_ME /* MISSING */ ) |
        (1ULL << MSR_SE /* MISSING */ ) |
        (1ULL << MSR_FE0 /* MISSING */ ) |
        (1ULL << MSR_FP /* MISSING */ ) |
        (1ULL << MSR_PR /* MISSING */ ) |
        (1ULL << MSR_EE /* MISSING */ );

The set of defines is incomplete -- the items marked MISSING are not currently there.
They could, of course, easily be added.

Unfortunately, this behavior has been repeated over 50 times in the target-ppc/translate_init.c
file and some MSR bit positions have multiple meanings based on processor family and era.  So
a thorough and accurate cleanup would provide a nice challenge :)

I'm willing to tackle this after I get done with some decimal floating point work (probably 2
weeks).

> The other issue has been that adding a new family, even after the
> initial round of cleanups, still requires a chunk of code to be copied,
> which seems prone to forgetting little bits on the new one, then maybe
> fixing up the original template but not the derived models, etc.

Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit

[Andreas Färber]

Hi Anton,

Am 25.03.2014 03:40, schrieb Anton Blanchard:
> Add MSR_LE to the msr_mask for POWER8.
> 
> Signed-off-by: Anton Blanchard <anton@samba.org>
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>

Something went wrong here - you're sending patches without placing your
Sob last, which breaks the DCO chain. Cédric indicated to me on IRC to
use Reviewed-by and/or Tested-by for him, fixed.

Please remember to include a cover letter next time.

I've picked up patches 1-4 for 2.0, tweaking two of the commit messages:
https://github.com/afaerber/qemu-cpu/commits/ppc-next

The SPR patches were too big for me to review right now, and it was not
clear to me from commit messages what those patches were fixing (test case).

Thanks,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg