* [PATCH v2 1/4] reset: add driver for socfpga
@ 2014-04-10 8:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Philipp Zabel, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Randy Dunlap, Dinh Nguyen,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Steffen Trumtrar
Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v1:
- use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
- print pdev->dev.of_node->full_name on error
- use proper IS_ERR/PTR_ERR
drivers/reset/Makefile | 1 +
drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 148 insertions(+)
create mode 100644 drivers/reset/reset-socfpga.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cc29832..ab64077 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index 0000000..bdcd2fa
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2014 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define NR_BANKS 4
+#define OFFSET_MODRST 0x10
+
+struct socfpga_reset_data {
+ spinlock_t lock;
+ void __iomem *membase;
+ struct reset_controller_dev rcdev;
+};
+
+static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct socfpga_reset_data *data = container_of(rcdev,
+ struct socfpga_reset_data,
+ rcdev);
+ int bank = id / BITS_PER_LONG;
+ int offset = id % BITS_PER_LONG;
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+ writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
+ (bank * NR_BANKS));
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct socfpga_reset_data *data = container_of(rcdev,
+ struct socfpga_reset_data,
+ rcdev);
+
+ int bank = id / BITS_PER_LONG;
+ int offset = id % BITS_PER_LONG;
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+ writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
+ (bank * NR_BANKS));
+
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops socfpga_reset_ops = {
+ .assert = socfpga_reset_assert,
+ .deassert = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct platform_device *pdev)
+{
+ struct socfpga_reset_data *data;
+ struct resource *res;
+ int ret;
+
+ /*
+ * The binding was mainlined without the required property.
+ * Do not continue, when we encounter an old DT.
+ */
+ if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
+ dev_err(&pdev->dev, "%s missing #reset-cells property\n",
+ pdev->dev.of_node->full_name);
+ return -EINVAL;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->membase = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->membase))
+ return PTR_ERR(data->membase);
+
+ spin_lock_init(&data->lock);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
+ data->rcdev.ops = &socfpga_reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+ reset_controller_register(&data->rcdev);
+
+ return 0;
+}
+
+static int socfpga_reset_remove(struct platform_device *pdev)
+{
+ struct socfpga_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(&data->rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id socfpga_reset_dt_ids[] = {
+ { .compatible = "altr,rst-mgr", },
+ { /* sentinel */ },
+};
+
+static struct platform_driver socfpga_reset_driver = {
+ .probe = socfpga_reset_probe,
+ .remove = socfpga_reset_remove,
+ .driver = {
+ .name = "socfpga-reset",
+ .owner = THIS_MODULE,
+ .of_match_table = socfpga_reset_dt_ids,
+ },
+};
+module_platform_driver(socfpga_reset_driver);
+
+MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org");
+MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 1/4] reset: add driver for socfpga
@ 2014-04-10 8:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Changes since v1:
- use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
- print pdev->dev.of_node->full_name on error
- use proper IS_ERR/PTR_ERR
drivers/reset/Makefile | 1 +
drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 148 insertions(+)
create mode 100644 drivers/reset/reset-socfpga.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cc29832..ab64077 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index 0000000..bdcd2fa
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define NR_BANKS 4
+#define OFFSET_MODRST 0x10
+
+struct socfpga_reset_data {
+ spinlock_t lock;
+ void __iomem *membase;
+ struct reset_controller_dev rcdev;
+};
+
+static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct socfpga_reset_data *data = container_of(rcdev,
+ struct socfpga_reset_data,
+ rcdev);
+ int bank = id / BITS_PER_LONG;
+ int offset = id % BITS_PER_LONG;
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+ writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
+ (bank * NR_BANKS));
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct socfpga_reset_data *data = container_of(rcdev,
+ struct socfpga_reset_data,
+ rcdev);
+
+ int bank = id / BITS_PER_LONG;
+ int offset = id % BITS_PER_LONG;
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+ writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
+ (bank * NR_BANKS));
+
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops socfpga_reset_ops = {
+ .assert = socfpga_reset_assert,
+ .deassert = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct platform_device *pdev)
+{
+ struct socfpga_reset_data *data;
+ struct resource *res;
+ int ret;
+
+ /*
+ * The binding was mainlined without the required property.
+ * Do not continue, when we encounter an old DT.
+ */
+ if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
+ dev_err(&pdev->dev, "%s missing #reset-cells property\n",
+ pdev->dev.of_node->full_name);
+ return -EINVAL;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->membase = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->membase))
+ return PTR_ERR(data->membase);
+
+ spin_lock_init(&data->lock);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
+ data->rcdev.ops = &socfpga_reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+ reset_controller_register(&data->rcdev);
+
+ return 0;
+}
+
+static int socfpga_reset_remove(struct platform_device *pdev)
+{
+ struct socfpga_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(&data->rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id socfpga_reset_dt_ids[] = {
+ { .compatible = "altr,rst-mgr", },
+ { /* sentinel */ },
+};
+
+static struct platform_driver socfpga_reset_driver = {
+ .probe = socfpga_reset_probe,
+ .remove = socfpga_reset_remove,
+ .driver = {
+ .name = "socfpga-reset",
+ .owner = THIS_MODULE,
+ .of_match_table = socfpga_reset_dt_ids,
+ },
+};
+module_platform_driver(socfpga_reset_driver);
+
+MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
+MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/4] Documentation: dt: socfpga: add reset-cells property
2014-04-10 8:21 ` Steffen Trumtrar
@ 2014-04-10 8:21 ` Steffen Trumtrar
-1 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Philipp Zabel, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Randy Dunlap, Dinh Nguyen,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Steffen Trumtrar
To be able to use the reset-controller framework, the property
#reset-cells
is mandatory.
Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
index ecdb57d..32c1c8b 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
@@ -3,9 +3,11 @@ Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)
+- #reset-cells: 1
Example:
rstmgr@ffd05000 {
+ #reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/4] Documentation: dt: socfpga: add reset-cells property
@ 2014-04-10 8:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel
To be able to use the reset-controller framework, the property
#reset-cells
is mandatory.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
index ecdb57d..32c1c8b 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
@@ -3,9 +3,11 @@ Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)
+- #reset-cells: 1
Example:
rstmgr at ffd05000 {
+ #reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/4] Documentation: dt: reset: move socfpga-reset
2014-04-10 8:21 ` Steffen Trumtrar
@ 2014-04-10 8:21 ` Steffen Trumtrar
-1 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Philipp Zabel, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Randy Dunlap, Dinh Nguyen,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Steffen Trumtrar
Instead of having the documentation for the socfpga-reset controller in a
vendor specific directory, move it to the reset folder to all the other
reset drivers.
Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Documentation/devicetree/bindings/{arm/altera => reset}/socfpga-reset.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{arm/altera => reset}/socfpga-reset.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
rename to Documentation/devicetree/bindings/reset/socfpga-reset.txt
--
1.9.1
--
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/4] Documentation: dt: reset: move socfpga-reset
@ 2014-04-10 8:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Instead of having the documentation for the socfpga-reset controller in a
vendor specific directory, move it to the reset folder to all the other
reset drivers.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Documentation/devicetree/bindings/{arm/altera => reset}/socfpga-reset.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{arm/altera => reset}/socfpga-reset.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
rename to Documentation/devicetree/bindings/reset/socfpga-reset.txt
--
1.9.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/4] ARM: socfpga: dts: add reset-controller
2014-04-10 8:21 ` Steffen Trumtrar
@ 2014-04-10 8:21 ` Steffen Trumtrar
-1 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Philipp Zabel, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Randy Dunlap, Dinh Nguyen,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Steffen Trumtrar
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/socfpga.dtsi | 8 ++-
include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 1f71e96..027d2c6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -16,6 +16,7 @@
*/
#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
/ {
#address-cells = <1>;
@@ -456,6 +457,8 @@
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac0_clk>;
clock-names = "stmmaceth";
+ resets = <&rst EMAC0_RESET>;
+ reset-names = "stmmaceth";
status = "disabled";
};
@@ -467,6 +470,8 @@
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac1_clk>;
clock-names = "stmmaceth";
+ resets = <&rst EMAC1_RESET>;
+ reset-names = "stmmaceth";
status = "disabled";
};
@@ -584,7 +589,8 @@
reg-io-width = <4>;
};
- rstmgr@ffd05000 {
+ rst: rstmgr@ffd05000 {
+ #reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
new file mode 100644
index 0000000..3f04908
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET 2
+#define SCUPER_RESET 3
+#define L2_RESET 4
+
+/* PERMODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define USB0_RESET 34
+#define USB1_RESET 35
+#define NAND_RESET 36
+#define QSPI_RESET 37
+#define L4WD0_RESET 38
+#define L4WD1_RESET 39
+#define OSC1TIMER0_RESET 40
+#define OSC1TIMER1_RESET 41
+#define SPTIMER0_RESET 42
+#define SPTIMER1_RESET 43
+#define I2C0_RESET 44
+#define I2C1_RESET 45
+#define I2C2_RESET 46
+#define I2C3_RESET 47
+#define UART0_RESET 48
+#define UART1_RESET 49
+#define SPIM0_RESET 50
+#define SPIM1_RESET 51
+#define SPIS0_RESET 52
+#define SPIS1_RESET 53
+#define SDMMC_RESET 54
+#define CAN0_RESET 55
+#define CAN1_RESET 56
+#define GPIO0_RESET 57
+#define GPIO1_RESET 58
+#define GPIO2_RESET 59
+#define DMA_RESET 60
+#define SDR_RESET 61
+
+/* PER2MODRST */
+#define DMAIF0_RESET 64
+#define DMAIF1_RESET 65
+#define DMAIF2_RESET 66
+#define DMAIF3_RESET 67
+#define DMAIF4_RESET 68
+#define DMAIF5_RESET 69
+#define DMAIF6_RESET 70
+#define DMAIF7_RESET 71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+
+/* MISCMODRST*/
+#define ROM_RESET 128
+#define OCRAM_RESET 129
+#define SYSMGR_RESET 130
+#define SYSMGRCOLD_RESET 131
+#define FPGAMGR_RESET 132
+#define ACPIDMAP_RESET 133
+#define S2F_RESET 134
+#define S2FCOLD_RESET 135
+#define NRSTPIN_RESET 136
+#define TIMESTAMPCOLD_RESET 137
+#define CLKMGRCOLD_RESET 138
+#define SCANMGR_RESET 139
+#define FRZCTRLCOLD_RESET 140
+#define SYSDBG_RESET 141
+#define DBG_RESET 142
+#define TAPCOLD_RESET 143
+#define SDRCOLD_RESET 144
+
+#endif
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/4] ARM: socfpga: dts: add reset-controller
@ 2014-04-10 8:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2014-04-10 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boot/dts/socfpga.dtsi | 8 ++-
include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 1f71e96..027d2c6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -16,6 +16,7 @@
*/
#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
/ {
#address-cells = <1>;
@@ -456,6 +457,8 @@
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac0_clk>;
clock-names = "stmmaceth";
+ resets = <&rst EMAC0_RESET>;
+ reset-names = "stmmaceth";
status = "disabled";
};
@@ -467,6 +470,8 @@
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac1_clk>;
clock-names = "stmmaceth";
+ resets = <&rst EMAC1_RESET>;
+ reset-names = "stmmaceth";
status = "disabled";
};
@@ -584,7 +589,8 @@
reg-io-width = <4>;
};
- rstmgr at ffd05000 {
+ rst: rstmgr at ffd05000 {
+ #reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
new file mode 100644
index 0000000..3f04908
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET 2
+#define SCUPER_RESET 3
+#define L2_RESET 4
+
+/* PERMODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define USB0_RESET 34
+#define USB1_RESET 35
+#define NAND_RESET 36
+#define QSPI_RESET 37
+#define L4WD0_RESET 38
+#define L4WD1_RESET 39
+#define OSC1TIMER0_RESET 40
+#define OSC1TIMER1_RESET 41
+#define SPTIMER0_RESET 42
+#define SPTIMER1_RESET 43
+#define I2C0_RESET 44
+#define I2C1_RESET 45
+#define I2C2_RESET 46
+#define I2C3_RESET 47
+#define UART0_RESET 48
+#define UART1_RESET 49
+#define SPIM0_RESET 50
+#define SPIM1_RESET 51
+#define SPIS0_RESET 52
+#define SPIS1_RESET 53
+#define SDMMC_RESET 54
+#define CAN0_RESET 55
+#define CAN1_RESET 56
+#define GPIO0_RESET 57
+#define GPIO1_RESET 58
+#define GPIO2_RESET 59
+#define DMA_RESET 60
+#define SDR_RESET 61
+
+/* PER2MODRST */
+#define DMAIF0_RESET 64
+#define DMAIF1_RESET 65
+#define DMAIF2_RESET 66
+#define DMAIF3_RESET 67
+#define DMAIF4_RESET 68
+#define DMAIF5_RESET 69
+#define DMAIF6_RESET 70
+#define DMAIF7_RESET 71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+
+/* MISCMODRST*/
+#define ROM_RESET 128
+#define OCRAM_RESET 129
+#define SYSMGR_RESET 130
+#define SYSMGRCOLD_RESET 131
+#define FPGAMGR_RESET 132
+#define ACPIDMAP_RESET 133
+#define S2F_RESET 134
+#define S2FCOLD_RESET 135
+#define NRSTPIN_RESET 136
+#define TIMESTAMPCOLD_RESET 137
+#define CLKMGRCOLD_RESET 138
+#define SCANMGR_RESET 139
+#define FRZCTRLCOLD_RESET 140
+#define SYSDBG_RESET 141
+#define DBG_RESET 142
+#define TAPCOLD_RESET 143
+#define SDRCOLD_RESET 144
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/4] reset: add driver for socfpga
2014-04-10 8:21 ` Steffen Trumtrar
@ 2014-04-14 22:31 ` Dinh Nguyen
-1 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2014-04-14 22:31 UTC (permalink / raw)
To: Steffen Trumtrar, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Philipp Zabel, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Randy Dunlap, Dinh Nguyen,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ
On 04/10/2014 03:21 AM, Steffen Trumtrar wrote:
> Add a reset-controller driver for the socfpga platform.
> The reset-controller has four banks with up to 32 entries all encapsulated in
> one module block.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> Changes since v1:
> - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> - print pdev->dev.of_node->full_name on error
> - use proper IS_ERR/PTR_ERR
>
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 148 insertions(+)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cc29832..ab64077 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_RESET_CONTROLLER) += core.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 0000000..bdcd2fa
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,147 @@
> +/*
> + * Copyright 2014 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * based on
> + * Allwinner SoCs Reset Controller driver
> + *
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#define NR_BANKS 4
> +#define OFFSET_MODRST 0x10
> +
> +struct socfpga_reset_data {
> + spinlock_t lock;
> + void __iomem *membase;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops socfpga_reset_ops = {
> + .assert = socfpga_reset_assert,
> + .deassert = socfpga_reset_deassert,
> +};
> +
> +static int socfpga_reset_probe(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data;
> + struct resource *res;
> + int ret;
'ret' is not used in this function.
Dinh
> +
> + /*
> + * The binding was mainlined without the required property.
> + * Do not continue, when we encounter an old DT.
> + */
> + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> + pdev->dev.of_node->full_name);
> + return -EINVAL;
> + }
> +
> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->membase))
> + return PTR_ERR(data->membase);
> +
> + spin_lock_init(&data->lock);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> + data->rcdev.ops = &socfpga_reset_ops;
> + data->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_remove(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id socfpga_reset_dt_ids[] = {
> + { .compatible = "altr,rst-mgr", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver socfpga_reset_driver = {
> + .probe = socfpga_reset_probe,
> + .remove = socfpga_reset_remove,
> + .driver = {
> + .name = "socfpga-reset",
> + .owner = THIS_MODULE,
> + .of_match_table = socfpga_reset_dt_ids,
> + },
> +};
> +module_platform_driver(socfpga_reset_driver);
> +
> +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org");
> +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> +MODULE_LICENSE("GPL");
>
--
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/4] reset: add driver for socfpga
@ 2014-04-14 22:31 ` Dinh Nguyen
0 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2014-04-14 22:31 UTC (permalink / raw)
To: linux-arm-kernel
On 04/10/2014 03:21 AM, Steffen Trumtrar wrote:
> Add a reset-controller driver for the socfpga platform.
> The reset-controller has four banks with up to 32 entries all encapsulated in
> one module block.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> Changes since v1:
> - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> - print pdev->dev.of_node->full_name on error
> - use proper IS_ERR/PTR_ERR
>
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 148 insertions(+)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cc29832..ab64077 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_RESET_CONTROLLER) += core.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 0000000..bdcd2fa
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,147 @@
> +/*
> + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
> + *
> + * based on
> + * Allwinner SoCs Reset Controller driver
> + *
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#define NR_BANKS 4
> +#define OFFSET_MODRST 0x10
> +
> +struct socfpga_reset_data {
> + spinlock_t lock;
> + void __iomem *membase;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops socfpga_reset_ops = {
> + .assert = socfpga_reset_assert,
> + .deassert = socfpga_reset_deassert,
> +};
> +
> +static int socfpga_reset_probe(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data;
> + struct resource *res;
> + int ret;
'ret' is not used in this function.
Dinh
> +
> + /*
> + * The binding was mainlined without the required property.
> + * Do not continue, when we encounter an old DT.
> + */
> + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> + pdev->dev.of_node->full_name);
> + return -EINVAL;
> + }
> +
> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->membase))
> + return PTR_ERR(data->membase);
> +
> + spin_lock_init(&data->lock);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> + data->rcdev.ops = &socfpga_reset_ops;
> + data->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_remove(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id socfpga_reset_dt_ids[] = {
> + { .compatible = "altr,rst-mgr", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver socfpga_reset_driver = {
> + .probe = socfpga_reset_probe,
> + .remove = socfpga_reset_remove,
> + .driver = {
> + .name = "socfpga-reset",
> + .owner = THIS_MODULE,
> + .of_match_table = socfpga_reset_dt_ids,
> + },
> +};
> +module_platform_driver(socfpga_reset_driver);
> +
> +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
> +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/4] reset: add driver for socfpga
2014-04-10 8:21 ` Steffen Trumtrar
@ 2014-04-15 7:20 ` Philipp Zabel
-1 siblings, 0 replies; 14+ messages in thread
From: Philipp Zabel @ 2014-04-15 7:20 UTC (permalink / raw)
To: Steffen Trumtrar
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Randy Dunlap,
Dinh Nguyen, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Hi Dinh,
Am Donnerstag, den 10.04.2014, 10:21 +0200 schrieb Steffen Trumtrar:
> Add a reset-controller driver for the socfpga platform.
> The reset-controller has four banks with up to 32 entries all encapsulated in
> one module block.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
in case you want to take this through your branch,
Acked-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
If you want me to take the reset controller driver, please let me know.
regards
Philipp
> ---
> Changes since v1:
> - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> - print pdev->dev.of_node->full_name on error
> - use proper IS_ERR/PTR_ERR
>
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 148 insertions(+)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cc29832..ab64077 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_RESET_CONTROLLER) += core.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 0000000..bdcd2fa
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,147 @@
> +/*
> + * Copyright 2014 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * based on
> + * Allwinner SoCs Reset Controller driver
> + *
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#define NR_BANKS 4
> +#define OFFSET_MODRST 0x10
> +
> +struct socfpga_reset_data {
> + spinlock_t lock;
> + void __iomem *membase;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops socfpga_reset_ops = {
> + .assert = socfpga_reset_assert,
> + .deassert = socfpga_reset_deassert,
> +};
> +
> +static int socfpga_reset_probe(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data;
> + struct resource *res;
> + int ret;
> +
> + /*
> + * The binding was mainlined without the required property.
> + * Do not continue, when we encounter an old DT.
> + */
> + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> + pdev->dev.of_node->full_name);
> + return -EINVAL;
> + }
> +
> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->membase))
> + return PTR_ERR(data->membase);
> +
> + spin_lock_init(&data->lock);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> + data->rcdev.ops = &socfpga_reset_ops;
> + data->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_remove(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id socfpga_reset_dt_ids[] = {
> + { .compatible = "altr,rst-mgr", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver socfpga_reset_driver = {
> + .probe = socfpga_reset_probe,
> + .remove = socfpga_reset_remove,
> + .driver = {
> + .name = "socfpga-reset",
> + .owner = THIS_MODULE,
> + .of_match_table = socfpga_reset_dt_ids,
> + },
> +};
> +module_platform_driver(socfpga_reset_driver);
> +
> +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org");
> +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> +MODULE_LICENSE("GPL");
--
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/4] reset: add driver for socfpga
@ 2014-04-15 7:20 ` Philipp Zabel
0 siblings, 0 replies; 14+ messages in thread
From: Philipp Zabel @ 2014-04-15 7:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Dinh,
Am Donnerstag, den 10.04.2014, 10:21 +0200 schrieb Steffen Trumtrar:
> Add a reset-controller driver for the socfpga platform.
> The reset-controller has four banks with up to 32 entries all encapsulated in
> one module block.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
in case you want to take this through your branch,
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
If you want me to take the reset controller driver, please let me know.
regards
Philipp
> ---
> Changes since v1:
> - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> - print pdev->dev.of_node->full_name on error
> - use proper IS_ERR/PTR_ERR
>
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 148 insertions(+)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cc29832..ab64077 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_RESET_CONTROLLER) += core.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 0000000..bdcd2fa
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,147 @@
> +/*
> + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
> + *
> + * based on
> + * Allwinner SoCs Reset Controller driver
> + *
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#define NR_BANKS 4
> +#define OFFSET_MODRST 0x10
> +
> +struct socfpga_reset_data {
> + spinlock_t lock;
> + void __iomem *membase;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct socfpga_reset_data *data = container_of(rcdev,
> + struct socfpga_reset_data,
> + rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> + (bank * NR_BANKS));
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops socfpga_reset_ops = {
> + .assert = socfpga_reset_assert,
> + .deassert = socfpga_reset_deassert,
> +};
> +
> +static int socfpga_reset_probe(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data;
> + struct resource *res;
> + int ret;
> +
> + /*
> + * The binding was mainlined without the required property.
> + * Do not continue, when we encounter an old DT.
> + */
> + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> + pdev->dev.of_node->full_name);
> + return -EINVAL;
> + }
> +
> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->membase))
> + return PTR_ERR(data->membase);
> +
> + spin_lock_init(&data->lock);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> + data->rcdev.ops = &socfpga_reset_ops;
> + data->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static int socfpga_reset_remove(struct platform_device *pdev)
> +{
> + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&data->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id socfpga_reset_dt_ids[] = {
> + { .compatible = "altr,rst-mgr", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver socfpga_reset_driver = {
> + .probe = socfpga_reset_probe,
> + .remove = socfpga_reset_remove,
> + .driver = {
> + .name = "socfpga-reset",
> + .owner = THIS_MODULE,
> + .of_match_table = socfpga_reset_dt_ids,
> + },
> +};
> +module_platform_driver(socfpga_reset_driver);
> +
> +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
> +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/4] reset: add driver for socfpga
2014-04-15 7:20 ` Philipp Zabel
@ 2014-04-15 22:22 ` Dinh Nguyen
-1 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2014-04-15 22:22 UTC (permalink / raw)
To: Philipp Zabel
Cc: Steffen Trumtrar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Randy Dunlap,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ
On Tue, 2014-04-15 at 09:20 +0200, Philipp Zabel wrote:
> Hi Dinh,
>
> Am Donnerstag, den 10.04.2014, 10:21 +0200 schrieb Steffen Trumtrar:
> > Add a reset-controller driver for the socfpga platform.
> > The reset-controller has four banks with up to 32 entries all encapsulated in
> > one module block.
> >
> > Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>
> in case you want to take this through your branch,
>
> Acked-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>
> If you want me to take the reset controller driver, please let me know.
>
Yes, I will.
Thanks,
Dinh
> regards
> Philipp
>
> > ---
> > Changes since v1:
> > - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> > - print pdev->dev.of_node->full_name on error
> > - use proper IS_ERR/PTR_ERR
> >
> > drivers/reset/Makefile | 1 +
> > drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 148 insertions(+)
> > create mode 100644 drivers/reset/reset-socfpga.c
> >
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index cc29832..ab64077 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -1,2 +1,3 @@
> > obj-$(CONFIG_RESET_CONTROLLER) += core.o
> > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> > +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> > diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> > new file mode 100644
> > index 0000000..bdcd2fa
> > --- /dev/null
> > +++ b/drivers/reset/reset-socfpga.c
> > @@ -0,0 +1,147 @@
> > +/*
> > + * Copyright 2014 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > + *
> > + * based on
> > + * Allwinner SoCs Reset Controller driver
> > + *
> > + * Copyright 2013 Maxime Ripard
> > + *
> > + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/types.h>
> > +
> > +#define NR_BANKS 4
> > +#define OFFSET_MODRST 0x10
> > +
> > +struct socfpga_reset_data {
> > + spinlock_t lock;
> > + void __iomem *membase;
> > + struct reset_controller_dev rcdev;
> > +};
> > +
> > +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct socfpga_reset_data *data = container_of(rcdev,
> > + struct socfpga_reset_data,
> > + rcdev);
> > + int bank = id / BITS_PER_LONG;
> > + int offset = id % BITS_PER_LONG;
> > + unsigned long flags;
> > + u32 reg;
> > +
> > + spin_lock_irqsave(&data->lock, flags);
> > +
> > + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> > + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> > + (bank * NR_BANKS));
> > + spin_unlock_irqrestore(&data->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct socfpga_reset_data *data = container_of(rcdev,
> > + struct socfpga_reset_data,
> > + rcdev);
> > +
> > + int bank = id / BITS_PER_LONG;
> > + int offset = id % BITS_PER_LONG;
> > + unsigned long flags;
> > + u32 reg;
> > +
> > + spin_lock_irqsave(&data->lock, flags);
> > +
> > + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> > + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> > + (bank * NR_BANKS));
> > +
> > + spin_unlock_irqrestore(&data->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static struct reset_control_ops socfpga_reset_ops = {
> > + .assert = socfpga_reset_assert,
> > + .deassert = socfpga_reset_deassert,
> > +};
> > +
> > +static int socfpga_reset_probe(struct platform_device *pdev)
> > +{
> > + struct socfpga_reset_data *data;
> > + struct resource *res;
> > + int ret;
> > +
> > + /*
> > + * The binding was mainlined without the required property.
> > + * Do not continue, when we encounter an old DT.
> > + */
> > + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> > + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> > + pdev->dev.of_node->full_name);
> > + return -EINVAL;
> > + }
> > +
> > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> > + if (!data)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + data->membase = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(data->membase))
> > + return PTR_ERR(data->membase);
> > +
> > + spin_lock_init(&data->lock);
> > +
> > + data->rcdev.owner = THIS_MODULE;
> > + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> > + data->rcdev.ops = &socfpga_reset_ops;
> > + data->rcdev.of_node = pdev->dev.of_node;
> > + reset_controller_register(&data->rcdev);
> > +
> > + return 0;
> > +}
> > +
> > +static int socfpga_reset_remove(struct platform_device *pdev)
> > +{
> > + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> > +
> > + reset_controller_unregister(&data->rcdev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id socfpga_reset_dt_ids[] = {
> > + { .compatible = "altr,rst-mgr", },
> > + { /* sentinel */ },
> > +};
> > +
> > +static struct platform_driver socfpga_reset_driver = {
> > + .probe = socfpga_reset_probe,
> > + .remove = socfpga_reset_remove,
> > + .driver = {
> > + .name = "socfpga-reset",
> > + .owner = THIS_MODULE,
> > + .of_match_table = socfpga_reset_dt_ids,
> > + },
> > +};
> > +module_platform_driver(socfpga_reset_driver);
> > +
> > +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org");
> > +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> > +MODULE_LICENSE("GPL");
>
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/4] reset: add driver for socfpga
@ 2014-04-15 22:22 ` Dinh Nguyen
0 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2014-04-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2014-04-15 at 09:20 +0200, Philipp Zabel wrote:
> Hi Dinh,
>
> Am Donnerstag, den 10.04.2014, 10:21 +0200 schrieb Steffen Trumtrar:
> > Add a reset-controller driver for the socfpga platform.
> > The reset-controller has four banks with up to 32 entries all encapsulated in
> > one module block.
> >
> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
>
> in case you want to take this through your branch,
>
> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
>
> If you want me to take the reset controller driver, please let me know.
>
Yes, I will.
Thanks,
Dinh
> regards
> Philipp
>
> > ---
> > Changes since v1:
> > - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
> > - print pdev->dev.of_node->full_name on error
> > - use proper IS_ERR/PTR_ERR
> >
> > drivers/reset/Makefile | 1 +
> > drivers/reset/reset-socfpga.c | 147 ++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 148 insertions(+)
> > create mode 100644 drivers/reset/reset-socfpga.c
> >
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index cc29832..ab64077 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -1,2 +1,3 @@
> > obj-$(CONFIG_RESET_CONTROLLER) += core.o
> > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> > +obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> > diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> > new file mode 100644
> > index 0000000..bdcd2fa
> > --- /dev/null
> > +++ b/drivers/reset/reset-socfpga.c
> > @@ -0,0 +1,147 @@
> > +/*
> > + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
> > + *
> > + * based on
> > + * Allwinner SoCs Reset Controller driver
> > + *
> > + * Copyright 2013 Maxime Ripard
> > + *
> > + * Maxime Ripard <maxime.ripard@free-electrons.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/types.h>
> > +
> > +#define NR_BANKS 4
> > +#define OFFSET_MODRST 0x10
> > +
> > +struct socfpga_reset_data {
> > + spinlock_t lock;
> > + void __iomem *membase;
> > + struct reset_controller_dev rcdev;
> > +};
> > +
> > +static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct socfpga_reset_data *data = container_of(rcdev,
> > + struct socfpga_reset_data,
> > + rcdev);
> > + int bank = id / BITS_PER_LONG;
> > + int offset = id % BITS_PER_LONG;
> > + unsigned long flags;
> > + u32 reg;
> > +
> > + spin_lock_irqsave(&data->lock, flags);
> > +
> > + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> > + writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> > + (bank * NR_BANKS));
> > + spin_unlock_irqrestore(&data->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct socfpga_reset_data *data = container_of(rcdev,
> > + struct socfpga_reset_data,
> > + rcdev);
> > +
> > + int bank = id / BITS_PER_LONG;
> > + int offset = id % BITS_PER_LONG;
> > + unsigned long flags;
> > + u32 reg;
> > +
> > + spin_lock_irqsave(&data->lock, flags);
> > +
> > + reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> > + writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> > + (bank * NR_BANKS));
> > +
> > + spin_unlock_irqrestore(&data->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static struct reset_control_ops socfpga_reset_ops = {
> > + .assert = socfpga_reset_assert,
> > + .deassert = socfpga_reset_deassert,
> > +};
> > +
> > +static int socfpga_reset_probe(struct platform_device *pdev)
> > +{
> > + struct socfpga_reset_data *data;
> > + struct resource *res;
> > + int ret;
> > +
> > + /*
> > + * The binding was mainlined without the required property.
> > + * Do not continue, when we encounter an old DT.
> > + */
> > + if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
> > + dev_err(&pdev->dev, "%s missing #reset-cells property\n",
> > + pdev->dev.of_node->full_name);
> > + return -EINVAL;
> > + }
> > +
> > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> > + if (!data)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + data->membase = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(data->membase))
> > + return PTR_ERR(data->membase);
> > +
> > + spin_lock_init(&data->lock);
> > +
> > + data->rcdev.owner = THIS_MODULE;
> > + data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> > + data->rcdev.ops = &socfpga_reset_ops;
> > + data->rcdev.of_node = pdev->dev.of_node;
> > + reset_controller_register(&data->rcdev);
> > +
> > + return 0;
> > +}
> > +
> > +static int socfpga_reset_remove(struct platform_device *pdev)
> > +{
> > + struct socfpga_reset_data *data = platform_get_drvdata(pdev);
> > +
> > + reset_controller_unregister(&data->rcdev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id socfpga_reset_dt_ids[] = {
> > + { .compatible = "altr,rst-mgr", },
> > + { /* sentinel */ },
> > +};
> > +
> > +static struct platform_driver socfpga_reset_driver = {
> > + .probe = socfpga_reset_probe,
> > + .remove = socfpga_reset_remove,
> > + .driver = {
> > + .name = "socfpga-reset",
> > + .owner = THIS_MODULE,
> > + .of_match_table = socfpga_reset_dt_ids,
> > + },
> > +};
> > +module_platform_driver(socfpga_reset_driver);
> > +
> > +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
> > +MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
> > +MODULE_LICENSE("GPL");
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2014-04-15 22:22 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-04-10 8:21 [PATCH v2 1/4] reset: add driver for socfpga Steffen Trumtrar
2014-04-10 8:21 ` Steffen Trumtrar
[not found] ` <1397118063-21619-1-git-send-email-s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-04-10 8:21 ` [PATCH v2 2/4] Documentation: dt: socfpga: add reset-cells property Steffen Trumtrar
2014-04-10 8:21 ` Steffen Trumtrar
2014-04-10 8:21 ` [PATCH v2 3/4] Documentation: dt: reset: move socfpga-reset Steffen Trumtrar
2014-04-10 8:21 ` Steffen Trumtrar
2014-04-10 8:21 ` [PATCH v2 4/4] ARM: socfpga: dts: add reset-controller Steffen Trumtrar
2014-04-10 8:21 ` Steffen Trumtrar
2014-04-14 22:31 ` [PATCH v2 1/4] reset: add driver for socfpga Dinh Nguyen
2014-04-14 22:31 ` Dinh Nguyen
2014-04-15 7:20 ` Philipp Zabel
2014-04-15 7:20 ` Philipp Zabel
[not found] ` <1397546425.3836.1.camel-+qGW7pzALmz7o/J7KWpOmN53zsg1cpMQ@public.gmane.org>
2014-04-15 22:22 ` Dinh Nguyen
2014-04-15 22:22 ` Dinh Nguyen
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