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From: Alexander Graf <agraf@suse.de>
To: David Laight <David.Laight@ACULAB.COM>
Cc: Mihai Caraman <mihai.caraman@freescale.com>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>
Subject: Re: [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
Date: Fri, 02 May 2014 13:10:51 +0200	[thread overview]
Message-ID: <53637D3B.4010205@suse.de> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D0F705051@AcuExch.aculab.com>

On 05/02/2014 12:12 PM, David Laight wrote:
> From: Alexander Graf
> ...
>>> +	page = pfn_to_page(pfn);
>>> +	eaddr = (unsigned long)kmap_atomic(page);
>>> +	eaddr |= addr & ~PAGE_MASK;
>>> +	*instr = *(u32 *)eaddr;
>>> +	kunmap_atomic((u32 *)eaddr);
>> I think I'd rather write this as
>>
>>     *instr = *(u32 *)(eaddr | (addr & ~PAGE));
>>     kunmap_atomic((void*)eaddr);
>>
>> to make sure we pass the unmap function the same value we got from the
>> map function.
>>
>> Otherwise looks good to me.
> Is there any mileage in keeping a virtual address page allocated (per cpu)
> for this (and similar) accesses to physical memory?
> Not having to search for a free VA page might speed things up (if that matters).

I like the idea, though I'm not sure how that would best fit into the 
current memory mapping ecosystem.

> You also probably want the page mapped uncached - no point polluting the data
> cache.

Do e500 chips have a shared I/D cache somewhere? If they do, that 
particular instruction would already be there, so no pollution but nice 
performance.


Alex

WARNING: multiple messages have this Message-ID (diff)
From: Alexander Graf <agraf@suse.de>
To: David Laight <David.Laight@ACULAB.COM>
Cc: Mihai Caraman <mihai.caraman@freescale.com>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
Date: Fri, 02 May 2014 13:10:51 +0200	[thread overview]
Message-ID: <53637D3B.4010205@suse.de> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D0F705051@AcuExch.aculab.com>

On 05/02/2014 12:12 PM, David Laight wrote:
> From: Alexander Graf
> ...
>>> +	page = pfn_to_page(pfn);
>>> +	eaddr = (unsigned long)kmap_atomic(page);
>>> +	eaddr |= addr & ~PAGE_MASK;
>>> +	*instr = *(u32 *)eaddr;
>>> +	kunmap_atomic((u32 *)eaddr);
>> I think I'd rather write this as
>>
>>     *instr = *(u32 *)(eaddr | (addr & ~PAGE));
>>     kunmap_atomic((void*)eaddr);
>>
>> to make sure we pass the unmap function the same value we got from the
>> map function.
>>
>> Otherwise looks good to me.
> Is there any mileage in keeping a virtual address page allocated (per cpu)
> for this (and similar) accesses to physical memory?
> Not having to search for a free VA page might speed things up (if that matters).

I like the idea, though I'm not sure how that would best fit into the 
current memory mapping ecosystem.

> You also probably want the page mapped uncached - no point polluting the data
> cache.

Do e500 chips have a shared I/D cache somewhere? If they do, that 
particular instruction would already be there, so no pollution but nice 
performance.


Alex

WARNING: multiple messages have this Message-ID (diff)
From: Alexander Graf <agraf@suse.de>
To: David Laight <David.Laight@ACULAB.COM>
Cc: Mihai Caraman <mihai.caraman@freescale.com>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>
Subject: Re: [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
Date: Fri, 02 May 2014 11:10:51 +0000	[thread overview]
Message-ID: <53637D3B.4010205@suse.de> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D0F705051@AcuExch.aculab.com>

On 05/02/2014 12:12 PM, David Laight wrote:
> From: Alexander Graf
> ...
>>> +	page = pfn_to_page(pfn);
>>> +	eaddr = (unsigned long)kmap_atomic(page);
>>> +	eaddr |= addr & ~PAGE_MASK;
>>> +	*instr = *(u32 *)eaddr;
>>> +	kunmap_atomic((u32 *)eaddr);
>> I think I'd rather write this as
>>
>>     *instr = *(u32 *)(eaddr | (addr & ~PAGE));
>>     kunmap_atomic((void*)eaddr);
>>
>> to make sure we pass the unmap function the same value we got from the
>> map function.
>>
>> Otherwise looks good to me.
> Is there any mileage in keeping a virtual address page allocated (per cpu)
> for this (and similar) accesses to physical memory?
> Not having to search for a free VA page might speed things up (if that matters).

I like the idea, though I'm not sure how that would best fit into the 
current memory mapping ecosystem.

> You also probably want the page mapped uncached - no point polluting the data
> cache.

Do e500 chips have a shared I/D cache somewhere? If they do, that 
particular instruction would already be there, so no pollution but nice 
performance.


Alex


  reply	other threads:[~2014-05-02 11:10 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-01  0:45 [PATCH v2 0/4] KVM: PPC: Read guest instruction from kvmppc_get_last_inst() Mihai Caraman
2014-05-01  0:45 ` Mihai Caraman
2014-05-01  0:45 ` Mihai Caraman
2014-05-01  0:45 ` [PATCH v2 1/4] KVM: PPC: e500mc: Revert "add load inst fixup" Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-02  9:24   ` Alexander Graf
2014-05-02  9:24     ` Alexander Graf
2014-05-02  9:24     ` Alexander Graf
2014-05-02 23:14     ` mihai.caraman
2014-05-02 23:14       ` mihai.caraman
2014-05-02 23:14       ` mihai.caraman
2014-05-03 22:14       ` Alexander Graf
2014-05-03 22:14         ` Alexander Graf
2014-05-03 22:14         ` Alexander Graf
2014-05-06 15:48         ` mihai.caraman
2014-05-06 15:48           ` mihai.caraman
2014-05-06 15:48           ` mihai.caraman
2014-05-06 15:54           ` Alexander Graf
2014-05-06 15:54             ` Alexander Graf
2014-05-06 15:54             ` Alexander Graf
2014-05-01  0:45 ` [PATCH v2 2/4] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-01  0:45 ` [PATCH v2 3/4] KVM: PPC: Alow kvmppc_get_last_inst() to fail Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-02  9:54   ` Alexander Graf
2014-05-02  9:54     ` Alexander Graf
2014-05-02  9:54     ` Alexander Graf
2014-05-06 19:06     ` mihai.caraman
2014-05-06 19:06       ` mihai.caraman
2014-05-06 19:06       ` mihai.caraman
2014-05-08 13:31       ` Alexander Graf
2014-05-08 13:31         ` Alexander Graf
2014-05-08 13:31         ` Alexander Graf
2014-05-01  0:45 ` [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-01  0:45   ` Mihai Caraman
2014-05-02 10:01   ` Alexander Graf
2014-05-02 10:01     ` Alexander Graf
2014-05-02 10:01     ` Alexander Graf
2014-05-02 10:12     ` David Laight
2014-05-02 10:12       ` David Laight
2014-05-02 10:12       ` David Laight
2014-05-02 11:10       ` Alexander Graf [this message]
2014-05-02 11:10         ` Alexander Graf
2014-05-02 11:10         ` Alexander Graf
2014-05-02 15:32         ` Scott Wood
2014-05-02 15:32           ` Scott Wood
2014-05-02 15:32           ` Scott Wood
  -- strict thread matches above, loose matches on Subject: below --
2014-05-01  0:39 [PATCH v2 0/4] KVM: PPC: Read guest instruction from kvmppc_get_last_inst() Mihai Caraman
2014-05-01  0:39 ` Mihai Caraman
2014-05-01  0:39 ` Mihai Caraman

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