* [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation
@ 2017-11-14 14:15 Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration Michal Simek
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Hi,
this series is trying to cleanup ps7_init* file that we don't need to
have the same copy of the same functions in different locations.
This work is done based on solution from Topic.nl for miami boards
where format was changed a little bit to save one word in config data
segment.
At the same time older method of simply copying files to particular
folder is still working.
Please test this in your board to make sure I didn't break anything.
I have tested it on zybo/zc702/zc706.
Thanks,
Michal
Changes in v2:
- Fix indentation by using tabs instead of spaces
- Add own opcode for write operation
- Change commit message (was Convert EMIT_WRITE to EMIT_MASKWRITE) -
requested by Mike
Michal Simek (9):
arm: zynq: Add missing ps7_post_config declaration
arm: zynq: Enable debug uart on zc706
arm: zynq: Remove ps7_debug code
arm: zynq: Move ps7_* to separate file
arm: zynq: Get rid of ps7_reset_apu() for syzygy board
arm: zynq: Move common ps7_init* initialization to arch code
arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
arm: zynq: Add support for EMIT_WRITE operation
arm: zynq: Convert all board to use arch ps7_init code
arch/arm/mach-zynq/Makefile | 2 +-
arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 48 ++++
arch/arm/mach-zynq/include/mach/sys_proto.h | 3 -
.../arm/mach-zynq/ps7_spl_init.c | 37 ++-
arch/arm/mach-zynq/spl.c | 18 +-
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 138 +---------
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 81 ------
board/topic/zynq/Makefile | 2 +-
board/topic/zynq/ps7_init_gpl.h | 34 ---
board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +-
.../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +-
.../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 2 +-
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 285 +-------------------
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 117 ---------
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 289 +-------------------
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 117 ---------
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 285 +-------------------
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 117 ---------
board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 285 +-------------------
board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 117 ---------
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 292 +--------------------
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 98 -------
configs/zynq_zc706_defconfig | 5 +
23 files changed, 100 insertions(+), 2276 deletions(-)
create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
rename board/topic/zynq/ps7_init_common.c => arch/arm/mach-zynq/ps7_spl_init.c (76%)
delete mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
delete mode 100644 board/topic/zynq/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 2/9] arm: zynq: Enable debug uart on zc706 Michal Simek
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Add missing declaration to header.
Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
arch/arm/mach-zynq/include/mach/sys_proto.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 67238e7fbcfd..0ef688309da3 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -22,5 +22,6 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
/* Driver extern functions */
extern void ps7_init(void);
+int ps7_post_config(void);
#endif /* _SYS_PROTO_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/9] arm: zynq: Enable debug uart on zc706
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 3/9] arm: zynq: Remove ps7_debug code Michal Simek
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Enable debug uart by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
configs/zynq_zc706_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index bc6fe3a30695..52999debc115 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
@@ -51,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 3/9] arm: zynq: Remove ps7_debug code
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 2/9] arm: zynq: Enable debug uart on zc706 Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 4/9] arm: zynq: Move ps7_* to separate file Michal Simek
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
SPL is not calling this code that's why it is dead code and can be
removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 10 --
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 1 -
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 112 --------------------
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 1 -
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 112 --------------------
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 1 -
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 112 --------------------
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 1 -
board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 112 --------------------
board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 1 -
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 114 ---------------------
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 1 -
12 files changed, 578 deletions(-)
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 7ae04758b7d5..f2a757a5cfeb 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -255,12 +255,6 @@ unsigned long ps7_post_config_3_0[] = {
EMIT_EXIT(),
};
-unsigned long ps7_debug_3_0[] = {
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- EMIT_EXIT(),
-};
unsigned long ps7_reset_apu_3_0[] = {
EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
@@ -353,10 +347,6 @@ int ps7_post_config(void)
return ps7_config(ps7_post_config_3_0);
}
-int ps7_debug(void)
-{
- return ps7_config(ps7_debug_3_0);
-}
int ps7_reset_apu(void)
{
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
index 158c25f3ae9b..cffffa90bbc5 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
@@ -69,7 +69,6 @@ extern "C" {
int ps7_config(unsigned long *);
int ps7_init(void);
int ps7_post_config(void);
-int ps7_debug(void);
void perf_start_clock(void);
void perf_disable_clock(void);
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index eb290023a1eb..58c31b8a50cf 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -4121,37 +4121,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8419,37 +8388,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12650,37 +12588,6 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
@@ -12844,25 +12751,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
index bdea5a0443c0..d775a33d98cb 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
@@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data;
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
-int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index abfd91187df3..99cf4681f84b 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -4228,37 +4228,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8639,37 +8608,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12983,37 +12921,6 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
@@ -13177,25 +13084,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
index 16fa8104a415..beb3b58b0c4d 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
@@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data;
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
-int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 77fd9499df76..c45cc6a6e514 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -4197,37 +4197,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8577,37 +8546,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12890,37 +12828,6 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
@@ -13084,25 +12991,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
index 8527eef447e7..694412a1e9d5 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
@@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data;
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
-int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index f4f45becd66a..783fd9a30b78 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -4087,37 +4087,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8351,37 +8320,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12548,37 +12486,6 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
@@ -12742,25 +12649,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
index 9b41e286976b..6d89863854e2 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
@@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data;
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
-int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 83daf7bf15b8..ed7c2a64e128 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4141,37 +4141,6 @@ unsigned long ps7_post_config_3_0[] = {
/* */
};
-unsigned long ps7_debug_3_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_2_0[] = {
/* START: top */
@@ -8467,37 +8436,6 @@ unsigned long ps7_post_config_2_0[] = {
/* */
};
-unsigned long ps7_debug_2_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_1_0[] = {
/* START: top */
@@ -12726,37 +12664,6 @@ unsigned long ps7_post_config_1_0[] = {
/* */
};
-unsigned long ps7_debug_1_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
#include "xil_io.h"
#define PS7_MASK_POLL_TIME 100000000
@@ -12926,27 +12833,6 @@ int ps7_post_config(void)
return PS7_INIT_SUCCESS;
}
-int ps7_debug(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config(ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config(ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else {
- ret = ps7_config(ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int ps7_init(void)
{
/* Get the PS_VERSION on run time */
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
index 22d9fd9250e8..929251afc5f2 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
@@ -85,7 +85,6 @@ extern unsigned long *ps7_peripherals_init_data;
int ps7_config(unsigned long *);
int ps7_init(void);
int ps7_post_config(void);
-int ps7_debug(void);
char *getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 4/9] arm: zynq: Move ps7_* to separate file
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (2 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 3/9] arm: zynq: Remove ps7_debug code Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board Michal Simek
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Extract ps7_* from spl code to prepare for extension.
And also return value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
arch/arm/mach-zynq/Makefile | 2 +-
arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 14 +++++++++++++
arch/arm/mach-zynq/include/mach/sys_proto.h | 4 ----
arch/arm/mach-zynq/ps7_spl_init.c | 27 ++++++++++++++++++++++++++
arch/arm/mach-zynq/spl.c | 18 +----------------
5 files changed, 43 insertions(+), 22 deletions(-)
create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
create mode 100644 arch/arm/mach-zynq/ps7_spl_init.c
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index bf29b4d396d3..e3f0117da563 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -15,4 +15,4 @@ obj-y += slcr.o
obj-y += clk.o
obj-y += lowlevel_init.o
AFLAGS_lowlevel_init.o := -mfpu=neon
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
new file mode 100644
index 000000000000..6e30108b23f4
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -0,0 +1,14 @@
+/*
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PS7_INIT_GPL_H
+#define _ASM_ARCH_PS7_INIT_GPL_H
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 0ef688309da3..af61352dd110 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -20,8 +20,4 @@ extern unsigned int zynq_get_silicon_version(void);
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
-/* Driver extern functions */
-extern void ps7_init(void);
-int ps7_post_config(void);
-
#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c
new file mode 100644
index 000000000000..6adf852578a6
--- /dev/null
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -0,0 +1,27 @@
+/*
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/ps7_init_gpl.h>
+
+__weak int ps7_init(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+ */
+ return 0;
+}
+
+__weak int ps7_post_config(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+ */
+ return 0;
+}
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index e8added15567..1672fa05c26a 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -11,6 +11,7 @@
#include <asm/spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -83,23 +84,6 @@ int spl_start_uboot(void)
}
#endif
-__weak void ps7_init(void)
-{
- /*
- * This function is overridden by the one in
- * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
- */
-}
-
-__weak int ps7_post_config(void)
-{
- /*
- * This function is overridden by the one in
- * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
- */
- return 0;
-}
-
void spl_board_prepare_for_boot(void)
{
ps7_post_config();
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (3 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 4/9] arm: zynq: Move ps7_* to separate file Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 6/9] arm: zynq: Move common ps7_init* initialization to arch code Michal Simek
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
There is no reason to call separate function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index f2a757a5cfeb..5aa3951b8017 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -347,17 +347,11 @@ int ps7_post_config(void)
return ps7_config(ps7_post_config_3_0);
}
-
-int ps7_reset_apu(void)
-{
- return ps7_config(ps7_reset_apu_3_0);
-}
-
int ps7_init(void)
{
int ret;
- ret = ps7_reset_apu();
+ ret = ps7_config(ps7_reset_apu_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 6/9] arm: zynq: Move common ps7_init* initialization to arch code
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (4 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init Michal Simek
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.
The patch is also marking ps7_config as weak function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2:
- Fix indentation by using tabs instead of spaces
arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 28 ++++-
arch/arm/mach-zynq/ps7_spl_init.c | 109 +++++++++++++++++++
board/topic/zynq/Makefile | 2 +-
board/topic/zynq/ps7_init_common.c | 117 ---------------------
board/topic/zynq/ps7_init_gpl.h | 34 ------
board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +-
.../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +-
.../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 2 +-
8 files changed, 140 insertions(+), 156 deletions(-)
delete mode 100644 board/topic/zynq/ps7_init_common.c
delete mode 100644 board/topic/zynq/ps7_init_gpl.h
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index 6e30108b23f4..c7c716e7f2c4 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -1,5 +1,6 @@
/*
- * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -7,8 +8,33 @@
#ifndef _ASM_ARCH_PS7_INIT_GPL_H
#define _ASM_ARCH_PS7_INIT_GPL_H
+/* Opcode exit is 0 all the time */
+#define OPCODE_EXIT 0U
+#define OPCODE_MASKWRITE 0U
+#define OPCODE_MASKPOLL 1U
+#define OPCODE_MASKDELAY 2U
+#define OPCODE_ADDRESS_MASK (~3U)
+
+/* Sentinel */
+#define EMIT_EXIT() OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS (0)
+#define PS7_INIT_CORRUPT (1)
+#define PS7_INIT_TIMEOUT (2)
+#define PS7_POLL_FAILED_DDR_INIT (3)
+#define PS7_POLL_FAILED_DMA (4)
+#define PS7_POLL_FAILED_PLL (5)
+
/* Called by spl.c */
int ps7_init(void);
int ps7_post_config(void);
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
+
#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c
index 6adf852578a6..180099577b04 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -1,5 +1,6 @@
/*
* (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -25,3 +26,111 @@ __weak int ps7_post_config(void)
*/
return 0;
}
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+#define APU_FREQ 666666666
+
+#define PS7_MASK_POLL_TIME 100000000
+
+/* IO accessors. No memory barriers desired. */
+static inline void iowrite(unsigned long val, unsigned long addr)
+{
+ __raw_writel(val, addr);
+}
+
+static inline unsigned long ioread(unsigned long addr)
+{
+ return __raw_readl(addr);
+}
+
+/* start timer */
+static void perf_start_clock(void)
+{
+ iowrite((1 << 0) | /* Timer Enable */
+ (1 << 3) | /* Auto-increment */
+ (0 << 8), /* Pre-scale */
+ SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* Compute mask for given delay in miliseconds*/
+static int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ return (APU_FREQ / (2 * 1000)) * delay;
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+ iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
+ iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
+}
+
+static void perf_reset_and_start_timer(void)
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+int __weak ps7_config(unsigned long *ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+ unsigned long opcode;
+ unsigned long addr;
+ unsigned long val;
+ unsigned long mask;
+ unsigned int numargs;
+ int i;
+ int delay;
+
+ for (;;) {
+ opcode = ptr[0];
+ if (opcode == OPCODE_EXIT)
+ return PS7_INIT_SUCCESS;
+ addr = (opcode & OPCODE_ADDRESS_MASK);
+
+ switch (opcode & ~OPCODE_ADDRESS_MASK) {
+ case OPCODE_MASKWRITE:
+ numargs = 3;
+ mask = ptr[1];
+ val = ptr[2];
+ iowrite((ioread(addr) & ~mask) | (val & mask), addr);
+ break;
+
+ case OPCODE_MASKPOLL:
+ numargs = 2;
+ mask = ptr[1];
+ i = 0;
+ while (!(ioread(addr) & mask)) {
+ if (i == PS7_MASK_POLL_TIME)
+ return PS7_INIT_TIMEOUT;
+ i++;
+ }
+ break;
+
+ case OPCODE_MASKDELAY:
+ numargs = 2;
+ mask = ptr[1];
+ delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while (ioread(addr) < delay)
+ ;
+ break;
+
+ default:
+ return PS7_INIT_CORRUPT;
+ }
+
+ ptr += numargs;
+ }
+}
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
index eaf59cd55c6c..789348207535 100644
--- a/board/topic/zynq/Makefile
+++ b/board/topic/zynq/Makefile
@@ -7,4 +7,4 @@ obj-y := board.o
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c
deleted file mode 100644
index b1d45c242f80..000000000000
--- a/board/topic/zynq/ps7_init_common.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
- * (c) Copyright 2016 Topic Embedded Products.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "ps7_init_gpl.h"
-#include <asm/io.h>
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-#define APU_FREQ 666666666
-
-#define PS7_MASK_POLL_TIME 100000000
-
-/* IO accessors. No memory barriers desired. */
-static inline void iowrite(unsigned long val, unsigned long addr)
-{
- __raw_writel(val, addr);
-}
-
-static inline unsigned long ioread(unsigned long addr)
-{
- return __raw_readl(addr);
-}
-
-/* start timer */
-static void perf_start_clock(void)
-{
- iowrite((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8), /* Pre-scale */
- SCU_GLOBAL_TIMER_CONTROL);
-}
-
-/* Compute mask for given delay in miliseconds*/
-static int get_number_of_cycles_for_delay(unsigned int delay)
-{
- return (APU_FREQ / (2 * 1000)) * delay;
-}
-
-/* stop timer */
-static void perf_disable_clock(void)
-{
- iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
-}
-
-/* stop timer and reset timer count regs */
-static void perf_reset_clock(void)
-{
- perf_disable_clock();
- iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
- iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
-}
-
-static void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
- unsigned long opcode;
- unsigned long addr;
- unsigned long val;
- unsigned long mask;
- unsigned int numargs;
- int i;
- int delay;
-
- for (;;) {
- opcode = ptr[0];
- if (opcode == OPCODE_EXIT)
- return PS7_INIT_SUCCESS;
- addr = (opcode & OPCODE_ADDRESS_MASK);
-
- switch (opcode & ~OPCODE_ADDRESS_MASK) {
- case OPCODE_MASKWRITE:
- numargs = 3;
- mask = ptr[1];
- val = ptr[2];
- iowrite((ioread(addr) & ~mask) | (val & mask), addr);
- break;
-
- case OPCODE_MASKPOLL:
- numargs = 2;
- mask = ptr[1];
- i = 0;
- while (!(ioread(addr) & mask)) {
- if (i == PS7_MASK_POLL_TIME)
- return PS7_INIT_TIMEOUT;
- i++;
- }
- break;
-
- case OPCODE_MASKDELAY:
- numargs = 2;
- mask = ptr[1];
- delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while (ioread(addr) < delay)
- ;
- break;
-
- default:
- return PS7_INIT_CORRUPT;
- }
-
- ptr += numargs;
- }
-}
diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h
deleted file mode 100644
index ef719acabadb..000000000000
--- a/board/topic/zynq/ps7_init_gpl.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
- * (c) Copyright 2016 Topic Embedded Products.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define OPCODE_EXIT 0U
-#define OPCODE_MASKWRITE 0U
-#define OPCODE_MASKPOLL 1U
-#define OPCODE_MASKDELAY 2U
-#define OPCODE_ADDRESS_MASK (~3U)
-
-/* Sentinel */
-#define EMIT_EXIT() OPCODE_EXIT
-/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
-#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
-#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
-
-/* Returns codes of ps7_init* */
-#define PS7_INIT_SUCCESS (0)
-#define PS7_INIT_CORRUPT (1)
-#define PS7_INIT_TIMEOUT (2)
-#define PS7_POLL_FAILED_DDR_INIT (3)
-#define PS7_POLL_FAILED_DMA (4)
-#define PS7_POLL_FAILED_PLL (5)
-
-/* Called by spl.c */
-int ps7_init(void);
-int ps7_post_config(void);
-
-/* Defined in ps7_init_common.c */
-int ps7_config(unsigned long *ps7_config_init);
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
index b195d7a25bf4..ceed04383f5f 100644
--- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
index ec0cc7d19d0c..1205d19d9a35 100644
--- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
index 5a923366eb78..f42632b7fab5 100644
--- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (5 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 6/9] arm: zynq: Move common ps7_init* initialization to arch code Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 8/9] arm: zynq: Add support for EMIT_WRITE operation Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 9/9] arm: zynq: Convert all board to use arch ps7_init code Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Unfortunately camelcase is coming from ps7_init* format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 6 ++++++
arch/arm/mach-zynq/ps7_spl_init.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index c7c716e7f2c4..fa5d486afb0c 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -30,6 +30,10 @@
#define PS7_POLL_FAILED_DMA (4)
#define PS7_POLL_FAILED_PLL (5)
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
/* Called by spl.c */
int ps7_init(void);
int ps7_post_config(void);
@@ -37,4 +41,6 @@ int ps7_post_config(void);
/* Defined in ps7_init_common.c */
int ps7_config(unsigned long *ps7_config_init);
+unsigned long ps7GetSiliconVersion(void);
+
#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c
index 180099577b04..069827880d10 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -7,6 +7,7 @@
#include <asm/io.h>
#include <asm/spl.h>
+#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>
__weak int ps7_init(void)
@@ -134,3 +135,8 @@ int __weak ps7_config(unsigned long *ps7_config_init)
ptr += numargs;
}
}
+
+unsigned long __weak __maybe_unused ps7GetSiliconVersion(void)
+{
+ return zynq_get_silicon_version();
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 8/9] arm: zynq: Add support for EMIT_WRITE operation
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (6 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 9/9] arm: zynq: Convert all board to use arch ps7_init code Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2:
- Add own opcode for write operation
- Change commit message (was Convert EMIT_WRITE to EMIT_MASKWRITE) -
requested by Mike
arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 2 ++
arch/arm/mach-zynq/ps7_spl_init.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index fa5d486afb0c..0af4165a3ef1 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -13,6 +13,7 @@
#define OPCODE_MASKWRITE 0U
#define OPCODE_MASKPOLL 1U
#define OPCODE_MASKDELAY 2U
+#define OPCODE_WRITE 3U
#define OPCODE_ADDRESS_MASK (~3U)
/* Sentinel */
@@ -21,6 +22,7 @@
#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+#define EMIT_WRITE(addr, val) OPCODE_WRITE | addr, val
/* Returns codes of ps7_init* */
#define PS7_INIT_SUCCESS (0)
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c
index 069827880d10..6dc4e0364d8b 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -108,6 +108,12 @@ int __weak ps7_config(unsigned long *ps7_config_init)
iowrite((ioread(addr) & ~mask) | (val & mask), addr);
break;
+ case OPCODE_WRITE:
+ numargs = 2;
+ val = ptr[1];
+ iowrite(val, addr);
+ break;
+
case OPCODE_MASKPOLL:
numargs = 2;
mask = ptr[1];
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 9/9] arm: zynq: Convert all board to use arch ps7_init code
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
` (7 preceding siblings ...)
2017-11-14 14:15 ` [U-Boot] [PATCH v2 8/9] arm: zynq: Add support for EMIT_WRITE operation Michal Simek
@ 2017-11-14 14:15 ` Michal Simek
8 siblings, 0 replies; 10+ messages in thread
From: Michal Simek @ 2017-11-14 14:15 UTC (permalink / raw)
To: u-boot
Use generic implementation. It will also reduce config data size for
converted boards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 120 +-------------
.../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 80 ---------
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 173 +-------------------
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 116 --------------
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 177 +-------------------
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 116 --------------
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 173 +-------------------
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 116 --------------
board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 173 +-------------------
board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 116 --------------
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 178 +--------------------
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 97 -----------
12 files changed, 6 insertions(+), 1629 deletions(-)
delete mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 5aa3951b8017..3bd02f3c83ec 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -5,8 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*****************************************************************************/
-#include "ps7_init_gpl.h"
-#include "asm/io.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
@@ -255,92 +254,11 @@ unsigned long ps7_post_config_3_0[] = {
EMIT_EXIT(),
};
-
unsigned long ps7_reset_apu_3_0[] = {
EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
EMIT_EXIT(),
};
-#define PS7_MASK_POLL_TIME 100000000
-
-static inline void iowrite(unsigned long val, unsigned long addr)
-{
- __raw_writel(val, addr);
-}
-
-static inline unsigned long ioread(unsigned long addr)
-{
- return __raw_readl(addr);
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; /* current instruction .. */
- unsigned long args[16]; /* no opcode has so many args ... */
- int numargs; /* number of arguments of this instruction */
- int j; /* general purpose index */
-
- unsigned long addr;
- unsigned long val, mask;
-
- int finish = -1; /* loop while this is negative ! */
- int i = 0; /* Timeout variable */
-
- while (finish < 0) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for (j = 0; j < numargs; j++)
- args[j] = ptr[j + 1];
- ptr += numargs + 1;
-
- switch (opcode) {
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_WRITE:
- addr = args[0];
- val = args[1];
- iowrite(val, addr);
- break;
-
- case OPCODE_MASKWRITE:
- addr = args[0];
- mask = args[1];
- val = args[2];
- iowrite((val & mask) | (ioread(addr) & ~mask) , addr);
- break;
-
- case OPCODE_MASKPOLL:
- addr = args[0];
- mask = args[1];
- i = 0;
- while (!(ioread(addr) & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while (ioread(addr) < delay)
- ;
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
int ps7_post_config(void)
{
@@ -377,39 +295,3 @@ int ps7_init(void)
return PS7_INIT_SUCCESS;
}
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
- iowrite((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8), /* Pre-scale */
- SCU_GLOBAL_TIMER_CONTROL);
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
- perf_disable_clock();
- iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
- iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
- iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
-}
-
-void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
deleted file mode 100644
index cffffa90bbc5..000000000000
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
-#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) ,\
- addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) ,\
- addr, mask
-#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) ,\
- addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0)
-#define PS7_INIT_CORRUPT (1)
-#define PS7_INIT_TIMEOUT (2)
-#define PS7_POLL_FAILED_DDR_INIT (3)
-#define PS7_POLL_FAILED_DMA (4)
-#define PS7_POLL_FAILED_PLL (5)
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 100000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index 58c31b8a50cf..5cf627d2233d 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -12591,139 +12591,6 @@ unsigned long ps7_post_config_1_0[] = {
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12811,41 +12678,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked@1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
deleted file mode 100644
index d775a33d98cb..000000000000
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 100000000
-#define FPGA2_FREQ 33333336
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index 99cf4681f84b..fc325a6b028a 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -12924,139 +12924,6 @@ unsigned long ps7_post_config_1_0[] = {
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13140,45 +13007,3 @@ ps7_init()
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked@1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
deleted file mode 100644
index beb3b58b0c4d..000000000000
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 23809523
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index c45cc6a6e514..ca5490f0b0e3 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -12831,139 +12831,6 @@ unsigned long ps7_post_config_1_0[] = {
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13051,41 +12918,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked@1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
deleted file mode 100644
index 694412a1e9d5..000000000000
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index 783fd9a30b78..54c803cfa659 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -12489,139 +12489,6 @@ unsigned long ps7_post_config_1_0[] = {
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12709,41 +12576,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked@1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
deleted file mode 100644
index 6d89863854e2..000000000000
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index ed7c2a64e128..84625f07462e 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
/* START: top */
@@ -12666,145 +12666,6 @@ unsigned long ps7_post_config_1_0[] = {
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
- char *err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS:
- err_msg = "PS7 initialization successful";
- break;
- case PS7_INIT_CORRUPT:
- err_msg = "PS7 init Data Corrupted";
- break;
- case PS7_INIT_TIMEOUT:
- err_msg = "PS7 init mask poll timeout";
- break;
- case PS7_POLL_FAILED_DDR_INIT:
- err_msg = "Mask Poll failed for DDR Init";
- break;
- case PS7_POLL_FAILED_DMA:
- err_msg = "Mask Poll failed for PLL Init";
- break;
- case PS7_POLL_FAILED_PLL:
- err_msg = "Mask Poll failed for DMA done bit";
- break;
- default:
- err_msg = "Undefined error status";
- break;
- }
-
- return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
- /* Read PS version from MCTRL register [31:28] */
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long *)0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
- unsigned long *addr = (unsigned long *)add;
- *addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
- volatile unsigned long *addr = (volatile unsigned long *)add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME)
- return -1;
- i++;
- }
- return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
- unsigned long *addr = (unsigned long *)add;
- unsigned long val = (*addr & mask);
- return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; /* current instruction .. */
- unsigned long args[16]; /* no opcode has so many args ... */
- int numargs; /* number of arguments of this instruction */
- int j; /* general purpose index */
-
- volatile unsigned long *addr; /* some variable to make code readable */
- unsigned long val, mask; /* some variable to make code readable */
-
- int finish = -1; /* loop while this is negative ! */
- int i = 0; /* Timeout variable */
-
- while (finish < 0) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for (j = 0; j < numargs; j++)
- args[j] = ptr[j + 1];
- ptr += numargs + 1;
-
- switch (opcode) {
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long *)args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long *)args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long *)args[0];
- mask = args[1];
- val = args[2];
- *addr = (val & mask) | (*addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long *)args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long *)args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay))
- ;
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12892,40 +12753,3 @@ int ps7_init(void)
return PS7_INIT_SUCCESS;
}
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8) /* Pre-scale */
- );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- /* GTC is always clocked@1/2 of the CPU frequency (CPU_3x2x) */
- return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
deleted file mode 100644
index 929251afc5f2..000000000000
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
-#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
-#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
-#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 200000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-11-14 14:15 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-14 14:15 [U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 2/9] arm: zynq: Enable debug uart on zc706 Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 3/9] arm: zynq: Remove ps7_debug code Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 4/9] arm: zynq: Move ps7_* to separate file Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 6/9] arm: zynq: Move common ps7_init* initialization to arch code Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 8/9] arm: zynq: Add support for EMIT_WRITE operation Michal Simek
2017-11-14 14:15 ` [U-Boot] [PATCH v2 9/9] arm: zynq: Convert all board to use arch ps7_init code Michal Simek
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