Re: [PATCH] net/cadence/macb: clear interrupts simply and correctly

From: Nicolas Ferre <nicolas.ferre@atmel.com>
To: "Jongsung Kim" <neidhard.kim@lge.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Hayun Hwang <hwang.hayun@lge.com>,
	"Youngkyu Choi" <youngkyu7.choi@lge.com>,
	Cyrille Pitchen <cyrille.pitchen@atmel.com>
Subject: Re: [PATCH] net/cadence/macb: clear interrupts simply and correctly
Date: Tue, 17 Jun 2014 09:54:38 +0200	[thread overview]
Message-ID: <539FF43E.2020002@atmel.com> (raw)
In-Reply-To: <539FB874.1040003@lge.com>

On 17/06/2014 05:39, Jongsung Kim :
> On 06/17/2014 06:28 AM, Sören Brinkmann wrote:
>> Shouldn't it be sufficient to replace 'MACB_BIT(RCOMP) with 'MACB_RX_INT_FLAGS'
>> to clear all the RX IRQ flags.
> 
> I'm afraid not.
> 
> You know, this driver initially targeted only GEMs configured with "gem_irq_clear_read."
> For this implementation of GEM, the ISR is automatically cleared by reading. The driver
> was designed to operate with the value read from ISR, not with the ISR itself.
> 
> However, there are other GEMs configured without "gem_irq_clear_read," people like you
> and I working with. To support them, they insert similar codes conditionally clearing
> the ISR here and there. Now they are found at 6 places. Not enough yet. Do you want to
> insert another at the end of macb_reset_hw..? Maybe not.

Can't we separate a bit more the implementations of "clear on read" and
"clear on write" so that we do not spread the tests that you are talking
about all over the place and slower the driver's hot paths?

I am more and more skeptical about the mix of MACB/GEM versions in this
single driver as I realized recently that the old MACB-equipped devices
are behaving strangely and with lower performance figures than in the past.

Best regards,
-- 
Nicolas Ferre