[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[Nikolay Dimitrov]

Hi Gabriel,

> This allows u-boot to load different OS or Bare Metal application on the
> different cores of the i.MX6DQ.
> For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

I think this explanation is a little misleading - if you run unmodified 
versions of Android & some RTOS, they will fight for the imx6 interrupt 
controller, power management and clocks. As far as I know, imx6 is not 
appropriate for AMP (asymmetric multi-processing) because it doesn't 
support virtualization extensions.

Kind regards,
Nikolay

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[gabriel huau]

Hi Nikolay,

I agree that you have to modify those OS to support 'multi-OS' on 
different core but this customization is not part of u-boot in my sense. 
For the second point, I have to disagree, the imx6 is totally 
appropriate for AMP/multi-OS, in my case, I wasn't thinking about 
virtualization which is something different but really about 
multi-OS/Bare Metal application. The interrupt controller (GIC) can be 
configured to distribute any interrupt on any core, for example, you can 
have UART1 interrupt on core0 and UART2 interrupt on core1.
The only problem is the resource partitioning but as I said this is 
another subject which is not really part of u-boot and I already did 
some test by running Android on core0 and QNX on core1 without any 
problem as a proof of concept.

A good example may be the support on this kind of application on the 
Zynq: http://www.wiki.xilinx.com/Multi-OS+Support+%28AMP+%26+Hypervisor%29
This is also a Cortex A9 without the support of virtualization extensions.

Regards,
Gabriel

On 06/22/2014 07:09 AM, Nikolay Dimitrov wrote:
> Hi Gabriel,
>
>> This allows u-boot to load different OS or Bare Metal application on the
>> different cores of the i.MX6DQ.
>> For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS 
>> on cpu1.
>
> I think this explanation is a little misleading - if you run 
> unmodified versions of Android & some RTOS, they will fight for the 
> imx6 interrupt controller, power management and clocks. As far as I 
> know, imx6 is not appropriate for AMP (asymmetric multi-processing) 
> because it doesn't support virtualization extensions.
>
> Kind regards,
> Nikolay

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[Nikolay Dimitrov]

Hi Gabriel,

On 6/22/2014 5:24 PM, gabriel huau wrote:
> Hi Nikolay,
>
> I agree that you have to modify those OS to support 'multi-OS' on 
> different core but this customization is not part of u-boot in my 
> sense. For the second point, I have to disagree, the imx6 is totally 
> appropriate for AMP/multi-OS, in my case, I wasn't thinking about 
> virtualization which is something different but really about 
> multi-OS/Bare Metal application. The interrupt controller (GIC) can be 
> configured to distribute any interrupt on any core, for example, you 
> can have UART1 interrupt on core0 and UART2 interrupt on core1.
> The only problem is the resource partitioning but as I said this is 
> another subject which is not really part of u-boot and I already did 
> some test by running Android on core0 and QNX on core1 without any 
> problem as a proof of concept.
>
> A good example may be the support on this kind of application on the 
> Zynq: 
> http://www.wiki.xilinx.com/Multi-OS+Support+%28AMP+%26+Hypervisor%29
> This is also a Cortex A9 without the support of virtualization 
> extensions.
Thanks for sharing this info, I'll check it out. I come from the 
automotive industry where no one will allow running 2 OSes without 
hardware isolation, so this is how my opinion about AMP on imx6 was 
formed. And I agree that this actually isn't related with U-Boot itself 
other than just loading the payload and starting the extra cores.

Kind regards,
Nikolay

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[Pavel Machek]

On Sun 2014-06-22 17:09:28, Nikolay Dimitrov wrote:
> Hi Gabriel,
> 
> >This allows u-boot to load different OS or Bare Metal application on the
> >different cores of the i.MX6DQ.
> >For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
> 
> I think this explanation is a little misleading - if you run
> unmodified versions of Android & some RTOS, they will fight for the
> imx6 interrupt controller, power management and clocks. As far as I
> know, imx6 is not appropriate for AMP (asymmetric multi-processing)
> because it doesn't support virtualization extensions.

I did AMP configuration on socfpga (similar to i.mx6 in this
regard). Yes, Linux needs to be modified for this to work... but it
seems mostly unmodified u-boot can be used.

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[gabriel huau]

Agreed, I'll submit a patch to fix that.

Regards,
Gabriel

On 06/22/2014 02:14 AM, Jeroen Hofstee wrote:
> Hello Gabriel,
>
> On 22-06-14 01:55, Gabriel Huau wrote:
>> This allows u-boot to load different OS or Bare Metal application on the
>> different cores of the i.MX6DQ.
>> For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS 
>> on cpu1.
>>
>> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> funny..
>> +int is_core_valid(unsigned int nr)
>> +{
>> +    if (nr < 0 || nr >= CONFIG_NUM_CPUS)
>> +        return 0;
>> +
>> +    return 1;
>> +}
>> +
>>
> I am not sure if u-boot has rules for it, but personally I would prefer
> not to test values which are obvious unsigned for negativity, since it
> causes unnecessary noise when compiling u-boot with W=1, W=2.
>
> Regards,
> Jeroen
>
>

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[Jeroen Hofstee]

Hello Gabriel,

On 22-06-14 01:55, Gabriel Huau wrote:
> This allows u-boot to load different OS or Bare Metal application on the
> different cores of the i.MX6DQ.
> For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
funny..
> +int is_core_valid(unsigned int nr)
> +{
> +	if (nr < 0 || nr >= CONFIG_NUM_CPUS)
> +		return 0;
> +
> +	return 1;
> +}
> +
>
I am not sure if u-boot has rules for it, but personally I would prefer
not to test values which are obvious unsigned for negativity, since it
causes unnecessary noise when compiling u-boot with W=1, W=2.

Regards,
Jeroen

[U-Boot] [PATCH v2] mx6: add support of multi-processor command

[Gabriel Huau]

This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
 arch/arm/cpu/armv7/mx6/Makefile          |   1 +
 arch/arm/cpu/armv7/mx6/mp.c              | 131 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h |  13 +++
 3 files changed, 145 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/mx6/mp.c

diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
 
 obj-y	:= soc.o clock.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
+obj-$(CONFIG_MP)             += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 0000000..a805be8
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+
+int cpu_reset(int nr)
+{
+	uint32_t reg;
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+
+	reg = __raw_readl(&src->scr);
+
+	switch (nr) {
+	case 1:
+		reg |= SRC_SCR_CORE_1_RESET_MASK;
+		break;
+
+	case 2:
+		reg |= SRC_SCR_CORE_2_RESET_MASK;
+		break;
+
+	case 3:
+		reg |= SRC_SCR_CORE_3_RESET_MASK;
+		break;
+	}
+
+	/* Software reset of the CPU N */
+	__raw_writel(reg, &src->scr);
+
+	return 0;
+}
+
+int cpu_status(int nr)
+{
+	uint32_t reg;
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+
+	reg = __raw_readl(&src->scr);
+
+	switch (nr) {
+	case 1:
+		printf("core 1: %d\n", !!(reg & SRC_SCR_CORE_1_ENABLE_MASK));
+		break;
+
+	case 2:
+		printf("core 2: %d\n", !!(reg & SRC_SCR_CORE_2_ENABLE_MASK));
+		break;
+
+	case 3:
+		printf("core 3: %d\n", !!(reg & SRC_SCR_CORE_3_ENABLE_MASK));
+		break;
+	}
+
+	return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+	uint32_t reg;
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+	uint32_t boot_addr;
+
+	boot_addr = simple_strtoul(argv[0], NULL, 16);
+	reg = __raw_readl(&src->scr);
+
+	switch (nr) {
+	case 1:
+		__raw_writel(boot_addr, &src->gpr3);
+		reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+		break;
+
+	case 2:
+		__raw_writel(boot_addr, &src->gpr5);
+		reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+		break;
+
+	case 3:
+		__raw_writel(boot_addr, &src->gpr7);
+		reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+		break;
+	}
+
+	/* CPU N is ready to start */
+	__raw_writel(reg, &src->scr);
+
+	return 0;
+}
+
+int is_core_valid(unsigned int nr)
+{
+	if (nr < 0 || nr >= CONFIG_NUM_CPUS)
+		return 0;
+
+	return 1;
+}
+
+int cpu_disable(int nr)
+{
+	uint32_t reg;
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+
+	reg = __raw_readl(&src->scr);
+
+	switch (nr) {
+	case 1:
+		reg &= ~SRC_SCR_CORE_1_ENABLE_MASK;
+		break;
+
+	case 2:
+		reg &= ~SRC_SCR_CORE_2_ENABLE_MASK;
+		break;
+
+	case 3:
+		reg &= ~SRC_SCR_CORE_3_ENABLE_MASK;
+		break;
+	}
+
+	/* Disable the CPU N */
+	__raw_writel(reg, &src->scr);
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..3f8c2ee 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -225,6 +225,19 @@
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 
+#define SRC_SCR_CORE_1_RESET_OFFSET     14
+#define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET     15
+#define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET     16
+#define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET    22
+#define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET    23
+#define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET    24
+#define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+
 /* System Reset Controller (SRC) */
 struct src {
 	u32	scr;
-- 
2.0.0