* [PATCHv2 0/3] iio: adc: exynos_adc: Add support for s3c64xx/s3c24xx ADC
@ 2014-07-28 12:43 ` Chanwoo Choi
0 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:43 UTC (permalink / raw)
To: jic23
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc, Chanwoo Choi
This patch add support for s3c64xx/s3c24xx ADC. s3c64xx/s3c24xx is alomost same
as ADCv1. But, s3c64xx/s3c24xx has a little difference from ADCv1 as following:
- ADCMUX register address to select channel
- ADCDAT mask (10bit or 12bit ADC resolution according to SoC version)
- s3c24xx/s3c64xx has not included ADC_PHY enable register
Changes from v1:
- Fix minor coding style.
- Remove the sentence which reading DATY register.
- Add ARCH_S3C24XX / ARCH_S3C64XX dependency for EXYNOS_ADC to Kconfig.
- Remove the function pointer of 'clear_irq' for s3c24xx becase s3c24xx
has not included ADC_V1_INTCLR register.
- Remove un-necessary white-space in dt-binding documentation
Arnd Bergmann (1):
iio: adc: exynos_adc: add support for s3c64xx adc
Chanwoo Choi (2):
iio: adc: exynos_adc: Add support for s3c24xx ADC
dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 20 ++-
drivers/iio/adc/Kconfig | 2 +-
drivers/iio/adc/exynos_adc.c | 137 +++++++++++++++++++--
3 files changed, 144 insertions(+), 15 deletions(-)
--
1.8.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 0/3] iio: adc: exynos_adc: Add support for s3c64xx/s3c24xx ADC
@ 2014-07-28 12:43 ` Chanwoo Choi
0 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:43 UTC (permalink / raw)
To: linux-arm-kernel
This patch add support for s3c64xx/s3c24xx ADC. s3c64xx/s3c24xx is alomost same
as ADCv1. But, s3c64xx/s3c24xx has a little difference from ADCv1 as following:
- ADCMUX register address to select channel
- ADCDAT mask (10bit or 12bit ADC resolution according to SoC version)
- s3c24xx/s3c64xx has not included ADC_PHY enable register
Changes from v1:
- Fix minor coding style.
- Remove the sentence which reading DATY register.
- Add ARCH_S3C24XX / ARCH_S3C64XX dependency for EXYNOS_ADC to Kconfig.
- Remove the function pointer of 'clear_irq' for s3c24xx becase s3c24xx
has not included ADC_V1_INTCLR register.
- Remove un-necessary white-space in dt-binding documentation
Arnd Bergmann (1):
iio: adc: exynos_adc: add support for s3c64xx adc
Chanwoo Choi (2):
iio: adc: exynos_adc: Add support for s3c24xx ADC
dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 20 ++-
drivers/iio/adc/Kconfig | 2 +-
drivers/iio/adc/exynos_adc.c | 137 +++++++++++++++++++--
3 files changed, 144 insertions(+), 15 deletions(-)
--
1.8.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 1/3] iio: adc: exynos_adc: add support for s3c64xx adc
2014-07-28 12:43 ` Chanwoo Choi
@ 2014-07-28 12:44 ` Chanwoo Choi
-1 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: jic23
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc, Chanwoo Choi
From: Arnd Bergmann <arnd@arndb.de>
The ADC in s3c64xx is almost the same as exynosv1, but
has a different 'select' method. Adding this here will be
helpful to move over the existing s3c64xx platform from the
legacy plat-samsung/adc driver to the new exynos-adc.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 2 ++
drivers/iio/adc/exynos_adc.c | 28 +++++++++++++++++++++-
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index adc61b0..d3dad46 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -16,6 +16,8 @@ Required properties:
future controllers.
Must be "samsung,exynos3250-adc" for
controllers compatible with ADC of Exynos3250.
+ Must be "samsung,s3c6410-adc" for
+ the ADC in s3c6410 and compatibles
- reg: Contains ADC register address range (base address and
length) and the address of the phy enable register.
- interrupts: Contains the interrupt information for the timer. The
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 87e0895..ed9e4c8 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -40,7 +40,7 @@
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
-/* EXYNOS4412/5250 ADC_V1 registers definitions */
+/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
#define ADC_V1_DLY(x) ((x) + 0x08)
#define ADC_V1_DATX(x) ((x) + 0x0C)
@@ -61,6 +61,9 @@
#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
#define ADC_V1_CON_STANDBY (1u << 2)
+/* Bit definitions for S3C2410 ADC */
+#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
+
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
@@ -217,6 +220,26 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
.start_conv = exynos_adc_v1_start_conv,
};
+static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
+ con1 |= ADC_S3C2410_CON_SELMUX(addr);
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .clear_irq = exynos_adc_v1_clear_irq,
+ .start_conv = exynos_adc_s3c64xx_start_conv,
+};
+
static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
@@ -285,6 +308,9 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
static const struct of_device_id exynos_adc_match[] = {
{
+ .compatible = "samsung,s3c6410-adc",
+ .data = &exynos_adc_s3c64xx_data,
+ }, {
.compatible = "samsung,exynos-adc-v1",
.data = &exynos_adc_v1_data,
}, {
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 1/3] iio: adc: exynos_adc: add support for s3c64xx adc
@ 2014-07-28 12:44 ` Chanwoo Choi
0 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Arnd Bergmann <arnd@arndb.de>
The ADC in s3c64xx is almost the same as exynosv1, but
has a different 'select' method. Adding this here will be
helpful to move over the existing s3c64xx platform from the
legacy plat-samsung/adc driver to the new exynos-adc.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 2 ++
drivers/iio/adc/exynos_adc.c | 28 +++++++++++++++++++++-
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index adc61b0..d3dad46 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -16,6 +16,8 @@ Required properties:
future controllers.
Must be "samsung,exynos3250-adc" for
controllers compatible with ADC of Exynos3250.
+ Must be "samsung,s3c6410-adc" for
+ the ADC in s3c6410 and compatibles
- reg: Contains ADC register address range (base address and
length) and the address of the phy enable register.
- interrupts: Contains the interrupt information for the timer. The
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 87e0895..ed9e4c8 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -40,7 +40,7 @@
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
-/* EXYNOS4412/5250 ADC_V1 registers definitions */
+/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
#define ADC_V1_DLY(x) ((x) + 0x08)
#define ADC_V1_DATX(x) ((x) + 0x0C)
@@ -61,6 +61,9 @@
#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
#define ADC_V1_CON_STANDBY (1u << 2)
+/* Bit definitions for S3C2410 ADC */
+#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
+
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
@@ -217,6 +220,26 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
.start_conv = exynos_adc_v1_start_conv,
};
+static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
+ con1 |= ADC_S3C2410_CON_SELMUX(addr);
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .clear_irq = exynos_adc_v1_clear_irq,
+ .start_conv = exynos_adc_s3c64xx_start_conv,
+};
+
static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
@@ -285,6 +308,9 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
static const struct of_device_id exynos_adc_match[] = {
{
+ .compatible = "samsung,s3c6410-adc",
+ .data = &exynos_adc_s3c64xx_data,
+ }, {
.compatible = "samsung,exynos-adc-v1",
.data = &exynos_adc_v1_data,
}, {
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 2/3] iio: adc: exynos_adc: Add support for s3c24xx ADC
2014-07-28 12:43 ` Chanwoo Choi
@ 2014-07-28 12:44 ` Chanwoo Choi
-1 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: jic23
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc, Chanwoo Choi
This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx
is alomost same as ADCv1. But, There are a little difference as following:
- ADCMUX register address
- ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version)
- s3c24xx/s3c64xx has not included ADC_PHY enable register
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 16 ++-
drivers/iio/adc/Kconfig | 2 +-
drivers/iio/adc/exynos_adc.c | 109 +++++++++++++++++++--
3 files changed, 114 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index d3dad46..709efaa 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -11,15 +11,25 @@ New driver handles the following
Required properties:
- compatible: Must be "samsung,exynos-adc-v1"
- for exynos4412/5250 controllers.
+ for exynos4412/5250 and s5pv210 controllers.
Must be "samsung,exynos-adc-v2" for
future controllers.
Must be "samsung,exynos3250-adc" for
controllers compatible with ADC of Exynos3250.
+ Must be "samsung,s3c2410-adc" for
+ the ADC in s3c2410 and compatibles
+ Must be "samsung,s3c2416-adc" for
+ the ADC in s3c2416 and compatibles
+ Must be "samsung,s3c2440-adc" for
+ the ADC in s3c2440 and compatibles
+ Must be "samsung,s3c2443-adc" for
+ the ADC in s3c2443 and compatibles
Must be "samsung,s3c6410-adc" for
the ADC in s3c6410 and compatibles
-- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
+- reg: List of ADC register address range
+ - The base address and range of ADC register
+ - The base address and range of ADC_PHY register (every
+ SoC except for s3c24xx/s3c64xx ADC)
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index a80d236..a247655 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -119,7 +119,7 @@ config AT91_ADC
config EXYNOS_ADC
tristate "Exynos ADC driver support"
- depends on ARCH_EXYNOS || (OF && COMPILE_TEST)
+ depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || (OF && COMPILE_TEST)
help
Core support for the ADC block found in the Samsung EXYNOS series
of SoCs for drivers such as the touchscreen and hwmon to use to share
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index ed9e4c8..3b17faa 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -47,6 +47,9 @@
#define ADC_V1_INTCLR(x) ((x) + 0x18)
#define ADC_V1_MUX(x) ((x) + 0x1c)
+/* S3C2410 ADC registers definitions */
+#define ADC_S3C2410_MUX(x) ((x) + 0x18)
+
/* Future ADC_V2 registers definitions */
#define ADC_V2_CON1(x) ((x) + 0x00)
#define ADC_V2_CON2(x) ((x) + 0x04)
@@ -63,6 +66,8 @@
/* Bit definitions for S3C2410 ADC */
#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
+#define ADC_S3C2410_DATX_MASK 0x3FF
+#define ADC_S3C2416_CON_RES_SEL (1u << 3)
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
@@ -80,6 +85,7 @@
/* Bit definitions common for ADC_V1 and ADC_V2 */
#define ADC_CON_EN_START (1u << 0)
+#define ADC_CON_EN_START_MASK (0x3 << 0)
#define ADC_DATX_MASK 0xFFF
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
@@ -103,6 +109,8 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ bool needs_adc_phy;
+ u32 mask;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -174,7 +182,8 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(1, info->enable_reg);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -188,7 +197,8 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(0, info->enable_reg);
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
@@ -213,6 +223,8 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
static const struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
@@ -220,6 +232,53 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
.start_conv = exynos_adc_v1_start_conv,
};
+static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ /* Enable 12 bit ADC resolution */
+ con1 = readl(ADC_V1_CON(info->regs));
+ con1 |= ADC_S3C2416_CON_RES_SEL;
+ writel(con1, ADC_V1_CON(info->regs));
+
+ /* Select channel for S3C2416 */
+ writel(addr, ADC_S3C2410_MUX(info->regs));
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c2416_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c2416_start_conv,
+};
+
+static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ /* Select channel for S3C2433 */
+ writel(addr, ADC_S3C2410_MUX(info->regs));
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c2443_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c2443_start_conv,
+};
+
static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
unsigned long addr)
{
@@ -231,8 +290,18 @@ static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
+static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c64xx_start_conv,
+};
+
static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
@@ -244,7 +313,8 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(1, info->enable_reg);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
@@ -261,7 +331,8 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(0, info->enable_reg);
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
@@ -289,6 +360,8 @@ static void exynos_adc_v2_start_conv(struct exynos_adc *info,
static const struct exynos_adc_data const exynos_adc_v2_data = {
.num_channels = MAX_ADC_V2_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
@@ -298,7 +371,9 @@ static const struct exynos_adc_data const exynos_adc_v2_data = {
static const struct exynos_adc_data const exynos3250_adc_data = {
.num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_sclk = true,
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
@@ -308,6 +383,18 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
static const struct of_device_id exynos_adc_match[] = {
{
+ .compatible = "samsung,s3c2410-adc",
+ .data = &exynos_adc_s3c24xx_data,
+ }, {
+ .compatible = "samsung,s3c2416-adc",
+ .data = &exynos_adc_s3c2416_data,
+ }, {
+ .compatible = "samsung,s3c2440-adc",
+ .data = &exynos_adc_s3c24xx_data,
+ }, {
+ .compatible = "samsung,s3c2443-adc",
+ .data = &exynos_adc_s3c2443_data,
+ }, {
.compatible = "samsung,s3c6410-adc",
.data = &exynos_adc_s3c64xx_data,
}, {
@@ -373,9 +460,10 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
{
struct exynos_adc *info = (struct exynos_adc *)dev_id;
+ u32 mask = info->data->mask;
/* Read value */
- info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
+ info->value = readl(ADC_V1_DATX(info->regs)) & mask;
/* clear irq */
if (info->data->clear_irq)
@@ -468,10 +556,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(info->enable_reg))
- return PTR_ERR(info->enable_reg);
+
+ if (info->data->needs_adc_phy) {
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(info->enable_reg))
+ return PTR_ERR(info->enable_reg);
+ }
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 2/3] iio: adc: exynos_adc: Add support for s3c24xx ADC
@ 2014-07-28 12:44 ` Chanwoo Choi
0 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: linux-arm-kernel
This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx
is alomost same as ADCv1. But, There are a little difference as following:
- ADCMUX register address
- ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version)
- s3c24xx/s3c64xx has not included ADC_PHY enable register
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 16 ++-
drivers/iio/adc/Kconfig | 2 +-
drivers/iio/adc/exynos_adc.c | 109 +++++++++++++++++++--
3 files changed, 114 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index d3dad46..709efaa 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -11,15 +11,25 @@ New driver handles the following
Required properties:
- compatible: Must be "samsung,exynos-adc-v1"
- for exynos4412/5250 controllers.
+ for exynos4412/5250 and s5pv210 controllers.
Must be "samsung,exynos-adc-v2" for
future controllers.
Must be "samsung,exynos3250-adc" for
controllers compatible with ADC of Exynos3250.
+ Must be "samsung,s3c2410-adc" for
+ the ADC in s3c2410 and compatibles
+ Must be "samsung,s3c2416-adc" for
+ the ADC in s3c2416 and compatibles
+ Must be "samsung,s3c2440-adc" for
+ the ADC in s3c2440 and compatibles
+ Must be "samsung,s3c2443-adc" for
+ the ADC in s3c2443 and compatibles
Must be "samsung,s3c6410-adc" for
the ADC in s3c6410 and compatibles
-- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
+- reg: List of ADC register address range
+ - The base address and range of ADC register
+ - The base address and range of ADC_PHY register (every
+ SoC except for s3c24xx/s3c64xx ADC)
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index a80d236..a247655 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -119,7 +119,7 @@ config AT91_ADC
config EXYNOS_ADC
tristate "Exynos ADC driver support"
- depends on ARCH_EXYNOS || (OF && COMPILE_TEST)
+ depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || (OF && COMPILE_TEST)
help
Core support for the ADC block found in the Samsung EXYNOS series
of SoCs for drivers such as the touchscreen and hwmon to use to share
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index ed9e4c8..3b17faa 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -47,6 +47,9 @@
#define ADC_V1_INTCLR(x) ((x) + 0x18)
#define ADC_V1_MUX(x) ((x) + 0x1c)
+/* S3C2410 ADC registers definitions */
+#define ADC_S3C2410_MUX(x) ((x) + 0x18)
+
/* Future ADC_V2 registers definitions */
#define ADC_V2_CON1(x) ((x) + 0x00)
#define ADC_V2_CON2(x) ((x) + 0x04)
@@ -63,6 +66,8 @@
/* Bit definitions for S3C2410 ADC */
#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
+#define ADC_S3C2410_DATX_MASK 0x3FF
+#define ADC_S3C2416_CON_RES_SEL (1u << 3)
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
@@ -80,6 +85,7 @@
/* Bit definitions common for ADC_V1 and ADC_V2 */
#define ADC_CON_EN_START (1u << 0)
+#define ADC_CON_EN_START_MASK (0x3 << 0)
#define ADC_DATX_MASK 0xFFF
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
@@ -103,6 +109,8 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ bool needs_adc_phy;
+ u32 mask;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -174,7 +182,8 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(1, info->enable_reg);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -188,7 +197,8 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(0, info->enable_reg);
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
@@ -213,6 +223,8 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
static const struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
@@ -220,6 +232,53 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
.start_conv = exynos_adc_v1_start_conv,
};
+static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ /* Enable 12 bit ADC resolution */
+ con1 = readl(ADC_V1_CON(info->regs));
+ con1 |= ADC_S3C2416_CON_RES_SEL;
+ writel(con1, ADC_V1_CON(info->regs));
+
+ /* Select channel for S3C2416 */
+ writel(addr, ADC_S3C2410_MUX(info->regs));
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c2416_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c2416_start_conv,
+};
+
+static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
+ unsigned long addr)
+{
+ u32 con1;
+
+ /* Select channel for S3C2433 */
+ writel(addr, ADC_S3C2410_MUX(info->regs));
+
+ con1 = readl(ADC_V1_CON(info->regs));
+ writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_s3c2443_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c2443_start_conv,
+};
+
static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
unsigned long addr)
{
@@ -231,8 +290,18 @@ static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
+static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
+ .num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
+
+ .init_hw = exynos_adc_v1_init_hw,
+ .exit_hw = exynos_adc_v1_exit_hw,
+ .start_conv = exynos_adc_s3c64xx_start_conv,
+};
+
static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
@@ -244,7 +313,8 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(1, info->enable_reg);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
@@ -261,7 +331,8 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ if (info->data->needs_adc_phy)
+ writel(0, info->enable_reg);
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
@@ -289,6 +360,8 @@ static void exynos_adc_v2_start_conv(struct exynos_adc *info,
static const struct exynos_adc_data const exynos_adc_v2_data = {
.num_channels = MAX_ADC_V2_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
@@ -298,7 +371,9 @@ static const struct exynos_adc_data const exynos_adc_v2_data = {
static const struct exynos_adc_data const exynos3250_adc_data = {
.num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_sclk = true,
+ .needs_adc_phy = true,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
@@ -308,6 +383,18 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
static const struct of_device_id exynos_adc_match[] = {
{
+ .compatible = "samsung,s3c2410-adc",
+ .data = &exynos_adc_s3c24xx_data,
+ }, {
+ .compatible = "samsung,s3c2416-adc",
+ .data = &exynos_adc_s3c2416_data,
+ }, {
+ .compatible = "samsung,s3c2440-adc",
+ .data = &exynos_adc_s3c24xx_data,
+ }, {
+ .compatible = "samsung,s3c2443-adc",
+ .data = &exynos_adc_s3c2443_data,
+ }, {
.compatible = "samsung,s3c6410-adc",
.data = &exynos_adc_s3c64xx_data,
}, {
@@ -373,9 +460,10 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
{
struct exynos_adc *info = (struct exynos_adc *)dev_id;
+ u32 mask = info->data->mask;
/* Read value */
- info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
+ info->value = readl(ADC_V1_DATX(info->regs)) & mask;
/* clear irq */
if (info->data->clear_irq)
@@ -468,10 +556,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(info->enable_reg))
- return PTR_ERR(info->enable_reg);
+
+ if (info->data->needs_adc_phy) {
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(info->enable_reg))
+ return PTR_ERR(info->enable_reg);
+ }
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 3/3] dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
2014-07-28 12:43 ` Chanwoo Choi
@ 2014-07-28 12:44 ` Chanwoo Choi
-1 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: jic23
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc, Chanwoo Choi
This patch remove un-necessary white-sapce to code clean.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 709efaa..5ee0266 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -30,7 +30,7 @@ Required properties:
- The base address and range of ADC register
- The base address and range of ADC_PHY register (every
SoC except for s3c24xx/s3c64xx ADC)
-- interrupts: Contains the interrupt information for the timer. The
+- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
- #io-channel-cells = <1>; As ADC has multiple outputs
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 3/3] dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
@ 2014-07-28 12:44 ` Chanwoo Choi
0 siblings, 0 replies; 14+ messages in thread
From: Chanwoo Choi @ 2014-07-28 12:44 UTC (permalink / raw)
To: linux-arm-kernel
This patch remove un-necessary white-sapce to code clean.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 709efaa..5ee0266 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -30,7 +30,7 @@ Required properties:
- The base address and range of ADC register
- The base address and range of ADC_PHY register (every
SoC except for s3c24xx/s3c64xx ADC)
-- interrupts: Contains the interrupt information for the timer. The
+- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
- #io-channel-cells = <1>; As ADC has multiple outputs
--
1.8.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCHv2 1/3] iio: adc: exynos_adc: add support for s3c64xx adc
2014-07-28 12:44 ` Chanwoo Choi
@ 2014-08-07 16:51 ` Jonathan Cameron
-1 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:51 UTC (permalink / raw)
To: Chanwoo Choi
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc
On 28/07/14 13:44, Chanwoo Choi wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The ADC in s3c64xx is almost the same as exynosv1, but
> has a different 'select' method. Adding this here will be
> helpful to move over the existing s3c64xx platform from the
> legacy plat-samsung/adc driver to the new exynos-adc.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Applied to the togreg branch of iio.git. Initially pushed out as testing
for the autobuilders to play.
Thanks,
> ---
> .../devicetree/bindings/arm/samsung/exynos-adc.txt | 2 ++
> drivers/iio/adc/exynos_adc.c | 28 +++++++++++++++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index adc61b0..d3dad46 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -16,6 +16,8 @@ Required properties:
> future controllers.
> Must be "samsung,exynos3250-adc" for
> controllers compatible with ADC of Exynos3250.
> + Must be "samsung,s3c6410-adc" for
> + the ADC in s3c6410 and compatibles
> - reg: Contains ADC register address range (base address and
> length) and the address of the phy enable register.
> - interrupts: Contains the interrupt information for the timer. The
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index 87e0895..ed9e4c8 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -40,7 +40,7 @@
> #include <linux/iio/machine.h>
> #include <linux/iio/driver.h>
>
> -/* EXYNOS4412/5250 ADC_V1 registers definitions */
> +/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
> #define ADC_V1_CON(x) ((x) + 0x00)
> #define ADC_V1_DLY(x) ((x) + 0x08)
> #define ADC_V1_DATX(x) ((x) + 0x0C)
> @@ -61,6 +61,9 @@
> #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
> #define ADC_V1_CON_STANDBY (1u << 2)
>
> +/* Bit definitions for S3C2410 ADC */
> +#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
> +
> /* Bit definitions for ADC_V2 */
> #define ADC_V2_CON1_SOFT_RESET (1u << 2)
>
> @@ -217,6 +220,26 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
> .start_conv = exynos_adc_v1_start_conv,
> };
>
> +static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
> + con1 |= ADC_S3C2410_CON_SELMUX(addr);
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .clear_irq = exynos_adc_v1_clear_irq,
> + .start_conv = exynos_adc_s3c64xx_start_conv,
> +};
> +
> static void exynos_adc_v2_init_hw(struct exynos_adc *info)
> {
> u32 con1, con2;
> @@ -285,6 +308,9 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
>
> static const struct of_device_id exynos_adc_match[] = {
> {
> + .compatible = "samsung,s3c6410-adc",
> + .data = &exynos_adc_s3c64xx_data,
> + }, {
> .compatible = "samsung,exynos-adc-v1",
> .data = &exynos_adc_v1_data,
> }, {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 1/3] iio: adc: exynos_adc: add support for s3c64xx adc
@ 2014-08-07 16:51 ` Jonathan Cameron
0 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:51 UTC (permalink / raw)
To: linux-arm-kernel
On 28/07/14 13:44, Chanwoo Choi wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The ADC in s3c64xx is almost the same as exynosv1, but
> has a different 'select' method. Adding this here will be
> helpful to move over the existing s3c64xx platform from the
> legacy plat-samsung/adc driver to the new exynos-adc.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Applied to the togreg branch of iio.git. Initially pushed out as testing
for the autobuilders to play.
Thanks,
> ---
> .../devicetree/bindings/arm/samsung/exynos-adc.txt | 2 ++
> drivers/iio/adc/exynos_adc.c | 28 +++++++++++++++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index adc61b0..d3dad46 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -16,6 +16,8 @@ Required properties:
> future controllers.
> Must be "samsung,exynos3250-adc" for
> controllers compatible with ADC of Exynos3250.
> + Must be "samsung,s3c6410-adc" for
> + the ADC in s3c6410 and compatibles
> - reg: Contains ADC register address range (base address and
> length) and the address of the phy enable register.
> - interrupts: Contains the interrupt information for the timer. The
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index 87e0895..ed9e4c8 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -40,7 +40,7 @@
> #include <linux/iio/machine.h>
> #include <linux/iio/driver.h>
>
> -/* EXYNOS4412/5250 ADC_V1 registers definitions */
> +/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
> #define ADC_V1_CON(x) ((x) + 0x00)
> #define ADC_V1_DLY(x) ((x) + 0x08)
> #define ADC_V1_DATX(x) ((x) + 0x0C)
> @@ -61,6 +61,9 @@
> #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
> #define ADC_V1_CON_STANDBY (1u << 2)
>
> +/* Bit definitions for S3C2410 ADC */
> +#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
> +
> /* Bit definitions for ADC_V2 */
> #define ADC_V2_CON1_SOFT_RESET (1u << 2)
>
> @@ -217,6 +220,26 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
> .start_conv = exynos_adc_v1_start_conv,
> };
>
> +static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
> + con1 |= ADC_S3C2410_CON_SELMUX(addr);
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .clear_irq = exynos_adc_v1_clear_irq,
> + .start_conv = exynos_adc_s3c64xx_start_conv,
> +};
> +
> static void exynos_adc_v2_init_hw(struct exynos_adc *info)
> {
> u32 con1, con2;
> @@ -285,6 +308,9 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
>
> static const struct of_device_id exynos_adc_match[] = {
> {
> + .compatible = "samsung,s3c6410-adc",
> + .data = &exynos_adc_s3c64xx_data,
> + }, {
> .compatible = "samsung,exynos-adc-v1",
> .data = &exynos_adc_v1_data,
> }, {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 2/3] iio: adc: exynos_adc: Add support for s3c24xx ADC
2014-07-28 12:44 ` Chanwoo Choi
@ 2014-08-07 16:51 ` Jonathan Cameron
-1 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:51 UTC (permalink / raw)
To: Chanwoo Choi
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc
On 28/07/14 13:44, Chanwoo Choi wrote:
> This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx
> is alomost same as ADCv1. But, There are a little difference as following:
> - ADCMUX register address
> - ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version)
> - s3c24xx/s3c64xx has not included ADC_PHY enable register
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
Applied - with a little bit of fuzz and pushed out as testing for the autobuilders
to play with it.
Thanks
Jonathan
> ---
> .../devicetree/bindings/arm/samsung/exynos-adc.txt | 16 ++-
> drivers/iio/adc/Kconfig | 2 +-
> drivers/iio/adc/exynos_adc.c | 109 +++++++++++++++++++--
> 3 files changed, 114 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index d3dad46..709efaa 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -11,15 +11,25 @@ New driver handles the following
>
> Required properties:
> - compatible: Must be "samsung,exynos-adc-v1"
> - for exynos4412/5250 controllers.
> + for exynos4412/5250 and s5pv210 controllers.
> Must be "samsung,exynos-adc-v2" for
> future controllers.
> Must be "samsung,exynos3250-adc" for
> controllers compatible with ADC of Exynos3250.
> + Must be "samsung,s3c2410-adc" for
> + the ADC in s3c2410 and compatibles
> + Must be "samsung,s3c2416-adc" for
> + the ADC in s3c2416 and compatibles
> + Must be "samsung,s3c2440-adc" for
> + the ADC in s3c2440 and compatibles
> + Must be "samsung,s3c2443-adc" for
> + the ADC in s3c2443 and compatibles
> Must be "samsung,s3c6410-adc" for
> the ADC in s3c6410 and compatibles
> -- reg: Contains ADC register address range (base address and
> - length) and the address of the phy enable register.
> +- reg: List of ADC register address range
> + - The base address and range of ADC register
> + - The base address and range of ADC_PHY register (every
> + SoC except for s3c24xx/s3c64xx ADC)
> - interrupts: Contains the interrupt information for the timer. The
> format is being dependent on which interrupt controller
> the Samsung device uses.
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index a80d236..a247655 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -119,7 +119,7 @@ config AT91_ADC
>
> config EXYNOS_ADC
> tristate "Exynos ADC driver support"
> - depends on ARCH_EXYNOS || (OF && COMPILE_TEST)
> + depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || (OF && COMPILE_TEST)
> help
> Core support for the ADC block found in the Samsung EXYNOS series
> of SoCs for drivers such as the touchscreen and hwmon to use to share
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index ed9e4c8..3b17faa 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -47,6 +47,9 @@
> #define ADC_V1_INTCLR(x) ((x) + 0x18)
> #define ADC_V1_MUX(x) ((x) + 0x1c)
>
> +/* S3C2410 ADC registers definitions */
> +#define ADC_S3C2410_MUX(x) ((x) + 0x18)
> +
> /* Future ADC_V2 registers definitions */
> #define ADC_V2_CON1(x) ((x) + 0x00)
> #define ADC_V2_CON2(x) ((x) + 0x04)
> @@ -63,6 +66,8 @@
>
> /* Bit definitions for S3C2410 ADC */
> #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
> +#define ADC_S3C2410_DATX_MASK 0x3FF
> +#define ADC_S3C2416_CON_RES_SEL (1u << 3)
>
> /* Bit definitions for ADC_V2 */
> #define ADC_V2_CON1_SOFT_RESET (1u << 2)
> @@ -80,6 +85,7 @@
>
> /* Bit definitions common for ADC_V1 and ADC_V2 */
> #define ADC_CON_EN_START (1u << 0)
> +#define ADC_CON_EN_START_MASK (0x3 << 0)
> #define ADC_DATX_MASK 0xFFF
>
> #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
> @@ -103,6 +109,8 @@ struct exynos_adc {
> struct exynos_adc_data {
> int num_channels;
> bool needs_sclk;
> + bool needs_adc_phy;
> + u32 mask;
>
> void (*init_hw)(struct exynos_adc *info);
> void (*exit_hw)(struct exynos_adc *info);
> @@ -174,7 +182,8 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
> {
> u32 con1;
>
> - writel(1, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(1, info->enable_reg);
>
> /* set default prescaler values and Enable prescaler */
> con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
> @@ -188,7 +197,8 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
> {
> u32 con;
>
> - writel(0, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(0, info->enable_reg);
>
> con = readl(ADC_V1_CON(info->regs));
> con |= ADC_V1_CON_STANDBY;
> @@ -213,6 +223,8 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
>
> static const struct exynos_adc_data const exynos_adc_v1_data = {
> .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v1_init_hw,
> .exit_hw = exynos_adc_v1_exit_hw,
> @@ -220,6 +232,53 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
> .start_conv = exynos_adc_v1_start_conv,
> };
>
> +static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + /* Enable 12 bit ADC resolution */
> + con1 = readl(ADC_V1_CON(info->regs));
> + con1 |= ADC_S3C2416_CON_RES_SEL;
> + writel(con1, ADC_V1_CON(info->regs));
> +
> + /* Select channel for S3C2416 */
> + writel(addr, ADC_S3C2410_MUX(info->regs));
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c2416_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c2416_start_conv,
> +};
> +
> +static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + /* Select channel for S3C2433 */
> + writel(addr, ADC_S3C2410_MUX(info->regs));
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c2443_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c2443_start_conv,
> +};
> +
> static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> unsigned long addr)
> {
> @@ -231,8 +290,18 @@ static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> }
>
> +static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c64xx_start_conv,
> +};
> +
> static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
> .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
>
> .init_hw = exynos_adc_v1_init_hw,
> .exit_hw = exynos_adc_v1_exit_hw,
> @@ -244,7 +313,8 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
> {
> u32 con1, con2;
>
> - writel(1, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(1, info->enable_reg);
>
> con1 = ADC_V2_CON1_SOFT_RESET;
> writel(con1, ADC_V2_CON1(info->regs));
> @@ -261,7 +331,8 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
> {
> u32 con;
>
> - writel(0, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(0, info->enable_reg);
>
> con = readl(ADC_V2_CON1(info->regs));
> con &= ~ADC_CON_EN_START;
> @@ -289,6 +360,8 @@ static void exynos_adc_v2_start_conv(struct exynos_adc *info,
>
> static const struct exynos_adc_data const exynos_adc_v2_data = {
> .num_channels = MAX_ADC_V2_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v2_init_hw,
> .exit_hw = exynos_adc_v2_exit_hw,
> @@ -298,7 +371,9 @@ static const struct exynos_adc_data const exynos_adc_v2_data = {
>
> static const struct exynos_adc_data const exynos3250_adc_data = {
> .num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> .needs_sclk = true,
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v2_init_hw,
> .exit_hw = exynos_adc_v2_exit_hw,
> @@ -308,6 +383,18 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
>
> static const struct of_device_id exynos_adc_match[] = {
> {
> + .compatible = "samsung,s3c2410-adc",
> + .data = &exynos_adc_s3c24xx_data,
> + }, {
> + .compatible = "samsung,s3c2416-adc",
> + .data = &exynos_adc_s3c2416_data,
> + }, {
> + .compatible = "samsung,s3c2440-adc",
> + .data = &exynos_adc_s3c24xx_data,
> + }, {
> + .compatible = "samsung,s3c2443-adc",
> + .data = &exynos_adc_s3c2443_data,
> + }, {
> .compatible = "samsung,s3c6410-adc",
> .data = &exynos_adc_s3c64xx_data,
> }, {
> @@ -373,9 +460,10 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
> static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
> {
> struct exynos_adc *info = (struct exynos_adc *)dev_id;
> + u32 mask = info->data->mask;
>
> /* Read value */
> - info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
> + info->value = readl(ADC_V1_DATX(info->regs)) & mask;
>
> /* clear irq */
> if (info->data->clear_irq)
> @@ -468,10 +556,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
> if (IS_ERR(info->regs))
> return PTR_ERR(info->regs);
>
> - mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
> - if (IS_ERR(info->enable_reg))
> - return PTR_ERR(info->enable_reg);
> +
> + if (info->data->needs_adc_phy) {
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
> + if (IS_ERR(info->enable_reg))
> + return PTR_ERR(info->enable_reg);
> + }
>
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 2/3] iio: adc: exynos_adc: Add support for s3c24xx ADC
@ 2014-08-07 16:51 ` Jonathan Cameron
0 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:51 UTC (permalink / raw)
To: linux-arm-kernel
On 28/07/14 13:44, Chanwoo Choi wrote:
> This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx
> is alomost same as ADCv1. But, There are a little difference as following:
> - ADCMUX register address
> - ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version)
> - s3c24xx/s3c64xx has not included ADC_PHY enable register
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
Applied - with a little bit of fuzz and pushed out as testing for the autobuilders
to play with it.
Thanks
Jonathan
> ---
> .../devicetree/bindings/arm/samsung/exynos-adc.txt | 16 ++-
> drivers/iio/adc/Kconfig | 2 +-
> drivers/iio/adc/exynos_adc.c | 109 +++++++++++++++++++--
> 3 files changed, 114 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index d3dad46..709efaa 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -11,15 +11,25 @@ New driver handles the following
>
> Required properties:
> - compatible: Must be "samsung,exynos-adc-v1"
> - for exynos4412/5250 controllers.
> + for exynos4412/5250 and s5pv210 controllers.
> Must be "samsung,exynos-adc-v2" for
> future controllers.
> Must be "samsung,exynos3250-adc" for
> controllers compatible with ADC of Exynos3250.
> + Must be "samsung,s3c2410-adc" for
> + the ADC in s3c2410 and compatibles
> + Must be "samsung,s3c2416-adc" for
> + the ADC in s3c2416 and compatibles
> + Must be "samsung,s3c2440-adc" for
> + the ADC in s3c2440 and compatibles
> + Must be "samsung,s3c2443-adc" for
> + the ADC in s3c2443 and compatibles
> Must be "samsung,s3c6410-adc" for
> the ADC in s3c6410 and compatibles
> -- reg: Contains ADC register address range (base address and
> - length) and the address of the phy enable register.
> +- reg: List of ADC register address range
> + - The base address and range of ADC register
> + - The base address and range of ADC_PHY register (every
> + SoC except for s3c24xx/s3c64xx ADC)
> - interrupts: Contains the interrupt information for the timer. The
> format is being dependent on which interrupt controller
> the Samsung device uses.
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index a80d236..a247655 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -119,7 +119,7 @@ config AT91_ADC
>
> config EXYNOS_ADC
> tristate "Exynos ADC driver support"
> - depends on ARCH_EXYNOS || (OF && COMPILE_TEST)
> + depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || (OF && COMPILE_TEST)
> help
> Core support for the ADC block found in the Samsung EXYNOS series
> of SoCs for drivers such as the touchscreen and hwmon to use to share
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index ed9e4c8..3b17faa 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -47,6 +47,9 @@
> #define ADC_V1_INTCLR(x) ((x) + 0x18)
> #define ADC_V1_MUX(x) ((x) + 0x1c)
>
> +/* S3C2410 ADC registers definitions */
> +#define ADC_S3C2410_MUX(x) ((x) + 0x18)
> +
> /* Future ADC_V2 registers definitions */
> #define ADC_V2_CON1(x) ((x) + 0x00)
> #define ADC_V2_CON2(x) ((x) + 0x04)
> @@ -63,6 +66,8 @@
>
> /* Bit definitions for S3C2410 ADC */
> #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
> +#define ADC_S3C2410_DATX_MASK 0x3FF
> +#define ADC_S3C2416_CON_RES_SEL (1u << 3)
>
> /* Bit definitions for ADC_V2 */
> #define ADC_V2_CON1_SOFT_RESET (1u << 2)
> @@ -80,6 +85,7 @@
>
> /* Bit definitions common for ADC_V1 and ADC_V2 */
> #define ADC_CON_EN_START (1u << 0)
> +#define ADC_CON_EN_START_MASK (0x3 << 0)
> #define ADC_DATX_MASK 0xFFF
>
> #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
> @@ -103,6 +109,8 @@ struct exynos_adc {
> struct exynos_adc_data {
> int num_channels;
> bool needs_sclk;
> + bool needs_adc_phy;
> + u32 mask;
>
> void (*init_hw)(struct exynos_adc *info);
> void (*exit_hw)(struct exynos_adc *info);
> @@ -174,7 +182,8 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
> {
> u32 con1;
>
> - writel(1, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(1, info->enable_reg);
>
> /* set default prescaler values and Enable prescaler */
> con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
> @@ -188,7 +197,8 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
> {
> u32 con;
>
> - writel(0, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(0, info->enable_reg);
>
> con = readl(ADC_V1_CON(info->regs));
> con |= ADC_V1_CON_STANDBY;
> @@ -213,6 +223,8 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
>
> static const struct exynos_adc_data const exynos_adc_v1_data = {
> .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v1_init_hw,
> .exit_hw = exynos_adc_v1_exit_hw,
> @@ -220,6 +232,53 @@ static const struct exynos_adc_data const exynos_adc_v1_data = {
> .start_conv = exynos_adc_v1_start_conv,
> };
>
> +static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + /* Enable 12 bit ADC resolution */
> + con1 = readl(ADC_V1_CON(info->regs));
> + con1 |= ADC_S3C2416_CON_RES_SEL;
> + writel(con1, ADC_V1_CON(info->regs));
> +
> + /* Select channel for S3C2416 */
> + writel(addr, ADC_S3C2410_MUX(info->regs));
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c2416_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c2416_start_conv,
> +};
> +
> +static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
> + unsigned long addr)
> +{
> + u32 con1;
> +
> + /* Select channel for S3C2433 */
> + writel(addr, ADC_S3C2410_MUX(info->regs));
> +
> + con1 = readl(ADC_V1_CON(info->regs));
> + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> +}
> +
> +static struct exynos_adc_data const exynos_adc_s3c2443_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c2443_start_conv,
> +};
> +
> static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> unsigned long addr)
> {
> @@ -231,8 +290,18 @@ static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
> writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
> }
>
> +static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
> + .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .start_conv = exynos_adc_s3c64xx_start_conv,
> +};
> +
> static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
> .num_channels = MAX_ADC_V1_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
>
> .init_hw = exynos_adc_v1_init_hw,
> .exit_hw = exynos_adc_v1_exit_hw,
> @@ -244,7 +313,8 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
> {
> u32 con1, con2;
>
> - writel(1, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(1, info->enable_reg);
>
> con1 = ADC_V2_CON1_SOFT_RESET;
> writel(con1, ADC_V2_CON1(info->regs));
> @@ -261,7 +331,8 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
> {
> u32 con;
>
> - writel(0, info->enable_reg);
> + if (info->data->needs_adc_phy)
> + writel(0, info->enable_reg);
>
> con = readl(ADC_V2_CON1(info->regs));
> con &= ~ADC_CON_EN_START;
> @@ -289,6 +360,8 @@ static void exynos_adc_v2_start_conv(struct exynos_adc *info,
>
> static const struct exynos_adc_data const exynos_adc_v2_data = {
> .num_channels = MAX_ADC_V2_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v2_init_hw,
> .exit_hw = exynos_adc_v2_exit_hw,
> @@ -298,7 +371,9 @@ static const struct exynos_adc_data const exynos_adc_v2_data = {
>
> static const struct exynos_adc_data const exynos3250_adc_data = {
> .num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> .needs_sclk = true,
> + .needs_adc_phy = true,
>
> .init_hw = exynos_adc_v2_init_hw,
> .exit_hw = exynos_adc_v2_exit_hw,
> @@ -308,6 +383,18 @@ static const struct exynos_adc_data const exynos3250_adc_data = {
>
> static const struct of_device_id exynos_adc_match[] = {
> {
> + .compatible = "samsung,s3c2410-adc",
> + .data = &exynos_adc_s3c24xx_data,
> + }, {
> + .compatible = "samsung,s3c2416-adc",
> + .data = &exynos_adc_s3c2416_data,
> + }, {
> + .compatible = "samsung,s3c2440-adc",
> + .data = &exynos_adc_s3c24xx_data,
> + }, {
> + .compatible = "samsung,s3c2443-adc",
> + .data = &exynos_adc_s3c2443_data,
> + }, {
> .compatible = "samsung,s3c6410-adc",
> .data = &exynos_adc_s3c64xx_data,
> }, {
> @@ -373,9 +460,10 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
> static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
> {
> struct exynos_adc *info = (struct exynos_adc *)dev_id;
> + u32 mask = info->data->mask;
>
> /* Read value */
> - info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
> + info->value = readl(ADC_V1_DATX(info->regs)) & mask;
>
> /* clear irq */
> if (info->data->clear_irq)
> @@ -468,10 +556,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
> if (IS_ERR(info->regs))
> return PTR_ERR(info->regs);
>
> - mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
> - if (IS_ERR(info->enable_reg))
> - return PTR_ERR(info->enable_reg);
> +
> + if (info->data->needs_adc_phy) {
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
> + if (IS_ERR(info->enable_reg))
> + return PTR_ERR(info->enable_reg);
> + }
>
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 3/3] dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
2014-07-28 12:44 ` Chanwoo Choi
@ 2014-08-07 16:52 ` Jonathan Cameron
-1 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:52 UTC (permalink / raw)
To: Chanwoo Choi
Cc: ch.naveen, arnd, kgene.kim, kyungmin.park, heiko, knaack.h,
t.figa, linux-iio, linux-samsung-soc, linux-kernel,
linux-arm-kernel, devicetree, linux-doc
On 28/07/14 13:44, Chanwoo Choi wrote:
> This patch remove un-necessary white-sapce to code clean.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Applied to the togreg branch of iio.git. Obviously this didn't
need to go through my tree, but as it is so trivial it might
as well do so.
J
> ---
> Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index 709efaa..5ee0266 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -30,7 +30,7 @@ Required properties:
> - The base address and range of ADC register
> - The base address and range of ADC_PHY register (every
> SoC except for s3c24xx/s3c64xx ADC)
> -- interrupts: Contains the interrupt information for the timer. The
> +- interrupts: Contains the interrupt information for the timer. The
> format is being dependent on which interrupt controller
> the Samsung device uses.
> - #io-channel-cells = <1>; As ADC has multiple outputs
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 3/3] dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce
@ 2014-08-07 16:52 ` Jonathan Cameron
0 siblings, 0 replies; 14+ messages in thread
From: Jonathan Cameron @ 2014-08-07 16:52 UTC (permalink / raw)
To: linux-arm-kernel
On 28/07/14 13:44, Chanwoo Choi wrote:
> This patch remove un-necessary white-sapce to code clean.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Applied to the togreg branch of iio.git. Obviously this didn't
need to go through my tree, but as it is so trivial it might
as well do so.
J
> ---
> Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> index 709efaa..5ee0266 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
> @@ -30,7 +30,7 @@ Required properties:
> - The base address and range of ADC register
> - The base address and range of ADC_PHY register (every
> SoC except for s3c24xx/s3c64xx ADC)
> -- interrupts: Contains the interrupt information for the timer. The
> +- interrupts: Contains the interrupt information for the timer. The
> format is being dependent on which interrupt controller
> the Samsung device uses.
> - #io-channel-cells = <1>; As ADC has multiple outputs
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2014-08-07 16:52 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-28 12:43 [PATCHv2 0/3] iio: adc: exynos_adc: Add support for s3c64xx/s3c24xx ADC Chanwoo Choi
2014-07-28 12:43 ` Chanwoo Choi
2014-07-28 12:44 ` [PATCHv2 1/3] iio: adc: exynos_adc: add support for s3c64xx adc Chanwoo Choi
2014-07-28 12:44 ` Chanwoo Choi
2014-08-07 16:51 ` Jonathan Cameron
2014-08-07 16:51 ` Jonathan Cameron
2014-07-28 12:44 ` [PATCHv2 2/3] iio: adc: exynos_adc: Add support for s3c24xx ADC Chanwoo Choi
2014-07-28 12:44 ` Chanwoo Choi
2014-08-07 16:51 ` Jonathan Cameron
2014-08-07 16:51 ` Jonathan Cameron
2014-07-28 12:44 ` [PATCHv2 3/3] dt-bindings: samsung: exynos_adc: Remove un-necessary white-sapce Chanwoo Choi
2014-07-28 12:44 ` Chanwoo Choi
2014-08-07 16:52 ` Jonathan Cameron
2014-08-07 16:52 ` Jonathan Cameron
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