* [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation
@ 2014-08-07 14:34 Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
` (14 more replies)
0 siblings, 15 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Hi,
my aim is to add Infineon's TriCore architecture to QEMU. This series of patches adds the target stubs, a basic testboard and a softmmu for system mode emulation. Furthermore it adds all the 16 bit long instructions of the architecture grouped by opcode format.
After this series of patches. Another one will follow, which adds a lot of the 32 bit long instructions.
All the best
Bastian
v3 -> v4:
- tricore_cpu_type_info changed to abstract.
- Change documentation of PSW_USB_AV and PSW_USB_SAV bit to only use bit 31.
- Change psw_read/_write to only use bit 31 for PSW_USB_AV and PSW_USB_SAV.
- Remove gen_calc_psw_sv, gen_calc_psw_av, gen_calc_psw_sav functions.
- Rename gen_add_i32 to gen_add_d.
- Remove psw calculation from ADD_A.
- Replace makro OP_COND with function gen_cond_add, gen_cond_addi.
- gen_shaci now uses only 32 bit tcg shifts and implments special case of exactly 32 bit long shift.
- gen_cond_add now sets V and AV bits conditionaly through temp registers.
- Rename gen_sub_i32 to gen_sub_d.
- Fix V bit calculation in gen_sub_d and gen_mul_i32s.
- helper_add/sub_ssov now uses sign extended arguments.
- Remove unnecessary temp register in gen_adds/_subs.
- Add missing break in gen_compute_branch at CALL insn.
- Replace movcond with setcond at RSUB insn.
- Add AV, SAV calculation to RSUB insn.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
target-tricore: Add instructions of SRC opcode format
target-tricore: Add instructions of SRR opcode format
target-tricore: Add instructions of SSR opcode format
target-tricore: Add instructions of SRRS and SLRO opcode format
target-tricore: Add instructions of SB opcode format
target-tricore: Add instructions of SBC and SBRN opcode format
target-tricore: Add instructions of SBR opcode format
target-tricore: Add instructions of SC opcode format
target-tricore: Add instructions of SLR, SSRO and SRO opcode format
target-tricore: Add instructions of SR opcode format
arch_init.c | 2 +
configure | 5 +
cpu-exec.c | 11 +-
cpus.c | 6 +
default-configs/tricore-softmmu.mak | 3 +
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 ++++
include/elf.h | 2 +
include/hw/tricore/tricore.h | 54 ++
include/sysemu/arch_init.h | 1 +
target-tricore/Makefile.objs | 1 +
target-tricore/cpu-qom.h | 71 ++
target-tricore/cpu.c | 191 +++++
target-tricore/cpu.h | 401 ++++++++++
target-tricore/helper.c | 144 ++++
target-tricore/helper.h | 25 +
target-tricore/op_helper.c | 392 ++++++++++
target-tricore/translate.c | 1222 ++++++++++++++++++++++++++++++
target-tricore/tricore-defs.h | 28 +
target-tricore/tricore-opcodes.h | 1406 +++++++++++++++++++++++++++++++++++
20 files changed, 4094 insertions(+), 1 deletion(-)
create mode 100644 default-configs/tricore-softmmu.mak
create mode 100644 hw/tricore/Makefile.objs
create mode 100644 hw/tricore/tricore_testboard.c
create mode 100644 include/hw/tricore/tricore.h
create mode 100644 target-tricore/Makefile.objs
create mode 100644 target-tricore/cpu-qom.h
create mode 100644 target-tricore/cpu.c
create mode 100644 target-tricore/cpu.h
create mode 100644 target-tricore/helper.c
create mode 100644 target-tricore/helper.h
create mode 100644 target-tricore/op_helper.c
create mode 100644 target-tricore/translate.c
create mode 100644 target-tricore/tricore-defs.h
create mode 100644 target-tricore/tricore-opcodes.h
--
2.0.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-08 2:28 ` Richard Henderson
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
` (13 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v3 -> v4:
- tricore_cpu_type_info changed to abstract.
- Change documentation of PSW_USB_AV and PSW_USB_SAV bit to only use bit 31.
- Change psw_read/_write to only use bit 31 for PSW_USB_AV and PSW_USB_SAV.
arch_init.c | 2 +
cpu-exec.c | 11 +-
cpus.c | 6 +
include/elf.h | 2 +
include/sysemu/arch_init.h | 1 +
target-tricore/Makefile.objs | 1 +
target-tricore/cpu-qom.h | 71 ++++++++
target-tricore/cpu.c | 191 ++++++++++++++++++++
target-tricore/cpu.h | 401 ++++++++++++++++++++++++++++++++++++++++++
target-tricore/helper.c | 92 ++++++++++
target-tricore/helper.h | 0
target-tricore/op_helper.c | 27 +++
target-tricore/translate.c | 100 +++++++++++
target-tricore/tricore-defs.h | 28 +++
14 files changed, 932 insertions(+), 1 deletion(-)
create mode 100644 target-tricore/Makefile.objs
create mode 100644 target-tricore/cpu-qom.h
create mode 100644 target-tricore/cpu.c
create mode 100644 target-tricore/cpu.h
create mode 100644 target-tricore/helper.c
create mode 100644 target-tricore/helper.h
create mode 100644 target-tricore/op_helper.c
create mode 100644 target-tricore/translate.c
create mode 100644 target-tricore/tricore-defs.h
diff --git a/arch_init.c b/arch_init.c
index 8ddaf35..29a5821 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -104,6 +104,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_XTENSA
#elif defined(TARGET_UNICORE32)
#define QEMU_ARCH QEMU_ARCH_UNICORE32
+#elif defined(TARGET_TRICORE)
+#define QEMU_ARCH QEMU_ARCH_TRICORE
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/cpu-exec.c b/cpu-exec.c
index 38e5f02..bcfa943 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -277,6 +277,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_CRIS)
#elif defined(TARGET_S390X)
#elif defined(TARGET_XTENSA)
+#elif defined(TARGET_TRICORE)
/* XXXXX */
#else
#error unsupported target CPU
@@ -327,7 +328,8 @@ int cpu_exec(CPUArchState *env)
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
- defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
+ defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || \
+ defined(TARGET_UNICORE32) || defined(TARGET_TRICORE)
if (interrupt_request & CPU_INTERRUPT_HALT) {
cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
cpu->halted = 1;
@@ -443,6 +445,12 @@ int cpu_exec(CPUArchState *env)
cc->do_interrupt(cpu);
next_tb = 0;
}
+#elif defined(TARGET_TRICORE)
+ if ((interrupt_request & CPU_INTERRUPT_HARD)) {
+ cc->do_interrupt(cpu);
+ next_tb = 0;
+ }
+
#elif defined(TARGET_OPENRISC)
{
int idx = -1;
@@ -724,6 +732,7 @@ int cpu_exec(CPUArchState *env)
| env->cc_dest | (env->cc_x << 4);
#elif defined(TARGET_MICROBLAZE)
#elif defined(TARGET_MIPS)
+#elif defined(TARGET_TRICORE)
#elif defined(TARGET_MOXIE)
#elif defined(TARGET_OPENRISC)
#elif defined(TARGET_SH4)
diff --git a/cpus.c b/cpus.c
index 5e7f2cf..3262c6b 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1342,6 +1342,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_MIPS)
MIPSCPU *mips_cpu = MIPS_CPU(cpu);
CPUMIPSState *env = &mips_cpu->env;
+#elif defined(TARGET_TRICORE)
+ TRICORECPU *tricore_cpu = TRICORE_CPU(cpu);
+ CPUTRICOREState *env = &tricore_cpu->env;
#endif
cpu_synchronize_state(cpu);
@@ -1366,6 +1369,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_MIPS)
info->value->has_PC = true;
info->value->PC = env->active_tc.PC;
+#elif defined(TARGET_TRICORE)
+ info->value->has_PC = true;
+ info->value->PC = env->PC;
#endif
/* XXX: waiting for the qapi to support GSList */
diff --git a/include/elf.h b/include/elf.h
index e88d52f..70107f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -92,6 +92,8 @@ typedef int64_t Elf64_Sxword;
#define EM_SPARCV9 43 /* SPARC v9 64-bit */
+#define EM_TRICORE 44 /* Infineon TriCore */
+
#define EM_IA_64 50 /* HP/Intel IA-64 */
#define EM_X86_64 62 /* AMD x86-64 */
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 182d48d..8939233 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -22,6 +22,7 @@ enum {
QEMU_ARCH_OPENRISC = 8192,
QEMU_ARCH_UNICORE32 = 0x4000,
QEMU_ARCH_MOXIE = 0x8000,
+ QEMU_ARCH_TRICORE = 0x10000,
};
extern const uint32_t arch_type;
diff --git a/target-tricore/Makefile.objs b/target-tricore/Makefile.objs
new file mode 100644
index 0000000..21e820d
--- /dev/null
+++ b/target-tricore/Makefile.objs
@@ -0,0 +1 @@
+obj-y += translate.o helper.o cpu.o op_helper.o
diff --git a/target-tricore/cpu-qom.h b/target-tricore/cpu-qom.h
new file mode 100644
index 0000000..c8d34f3
--- /dev/null
+++ b/target-tricore/cpu-qom.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_TRICORE_CPU_QOM_H
+#define QEMU_TRICORE_CPU_QOM_H
+
+#include "qom/cpu.h"
+
+
+#define TYPE_TRICORE_CPU "tricore-cpu"
+
+#define TRICORE_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(TRICORECPUClass, (klass), TYPE_TRICORE_CPU)
+#define TRICORE_CPU(obj) \
+ OBJECT_CHECK(TRICORECPU, (obj), TYPE_TRICORE_CPU)
+#define TRICORE_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(TRICORECPUClass, (obj), TYPE_TRICORE_CPU)
+
+typedef struct TRICORECPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+ void (*parent_reset)(CPUState *cpu);
+} TRICORECPUClass;
+
+/**
+ * TRICORECPU:
+ * @env: #CPUTRICOREState
+ *
+ * A TRICORE CPU.
+ */
+typedef struct TRICORECPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUTRICOREState env;
+} TRICORECPU;
+
+static inline TRICORECPU *tricore_env_get_cpu(CPUTRICOREState *env)
+{
+ return TRICORE_CPU(container_of(env, TRICORECPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(TRICORECPU, env)
+
+hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+void tricore_cpu_do_interrupt(CPUState *cpu);
+void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
+
+
+#endif /*QEMU_TRICORE_CPU_QOM_H */
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
new file mode 100644
index 0000000..c4b7ef8
--- /dev/null
+++ b/target-tricore/cpu.c
@@ -0,0 +1,191 @@
+/*
+ * TRICORE emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+
+static inline void set_feature(CPUTRICOREState *env, int feature)
+{
+ env->features |= 1ULL << feature;
+}
+
+static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+
+ env->PC = value & ~(target_ulong)1;
+}
+
+static void tricore_cpu_synchronize_from_tb(CPUState *cs,
+ TranslationBlock *tb)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+
+ env->PC = tb->pc;
+}
+
+static void tricore_cpu_reset(CPUState *s)
+{
+ TRICORECPU *cpu = TRICORE_CPU(s);
+ TRICORECPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
+ CPUTRICOREState *env = &cpu->env;
+
+ tcc->parent_reset(s);
+
+ tlb_flush(s, 1);
+
+ cpu_state_reset(env);
+}
+
+static bool tricore_cpu_has_work(CPUState *cs)
+{
+ return true;
+}
+
+static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ CPUState *cs = CPU(dev);
+ TRICORECPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
+
+ cpu_reset(cs);
+ qemu_init_vcpu(cs);
+
+ tcc->parent_realize(dev, errp);
+}
+
+
+static void tricore_cpu_initfn(Object *obj)
+{
+ CPUState *cs = CPU(obj);
+ TRICORECPU *cpu = TRICORE_CPU(obj);
+ CPUTRICOREState *env = &cpu->env;
+
+ cs->env_ptr = env;
+ cpu_exec_init(env);
+
+ if (tcg_enabled()) {
+ tricore_tcg_init();
+ }
+}
+
+static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+ char *typename;
+
+ if (!cpu_model) {
+ return NULL;
+ }
+
+ typename = g_strdup_printf("%s-" TYPE_TRICORE_CPU, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU) ||
+ object_class_is_abstract(oc)) {
+ return NULL;
+ }
+ return oc;
+}
+
+static void tc1796_initfn(Object *obj)
+{
+ TRICORECPU *cpu = TRICORE_CPU(obj);
+
+ set_feature(&cpu->env, TRICORE_FEATURE_13);
+}
+
+static void aurix_initfn(Object *obj)
+{
+ TRICORECPU *cpu = TRICORE_CPU(obj);
+
+ set_feature(&cpu->env, TRICORE_FEATURE_16);
+}
+
+typedef struct TRICORECPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+ void (*class_init)(ObjectClass *oc, void *data);
+} TRICORECPUInfo;
+
+static const TRICORECPUInfo tricore_cpus[] = {
+ { .name = "tc1796", .initfn = tc1796_initfn },
+ { .name = "aurix", .initfn = aurix_initfn }
+};
+
+static void tricore_cpu_class_init(ObjectClass *c, void *data)
+{
+ TRICORECPUClass *mcc = TRICORE_CPU_CLASS(c);
+ CPUClass *cc = CPU_CLASS(c);
+ DeviceClass *dc = DEVICE_CLASS(c);
+
+ mcc->parent_realize = dc->realize;
+ dc->realize = tricore_cpu_realizefn;
+
+ mcc->parent_reset = cc->reset;
+ cc->reset = tricore_cpu_reset;
+ cc->class_by_name = tricore_cpu_class_by_name;
+ cc->has_work = tricore_cpu_has_work;
+
+ cc->do_interrupt = tricore_cpu_do_interrupt;
+ cc->dump_state = tricore_cpu_dump_state;
+ cc->set_pc = tricore_cpu_set_pc;
+ cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
+
+}
+
+static void cpu_register(const TRICORECPUInfo *info)
+{
+ TypeInfo type_info = {
+ .parent = TYPE_TRICORE_CPU,
+ .instance_size = sizeof(TRICORECPU),
+ .instance_init = info->initfn,
+ .class_size = sizeof(TRICORECPUClass),
+ .class_init = info->class_init,
+ };
+
+ type_info.name = g_strdup_printf("%s-" TYPE_TRICORE_CPU, info->name);
+ type_register(&type_info);
+ g_free((void *)type_info.name);
+}
+
+static const TypeInfo tricore_cpu_type_info = {
+ .name = TYPE_TRICORE_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(TRICORECPU),
+ .instance_init = tricore_cpu_initfn,
+ .abstract = true,
+ .class_size = sizeof(TRICORECPUClass),
+ .class_init = tricore_cpu_class_init,
+};
+
+static void tricore_cpu_register_types(void)
+{
+ const TRICORECPUInfo *info = tricore_cpus;
+
+ type_register_static(&tricore_cpu_type_info);
+
+ while (info->name) {
+ cpu_register(info);
+ info++;
+ }
+}
+
+type_init(tricore_cpu_register_types)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
new file mode 100644
index 0000000..41dc5af
--- /dev/null
+++ b/target-tricore/cpu.h
@@ -0,0 +1,401 @@
+/*
+ * TRICORE emulation for qemu: main CPU struct.
+ *
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#if !defined(__TRICORE_CPU_H__)
+#define __TRICORE_CPU_H__
+
+#include "tricore-defs.h"
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
+
+#define ELF_MACHINE EM_TRICORE
+
+#define CPUArchState struct CPUTRICOREState
+
+struct CPUTRICOREState;
+
+#define TRICORE_CPU_IRQ 0
+#define TRICORE_CPU_FIQ 1
+struct tricore_boot_info;
+
+#define NB_MMU_MODES 3
+
+typedef struct tricore_def_t tricore_def_t;
+
+typedef struct CPUTRICOREState CPUTRICOREState;
+struct CPUTRICOREState {
+ /* GPR Register */
+ target_ulong gpr_a[16];
+ target_ulong gpr_d[16];
+ /* CSFR Register */
+#define MASK_PCXI_PCPN 0xff000000
+#define MASK_PCXI_PIE 0x00800000
+#define MASK_PCXI_UL 0x00400000
+#define MASK_PCXI_PCXS 0x000f0000
+#define MASK_PCXI_PCXO 0x0000ffff
+ target_ulong PCXI;
+#define MASK_PSW_USB 0xff000000
+#define MASK_USB_C 0x80000000
+#define MASK_USB_V 0x40000000
+#define MASK_USB_SV 0x20000000
+#define MASK_USB_AV 0x10000000
+#define MASK_USB_SAV 0x08000000
+#define MASK_PSW_PRS 0x00003000
+#define MASK_PSW_IO 0x00000c00
+#define MASK_PSW_IS 0x00000200
+#define MASK_PSW_GW 0x00000100
+#define MASK_PSW_CDE 0x00000080
+#define MASK_PSW_CDC 0x0000007f
+/* Frequently accessed PSW_USB bits are stored separately for efficiency.
+ This contains all the other bits. Use psw_{read,write} to access
+ the whole PSW. */
+ target_ulong PSW;
+
+ /* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+ */
+ target_ulong PSW_USB_C;
+ target_ulong PSW_USB_V;
+ target_ulong PSW_USB_SV;
+ target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
+ target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
+
+ target_ulong PC;
+#define MASK_SYSCON_PRO_TEN 0x2
+#define MASK_SYSCON_FCD_SF 0x1
+ target_ulong SYSCON;
+#define MASK_CPUID_MOD 0xffff0000
+#define MASK_CPUID_MOD_32B 0x0000ff00
+#define MASK_CPUID_REV 0x000000ff
+ target_ulong CPU_ID;
+ target_ulong BIV;
+ target_ulong BTV;
+ target_ulong ISP;
+#define MASK_ICR_PIPN 0x00ff0000
+#define MASK_ICR_IE 0x00000100
+#define MASK_ICR_CCPN 0x000000ff
+ target_ulong ICR;
+#define MASK_FCX_FCXS 0x000f0000
+#define MASK_FCX_FCXO 0x0000ffff
+ target_ulong FCX;
+#define MASK_LCX_LCXS 0x000f0000
+#define MASK_LCX_LCX0 0x0000ffff
+ target_ulong LCX;
+ target_ulong COMPAT;
+
+ /* Mem Protection Register */
+ target_ulong DPR0_0L;
+ target_ulong DPR0_0U;
+ target_ulong DPR0_1L;
+ target_ulong DPR0_1U;
+ target_ulong DPR0_2L;
+ target_ulong DPR0_2U;
+ target_ulong DPR0_3L;
+ target_ulong DPR0_3U;
+
+ target_ulong DPR1_0L;
+ target_ulong DPR1_0U;
+ target_ulong DPR1_1L;
+ target_ulong DPR1_1U;
+ target_ulong DPR1_2L;
+ target_ulong DPR1_2U;
+ target_ulong DPR1_3L;
+ target_ulong DPR1_3U;
+
+ target_ulong DPR2_0L;
+ target_ulong DPR2_0U;
+ target_ulong DPR2_1L;
+ target_ulong DPR2_1U;
+ target_ulong DPR2_2L;
+ target_ulong DPR2_2U;
+ target_ulong DPR2_3L;
+ target_ulong DPR2_3U;
+
+ target_ulong DPR3_0L;
+ target_ulong DPR3_0U;
+ target_ulong DPR3_1L;
+ target_ulong DPR3_1U;
+ target_ulong DPR3_2L;
+ target_ulong DPR3_2U;
+ target_ulong DPR3_3L;
+ target_ulong DPR3_3U;
+
+ target_ulong CPR0_0L;
+ target_ulong CPR0_0U;
+ target_ulong CPR0_1L;
+ target_ulong CPR0_1U;
+ target_ulong CPR0_2L;
+ target_ulong CPR0_2U;
+ target_ulong CPR0_3L;
+ target_ulong CPR0_3U;
+
+ target_ulong CPR1_0L;
+ target_ulong CPR1_0U;
+ target_ulong CPR1_1L;
+ target_ulong CPR1_1U;
+ target_ulong CPR1_2L;
+ target_ulong CPR1_2U;
+ target_ulong CPR1_3L;
+ target_ulong CPR1_3U;
+
+ target_ulong CPR2_0L;
+ target_ulong CPR2_0U;
+ target_ulong CPR2_1L;
+ target_ulong CPR2_1U;
+ target_ulong CPR2_2L;
+ target_ulong CPR2_2U;
+ target_ulong CPR2_3L;
+ target_ulong CPR2_3U;
+
+ target_ulong CPR3_0L;
+ target_ulong CPR3_0U;
+ target_ulong CPR3_1L;
+ target_ulong CPR3_1U;
+ target_ulong CPR3_2L;
+ target_ulong CPR3_2U;
+ target_ulong CPR3_3L;
+ target_ulong CPR3_3U;
+
+ target_ulong DPM0;
+ target_ulong DPM1;
+ target_ulong DPM2;
+ target_ulong DPM3;
+
+ target_ulong CPM0;
+ target_ulong CPM1;
+ target_ulong CPM2;
+ target_ulong CPM3;
+
+ /* Memory Management Registers */
+ target_ulong MMU_CON;
+ target_ulong MMU_ASI;
+ target_ulong MMU_TVA;
+ target_ulong MMU_TPA;
+ target_ulong MMU_TPX;
+ target_ulong MMU_TFA;
+ /* {1.3.1 only */
+ target_ulong BMACON;
+ target_ulong SMACON;
+ target_ulong DIEAR;
+ target_ulong DIETR;
+ target_ulong CCDIER;
+ target_ulong MIECON;
+ target_ulong PIEAR;
+ target_ulong PIETR;
+ target_ulong CCPIER;
+ /*} */
+ /* Debug Registers */
+ target_ulong DBGSR;
+ target_ulong EXEVT;
+ target_ulong CREVT;
+ target_ulong SWEVT;
+ target_ulong TR0EVT;
+ target_ulong TR1EVT;
+ target_ulong DMS;
+ target_ulong DCX;
+ target_ulong DBGTCR;
+ target_ulong CCTRL;
+ target_ulong CCNT;
+ target_ulong ICNT;
+ target_ulong M1CNT;
+ target_ulong M2CNT;
+ target_ulong M3CNT;
+ /* Floating Point Registers */
+ /* XXX: */
+
+ /* QEMU */
+ int error_code;
+ uint32_t hflags; /* CPU State */
+
+ #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
+ #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
+ #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
+
+ CPU_COMMON
+
+ /* Internal CPU feature flags. */
+ uint64_t features;
+
+ const tricore_def_t *cpu_model;
+ void *irq[8];
+ struct QEMUTimer *timer; /* Internal timer */
+};
+
+enum tricore_features {
+ TRICORE_FEATURE_13,
+ TRICORE_FEATURE_131,
+ TRICORE_FEATURE_16,
+};
+
+static inline int tricore_feature(CPUTRICOREState *env, int feature)
+{
+ return (env->features & (1ULL << feature)) != 0;
+}
+
+/* TriCore Traps Classes*/
+enum {
+ TRAPC_NONE = -1,
+ TRAPC_MMU = 0,
+ TRAPC_PROT = 1,
+ TRAPC_INSN_ERR = 2,
+ TRAPC_CTX_MNG = 3,
+ TRAPC_SYSBUS = 4,
+ TRAPC_ASSERT = 5,
+ TRAPC_SYSCALL = 6,
+ TRAPC_NMI = 7,
+};
+
+/* Class 0 TIN */
+enum {
+ TIN0_VAF = 0,
+ TIN0_VAP = 1,
+};
+
+/* Class 1 TIN */
+enum {
+ TIN1_PRIV = 1,
+ TIN1_MPR = 2,
+ TIN1_MPW = 3,
+ TIN1_MPX = 4,
+ TIN1_MPP = 5,
+ TIN1_MPN = 6,
+ TIN1_GRWP = 7,
+};
+
+/* Class 2 TIN */
+enum {
+ TIN2_IOPC = 1,
+ TIN2_UOPC = 2,
+ TIN2_OPD = 3,
+ TIN2_ALN = 4,
+ TIN2_MEM = 5,
+};
+
+/* Class 3 TIN */
+enum {
+ TIN3_FCD = 1,
+ TIN3_CDO = 2,
+ TIN3_CDU = 3,
+ TIN3_FCU = 4,
+ TIN3_CSU = 5,
+ TIN3_CTYP = 6,
+ TIN3_NEST = 7,
+};
+
+/* Class 4 TIN */
+enum {
+ TIN4_PSE = 1,
+ TIN4_DSE = 2,
+ TIN4_DAE = 3,
+ TIN4_CAE = 4,
+ TIN4_PIE = 5,
+ TIN4_DIE = 6,
+};
+
+/* Class 5 TIN */
+enum {
+ TIN5_OVF = 1,
+ TIN5_SOVF = 1,
+};
+
+/* Class 6 TIN
+ *
+ * Is always TIN6_SYS
+ */
+
+/* Class 7 TIN */
+enum {
+ TIN7_NMI = 0,
+};
+
+uint32_t psw_read(CPUTRICOREState *env);
+void psw_write(CPUTRICOREState *env, uint32_t val);
+
+#include "cpu-qom.h"
+#define MMU_USER_IDX 2
+
+void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+
+#define cpu_exec cpu_tricore_exec
+#define cpu_signal_handler cpu_tricore_signal_handler
+#define cpu_list tricore_cpu_list
+
+static inline int cpu_mmu_index(CPUTRICOREState *env)
+{
+ return 0;
+}
+
+
+
+#include "exec/cpu-all.h"
+
+enum {
+ /* 1 bit to define user level / supervisor access */
+ ACCESS_USER = 0x00,
+ ACCESS_SUPER = 0x01,
+ /* 1 bit to indicate direction */
+ ACCESS_STORE = 0x02,
+ /* Type of instruction that generated the access */
+ ACCESS_CODE = 0x10, /* Code fetch access */
+ ACCESS_INT = 0x20, /* Integer load/store access */
+ ACCESS_FLOAT = 0x30, /* floating point load/store access */
+};
+
+void cpu_state_reset(CPUTRICOREState *s);
+int cpu_tricore_exec(CPUTRICOREState *s);
+void tricore_tcg_init(void);
+int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
+
+static inline void cpu_get_tb_cpu_state(CPUTRICOREState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->PC;
+ *cs_base = 0;
+ *flags = 0;
+}
+
+TRICORECPU *cpu_tricore_init(const char *cpu_model);
+
+static inline CPUTRICOREState *cpu_init(const char *cpu_model)
+{
+ TRICORECPU *cpu = cpu_tricore_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
+
+}
+
+
+/* helpers.c */
+int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
+ int rw, int mmu_idx);
+#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
+
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUTRICOREState *env, TranslationBlock *tb)
+{
+ env->PC = tb->pc;
+}
+
+void do_interrupt(CPUTRICOREState *env);
+
+#endif /*__TRICORE_CPU_H__ */
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
new file mode 100644
index 0000000..0794672
--- /dev/null
+++ b/target-tricore/helper.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <signal.h>
+
+#include "cpu.h"
+
+int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
+ int rw, int mmu_idx)
+{
+ return 0;
+}
+
+void tricore_cpu_do_interrupt(CPUState *cs)
+{
+}
+
+TRICORECPU *cpu_tricore_init(const char *cpu_model)
+{
+ return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model));
+}
+
+static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CPUListState *s = user_data;
+ const char *typename;
+ char *name;
+
+ typename = object_class_get_name(oc);
+ name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ name);
+ g_free(name);
+}
+
+void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ CPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_TRICORE_CPU, false);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, tricore_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
+uint32_t psw_read(CPUTRICOREState *env)
+{
+ /* clear all USB bits */
+ env->PSW &= 0xffffff;
+ /* now set them from the cache */
+ env->PSW |= ((env->PSW_USB_C != 0) << 31);
+ env->PSW |= ((env->PSW_USB_V != 0) << 30);
+ env->PSW |= ((env->PSW_USB_SV != 0) << 29);
+ env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3);
+ env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4);
+
+ return env->PSW;
+}
+
+void psw_write(CPUTRICOREState *env, uint32_t val)
+{
+ env->PSW_USB_C = (val & MASK_USB_C);
+ env->PSW_USB_V = (val & MASK_USB_V);
+ env->PSW_USB_SV = (val & MASK_USB_SV);
+ env->PSW_USB_AV = ((val & MASK_USB_AV) << 3);
+ env->PSW_USB_SAV = ((val & MASK_USB_SAV) << 4);
+ env->PSW = val;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
new file mode 100644
index 0000000..e69de29
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
new file mode 100644
index 0000000..275790b
--- /dev/null
+++ b/target-tricore/op_helper.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdlib.h>
+#include "cpu.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+}
+
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
new file mode 100644
index 0000000..5bb212d
--- /dev/null
+++ b/target-tricore/translate.c
@@ -0,0 +1,100 @@
+/*
+ * TRICORE emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "cpu.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
+
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+
+
+static const char *regnames_a[] = {
+ "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
+ "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
+ "a12" , "a13" , "a14" , "a15",
+ };
+
+static const char *regnames_d[] = {
+ "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
+ "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
+ "d12" , "d13" , "d14" , "d15",
+ };
+
+void tricore_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ int i;
+
+ cpu_fprintf(f, "PC=%08x\n", env->PC);
+ for (i = 0; i < 16; ++i) {
+ if ((i & 3) == 0) {
+ cpu_fprintf(f, "GPR A%02d:", i);
+ }
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
+ }
+ for (i = 0; i < 16; ++i) {
+ if ((i & 3) == 0) {
+ cpu_fprintf(f, "GPR D%02d:", i);
+ }
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
+ }
+
+}
+
+static inline void
+gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb,
+ int search_pc)
+{
+}
+
+void
+gen_intermediate_code(CPUTRICOREState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
+}
+
+void
+gen_intermediate_code_pc(CPUTRICOREState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
+}
+
+void
+restore_state_to_opc(CPUTRICOREState *env, TranslationBlock *tb, int pc_pos)
+{
+ env->PC = tcg_ctx.gen_opc_pc[pc_pos];
+}
+/*
+ *
+ * Initialization
+ *
+ */
+
+void cpu_state_reset(CPUTRICOREState *env)
+{
+}
+
+void tricore_tcg_init(void)
+{
+}
diff --git a/target-tricore/tricore-defs.h b/target-tricore/tricore-defs.h
new file mode 100644
index 0000000..4350b03
--- /dev/null
+++ b/target-tricore/tricore-defs.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if !defined(__QEMU_TRICORE_DEFS_H__)
+#define __QEMU_TRICORE_DEFS_H__
+
+#define TARGET_PAGE_BITS 14
+#define TARGET_LONG_BITS 32
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+
+#define TRICORE_TLB_MAX 128
+
+#endif /* __QEMU_TRICORE_DEFS_H__ */
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 02/15] target-tricore: Add board for systemmode
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 03/15] target-tricore: Add softmmu support Bastian Koppelmann
` (12 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +++++++++++++++++++++++++++++++++++++++++
include/hw/tricore/tricore.h | 54 +++++++++++++++++
3 files changed, 184 insertions(+)
create mode 100644 hw/tricore/Makefile.objs
create mode 100644 hw/tricore/tricore_testboard.c
create mode 100644 include/hw/tricore/tricore.h
diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs
new file mode 100644
index 0000000..435e095
--- /dev/null
+++ b/hw/tricore/Makefile.objs
@@ -0,0 +1 @@
+obj-y += tricore_testboard.o
diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c
new file mode 100644
index 0000000..fee67b1
--- /dev/null
+++ b/hw/tricore/tricore_testboard.c
@@ -0,0 +1,129 @@
+/*
+ * TriCore Baseboard System emulation.
+ *
+ * Copyright (c) 2014 Bastian Koppelmann
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw/hw.h"
+#include "hw/devices.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "sysemu/blockdev.h"
+#include "exec/address-spaces.h"
+#include "hw/block/flash.h"
+#include "elf.h"
+#include "hw/tricore/tricore.h"
+
+#define TRICORE_FLASH_ADDR 0xa0000000
+#define TRICORE_FLASH_SIZE (2 * 1024 * 1024)
+#define TRICORE_FLASH_SECT_SIZE (256 * 1024)
+
+
+/* Board init. */
+
+static struct tricore_boot_info tricoretb_binfo;
+
+static void tricore_load_kernel(CPUTRICOREState *env)
+{
+ int64_t entry;
+ long kernel_size;
+
+ kernel_size = load_elf(tricoretb_binfo.kernel_filename, NULL,
+ NULL, (uint64_t *)&entry, NULL,
+ NULL, 0,
+ ELF_MACHINE, 1);
+ if (kernel_size <= 0) {
+ fprintf(stderr, "qemu: no kernel file '%s'\n",
+ tricoretb_binfo.kernel_filename);
+ exit(1);
+ }
+ env->PC = entry;
+
+}
+
+static void tricore_testboard_init(MachineState *machine, int board_id)
+{
+ TRICORECPU *cpu;
+ CPUTRICOREState *env;
+
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ext_cram = g_new(MemoryRegion, 1);
+ MemoryRegion *ext_dram = g_new(MemoryRegion, 1);
+ MemoryRegion *int_cram = g_new(MemoryRegion, 1);
+ MemoryRegion *int_dram = g_new(MemoryRegion, 1);
+ MemoryRegion *pcp_data = g_new(MemoryRegion, 1);
+ MemoryRegion *pcp_text = g_new(MemoryRegion, 1);
+ DriveInfo *dinfo;
+
+ if (!machine->cpu_model) {
+ machine->cpu_model = "tc1796";
+ }
+ cpu = cpu_tricore_init(machine->cpu_model);
+ env = &cpu->env;
+ if (!cpu) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 2*1024*1024);
+ vmstate_register_ram_global(ext_cram);
+ memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram", 4*1024*1024);
+ vmstate_register_ram_global(ext_dram);
+ memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48*1024);
+ vmstate_register_ram_global(int_cram);
+ memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48*1024);
+ vmstate_register_ram_global(int_dram);
+ memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram", 16*1024);
+ vmstate_register_ram_global(pcp_data);
+ memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram", 32*1024);
+ vmstate_register_ram_global(pcp_text);
+
+ memory_region_add_subregion(sysmem, 0x80000000, ext_cram);
+ memory_region_add_subregion(sysmem, 0xa1000000, ext_dram);
+ memory_region_add_subregion(sysmem, 0xd4000000, int_cram);
+ memory_region_add_subregion(sysmem, 0xd0000000, int_dram);
+ memory_region_add_subregion(sysmem, 0xf0050000, pcp_data);
+ memory_region_add_subregion(sysmem, 0xf0060000, pcp_text);
+
+ dinfo = drive_get(IF_PFLASH, 0, 0);
+ if (!pflash_cfi01_register(TRICORE_FLASH_ADDR, NULL,
+ "tricore_testboard.flash",
+ TRICORE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+ TRICORE_FLASH_SECT_SIZE,
+ TRICORE_FLASH_SIZE / TRICORE_FLASH_SECT_SIZE,
+ 2, 0x00, 0x00, 0x0000, 0x0, 0)) {
+
+ fprintf(stderr, "qemu: Error registering flash memory.\n");
+ } else {
+ env->PC = TRICORE_FLASH_ADDR;
+ }
+
+ tricoretb_binfo.ram_size = machine->ram_size;
+ tricoretb_binfo.kernel_filename = machine->kernel_filename;
+
+ if (machine->kernel_filename) {
+ tricore_load_kernel(env);
+ }
+}
+
+static void tricoreboard_init(MachineState *machine)
+{
+ tricore_testboard_init(machine, 0x183);
+}
+
+static QEMUMachine ttb_machine = {
+ .name = "TriCore testboard",
+ .desc = "Just for testing",
+ .init = tricoreboard_init,
+ .is_default = 1,
+};
+
+static void tricore_testboard_machine_init(void)
+{
+ qemu_register_machine(&ttb_machine);
+}
+
+machine_init(tricore_testboard_machine_init);
diff --git a/include/hw/tricore/tricore.h b/include/hw/tricore/tricore.h
new file mode 100644
index 0000000..4e68174
--- /dev/null
+++ b/include/hw/tricore/tricore.h
@@ -0,0 +1,54 @@
+#ifndef TRICORE_MISC_H
+#define TRICORE_MISC_H 1
+
+#include "exec/memory.h"
+#include "hw/irq.h"
+
+struct tricore_boot_info {
+ uint64_t ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+ const char *dtb_filename;
+ hwaddr loader_start;
+ /* multicore boards that use the default secondary core boot functions
+ * need to put the address of the secondary boot code, the boot reg,
+ * and the GIC address in the next 3 values, respectively. boards that
+ * have their own boot functions can use these values as they want.
+ */
+ hwaddr smp_loader_start;
+ hwaddr smp_bootreg_addr;
+ hwaddr gic_cpu_if_addr;
+ int nb_cpus;
+ int board_id;
+ int (*atag_board)(const struct tricore_boot_info *info, void *p);
+ /* multicore boards that use the default secondary core boot functions
+ * can ignore these two function calls. If the default functions won't
+ * work, then write_secondary_boot() should write a suitable blob of
+ * code mimicking the secondary CPU startup process used by the board's
+ * boot loader/boot ROM code, and secondary_cpu_reset_hook() should
+ * perform any necessary CPU reset handling and set the PC for the
+ * secondary CPUs to point at this boot blob.
+ */
+ void (*write_secondary_boot)(TRICORECPU *cpu,
+ const struct tricore_boot_info *info);
+ void (*secondary_cpu_reset_hook)(TRICORECPU *cpu,
+ const struct tricore_boot_info *info);
+ /* if a board is able to create a dtb without a dtb file then it
+ * sets get_dtb. This will only be used if no dtb file is provided
+ * by the user. On success, sets *size to the length of the created
+ * dtb, and returns a pointer to it. (The caller must free this memory
+ * with g_free() when it has finished with it.) On failure, returns NULL.
+ */
+ void *(*get_dtb)(const struct tricore_boot_info *info, int *size);
+ /* if a board needs to be able to modify a device tree provided by
+ * the user it should implement this hook.
+ */
+ void (*modify_dtb)(const struct tricore_boot_info *info, void *fdt);
+ /* Used internally by arm_boot.c */
+ int is_linux;
+ hwaddr initrd_start;
+ hwaddr initrd_size;
+ hwaddr entry;
+};
+#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 03/15] target-tricore: Add softmmu support
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 04/15] target-tricore: Add initialization for translation and activate target Bastian Koppelmann
` (11 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
target-tricore/op_helper.c | 33 +++++++++++++++++++++++++++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index 0794672..22acb83 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -24,10 +24,62 @@
#include "cpu.h"
+enum {
+ TLBRET_DIRTY = -4,
+ TLBRET_INVALID = -3,
+ TLBRET_NOMATCH = -2,
+ TLBRET_BADADDR = -1,
+ TLBRET_MATCH = 0
+};
+
+#if defined(CONFIG_SOFTMMU)
+static int get_physical_address(CPUTRICOREState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
+{
+ int ret = TLBRET_MATCH;
+
+ *physical = address & 0xFFFFFFFF;
+ *prot = PAGE_READ | PAGE_WRITE;
+
+ return ret;
+}
+#endif
+
+/* TODO: Add exeption support*/
+static void raise_mmu_exception(CPUTRICOREState *env, target_ulong address,
+ int rw, int tlb_error)
+{
+}
+
int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
int rw, int mmu_idx)
{
- return 0;
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ hwaddr physical;
+ int prot;
+ int access_type;
+ int ret = 0;
+
+ rw &= 1;
+ access_type = ACCESS_INT;
+ ret = get_physical_address(env, &physical, &prot,
+ address, rw, access_type);
+ qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
+ " prot %d\n", __func__, address, ret, physical, prot);
+
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ mmu_idx, TARGET_PAGE_SIZE);
+ ret = 0;
+ } else if (ret < 0) {
+ raise_mmu_exception(env, address, rw, ret);
+ ret = 1;
+ }
+
+ return ret;
}
void tricore_cpu_do_interrupt(CPUState *cs)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 275790b..2e5981f 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -20,8 +20,39 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
+ uint32_t exception,
+ int error_code,
+ uintptr_t pc)
+{
+ CPUState *cs = CPU(tricore_env_get_cpu(env));
+ cs->exception_index = exception;
+ env->error_code = error_code;
+
+ if (pc) {
+ /* now we have a real cpu fault */
+ cpu_restore_state(cs, pc);
+ }
+
+ cpu_loop_exit(cs);
+}
+
+static inline void QEMU_NORETURN do_raise_exception(CPUTRICOREState *env,
+ uint32_t exception,
+ uintptr_t pc)
+{
+ do_raise_exception_err(env, exception, 0, pc);
+}
+
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ int ret;
+ ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
+ if (ret) {
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ do_raise_exception_err(env, cs->exception_index,
+ env->error_code, retaddr);
+ }
}
-
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 04/15] target-tricore: Add initialization for translation and activate target
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (2 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 03/15] target-tricore: Add softmmu support Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
` (10 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
configure | 5 ++
default-configs/tricore-softmmu.mak | 3 +
target-tricore/translate.c | 165 ++++++++++++++++++++++++++++++++++++
3 files changed, 173 insertions(+)
create mode 100644 default-configs/tricore-softmmu.mak
diff --git a/configure b/configure
index f7685b5..5003e28 100755
--- a/configure
+++ b/configure
@@ -4965,6 +4965,9 @@ case "$target_name" in
TARGET_BASE_ARCH=mips
echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
;;
+ tricore)
+ target_phys_bits=32
+ ;;
moxie)
;;
or32)
@@ -5162,6 +5165,8 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
echo "CONFIG_MIPS_DIS=y" >> $config_target_mak
echo "CONFIG_MIPS_DIS=y" >> config-all-disas.mak
;;
+ tricore*)
+ ;;
moxie*)
echo "CONFIG_MOXIE_DIS=y" >> $config_target_mak
echo "CONFIG_MOXIE_DIS=y" >> config-all-disas.mak
diff --git a/default-configs/tricore-softmmu.mak b/default-configs/tricore-softmmu.mak
new file mode 100644
index 0000000..48ccd12
--- /dev/null
+++ b/default-configs/tricore-softmmu.mak
@@ -0,0 +1,3 @@
+include pci.mak
+CONFIG_PFLASH_CFI01=y
+CONFIG_SMC91C111=y
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5bb212d..7275c49 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -26,6 +26,26 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+/*
+ * TCG registers
+ */
+static TCGv cpu_PC;
+static TCGv cpu_PCXI;
+static TCGv cpu_PSW;
+static TCGv cpu_ICR;
+/* GPR registers */
+static TCGv cpu_gpr_a[16];
+static TCGv cpu_gpr_d[16];
+/* PSW Flag cache */
+static TCGv cpu_PSW_C;
+static TCGv cpu_PSW_V;
+static TCGv cpu_PSW_SV;
+static TCGv cpu_PSW_AV;
+static TCGv cpu_PSW_SAV;
+/* CPU env */
+static TCGv_ptr cpu_env;
+
+#include "exec/gen-icount.h"
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
@@ -39,6 +59,25 @@ static const char *regnames_d[] = {
"d12" , "d13" , "d14" , "d15",
};
+typedef struct DisasContext {
+ struct TranslationBlock *tb;
+ target_ulong pc, saved_pc, next_pc;
+ uint32_t opcode;
+ int singlestep_enabled;
+ /* Routine used to access memory */
+ int mem_idx;
+ uint32_t hflags, saved_hflags;
+ int bstate;
+} DisasContext;
+
+enum {
+
+ BS_NONE = 0,
+ BS_STOP = 1,
+ BS_BRANCH = 2,
+ BS_EXCP = 3,
+};
+
void tricore_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
@@ -62,10 +101,88 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
}
+static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_opc(CPUTRICOREState *env, DisasContext *ctx, int *is_branch)
+{
+ /* 16-Bit Instruction */
+ if ((ctx->opcode & 0x1) == 0) {
+ ctx->next_pc = ctx->pc + 2;
+ decode_16Bit_opc(env, ctx);
+ /* 32-Bit Instruction */
+ } else {
+ ctx->next_pc = ctx->pc + 4;
+ decode_32Bit_opc(env, ctx);
+ }
+}
+
static inline void
gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb,
int search_pc)
{
+ CPUState *cs = CPU(cpu);
+ CPUTRICOREState *env = &cpu->env;
+ DisasContext ctx;
+ target_ulong pc_start;
+ int num_insns;
+ uint16_t *gen_opc_end;
+
+ if (search_pc) {
+ qemu_log("search pc %d\n", search_pc);
+ }
+
+ num_insns = 0;
+ pc_start = tb->pc;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
+ ctx.pc = pc_start;
+ ctx.saved_pc = -1;
+ ctx.tb = tb;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.bstate = BS_NONE;
+ ctx.mem_idx = cpu_mmu_index(env);
+
+ tcg_clear_temp_count();
+ gen_tb_start();
+ while (ctx.bstate == BS_NONE) {
+ ctx.opcode = cpu_ldl_code(env, ctx.pc);
+ decode_opc(env, &ctx, 0);
+
+ num_insns++;
+
+ ctx.pc = ctx.next_pc;
+ if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
+ break;
+ }
+ if (singlestep) {
+ break;
+ }
+ }
+
+ gen_tb_end(tb, num_insns);
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
+ if (search_pc) {
+ printf("done_generating search pc\n");
+ } else {
+ tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
+ }
+ if (tcg_check_temp_count()) {
+ printf("LEAK at %08x\n", env->PC);
+ }
+
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
+ qemu_log("\n");
+ }
+#endif
}
void
@@ -93,8 +210,56 @@ restore_state_to_opc(CPUTRICOREState *env, TranslationBlock *tb, int pc_pos)
void cpu_state_reset(CPUTRICOREState *env)
{
+ /* Reset Regs to Default Value */
+ env->PSW = 0xb80;
+}
+
+static void tricore_tcg_init_csfr(void)
+{
+ cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PCXI), "PCXI");
+ cpu_PSW = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW), "PSW");
+ cpu_PC = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PC), "PC");
+ cpu_ICR = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, ICR), "ICR");
}
void tricore_tcg_init(void)
{
+ int i;
+ static int inited;
+ if (inited) {
+ return;
+ }
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ /* reg init */
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, gpr_a[i]),
+ regnames_a[i]);
+ }
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, gpr_d[i]),
+ regnames_d[i]);
+ }
+ tricore_tcg_init_csfr();
+ /* init PSW flag cache */
+ cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW_USB_C),
+ "PSW_C");
+ cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW_USB_V),
+ "PSW_V");
+ cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW_USB_SV),
+ "PSW_SV");
+ cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW_USB_AV),
+ "PSW_AV");
+ cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, PSW_USB_SAV),
+ "PSW_SAV");
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 05/15] target-tricore: Add masks and opcodes for decoding
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (3 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 04/15] target-tricore: Add initialization for translation and activate target Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
` (9 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 1 +
target-tricore/tricore-opcodes.h | 1406 ++++++++++++++++++++++++++++++++++++++
2 files changed, 1407 insertions(+)
create mode 100644 target-tricore/tricore-opcodes.h
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 7275c49..0d30c51 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -26,6 +26,7 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "tricore-opcodes.h"
/*
* TCG registers
*/
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
new file mode 100644
index 0000000..9c6ec01
--- /dev/null
+++ b/target-tricore/tricore-opcodes.h
@@ -0,0 +1,1406 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Opcode Masks for Tricore
+ * Format MASK_OP_InstrFormatName_Field
+ */
+
+/* This creates a mask with bits start .. end set to 1 and applies it to op */
+#define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
+ (end) - (start) + 1))
+#define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
+ (end) - (start) + 1))
+
+/* new opcode masks */
+
+#define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
+
+/* 16-Bit Formats */
+#define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
+#define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
+
+#define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
+#define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
+
+#define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
+#define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+#define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
+
+#define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* 32-Bit Formats */
+
+/* ABS Format */
+#define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
+ (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
+ (MASK_BITS_SHIFT(op, 12, 15) << 14))
+#define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
+#define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* ABSB Format */
+#define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
+#define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
+#define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
+#define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 7, 10)
+
+/* B Format */
+#define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
+ (MASK_BITS_SHIFT(op, 8, 15) << 16))
+/* BIT Format */
+#define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
+#define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BO Format */
+#define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS_SHIFT(op, 28, 31) << 6))
+#define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
+#define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BOL Format */
+#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
+ (MASK_BITS_SHIFT(op, 22, 27) >> 10))
+
+#define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BRC Format */
+#define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BRN Format */
+#define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
+ (MASK_BITS_SHIFT(op, 7, 7) << 4))
+#define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+/* BRR Format */
+#define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* META MASK for similar instr Formats */
+#define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
+#define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* RC Format */
+#define MASK_OP_RC_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
+#define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
+#define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
+
+/* RCPW Format */
+
+#define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
+
+/* RCR Format */
+
+#define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
+#define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
+
+/* RCRR Format */
+
+#define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
+
+/* RCRW Format */
+
+#define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
+
+/* RLC Format */
+
+#define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
+#define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
+
+/* RR Format */
+#define MASK_OP_RR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
+#define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
+
+/* RR1 Format */
+#define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
+#define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
+
+/* RR2 Format */
+#define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
+#define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
+
+/* RRPW Format */
+#define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
+
+/* RRR Format */
+#define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
+#define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
+
+/* RRR1 Format */
+#define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
+#define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
+
+/* RRR2 Format */
+#define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
+#define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
+
+/* RRRR Format */
+#define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
+
+/* RRRW Format */
+#define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
+
+/* SYS Format */
+#define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
+#define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
+
+
+
+/*
+ * Tricore Opcodes Enums
+ *
+ * Format: OPC(1|2|M)_InstrLen_Name
+ * OPC1 = only op1 field is used
+ * OPC2 = op1 and op2 field used part of OPCM
+ * OPCM = op1 field used to group Instr
+ * InstrLen = 16|32
+ * Name = Name of Instr
+ */
+
+/* 16-Bit */
+enum {
+
+ OPCM_16_SR_SYSTEM = 0x00,
+ OPCM_16_SR_ACCU = 0x32,
+
+ OPC1_16_SRC_ADD = 0xc2,
+ OPC1_16_SRC_ADD_A15 = 0x92,
+ OPC1_16_SRC_ADD_15A = 0x9a,
+ OPC1_16_SRR_ADD = 0x42,
+ OPC1_16_SRR_ADD_A15 = 0x12,
+ OPC1_16_SRR_ADD_15A = 0x1a,
+ OPC1_16_SRC_ADD_A = 0xb0,
+ OPC1_16_SRR_ADD_A = 0x30,
+ OPC1_16_SRR_ADDS = 0x22,
+ OPC1_16_SRRS_ADDSC_A = 0x10,
+ OPC1_16_SC_AND = 0x16,
+ OPC1_16_SRR_AND = 0x26,
+ OPC1_16_SC_BISR = 0xe0,
+ OPC1_16_SRC_CADD = 0x8a,
+ OPC1_16_SRC_CADDN = 0xca,
+ OPC1_16_SB_CALL = 0x5c,
+ OPC1_16_SRC_CMOV = 0xaa,
+ OPC1_16_SRR_CMOV = 0x2a,
+ OPC1_16_SRC_CMOVN = 0xea,
+ OPC1_16_SRR_CMOVN = 0x6a,
+ OPC1_16_SRC_EQ = 0xba,
+ OPC1_16_SRR_EQ = 0x3a,
+ OPC1_16_SB_J = 0x3c,
+ OPC1_16_SBC_JEQ = 0x1e,
+ OPC1_16_SBR_JEQ = 0x3e,
+ OPC1_16_SBR_JGEZ = 0xce,
+ OPC1_16_SBR_JGTZ = 0x4e,
+ OPC1_16_SR_JI = 0xdc,
+ OPC1_16_SBR_JLEZ = 0x8e,
+ OPC1_16_SBR_JLTZ = 0x0e,
+ OPC1_16_SBC_JNE = 0x5e,
+ OPC1_16_SBR_JNE = 0x7e,
+ OPC1_16_SB_JNZ = 0xee,
+ OPC1_16_SBR_JNZ = 0xf6,
+ OPC1_16_SBR_JNZ_A = 0x7c,
+ OPC1_16_SBRN_JNZ_T = 0xae,
+ OPC1_16_SB_JZ = 0x6e,
+ OPC1_16_SBR_JZ = 0x76,
+ OPC1_16_SBR_JZ_A = 0xbc,
+ OPC1_16_SBRN_JZ_T = 0x2e,
+ OPC1_16_SC_LD_A = 0xd8,
+ OPC1_16_SLR_LD_A = 0xd4,
+ OPC1_16_SLR_LD_A_POSTINC = 0xc4,
+ OPC1_16_SLRO_LD_A = 0xc8,
+ OPC1_16_SRO_LD_A = 0xcc,
+ OPC1_16_SLR_LD_BU = 0x14,
+ OPC1_16_SLR_LD_BU_POSTINC = 0x04,
+ OPC1_16_SLRO_LD_BU = 0x08,
+ OPC1_16_SRO_LD_BU = 0x0c,
+ OPC1_16_SLR_LD_H = 0x94,
+ OPC1_16_SLR_LD_H_POSTINC = 0x84,
+ OPC1_16_SLRO_LD_H = 0x88,
+ OPC1_16_SRO_LD_H = 0x8c,
+ OPC1_16_SC_LD_W = 0x58,
+ OPC1_16_SLR_LD_W = 0x54,
+ OPC1_16_SLR_LD_W_POSTINC = 0x44,
+ OPC1_16_SLRO_LD_W = 0x48,
+ OPC1_16_SRO_LD_W = 0x4c,
+ OPC1_16_SBR_LOOP = 0xfc,
+ OPC1_16_SRC_LT = 0xfa,
+ OPC1_16_SRR_LT = 0x7a,
+ OPC1_16_SC_MOV = 0xda,
+ OPC1_16_SRC_MOV = 0x82,
+ OPC1_16_SRR_MOV = 0x02,
+ OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
+ OPC1_16_SRC_MOV_A = 0xa0,
+ OPC1_16_SRR_MOV_A = 0x60,
+ OPC1_16_SRR_MOV_AA = 0x40,
+ OPC1_16_SRR_MOV_D = 0x80,
+ OPC1_16_SRR_MUL = 0xe2,
+ OPC1_16_SR_NOT = 0x46,
+ OPC1_16_SC_OR = 0x96,
+ OPC1_16_SRR_OR = 0xa6,
+ OPC1_16_SRC_SH = 0x06,
+ OPC1_16_SRC_SHA = 0x86,
+ OPC1_16_SC_ST_A = 0xf8,
+ OPC1_16_SRO_ST_A = 0xec,
+ OPC1_16_SSR_ST_A = 0xf4,
+ OPC1_16_SSR_ST_A_POSTINC = 0xe4,
+ OPC1_16_SSRO_ST_A = 0xe8,
+ OPC1_16_SRO_ST_B = 0x2c,
+ OPC1_16_SSR_ST_B = 0x34,
+ OPC1_16_SSR_ST_B_POSTINC = 0x24,
+ OPC1_16_SSRO_ST_B = 0x28,
+ OPC1_16_SRO_ST_H = 0xac,
+ OPC1_16_SSR_ST_H = 0xb4,
+ OPC1_16_SSR_ST_H_POSTINC = 0xa4,
+ OPC1_16_SSRO_ST_H = 0xa8,
+ OPC1_16_SC_ST_W = 0x78,
+ OPC1_16_SRO_ST_W = 0x6c,
+ OPC1_16_SSR_ST_W = 0x74,
+ OPC1_16_SSR_ST_W_POSTINC = 0x64,
+ OPC1_16_SSRO_ST_W = 0x68,
+ OPC1_16_SRR_SUB = 0xa2,
+ OPC1_16_SRR_SUB_A15B = 0x52,
+ OPC1_16_SRR_SUB_15AB = 0x5a,
+ OPC1_16_SC_SUB_A = 0x20,
+ OPC1_16_SRR_SUBS = 0x62,
+ OPC1_16_SRR_XOR = 0xc6,
+
+};
+
+/*
+ * SR Format
+ */
+/* OPCM_16_SR_SYSTEM */
+enum {
+
+ OPC2_16_SR_NOP = 0x00,
+ OPC2_16_SR_RET = 0x09,
+ OPC2_16_SR_RFE = 0x08,
+ OPC2_16_SR_DEBUG = 0x0a,
+};
+/* OPCM_16_SR_ACCU */
+enum {
+ OPC2_16_SR_RSUB = 0x05,
+ OPC2_16_SR_SAT_B = 0x00,
+ OPC2_16_SR_SAT_BU = 0x01,
+ OPC2_16_SR_SAT_H = 0x02,
+ OPC2_16_SR_SAT_HU = 0x03,
+
+};
+
+/* 32-Bit */
+
+enum {
+/* ABS Format 1, M */
+ OPCM_32_ABS_LDW = 0x85,
+ OPCM_32_ABS_LDB = 0x05,
+ OPCM_32_ABS_LDMST_SWAP = 0xe5,
+ OPCM_32_ABS_LDST_CONTEXT = 0x15,
+ OPCM_32_ABS_STORE = 0xa5,
+ OPCM_32_ABS_STOREB_H = 0x25,
+ OPC1_32_ABS_STOREQ = 0x65,
+ OPC1_32_ABS_LD_Q = 0x45,
+ OPC1_32_ABS_LEA = 0xc5,
+/* ABSB Format */
+ OPC1_32_ABSB_ST_T = 0xd5,
+/* B Format */
+ OPC1_32_B_CALL = 0x6d,
+ OPC1_32_B_CALLA = 0xed,
+ OPC1_32_B_J = 0x1d,
+ OPC1_32_B_JA = 0x9d,
+ OPC1_32_B_JL = 0x5d,
+ OPC1_32_B_JLA = 0xdd,
+/* Bit Format */
+ OPCM_32_BIT_ANDACC = 0x47,
+ OPCM_32_BIT_LOGICAL_T1 = 0x87,
+ OPCM_32_BIT_INSERT = 0x67,
+ OPCM_32_BIT_LOGICAL_T2 = 0x07,
+ OPCM_32_BIT_ORAND = 0xc7,
+ OPCM_32_BIT_SH_LOGIC1 = 0x27,
+ OPCM_32_BIT_SH_LOGIC2 = 0xa7,
+/* BO Format */
+ OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
+ OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
+ OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
+ OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
+ OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
+ OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
+/* BOL Format */
+ OPC1_32_BOL_LD_A_LONGOFF = 0x99,
+ OPC1_32_BOL_LD_W_LONFOFF = 0x19,
+ OPC1_32_BOL_LEA_LONGOFF = 0xd9,
+ OPC1_32_BOL_ST_W_LONGOFF = 0x59,
+ OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
+/* BRC Format */
+ OPCM_32_BRC_EQ_NEQ = 0xdf,
+ OPCM_32_BRC_GE = 0xff,
+ OPCM_32_BRC_JLT = 0xbf,
+ OPCM_32_BRC_JNE = 0x9f,
+/* BRN Format */
+ OPCM_32_BRN_JTT = 0x6f,
+/* BRR Format */
+ OPCM_32_BRR_EQ_NEQ = 0x5f,
+ OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
+ OPCM_32_BRR_GE = 0x7f,
+ OPCM_32_BRR_JLT = 0x3f,
+ OPCM_32_BRR_JNE = 0x1f,
+ OPCM_32_BRR_JNZ = 0xbd,
+ OPCM_32_BRR_LOOP = 0xfd,
+/* RC Format */
+ OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
+ OPCM_32_RC_ACCUMULATOR = 0x8b,
+ OPCM_32_RC_SERVICEROUTINE = 0xad,
+ OPCM_32_RC_MUL = 0x53,
+/* RCPW Format */
+ OPCM_32_RCPW_MASK_INSERT = 0xb7,
+/* RCR Format */
+ OPCM_32_RCR_COND_SELECT = 0xab,
+ OPCM_32_RCR_MADD = 0x13,
+ OPCM_32_RCR_MSUB = 0x33,
+/* RCRR Format */
+ OPC1_32_RCRR_INSERT = 0x97,
+/* RCRW Format */
+ OPCM_32_RCRW_MASK_INSERT = 0xd7,
+/* RLC Format */
+ OPC1_32_RLC_ADDI = 0x1b,
+ OPC1_32_RLC_ADDIH = 0x9b,
+ OPC1_32_RLC_ADDIH_A = 0x11,
+ OPC1_32_RLC_MFCR = 0x4d,
+ OPC1_32_RLC_MOV = 0x3b,
+ OPC1_32_RLC_MOV_U = 0xbb,
+ OPC1_32_RLC_MOV_H = 0x7b,
+ OPC1_32_RLC_MOVH_A = 0x91,
+ OPC1_32_RLC_MTCR = 0xcd,
+/* RR Format */
+ OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
+ OPCM_32_RR_ACCUMULATOR = 0x0b,
+ OPCM_32_RR_ADRESS = 0x01,
+ OPCM_32_RR_FLOAT = 0x4b,
+ OPCM_32_RR_IDIRECT = 0x2d,
+/* RR1 Format */
+ OPCM_32_RR1_MUL = 0xb3,
+ OPCM_32_RR1_MULQ = 0x93,
+/* RR2 Format */
+ OPCM_32_RR2_MUL = 0x73,
+/* RRPW Format */
+ OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
+ OPC1_32_RRPW_DEXTR = 0x77,
+/* RRR Format */
+ OPCM_32_RRR_COND_SELECT = 0x2b,
+ OPCM_32_RRR_FLOAT = 0x6b,
+/* RRR1 Format */
+ OPCM_32_RRR1_MADD = 0x83,
+ OPCM_32_RRR1_MADDQ_H = 0x43,
+ OPCM_32_RRR1_MADDSU_H = 0xc3,
+ OPCM_32_RRR1_MSUB_H = 0xa3,
+ OPCM_32_RRR1_MSUB_Q = 0x63,
+ OPCM_32_RRR1_MSUBADS_H = 0xe3,
+/* RRR2 Format */
+ OPCM_32_RRR2_MADD = 0x03,
+ OPCM_32_RRR2_MSUB = 0x23,
+/* RRRR Format */
+ OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
+/* RRRW Format */
+ OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
+/* SYS Format */
+ OPCM_32_SYS_INTERRUPTS = 0x0d,
+ OPC1_32_SYS_RSTV = 0x2f,
+};
+
+
+
+/*
+ * ABS Format
+ */
+
+/* OPCM_32_ABS_LDW */
+enum {
+
+ OPC2_32_ABS_LD_A = 0x02,
+ OPC2_32_ABS_LD_D = 0x01,
+ OPC2_32_ABS_LD_DA = 0x03,
+ OPC2_32_ABS_LD_W = 0x00,
+};
+
+/* OPCM_32_ABS_LDB */
+enum {
+ OPC2_32_ABS_LD_B = 0x00,
+ OPC2_32_ABS_LD_BU = 0x01,
+ OPC2_32_ABS_LD_H = 0x02,
+ OPC2_32_ABS_LD_HU = 0x03,
+};
+/* OPCM_32_ABS_LDMST_SWAP */
+enum {
+ OPC2_32_ABS_LDMST = 0x01,
+ OPC2_32_ABS_SWAP_W = 0x00,
+};
+/* OPCM_32_ABS_LDST_CONTEXT */
+enum {
+ OPC2_32_ABS_LDLCX = 0x02,
+ OPC2_32_ABS_LDUCX = 0x03,
+ OPC2_32_ABS_STLCX = 0x00,
+ OPC2_32_ABS_STUCX = 0x01,
+};
+/* OPCM_32_ABS_STORE */
+enum {
+ OPC2_32_ABS_ST_A = 0x02,
+ OPC2_32_ABS_ST_D = 0x01,
+ OPC2_32_ABS_ST_DA = 0x03,
+ OPC2_32_ABS_ST_W = 0x00,
+};
+/* OPCM_32_ABS_STOREB_H */
+enum {
+ OPC2_32_ABS_ST_B = 0x00,
+ OPC2_32_ABS_ST_H = 0x02,
+};
+/*
+ * Bit Format
+ */
+/* OPCM_32_BIT_ANDACC */
+enum {
+ OPC2_32_BIT_AND_AND_T = 0x00,
+ OPC2_32_BIT_AND_ANDN_T = 0x03,
+ OPC2_32_BIT_AND_NOR_T = 0x02,
+ OPC2_32_BIT_AND_OR_T = 0x01,
+};
+/* OPCM_32_BIT_LOGICAL_T */
+enum {
+ OPC2_32_BIT_AND_T = 0x00,
+ OPC2_32_BIT_ANDN_T = 0x03,
+ OPC2_32_BIT_NOR_T = 0x02,
+ OPC2_32_BIT_OR_T = 0x01,
+};
+/* OPCM_32_BIT_INSERT */
+enum {
+ OPC2_32_BIT_INS_T = 0x00,
+ OPC2_32_BIT_INSN_T = 0x01,
+};
+/* OPCM_32_BIT_LOGICAL_T2 */
+enum {
+ OPC2_32_BIT_NAND_T = 0x00,
+ OPC2_32_BIT_ORN_T = 0x01,
+ OPC2_32_BIT_XNOR_T = 0x02,
+ OPC2_32_BIT_XOR_T = 0x03,
+};
+/* OPCM_32_BIT_ORAND */
+enum {
+ OPC2_32_BIT_OR_AND_T = 0x00,
+ OPC2_32_BIT_OR_ANDN_T = 0x03,
+ OPC2_32_BIT_OR_NOR_T = 0x02,
+ OPC2_32_BIT_OR_OR_T = 0x01,
+};
+/*OPCM_32_BIT_SH_LOGIC1 */
+enum {
+ OPC2_32_BIT_SH_AND_T = 0x00,
+ OPC2_32_BIT_SH_ANDN_T = 0x03,
+ OPC2_32_BIT_SH_NOR_T = 0x02,
+ OPC2_32_BIT_SH_OR_T = 0x01,
+};
+/* OPCM_32_BIT_SH_LOGIC2 */
+enum {
+ OPC2_32_BIT_SH_NAND_T = 0x00,
+ OPC2_32_BIT_SH_ORN_T = 0x01,
+ OPC2_32_BIT_SH_XNOR_T = 0x02,
+ OPC2_32_BIT_SH_XOR_T = 0x03,
+};
+/*
+ * BO Format
+ */
+/* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
+ OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
+ OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
+ OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
+ OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
+ OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
+ OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
+ OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
+ OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
+ /* 1.3.1 only */
+ OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
+ OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
+ OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
+ OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
+ OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
+ OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
+ /* end 1.3.1 only */
+ OPC2_32_BO_ST_A_SHORTOFF = 0x26,
+ OPC2_32_BO_ST_A_POSTINC = 0x06,
+ OPC2_32_BO_ST_A_PREINC = 0x16,
+ OPC2_32_BO_ST_B_SHORTOFF = 0x20,
+ OPC2_32_BO_ST_B_POSTINC = 0x00,
+ OPC2_32_BO_ST_B_PREINC = 0x10,
+ OPC2_32_BO_ST_D_SHORTOFF = 0x25,
+ OPC2_32_BO_ST_D_POSTINC = 0x05,
+ OPC2_32_BO_ST_D_PREINC = 0x15,
+ OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
+ OPC2_32_BO_ST_DA_POSTINC = 0x07,
+ OPC2_32_BO_ST_DA_PREINC = 0x17,
+ OPC2_32_BO_ST_H_SHORTOFF = 0x22,
+ OPC2_32_BO_ST_H_POSTINC = 0x02,
+ OPC2_32_BO_ST_H_PREINC = 0x12,
+ OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
+ OPC2_32_BO_ST_Q_POSTINC = 0x08,
+ OPC2_32_BO_ST_Q_PREINC = 0x18,
+ OPC2_32_BO_ST_W_SHORTOFF = 0x24,
+ OPC2_32_BO_ST_W_POSTINC = 0x04,
+ OPC2_32_BO_ST_W_PREINC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_CACHEA_I_BR = 0x0e,
+ OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
+ OPC2_32_BO_CACHEA_W_BR = 0x0c,
+ OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
+ OPC2_32_BO_CACHEA_WI_BR = 0x0d,
+ OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
+ OPC2_32_BO_ST_A_BR = 0x06,
+ OPC2_32_BO_ST_A_CIRC = 0x16,
+ OPC2_32_BO_ST_B_BR = 0x00,
+ OPC2_32_BO_ST_B_CIRC = 0x10,
+ OPC2_32_BO_ST_D_BR = 0x05,
+ OPC2_32_BO_ST_D_CIRC = 0x15,
+ OPC2_32_BO_ST_DA_BR = 0x07,
+ OPC2_32_BO_ST_DA_CIRC = 0x17,
+ OPC2_32_BO_ST_H_BR = 0x02,
+ OPC2_32_BO_ST_H_CIRC = 0x12,
+ OPC2_32_BO_ST_Q_BR = 0x08,
+ OPC2_32_BO_ST_Q_CIRC = 0x18,
+ OPC2_32_BO_ST_W_BR = 0x04,
+ OPC2_32_BO_ST_W_CIRC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_LD_A_SHORTOFF = 0x26,
+ OPC2_32_BO_LD_A_POSTINC = 0x06,
+ OPC2_32_BO_LD_A_PREINC = 0x16,
+ OPC2_32_BO_LD_B_SHORTOFF = 0x20,
+ OPC2_32_BO_LD_B_POSTINC = 0x00,
+ OPC2_32_BO_LD_B_PREINC = 0x10,
+ OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
+ OPC2_32_BO_LD_BU_POSTINC = 0x01,
+ OPC2_32_BO_LD_BU_PREINC = 0x11,
+ OPC2_32_BO_LD_D_SHORTOFF = 0x25,
+ OPC2_32_BO_LD_D_POSTINC = 0x05,
+ OPC2_32_BO_LD_D_PREINC = 0x15,
+ OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
+ OPC2_32_BO_LD_DA_POSTINC = 0x07,
+ OPC2_32_BO_LD_DA_PREINC = 0x17,
+ OPC2_32_BO_LD_H_SHORTOFF = 0x22,
+ OPC2_32_BO_LD_H_POSTINC = 0x02,
+ OPC2_32_BO_LD_H_PREINC = 0x12,
+ OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
+ OPC2_32_BO_LD_HU_POSTINC = 0x03,
+ OPC2_32_BO_LD_HU_PREINC = 0x13,
+ OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
+ OPC2_32_BO_LD_Q_POSTINC = 0x08,
+ OPC2_32_BO_LD_Q_PREINC = 0x18,
+ OPC2_32_BO_LD_W_SHORTOFF = 0x24,
+ OPC2_32_BO_LD_W_POSTINC = 0x04,
+ OPC2_32_BO_LD_W_PREINC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_LD_A_BR = 0x06,
+ OPC2_32_BO_LD_A_CIRC = 0x16,
+ OPC2_32_BO_LD_B_BR = 0x00,
+ OPC2_32_BO_LD_B_CIRC = 0x10,
+ OPC2_32_BO_LD_BU_BR = 0x01,
+ OPC2_32_BO_LD_BU_CIRC = 0x11,
+ OPC2_32_BO_LD_D_BR = 0x05,
+ OPC2_32_BO_LD_D_CIRC = 0x15,
+ OPC2_32_BO_LD_DA_BR = 0x07,
+ OPC2_32_BO_LD_DA_CIRC = 0x17,
+ OPC2_32_BO_LD_H_BR = 0x02,
+ OPC2_32_BO_LD_H_CIRC = 0x12,
+ OPC2_32_BO_LD_HU_BR = 0x03,
+ OPC2_32_BO_LD_HU_CIRC = 0x13,
+ OPC2_32_BO_LD_Q_BR = 0x08,
+ OPC2_32_BO_LD_Q_CIRC = 0x18,
+ OPC2_32_BO_LD_W_BR = 0x04,
+ OPC2_32_BO_LD_W_CIRC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
+ OPC2_32_BO_LDMST_SHORTOFF = 0x21,
+ OPC2_32_BO_LDMST_POSTINC = 0x01,
+ OPC2_32_BO_LDMST_PREINC = 0x11,
+ OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
+ OPC2_32_BO_LEA_SHORTOFF = 0x28,
+ OPC2_32_BO_STLCX_SHORTOFF = 0x26,
+ OPC2_32_BO_STUCX_SHORTOFF = 0x27,
+ OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
+ OPC2_32_BO_SWAP_W_POSTINC = 0x00,
+ OPC2_32_BO_SWAP_W_PREINC = 0x10,
+};
+/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_LDMST_BR = 0x01,
+ OPC2_32_BO_LDMST_CIRC = 0x11,
+ OPC2_32_BO_SWAP_W_BR = 0x00,
+ OPC2_32_BO_SWAP_W_CIRC = 0x10,
+};
+/*
+ * BRC Format
+ */
+/*OPCM_32_BRC_EQ_NEQ */
+enum {
+ OPC2_32_BRC_JEQ = 0x00,
+ OPC2_32_BRC_JNE = 0x01,
+};
+/* OPCM_32_BRC_GE */
+enum {
+ OP2_BRC_JGE = 0x00,
+ OPC_BRC_JGE_U = 0x01,
+};
+/* OPCM_32_BRC_JLT */
+enum {
+ OPC2_32_BRC_JLT = 0x00,
+ OPC2_32_BRC_JLT_U = 0x01,
+};
+/* OPCM_32_BRC_JNE */
+enum {
+ OPC2_32_BRC_JNED = 0x01,
+ OPC2_32_BRC_JNEI = 0x00,
+};
+/*
+ * BRN Format
+ */
+/* OPCM_32_BRN_JTT */
+enum {
+ OPC2_32_BRN_JNZ_T = 0x01,
+ OPC2_32_BRN_JZ_T = 0x00,
+};
+/*
+ * BRR Format
+ */
+/* OPCM_32_BRR_EQ_NEQ */
+enum {
+ OPC2_32_BRR_JEQ = 0x00,
+ OPC2_32_BRR_JNE = 0x01,
+};
+/* OPCM_32_BRR_ADDR_EQ_NEQ */
+enum {
+ OPC2_32_BRR_JEQ_A = 0x00,
+ OPC2_32_BRR_JNE_A = 0x01,
+};
+/*OPCM_32_BRR_GE */
+enum {
+ OPC2_32_BRR_JGE = 0x00,
+ OPC2_32_BRR_JGE_U = 0x01,
+};
+/* OPCM_32_BRR_JLT */
+enum {
+ OPC2_32_BRR_JLT = 0x00,
+ OPC2_32_BRR_JLT_U = 0x01,
+};
+/* OPCM_32_BRR_JNE */
+enum {
+ OPC2_32_BRR_JNED = 0x01,
+ OPC2_32_BRR_JNEI = 0x00,
+};
+/* OPCM_32_BRR_JNZ */
+enum {
+ OPC2_32_BRR_JNZ_A = 0x01,
+ OPC2_32_BRR_JZ_A = 0x00,
+};
+/* OPCM_32_BRR_LOOP */
+enum {
+ OPC2_32_BRR_LOOP = 0x00,
+ OPC2_32_BRR_LOOPU = 0x01,
+};
+/*
+ * RC Format
+ */
+/* OPCM_32_RC_LOGICAL_SHIFT */
+enum {
+ OPC2_32_RC_AND = 0x08,
+ OPC2_32_RC_ANDN = 0x0e,
+ OPC2_32_RC_NAND = 0x09,
+ OPC2_32_RC_NOR = 0x0b,
+ OPC2_32_RC_OR = 0x0a,
+ OPC2_32_RC_ORN = 0x0f,
+ OPC2_32_RC_SH = 0x00,
+ OPC2_32_RC_SH_H = 0x40,
+ OPC2_32_RC_SHA = 0x01,
+ OPC2_32_RC_SHA_H = 0x41,
+ OPC2_32_RC_SHAS = 0x02,
+ OPC2_32_RC_XNOR = 0x0d,
+ OPC2_32_RC_XOR = 0x0c,
+};
+/* OPCM_32_RC_ACCUMULATOR */
+enum {
+ OPC2_32_RC_ABSDIF = 0x0e,
+ OPC2_32_RC_ABSDIFS = 0x0f,
+ OPC2_32_RC_ADD = 0x00,
+ OPC2_32_RC_ADDC = 0x05,
+ OPC2_32_RC_ADDS = 0x02,
+ OPC2_32_RC_ADDS_U = 0x03,
+ OPC2_32_RC_ADDX = 0x04,
+ OPC2_32_RC_AND_EQ = 0x20,
+ OPC2_32_RC_AND_GE = 0x24,
+ OPC2_32_RC_AND_GE_U = 0x25,
+ OPC2_32_RC_AND_LT = 0x22,
+ OPC2_32_RC_AND_LT_U = 0x23,
+ OPC2_32_RC_AND_NE = 0x21,
+ OPC2_32_RC_EQ = 0x10,
+ OPC2_32_RC_EQANY_B = 0x56,
+ OPC2_32_RC_EQANY_H = 0x76,
+ OPC2_32_RC_GE = 0x14,
+ OPC2_32_RC_GE_U = 0x15,
+ OPC2_32_RC_LT = 0x12,
+ OPC2_32_RC_LT_U = 0x13,
+ OPC2_32_RC_MAX = 0x1a,
+ OPC2_32_RC_MAX_U = 0x1b,
+ OPC2_32_RC_MIN = 0x18,
+ OPC2_32_RC_MIN_U = 0x19,
+ OPC2_32_RC_NE = 0x11,
+ OPC2_32_RC_OR_EQ = 0x27,
+ OPC2_32_RC_OR_GE = 0x2b,
+ OPC2_32_RC_OR_GE_U = 0x2c,
+ OPC2_32_RC_OR_LT = 0x29,
+ OPC2_32_RC_OR_LT_U = 0x2a,
+ OPC2_32_RC_OR_NE = 0x28,
+ OPC2_32_RC_RSUB = 0x08,
+ OPC2_32_RC_RSUBS = 0x0a,
+ OPC2_32_RC_RSUBS_U = 0x0b,
+ OPC2_32_RC_SH_EQ = 0x37,
+ OPC2_32_RC_SH_GE = 0x3b,
+ OPC2_32_RC_SH_GE_U = 0x3c,
+ OPC2_32_RC_SH_LT = 0x39,
+ OPC2_32_RC_SH_LT_U = 0x3a,
+ OPC2_32_RC_SH_NE = 0x38,
+ OPC2_32_RC_XOR_EQ = 0x2f,
+ OPC2_32_RC_XOR_GE = 0x33,
+ OPC2_32_RC_XOR_GE_U = 0x34,
+ OPC2_32_RC_XOR_LT = 0x31,
+ OPC2_32_RC_XOR_LT_U = 0x32,
+ OPC2_32_RC_XOR_NE = 0x30,
+};
+/* OPCM_32_RC_SERVICEROUTINE */
+enum {
+ OPC2_32_RC_BISR = 0x00,
+ OPC2_32_RC_SYSCALL = 0x04,
+};
+/* OPCM_32_RC_MUL */
+enum {
+ OPC2_32_RC_MUL_32 = 0x01,
+ OPC2_32_RC_MUL_64 = 0x03,
+ OPC2_32_RC_MULS_32 = 0x05,
+ OPC2_32_RC_MUL_U_64 = 0x02,
+ OPC2_32_RC_MULS_U_32 = 0x04,
+};
+/*
+ * RCPW Format
+ */
+/* OPCM_32_RCPW_MASK_INSERT */
+enum {
+ OPC2_32_RCPW_IMASK = 0x01,
+ OPC2_32_RCPW_INSERT = 0x00,
+};
+/*
+ * RCR Format
+ */
+/* OPCM_32_RCR_COND_SELECT */
+enum {
+ OPC2_32_RCR_CADD = 0x00,
+ OPC2_32_RCR_CADDN = 0x01,
+ OPC2_32_RCR_SEL = 0x04,
+ OPC2_32_RCR_SELN = 0x05,
+};
+/* OPCM_32_RCR_MADD */
+enum {
+ OPC2_32_RCR_MADD_32 = 0x01,
+ OPC2_32_RCR_MADD_64 = 0x03,
+ OPC2_32_RCR_MADDS_32 = 0x05,
+ OPC2_32_RCR_MADDS_64 = 0x07,
+ OPC2_32_RCR_MADD_U_64 = 0x02,
+ OPC2_32_RCR_MADDS_U_32 = 0x04,
+ OPC2_32_RCR_MADDS_U_64 = 0x06,
+};
+/* OPCM_32_RCR_MSUB */
+enum {
+ OPC2_32_RCR_MSUB_32 = 0x01,
+ OPC2_32_RCR_MSUB_64 = 0x03,
+ OPC2_32_RCR_MSUBS_32 = 0x05,
+ OPC2_32_RCR_MSUBS_64 = 0x07,
+ OPC2_32_RCR_MSUB_U_32 = 0x02,
+ OPC2_32_RCR_MSUBS_U_32 = 0x04,
+ OPC2_32_RCR_MSUBS_U_64 = 0x06,
+};
+/*
+ * RCRW Format
+ */
+/* OPCM_32_RCRW_MASK_INSERT */
+enum {
+ OPC2_32_RCRW_IMASK = 0x01,
+ OPC2_32_RCRW_INSERT = 0x00,
+};
+
+/*
+ * RR Format
+ */
+/* OPCM_32_RR_LOGICAL_SHIFT */
+enum {
+ OPC2_32_RR_AND = 0x08,
+ OPC2_32_RR_ANDN = 0x0e,
+ OPC2_32_RR_CLO = 0x1c,
+ OPC2_32_RR_CLO_H = 0x7d,
+ OPC2_32_RR_CLS = 0x1d,
+ OPC2_32_RR_CLS_H = 0x7e,
+ OPC2_32_RR_CLZ = 0x1b,
+ OPC2_32_RR_CLZ_H = 0x7c,
+ OPC2_32_RR_NAND = 0x09,
+ OPC2_32_RR_NOR = 0x0b,
+ OPC2_32_RR_OR = 0x0a,
+ OPC2_32_RR_ORN = 0x0f,
+ OPC2_32_RR_SH = 0x00,
+ OPC2_32_RR_SH_H = 0x40,
+ OPC2_32_RR_SHA = 0x01,
+ OPC2_32_RR_SHA_H = 0x41,
+ OPC2_32_RR_SHAS = 0x02,
+ OPC2_32_RR_XNOR = 0x0d,
+ OPC2_32_RR_XOR = 0x0c,
+};
+/* OPCM_32_RR_ACCUMULATOR */
+enum {
+ OPC2_32_RR_ABS = 0x1c,
+ OPC2_32_RR_ABS_B = 0x5c,
+ OPC2_32_RR_ABS_H = 0x7c,
+ OPC2_32_RR_ABSDIF = 0x0e,
+ OPC2_32_RR_ABSDIF_B = 0x4e,
+ OPC2_32_RR_ABSDIF_H = 0x6e,
+ OPC2_32_RR_ABSDIFS = 0x0f,
+ OPC2_32_RR_ABSDIFS_H = 0x6f,
+ OPC2_32_RR_ABSS = 0x1d,
+ OPC2_32_RR_ABSS_H = 0x7d,
+ OPC2_32_RR_ADD = 0x00,
+ OPC2_32_RR_ADD_B = 0x40,
+ OPC2_32_RR_ADD_H = 0x60,
+ OPC2_32_RR_ADDC = 0x05,
+ OPC2_32_RR_ADDS = 0x02,
+ OPC2_32_RR_ADDS_H = 0x62,
+ OPC2_32_RR_ADDS_HU = 0x63,
+ OPC2_32_RR_ADDS_U = 0x03,
+ OPC2_32_RR_ADDX = 0x04,
+ OPC2_32_RR_AND_EQ = 0x20,
+ OPC2_32_RR_AND_GE = 0x24,
+ OPC2_32_RR_AND_GE_U = 0x25,
+ OPC2_32_RR_AND_LT = 0x22,
+ OPC2_32_RR_AND_LT_U = 0x23,
+ OPC2_32_RR_AND_NE = 0x21,
+ OPC2_32_RR_EQ = 0x10,
+ OPC2_32_RR_EQ_B = 0x50,
+ OPC2_32_RR_EQ_H = 0x70,
+ OPC2_32_RR_EQ_W = 0x90,
+ OPC2_32_RR_EQANY_B = 0x56,
+ OPC2_32_RR_EQANY_H = 0x76,
+ OPC2_32_RR_GE = 0x14,
+ OPC2_32_RR_GE_U = 0x15,
+ OPC2_32_RR_LT = 0x12,
+ OPC2_32_RR_LT_U = 0x13,
+ OPC2_32_RR_LT_B = 0x52,
+ OPC2_32_RR_LT_BU = 0x53,
+ OPC2_32_RR_LT_H = 0x72,
+ OPC2_32_RR_LT_HU = 0x73,
+ OPC2_32_RR_LT_W = 0x92,
+ OPC2_32_RR_LT_WU = 0x93,
+ OPC2_32_RR_MAX = 0x1a,
+ OPC2_32_RR_MAX_U = 0x1b,
+ OPC2_32_RR_MAX_B = 0x5a,
+ OPC2_32_RR_MAX_BU = 0x5b,
+ OPC2_32_RR_MAX_H = 0x7a,
+ OPC2_32_RR_MAX_HU = 0x7b,
+ OPC2_32_RR_MIN = 0x19,
+ OPC2_32_RR_MIN_U = 0x18,
+ OPC2_32_RR_MIN_B = 0x58,
+ OPC2_32_RR_MIN_BU = 0x59,
+ OPC2_32_RR_MIN_H = 0x78,
+ OPC2_32_RR_MIN_HU = 0x79,
+ OPC2_32_RR_MOV = 0x1f,
+ OPC2_32_RR_NE = 0x11,
+ OPC2_32_RR_OR_EQ = 0x27,
+ OPC2_32_RR_OR_GE = 0x2b,
+ OPC2_32_RR_OR_GE_U = 0x2c,
+ OPC2_32_RR_OR_LT = 0x29,
+ OPC2_32_RR_OR_LT_U = 0x2a,
+ OPC2_32_RR_OR_NE = 0x28,
+ OPC2_32_RR_SAT_B = 0x5e,
+ OPC2_32_RR_SAT_BU = 0x5f,
+ OPC2_32_RR_SAT_H = 0x7e,
+ OPC2_32_RR_SAT_HU = 0x7f,
+ OPC2_32_RR_SH_EQ = 0x37,
+ OPC2_32_RR_SH_GE = 0x3b,
+ OPC2_32_RR_SH_GE_U = 0x3c,
+ OPC2_32_RR_SH_LT = 0x39,
+ OPC2_32_RR_SH_LT_U = 0x3a,
+ OPC2_32_RR_SH_NE = 0x38,
+ OPC2_32_RR_SUB = 0x08,
+ OPC2_32_RR_SUB_B = 0x48,
+ OPC2_32_RR_SUB_H = 0x68,
+ OPC2_32_RR_SUBC = 0x0d,
+ OPC2_32_RR_SUBS = 0x0a,
+ OPC2_32_RR_SUBS_U = 0x0b,
+ OPC2_32_RR_SUBS_H = 0x6a,
+ OPC2_32_RR_SUBS_HU = 0x6b,
+ OPC2_32_RR_SUBX = 0x0c,
+ OPC2_32_RR_XOR_EQ = 0x2f,
+ OPC2_32_RR_XOR_GE = 0x33,
+ OPC2_32_RR_XOR_GE_U = 0x34,
+ OPC2_32_RR_XOR_LT = 0x31,
+ OPC2_32_RR_XOR_LT_U = 0x32,
+ OPC2_32_RR_XOR_NE = 0x30,
+};
+/* OPCM_32_RR_ADRESS */
+enum {
+ OPC2_32_RR_ADD_A = 0x01,
+ OPC2_32_RR_ADDSC_A = 0x60,
+ OPC2_32_RR_ADDSC_AT = 0x62,
+ OPC2_32_RR_EQ_A = 0x40,
+ OPC2_32_RR_EQZ = 0x48,
+ OPC2_32_RR_GE_A = 0x43,
+ OPC2_32_RR_LT_A = 0x42,
+ OPC2_32_RR_MOV_A = 0x63,
+ OPC2_32_RR_MOV_AA = 0x00,
+ OPC2_32_RR_MOV_D = 0x4c,
+ OPC2_32_RR_NE_A = 0x41,
+ OPC2_32_RR_NEZ_A = 0x49,
+ OPC2_32_RR_SUB_A = 0x02,
+};
+/* OPCM_32_RR_FLOAT */
+enum {
+ OPC2_32_RR_BMERGE = 0x01,
+ OPC2_32_RR_BSPLIT = 0x09,
+ OPC2_32_RR_DVINIT_B = 0x5a,
+ OPC2_32_RR_DVINIT_BU = 0x4a,
+ OPC2_32_RR_DVINIT_H = 0x3a,
+ OPC2_32_RR_DVINIT_HU = 0x2a,
+ OPC2_32_RR_DVINIT = 0x1a,
+ OPC2_32_RR_DVINIT_U = 0x0a,
+ OPC2_32_RR_PARITY = 0x02,
+ OPC2_32_RR_UNPACK = 0x08,
+};
+/* OPCM_32_RR_IDIRECT */
+enum {
+ OPC2_32_RR_JI = 0x03,
+ OPC2_32_RR_JLI = 0x02,
+ OPC2_32_RR_CALLI = 0x00,
+};
+/*
+ * RR1 Format
+ */
+/* OPCM_32_RR1_MUL */
+enum {
+ OPC2_32_RR1_MUL_H_32_LL = 0x1a,
+ OPC2_32_RR1_MUL_H_32_LU = 0x19,
+ OPC2_32_RR1_MUL_H_32_UL = 0x18,
+ OPC2_32_RR1_MUL_H_32_UU = 0x1b,
+ OPC2_32_RR1_MULM_H_64_LL = 0x1e,
+ OPC2_32_RR1_MULM_H_64_LU = 0x1d,
+ OPC2_32_RR1_MULM_H_64_UL = 0x1c,
+ OPC2_32_RR1_MULM_H_64_UU = 0x1f,
+ OPC2_32_RR1_MULR_H_16_LL = 0x0e,
+ OPC2_32_RR1_MULR_H_16_LU = 0x0d,
+ OPC2_32_RR1_MULR_H_16_UL = 0x0c,
+ OPC2_32_RR1_MULR_H_16_UU = 0x0f,
+};
+/* OPCM_32_RR1_MULQ */
+enum {
+ OPC2_32_RR1_MUL_Q_32 = 0x02,
+ OPC2_32_RR1_MUL_Q_64 = 0x1b,
+ OPC2_32_RR1_MUL_Q_32_L = 0x01,
+ OPC2_32_RR1_MUL_Q_64_L = 0x19,
+ OPC2_32_RR1_MUL_Q_32_U = 0x00,
+ OPC2_32_RR1_MUL_Q_64_U = 0x18,
+ OPC2_32_RR1_MUL_Q_32_LL = 0x05,
+ OPC2_32_RR1_MUL_Q_32_UU = 0x04,
+ OPC2_32_RR1_MULR_Q_32_L = 0x07,
+ OPC2_32_RR1_MULR_Q_32_U = 0x06,
+};
+/*
+ * RR2 Format
+ */
+/* OPCM_32_RR2_MUL */
+enum {
+ OPC2_32_RR2_MUL_32 = 0x0a,
+ OPC2_32_RR2_MUL_64 = 0x6a,
+ OPC2_32_RR2_MULS_32 = 0x8a,
+ OPC2_32_RR2_MUL_U_64 = 0x68,
+ OPC2_32_RR2_MULS_U_32 = 0x88,
+};
+/*
+ * RRPW Format
+ */
+/* OPCM_32_RRPW_EXTRACT_INSERT */
+enum {
+
+ OPC2_32_RRPW_EXTR = 0x02,
+ OPC2_32_RRPW_EXTR_U = 0x03,
+ OPC2_32_RRPW_IMASK = 0x01,
+ OPC2_32_RRPW_INSERT = 0x00,
+};
+/*
+ * RRR Format
+ */
+/* OPCM_32_RRR_COND_SELECT */
+enum {
+ OPC2_32_RRR_CADD = 0x00,
+ OPC2_32_RRR_CADDN = 0x01,
+ OPC2_32_RRR_CSUB = 0x02,
+ OPC2_32_RRR_CSUBN = 0x03,
+ OPC2_32_RRR_SEL = 0x04,
+ OPC2_32_RRR_SELN = 0x05,
+};
+/* OPCM_32_RRR_FLOAT */
+enum {
+ OPC2_32_RRR_DVADJ = 0x0d,
+ OPC2_32_RRR_DVSTEP = 0x0f,
+ OPC2_32_RRR_DVSTEP_U = 0x0e,
+ OPC2_32_RRR_IXMAX = 0x0a,
+ OPC2_32_RRR_IXMAX_U = 0x0b,
+ OPC2_32_RRR_IXMIN = 0x08,
+ OPC2_32_RRR_IXMIN_U = 0x09,
+ OPC2_32_RRR_PACK = 0x00,
+};
+/*
+ * RRR1 Format
+ */
+/* OPCM_32_RRR1_MADD */
+enum {
+ OPC2_32_RRR1_MADD_H_LL = 0x1a,
+ OPC2_32_RRR1_MADD_H_LU = 0x19,
+ OPC2_32_RRR1_MADD_H_UL = 0x18,
+ OPC2_32_RRR1_MADD_H_UU = 0x1b,
+ OPC2_32_RRR1_MADDS_H_LL = 0x3a,
+ OPC2_32_RRR1_MADDS_H_LU = 0x39,
+ OPC2_32_RRR1_MADDS_H_UL = 0x38,
+ OPC2_32_RRR1_MADDS_H_UU = 0x3b,
+ OPC2_32_RRR1_MADDM_H_LL = 0x1e,
+ OPC2_32_RRR1_MADDM_H_LU = 0x1d,
+ OPC2_32_RRR1_MADDM_H_UL = 0x1c,
+ OPC2_32_RRR1_MADDM_H_UU = 0x1f,
+ OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
+ OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
+ OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
+ OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
+ OPC2_32_RRR1_MADDR_H_LL = 0x0e,
+ OPC2_32_RRR1_MADDR_H_LU = 0x0d,
+ OPC2_32_RRR1_MADDR_H_UL = 0x0c,
+ OPC2_32_RRR1_MADDR_H_UU = 0x0f,
+ OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
+ OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
+ OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
+ OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MADDQ_H */
+enum {
+ OPC2_32_RRR1_MADD_Q_32 = 0x02,
+ OPC2_32_RRR1_MADD_Q_64 = 0x1b,
+ OPC2_32_RRR1_MADD_Q_32_L = 0x01,
+ OPC2_32_RRR1_MADD_Q_64_L = 0x19,
+ OPC2_32_RRR1_MADD_Q_32_U = 0x00,
+ OPC2_32_RRR1_MADD_Q_64_U = 0x18,
+ OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
+ OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
+ OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
+ OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
+ OPC2_32_RRR1_MADDS_Q_32 = 0x22,
+ OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
+ OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
+ OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
+ OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
+ OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
+ OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
+ OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
+ OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
+ OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
+ OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
+ OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
+ OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
+ OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
+ OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
+ OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
+};
+/* OPCM_32_RRR1_MADDSU_H */
+enum {
+ OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
+ OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
+ OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
+ OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MSUB_H */
+enum {
+ OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
+ OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
+ OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
+ OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MSUB_Q */
+enum {
+ OPC2_32_RRR1_MSUB_Q_32 = 0x02,
+ OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
+ OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
+ OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
+ OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
+ OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
+ OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
+ OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
+ OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
+ OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
+ OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
+ OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
+ OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
+ OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
+ OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
+ OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
+ OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
+ OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
+ OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
+ OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
+ OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
+ OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
+ OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
+ OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
+ OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
+ OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
+};
+/* OPCM_32_RRR1_MSUBADS_H */
+enum {
+ OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
+ OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
+ OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
+ OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
+};
+/*
+ * RRR2 Format
+ */
+/* OPCM_32_RRR2_MADD */
+enum {
+ OPC2_32_RRR2_MADD_32 = 0x0a,
+ OPC2_32_RRR2_MADD_64 = 0x6a,
+ OPC2_32_RRR2_MADDS_32 = 0x8a,
+ OPC2_32_RRR2_MADDS_64 = 0xea,
+ OPC2_32_RRR2_MADD_U_32 = 0x68,
+ OPC2_32_RRR2_MADDS_U_32 = 0x88,
+ OPC2_32_RRR2_MADDS_U_64 = 0xe8,
+};
+/* OPCM_32_RRR2_MSUB */
+enum {
+ OPC2_32_RRR2_MSUB_32 = 0x0a,
+ OPC2_32_RRR2_MSUB_64 = 0x6a,
+ OPC2_32_RRR2_MSUBS_32 = 0x8a,
+ OPC2_32_RRR2_MSUBS_64 = 0xea,
+ OPC2_32_RRR2_MSUB_U_64 = 0x68,
+ OPC2_32_RRR2_MSUBS_U_32 = 0x88,
+ OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
+};
+/*
+ * RRRR Format
+ */
+/* OPCM_32_RRRR_EXTRACT_INSERT */
+enum {
+ OPC2_32_RRRR_DEXTR = 0x04,
+ OPC2_32_RRRR_EXTR = 0x02,
+ OPC2_32_RRRR_EXTR_U = 0x03,
+ OPC2_32_RRRR_INSERT = 0x00,
+};
+/*
+ * RRRW Format
+ */
+/* OPCM_32_RRRW_EXTRACT_INSERT */
+enum {
+ OPC2_32_RRRW_EXTR = 0x02,
+ OPC2_32_RRRW_EXTR_U = 0x03,
+ OPC2_32_RRRW_IMASK = 0x01,
+ OPC2_32_RRRW_INSERT = 0x00,
+};
+/*
+ * SYS Format
+ */
+/* OPCM_32_SYS_INTERRUPTS */
+enum {
+ OPC2_32_SYS_DEBUG = 0x04,
+ OPC2_32_SYS_DISABLE = 0x0d,
+ OPC2_32_SYS_DSYNC = 0x12,
+ OPC2_32_SYS_ENABLE = 0x0c,
+ OPC2_32_SYS_ISYNC = 0x13,
+ OPC2_32_SYS_NOP = 0x00,
+ OPC2_32_SYS_RET = 0x06,
+ OPC2_32_SYS_RFE = 0x07,
+ OPC2_32_SYS_RFM = 0x05,
+ OPC2_32_SYS_RSLCX = 0x09,
+ OPC2_32_SYS_SVLCX = 0x08,
+ OPC2_32_SYS_TRAPSV = 0x15,
+ OPC2_32_SYS_TRAPV = 0x14,
+};
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (4 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-08 2:58 ` Richard Henderson
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
` (8 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v3 -> v4:
- Remove gen_calc_psw_sv, gen_calc_psw_av, gen_calc_psw_sav functions.
- Replace gen_calc_psw_sv, gen_calc_psw_sav, gen_calc_psw_av calls.
- Rename gen_add_i32 to gen_add_d.
- Remove psw calculation from ADD_A.
- Replace makro OP_COND with function gen_cond_add, gen_cond_addi.
- gen_shaci now uses only 32 bit tcg shifts and implments special case of exactly 32 bit long shift.
- gen_cond_add now sets V and AV bits conditionaly through temp registers.
target-tricore/helper.h | 16 ++++
target-tricore/translate.c | 222 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index e69de29..5884240 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 0d30c51..ed2bf9b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -27,6 +27,7 @@
#include "exec/helper-gen.h"
#include "tricore-opcodes.h"
+
/*
* TCG registers
*/
@@ -102,8 +103,229 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
}
+/*
+ * Functions to generate micro-ops
+ */
+
+/* Functions for arithmetic instructions */
+
+static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
+{
+ TCGv t0 = tcg_temp_new_i32();
+ /* Addition and set V/SV bits */
+ tcg_gen_add_tl(ret, r1, r2);
+ /* calc V bit */
+ tcg_gen_xor_tl(cpu_PSW_V, ret, r1);
+ tcg_gen_xor_tl(t0, r1, r2);
+ tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
+ /* Calc SV bit */
+ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ /* Calc AV/SAV bits */
+ tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ /* calc SAV */
+ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_add_d(ret, r1, temp);
+ tcg_temp_free(temp);
+}
+
+static inline void gen_cond_add(int cond, TCGv r1, TCGv r2, TCGv r3,
+ TCGv r4)
+{
+ TCGv temp = tcg_temp_new();
+ TCGv temp2 = tcg_temp_new();
+ TCGv t0 = tcg_const_i32(0);
+
+ tcg_gen_add_tl(temp, r1, r2);
+ tcg_gen_movcond_tl(cond, r3, r4, t0, temp, r3);
+ /* Calc PSW_V */
+ tcg_gen_xor_tl(temp, temp, r1);
+ tcg_gen_xor_tl(temp, r1, r2);
+ tcg_gen_andc_tl(temp2, temp, t0);
+ tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp2, cpu_PSW_V);
+ /* Set PSW_SV */
+ tcg_gen_or_tl(cpu_PSW_SV, temp2, cpu_PSW_SV);
+ /* calc AV bit */
+ tcg_gen_add_tl(temp2, temp2, temp);
+ tcg_gen_xor_tl(temp2, temp2, temp);
+ tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp2, cpu_PSW_AV);
+ /* calc SAV bit */
+ tcg_gen_or_tl(cpu_PSW_SAV, temp2, cpu_PSW_SAV);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+}
+
+static inline void gen_condi_add(int cond, TCGv r1, int32_t r2,
+ TCGv r3, TCGv r4)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_cond_add(cond, r1, temp, r3, r4);
+ tcg_temp_free(temp);
+}
+
+static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
+{
+ if (shift_count == -32) {
+ tcg_gen_movi_tl(ret, 0);
+ } else if (shift_count >= 0) {
+ tcg_gen_shli_tl(ret, r1, shift_count);
+ } else {
+ tcg_gen_shri_tl(ret, r1, (-shift_count));
+ }
+}
+
+static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
+{
+ uint32_t msk, msk_start;
+ TCGv temp = tcg_temp_new();
+ TCGv temp2 = tcg_temp_new();
+ TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
+ TCGv t_min = tcg_const_i32(-(0x80000000L) >> shift_count);
+ TCGv t_0 = tcg_const_i32(0);
+
+ if (shift_count == 0) {
+ /* Clear PSW.C */
+ tcg_gen_movi_tl(cpu_PSW_C, 0);
+ tcg_gen_mov_tl(ret, r1);
+ } else if (shift_count == 32) {
+ /* fill ret completly with sign bit */
+ tcg_gen_sari_tl(ret, r1, 31);
+ } else if (shift_count > 0) {
+ tcg_gen_shli_tl(ret, r1, shift_count);
+ /* calc carry */
+ msk_start = 32 - shift_count;
+ msk = ((1 << shift_count) - 1) << msk_start;
+ tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
+ /* calc v/sv bits */
+ tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
+ tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
+ tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
+ /* calc sv */
+ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
+ } else {
+ tcg_gen_sari_tl(ret, r1, -(shift_count));
+ /* calc carry */
+ msk = (1 << (shift_count - 1)) - 1;
+ tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
+ }
+ /* calc av overflow bit */
+ tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ /* calc sav overflow bit */
+ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+ tcg_temp_free(t_0);
+ tcg_temp_free(t_max);
+ tcg_temp_free(t_min);
+}
+
+/*
+ * Functions for decoding instructions
+ */
+
+static void decode_src_opc(DisasContext *ctx, int op1)
+{
+ int r1;
+ int32_t const4;
+ TCGv temp, temp2;
+
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
+
+ switch (op1) {
+ case OPC1_16_SRC_ADD:
+ gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
+ break;
+ case OPC1_16_SRC_ADD_A15:
+ gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
+ break;
+ case OPC1_16_SRC_ADD_15A:
+ gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
+ break;
+ case OPC1_16_SRC_ADD_A:
+ tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
+ break;
+ case OPC1_16_SRC_CADD:
+ gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_CADDN:
+ gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_CMOV:
+ temp = tcg_const_tl(0);
+ temp2 = tcg_const_tl(const4);
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp2, cpu_gpr_d[r1]);
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+ break;
+ case OPC1_16_SRC_CMOVN:
+ temp = tcg_const_tl(0);
+ temp2 = tcg_const_tl(const4);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp2, cpu_gpr_d[r1]);
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+ break;
+ case OPC1_16_SRC_EQ:
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ const4);
+ break;
+ case OPC1_16_SRC_LT:
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ const4);
+ break;
+ case OPC1_16_SRC_MOV:
+ tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
+ break;
+ case OPC1_16_SRC_MOV_A:
+ tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
+ break;
+ case OPC1_16_SRC_SH:
+ gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
+ break;
+ case OPC1_16_SRC_SHA:
+ gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
+ int op1;
+
+ op1 = MASK_OP_MAJOR(ctx->opcode);
+
+ switch (op1) {
+ case OPC1_16_SRC_ADD:
+ case OPC1_16_SRC_ADD_A15:
+ case OPC1_16_SRC_ADD_15A:
+ case OPC1_16_SRC_ADD_A:
+ case OPC1_16_SRC_CADD:
+ case OPC1_16_SRC_CADDN:
+ case OPC1_16_SRC_CMOV:
+ case OPC1_16_SRC_CMOVN:
+ case OPC1_16_SRC_EQ:
+ case OPC1_16_SRC_LT:
+ case OPC1_16_SRC_MOV:
+ case OPC1_16_SRC_MOV_A:
+ case OPC1_16_SRC_SH:
+ case OPC1_16_SRC_SHA:
+ decode_src_opc(ctx, op1);
+ break;
+ }
}
static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 07/15] target-tricore: Add instructions of SRR opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (5 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
` (7 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v3 -> v4:
- Replace gen_calc_psw_sv, gen_calc_psw_sav, gen_calc_psw_av calls.
- Rename gen_sub_i32 to gen_sub_d.
- Fix V bit calculation in gen_sub_d and gen_mul_i32s.
- helper_add/sub_ssov now uses sign extended arguments.
- Remove unnecessary temp register in gen_adds/_subs.
target-tricore/helper.h | 4 ++
target-tricore/op_helper.c | 43 ++++++++++++
target-tricore/translate.c | 159 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 206 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 5884240..299bd77 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -14,3 +14,7 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+/* Arithmetic */
+DEF_HELPER_3(add_ssov, i32, env, i32, i32)
+DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 2e5981f..6d94f0b 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -20,6 +20,49 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+#define SSOV(env, ret, arg, len) do { \
+ int64_t max_pos = INT##len ##_MAX; \
+ int64_t max_neg = INT##len ##_MIN; \
+ if (arg > max_pos) { \
+ env->PSW_USB_V = 1; \
+ env->PSW_USB_SV = 1; \
+ ret = (target_ulong)max_pos; \
+ } else { \
+ if (arg < max_neg) { \
+ env->PSW_USB_V = 1; \
+ env->PSW_USB_SV = 1; \
+ ret = (target_ulong)max_neg; \
+ } else { \
+ env->PSW_USB_V = 0; \
+ ret = (target_ulong)arg; \
+ } \
+ } \
+ env->PSW_USB_AV = arg ^ arg * 2u; \
+ env->PSW_USB_SAV |= env->PSW_USB_AV; \
+} while (0)
+
+target_ulong helper_add_ssov(CPUTRICOREState *env, target_ulong r1,
+ target_ulong r2)
+{
+ target_ulong ret;
+ int64_t t1 = sextract64(r1, 0, 32);
+ int64_t t2 = sextract64(r2, 0, 32);
+ int64_t result = t1 + t2;
+ SSOV(env, ret, result, 32);
+ return ret;
+}
+
+target_ulong helper_sub_ssov(CPUTRICOREState *env, target_ulong r1,
+ target_ulong r2)
+{
+ target_ulong ret;
+ int64_t t1 = sextract64(r1, 0, 32);
+ int64_t t2 = sextract64(r2, 0, 32);
+ int64_t result = t1 - t2;
+ SSOV(env, ret, result, 32);
+ return ret;
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ed2bf9b..8778f3b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -171,6 +171,48 @@ static inline void gen_condi_add(int cond, TCGv r1, int32_t r2,
tcg_temp_free(temp);
}
+static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
+{
+ TCGv temp = tcg_temp_new_i32();
+
+ tcg_gen_sub_tl(ret, r1, r2);
+ /* calc V bit */
+ tcg_gen_xor_tl(cpu_PSW_V, ret, r1);
+ tcg_gen_xor_tl(temp, r1, r2);
+ tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ /* calc SV bit */
+ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ /* Calc AV bit */
+ tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ /* calc SAV bit */
+ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+
+ tcg_temp_free(temp);
+}
+
+static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
+{
+ TCGv high = tcg_temp_new();
+ TCGv low = tcg_temp_new();
+
+ tcg_gen_muls2_tl(low, high, r1, r2);
+ tcg_gen_mov_tl(ret, low);
+ /* calc V bit */
+ tcg_gen_sari_tl(low, low, 31);
+ tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
+ /* calc SV bit */
+ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ /* Calc AV bit */
+ tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ /* calc SAV bit */
+ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+
+ tcg_temp_free(high);
+ tcg_temp_free(low);
+}
+
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
{
if (shift_count == -32) {
@@ -229,6 +271,16 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
tcg_temp_free(t_min);
}
+static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
+{
+ gen_helper_add_ssov(ret, cpu_env, r1, r2);
+}
+
+static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
+{
+ gen_helper_sub_ssov(ret, cpu_env, r1, r2);
+}
+
/*
* Functions for decoding instructions
*/
@@ -302,6 +354,89 @@ static void decode_src_opc(DisasContext *ctx, int op1)
}
}
+static void decode_srr_opc(DisasContext *ctx, int op1)
+{
+ int r1, r2;
+ TCGv temp;
+
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+
+ switch (op1) {
+ case OPC1_16_SRR_ADD:
+ gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A15:
+ gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_15A:
+ gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A:
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_ADDS:
+ gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_AND:
+ tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_CMOV:
+ temp = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ cpu_gpr_d[r2], cpu_gpr_d[r1]);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_CMOVN:
+ temp = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ cpu_gpr_d[r2], cpu_gpr_d[r1]);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_EQ:
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_LT:
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV:
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_A:
+ tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_AA:
+ tcg_gen_mov_tl(cpu_gpr_a[r2], cpu_gpr_a[r1]);
+ break;
+ case OPC1_16_SRR_MOV_D:
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_MUL:
+ gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_OR:
+ tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB:
+ gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_A15B:
+ gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_15AB:
+ gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUBS:
+ gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_XOR:
+ tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
@@ -325,6 +460,30 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
case OPC1_16_SRC_SHA:
decode_src_opc(ctx, op1);
break;
+/* SRR-format */
+ case OPC1_16_SRR_ADD:
+ case OPC1_16_SRR_ADD_A15:
+ case OPC1_16_SRR_ADD_15A:
+ case OPC1_16_SRR_ADD_A:
+ case OPC1_16_SRR_ADDS:
+ case OPC1_16_SRR_AND:
+ case OPC1_16_SRR_CMOV:
+ case OPC1_16_SRR_CMOVN:
+ case OPC1_16_SRR_EQ:
+ case OPC1_16_SRR_LT:
+ case OPC1_16_SRR_MOV:
+ case OPC1_16_SRR_MOV_A:
+ case OPC1_16_SRR_MOV_AA:
+ case OPC1_16_SRR_MOV_D:
+ case OPC1_16_SRR_MUL:
+ case OPC1_16_SRR_OR:
+ case OPC1_16_SRR_SUB:
+ case OPC1_16_SRR_SUB_A15B:
+ case OPC1_16_SRR_SUB_15AB:
+ case OPC1_16_SRR_SUBS:
+ case OPC1_16_SRR_XOR:
+ decode_srr_opc(ctx, op1);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 08/15] target-tricore: Add instructions of SSR opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (6 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
` (6 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 8778f3b..6f696fb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -437,6 +437,45 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
}
}
+static void decode_ssr_opc(DisasContext *ctx, int op1)
+{
+ int r1, r2;
+
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+
+ switch (op1) {
+ case OPC1_16_SSR_ST_A:
+ tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ break;
+ case OPC1_16_SSR_ST_A_POSTINC:
+ tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ case OPC1_16_SSR_ST_B:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ break;
+ case OPC1_16_SSR_ST_B_POSTINC:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ break;
+ case OPC1_16_SSR_ST_H:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+ break;
+ case OPC1_16_SSR_ST_H_POSTINC:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ break;
+ case OPC1_16_SSR_ST_W:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ break;
+ case OPC1_16_SSR_ST_W_POSTINC:
+ tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
@@ -484,6 +523,17 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
case OPC1_16_SRR_XOR:
decode_srr_opc(ctx, op1);
break;
+/* SSR-format */
+ case OPC1_16_SSR_ST_A:
+ case OPC1_16_SSR_ST_A_POSTINC:
+ case OPC1_16_SSR_ST_B:
+ case OPC1_16_SSR_ST_B_POSTINC:
+ case OPC1_16_SSR_ST_H:
+ case OPC1_16_SSR_ST_H_POSTINC:
+ case OPC1_16_SSR_ST_W:
+ case OPC1_16_SSR_ST_W_POSTINC:
+ decode_ssr_opc(ctx, op1);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (7 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
` (5 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 6f696fb..5ddbc84 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -107,6 +107,26 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
* Functions to generate micro-ops
*/
+/* Functions for load/save to/from memory */
+
+static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, TCGMemOp mop)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, r2, con);
+ tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_temp_free(temp);
+}
+
+static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, TCGMemOp mop)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, r2, con);
+ tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_temp_free(temp);
+}
+
/* Functions for arithmetic instructions */
static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
@@ -479,6 +499,9 @@ static void decode_ssr_opc(DisasContext *ctx, int op1)
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
+ int r1, r2;
+ int32_t const16;
+ TCGv temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
@@ -534,6 +557,37 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
case OPC1_16_SSR_ST_W_POSTINC:
decode_ssr_opc(ctx, op1);
break;
+/* SRRS-format */
+ case OPC1_16_SRRS_ADDSC_A:
+ r2 = MASK_OP_SRRS_S2(ctx->opcode);
+ r1 = MASK_OP_SRRS_S1D(ctx->opcode);
+ const16 = MASK_OP_SRRS_N(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
+ tcg_temp_free(temp);
+ break;
+/* SLRO-format */
+ case OPC1_16_SLRO_LD_A:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SLRO_LD_BU:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
+ break;
+ case OPC1_16_SLRO_LD_H:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
+ break;
+ case OPC1_16_SLRO_LD_W:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 10/15] target-tricore: Add instructions of SB opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (8 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
` (4 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v3 -> v4:
- Add missing break in gen_compute_branch at CALL insn.
target-tricore/helper.h | 3 +
target-tricore/op_helper.c | 180 +++++++++++++++++++++++++++++++++++++++++++++
target-tricore/translate.c | 89 ++++++++++++++++++++++
3 files changed, 272 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 299bd77..adf5b26 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -18,3 +18,6 @@
/* Arithmetic */
DEF_HELPER_3(add_ssov, i32, env, i32, i32)
DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
+/* CSA */
+DEF_HELPER_2(call, void, env, i32)
+DEF_HELPER_1(ret, void, env)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 6d94f0b..0006d44 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -63,6 +63,186 @@ target_ulong helper_sub_ssov(CPUTRICOREState *env, target_ulong r1,
return ret;
}
+/* context save area (CSA) related helpers */
+
+static int cdc_increment(target_ulong *psw)
+{
+ if ((*psw & MASK_PSW_CDC) == 0x7f) {
+ return 0;
+ }
+
+ (*psw)++;
+ /* check for overflow */
+ int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
+ int mask = (1u << (7 - lo)) - 1;
+ int count = *psw & mask;
+ if (count == 0) {
+ (*psw)--;
+ return 1;
+ }
+ return 0;
+}
+
+static int cdc_decrement(target_ulong *psw)
+{
+ if ((*psw & MASK_PSW_CDC) == 0x7f) {
+ return 0;
+ }
+ /* check for underflow */
+ int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
+ int mask = (1u << (7 - lo)) - 1;
+ int count = *psw & mask;
+ if (count == 0) {
+ return 1;
+ }
+ (*psw)--;
+ return 0;
+}
+
+static void save_context_upper(CPUTRICOREState *env, int ea,
+ target_ulong *new_FCX)
+{
+ *new_FCX = cpu_ldl_data(env, ea);
+ cpu_stl_data(env, ea, env->PCXI);
+ cpu_stl_data(env, ea+4, env->PSW);
+ cpu_stl_data(env, ea+8, env->gpr_a[10]);
+ cpu_stl_data(env, ea+12, env->gpr_a[11]);
+ cpu_stl_data(env, ea+16, env->gpr_d[8]);
+ cpu_stl_data(env, ea+20, env->gpr_d[9]);
+ cpu_stl_data(env, ea+24, env->gpr_d[10]);
+ cpu_stl_data(env, ea+28, env->gpr_d[11]);
+ cpu_stl_data(env, ea+32, env->gpr_a[12]);
+ cpu_stl_data(env, ea+36, env->gpr_a[13]);
+ cpu_stl_data(env, ea+40, env->gpr_a[14]);
+ cpu_stl_data(env, ea+44, env->gpr_a[15]);
+ cpu_stl_data(env, ea+48, env->gpr_d[12]);
+ cpu_stl_data(env, ea+52, env->gpr_d[13]);
+ cpu_stl_data(env, ea+56, env->gpr_d[14]);
+ cpu_stl_data(env, ea+60, env->gpr_d[15]);
+
+}
+
+static void restore_context_upper(CPUTRICOREState *env, int ea,
+ target_ulong *new_PCXI, target_ulong *new_PSW)
+{
+ *new_PCXI = cpu_ldl_data(env, ea);
+ *new_PSW = cpu_ldl_data(env, ea+4);
+ env->gpr_a[10] = cpu_ldl_data(env, ea+8);
+ env->gpr_a[11] = cpu_ldl_data(env, ea+12);
+ env->gpr_d[8] = cpu_ldl_data(env, ea+16);
+ env->gpr_d[9] = cpu_ldl_data(env, ea+20);
+ env->gpr_d[10] = cpu_ldl_data(env, ea+24);
+ env->gpr_d[11] = cpu_ldl_data(env, ea+28);
+ env->gpr_a[12] = cpu_ldl_data(env, ea+32);
+ env->gpr_a[13] = cpu_ldl_data(env, ea+36);
+ env->gpr_a[14] = cpu_ldl_data(env, ea+40);
+ env->gpr_a[15] = cpu_ldl_data(env, ea+44);
+ env->gpr_d[12] = cpu_ldl_data(env, ea+48);
+ env->gpr_d[13] = cpu_ldl_data(env, ea+52);
+ env->gpr_d[14] = cpu_ldl_data(env, ea+56);
+ env->gpr_d[15] = cpu_ldl_data(env, ea+60);
+ cpu_stl_data(env, ea, env->FCX);
+}
+
+void helper_call(CPUTRICOREState *env, uint32_t next_pc)
+{
+ target_ulong tmp_FCX;
+ target_ulong ea;
+ target_ulong new_FCX;
+ target_ulong psw;
+
+ psw = psw_read(env);
+ /* if (FCX == 0) trap(FCU); */
+ if (env->FCX == 0) {
+ /* FCU trap */
+ }
+ /* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
+ if (psw & MASK_PSW_CDE) {
+ if (cdc_increment(&psw)) {
+ /* CDO trap */
+ }
+ }
+ /* PSW.CDE = 1;*/
+ psw |= MASK_PSW_CDE;
+ /* tmp_FCX = FCX; */
+ tmp_FCX = env->FCX;
+ /* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
+ ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
+ ((env->FCX & MASK_FCX_FCXO) << 6);
+ /* new_FCX = M(EA, word);
+ M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
+ A[12], A[13], A[14], A[15], D[12], D[13], D[14],
+ D[15]}; */
+ save_context_upper(env, ea, &new_FCX);
+
+ /* PCXI.PCPN = ICR.CCPN; */
+ env->PCXI = (env->PCXI & 0xffffff) +
+ ((env->ICR & MASK_ICR_CCPN) << 24);
+ /* PCXI.PIE = ICR.IE; */
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ ((env->ICR & MASK_ICR_IE) << 15));
+ /* PCXI.UL = 1; */
+ env->PCXI |= MASK_PCXI_UL;
+
+ /* PCXI[19: 0] = FCX[19: 0]; */
+ env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
+ /* FCX[19: 0] = new_FCX[19: 0]; */
+ env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
+ /* A[11] = next_pc[31: 0]; */
+ env->gpr_a[11] = next_pc;
+
+ /* if (tmp_FCX == LCX) trap(FCD);*/
+ if (tmp_FCX == env->LCX) {
+ /* FCD trap */
+ }
+ psw_write(env, psw);
+}
+
+void helper_ret(CPUTRICOREState *env)
+{
+ target_ulong ea;
+ target_ulong new_PCXI;
+ target_ulong new_PSW, psw;
+
+ psw = psw_read(env);
+ /* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
+ if (env->PSW & MASK_PSW_CDE) {
+ if (cdc_decrement(&(env->PSW))) {
+ /* CDU trap */
+ }
+ }
+ /* if (PCXI[19: 0] == 0) then trap(CSU); */
+ if ((env->PCXI & 0xfffff) == 0) {
+ /* CSU trap */
+ }
+ /* if (PCXI.UL == 0) then trap(CTYP); */
+ if ((env->PCXI & MASK_PCXI_UL) == 0) {
+ /* CTYP trap */
+ }
+ /* PC = {A11 [31: 1], 1’b0}; */
+ env->PC = env->gpr_a[11] & 0xfffffffe;
+
+ /* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
+ ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
+ ((env->PCXI & MASK_PCXI_PCXO) << 6);
+ /* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
+ A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
+ M(EA, word) = FCX; */
+ restore_context_upper(env, ea, &new_PCXI, &new_PSW);
+ /* FCX[19: 0] = PCXI[19: 0]; */
+ env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
+ /* PCXI = new_PCXI; */
+ env->PCXI = new_PCXI;
+
+ if (tricore_feature(env, TRICORE_FEATURE_13)) {
+ /* PSW = new_PSW */
+ psw_write(env, new_PSW);
+ } else {
+ /* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
+ psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
+ }
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5ddbc84..18bfffb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -107,6 +107,14 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
* Functions to generate micro-ops
*/
+/* Makros for generating helpers */
+
+#define gen_helper_1arg(name, arg) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg); \
+ gen_helper_##name(cpu_env, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while (0)
+
/* Functions for load/save to/from memory */
static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
@@ -301,6 +309,78 @@ static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
gen_helper_sub_ssov(ret, cpu_env, r1, r2);
}
+/* helpers for generating program flow micro-ops */
+
+static inline void gen_save_pc(target_ulong pc)
+{
+ tcg_gen_movi_tl(cpu_PC, pc);
+}
+
+static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+{
+ TranslationBlock *tb;
+ tb = ctx->tb;
+ if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
+ likely(!ctx->singlestep_enabled)) {
+ tcg_gen_goto_tb(n);
+ gen_save_pc(dest);
+ tcg_gen_exit_tb((uintptr_t)tb + n);
+ } else {
+ gen_save_pc(dest);
+ if (ctx->singlestep_enabled) {
+ /* raise exception debug */
+ }
+ tcg_gen_exit_tb(0);
+ }
+}
+
+static inline void gen_branch_cond(DisasContext *ctx, int cond, TCGv r1,
+ TCGv r2, int16_t address)
+{
+ int jumpLabel;
+ jumpLabel = gen_new_label();
+ tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
+
+ gen_goto_tb(ctx, 1, ctx->next_pc);
+
+ gen_set_label(jumpLabel);
+ gen_goto_tb(ctx, 0, ctx->pc + address * 2);
+}
+
+static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
+ int r2, int16_t address)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_branch_cond(ctx, cond, r1, temp, address);
+ tcg_temp_free(temp);
+}
+
+static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
+ int r2 , int32_t constant , int32_t offset)
+{
+ switch (opc) {
+/* SB-format jumps */
+ case OPC1_16_SB_J:
+ case OPC1_32_B_J:
+ gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
+ break;
+ case OPC1_16_SB_CALL:
+ gen_helper_1arg(call, ctx->next_pc);
+ gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
+ break;
+ case OPC1_16_SB_JZ:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
+ break;
+ case OPC1_16_SB_JNZ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
+ break;
+ default:
+ printf("Branch Error at %x\n", ctx->pc);
+ }
+ ctx->bstate = BS_BRANCH;
+}
+
+
/*
* Functions for decoding instructions
*/
@@ -501,6 +581,7 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
int op1;
int r1, r2;
int32_t const16;
+ int32_t address;
TCGv temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
@@ -588,6 +669,14 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
+/* SB-format */
+ case OPC1_16_SB_CALL:
+ case OPC1_16_SB_J:
+ case OPC1_16_SB_JNZ:
+ case OPC1_16_SB_JZ:
+ address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, 0, address);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 11/15] target-tricore: Add instructions of SBC and SBRN opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (9 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
` (3 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/translate.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 18bfffb..9a03544 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -358,6 +358,8 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
+ TCGv temp;
+
switch (opc) {
/* SB-format jumps */
case OPC1_16_SB_J:
@@ -374,6 +376,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
case OPC1_16_SB_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
break;
+/* SBC-format jumps */
+ case OPC1_16_SBC_JEQ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+ case OPC1_16_SBC_JNE:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+/* SBRN-format jumps */
+ case OPC1_16_SBRN_JZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SBRN_JNZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
+ tcg_temp_free(temp);
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -677,6 +699,20 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
+/* SBC-format */
+ case OPC1_16_SBC_JEQ:
+ case OPC1_16_SBC_JNE:
+ address = MASK_OP_SBC_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+/* SBRN-format */
+ case OPC1_16_SBRN_JNZ_T:
+ case OPC1_16_SBRN_JZ_T:
+ address = MASK_OP_SBRN_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBRN_N(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 12/15] target-tricore: Add instructions of SBR opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (10 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
` (2 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 9a03544..eb7be30 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -355,6 +355,18 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
tcg_temp_free(temp);
}
+static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
+{
+ int l1;
+ l1 = gen_new_label();
+
+ tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
+ gen_goto_tb(ctx, 1, ctx->pc + offset);
+ gen_set_label(l1);
+ gen_goto_tb(ctx, 0, ctx->next_pc);
+}
+
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
@@ -396,8 +408,44 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
tcg_temp_free(temp);
break;
+/* SBR-format jumps */
+ case OPC1_16_SBR_JEQ:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNE:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNZ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JNZ_A:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGEZ:
+ gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGTZ:
+ gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLEZ:
+ gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLTZ:
+ gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ_A:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_LOOP:
+ gen_loop(ctx, r1, offset * 2 - 32);
+ break;
default:
- printf("Branch Error at %x\n", ctx->pc);
+ printf("Branch Error at %x\n", ctx->pc);
}
ctx->bstate = BS_BRANCH;
}
@@ -713,6 +761,22 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SBRN_N(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
+/* SBR-format */
+ case OPC1_16_SBR_JEQ:
+ case OPC1_16_SBR_JGEZ:
+ case OPC1_16_SBR_JGTZ:
+ case OPC1_16_SBR_JLEZ:
+ case OPC1_16_SBR_JLTZ:
+ case OPC1_16_SBR_JNE:
+ case OPC1_16_SBR_JNZ:
+ case OPC1_16_SBR_JNZ_A:
+ case OPC1_16_SBR_JZ:
+ case OPC1_16_SBR_JZ_A:
+ case OPC1_16_SBR_LOOP:
+ r1 = MASK_OP_SBR_S2(ctx->opcode);
+ address = MASK_OP_SBR_DISP4(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, address);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 13/15] target-tricore: Add instructions of SC opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (11 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/helper.h | 1 +
target-tricore/op_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
target-tricore/translate.c | 48 +++++++++++++++++++++++++++++++++++++
3 files changed, 108 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index adf5b26..3c73234 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -21,3 +21,4 @@ DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)
+DEF_HELPER_2(bisr, void, env, i32)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 0006d44..c9cf0de 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -122,6 +122,28 @@ static void save_context_upper(CPUTRICOREState *env, int ea,
}
+static void save_context_lower(CPUTRICOREState *env, int ea,
+ target_ulong *new_FCX)
+{
+ *new_FCX = cpu_ldl_data(env, ea);
+ cpu_stl_data(env, ea, env->PCXI);
+ cpu_stl_data(env, ea+4, env->PSW);
+ cpu_stl_data(env, ea+8, env->gpr_a[2]);
+ cpu_stl_data(env, ea+12, env->gpr_a[3]);
+ cpu_stl_data(env, ea+16, env->gpr_d[0]);
+ cpu_stl_data(env, ea+20, env->gpr_d[1]);
+ cpu_stl_data(env, ea+24, env->gpr_d[2]);
+ cpu_stl_data(env, ea+28, env->gpr_d[3]);
+ cpu_stl_data(env, ea+32, env->gpr_a[4]);
+ cpu_stl_data(env, ea+36, env->gpr_a[5]);
+ cpu_stl_data(env, ea+40, env->gpr_a[6]);
+ cpu_stl_data(env, ea+44, env->gpr_a[7]);
+ cpu_stl_data(env, ea+48, env->gpr_d[4]);
+ cpu_stl_data(env, ea+52, env->gpr_d[5]);
+ cpu_stl_data(env, ea+56, env->gpr_d[6]);
+ cpu_stl_data(env, ea+60, env->gpr_d[7]);
+}
+
static void restore_context_upper(CPUTRICOREState *env, int ea,
target_ulong *new_PCXI, target_ulong *new_PSW)
{
@@ -243,6 +265,43 @@ void helper_ret(CPUTRICOREState *env)
}
}
+void helper_bisr(CPUTRICOREState *env, uint32_t const9)
+{
+ target_ulong tmp_FCX;
+ target_ulong ea;
+ target_ulong new_FCX;
+
+ if (env->FCX == 0) {
+ /* FCU trap */
+ }
+
+ tmp_FCX = env->FCX;
+ ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
+
+ save_context_lower(env, ea, &new_FCX);
+
+ /* PCXI.PCPN = ICR.CCPN */
+ env->PCXI = (env->PCXI & 0xffffff) +
+ ((env->ICR & MASK_ICR_CCPN) << 24);
+ /* PCXI.PIE = ICR.IE */
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ ((env->ICR & MASK_ICR_IE) << 15));
+ /* PCXI.UL = 0 */
+ env->PCXI &= ~(MASK_PCXI_UL);
+ /* PCXI[19: 0] = FCX[19: 0] */
+ env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
+ /* FXC[19: 0] = new_FCX[19: 0] */
+ env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
+ /* ICR.IE = 1 */
+ env->ICR |= MASK_ICR_IE;
+
+ env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
+
+ if (tmp_FCX == env->LCX) {
+ /* FCD trap */
+ }
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index eb7be30..ce90a60 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -646,6 +646,42 @@ static void decode_ssr_opc(DisasContext *ctx, int op1)
}
}
+static void decode_sc_opc(DisasContext *ctx, int op1)
+{
+ int32_t const16;
+
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+
+ switch (op1) {
+ case OPC1_16_SC_AND:
+ tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_BISR:
+ gen_helper_1arg(bisr, const16 & 0xff);
+ break;
+ case OPC1_16_SC_LD_A:
+ gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SC_LD_W:
+ gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SC_MOV:
+ tcg_gen_movi_tl(cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_OR:
+ tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_ST_A:
+ gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SC_ST_W:
+ gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SC_SUB_A:
+ tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
+ break;
+ }
+}
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
@@ -777,6 +813,18 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
break;
+/* SC-format */
+ case OPC1_16_SC_AND:
+ case OPC1_16_SC_BISR:
+ case OPC1_16_SC_LD_A:
+ case OPC1_16_SC_LD_W:
+ case OPC1_16_SC_MOV:
+ case OPC1_16_SC_OR:
+ case OPC1_16_SC_ST_A:
+ case OPC1_16_SC_ST_W:
+ case OPC1_16_SC_SUB_A:
+ decode_sc_opc(ctx, op1);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (12 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-tricore/translate.c | 121 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ce90a60..0bb6ea1 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -682,6 +682,84 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
break;
}
}
+
+static void decode_slr_opc(DisasContext *ctx, int op1)
+{
+ int r1, r2;
+
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+
+ switch (op1) {
+/* SLR-format */
+ case OPC1_16_SLR_LD_A:
+ tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ break;
+ case OPC1_16_SLR_LD_A_POSTINC:
+ tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ case OPC1_16_SLR_LD_BU:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ break;
+ case OPC1_16_SLR_LD_BU_POSTINC:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ break;
+ case OPC1_16_SLR_LD_H:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ break;
+ case OPC1_16_SLR_LD_H_POSTINC:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ break;
+ case OPC1_16_SLR_LD_W:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ break;
+ case OPC1_16_SLR_LD_W_POSTINC:
+ tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ }
+}
+
+static void decode_sro_opc(DisasContext *ctx, int op1)
+{
+ int r2;
+ int32_t address;
+
+ r2 = MASK_OP_SRO_S2(ctx->opcode);
+ address = MASK_OP_SRO_OFF4(ctx->opcode);
+
+/* SRO-format */
+ switch (op1) {
+ case OPC1_16_SRO_LD_A:
+ gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+ break;
+ case OPC1_16_SRO_LD_BU:
+ gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
+ break;
+ case OPC1_16_SRO_LD_H:
+ gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
+ break;
+ case OPC1_16_SRO_LD_W:
+ gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+ break;
+ case OPC1_16_SRO_ST_A:
+ gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+ break;
+ case OPC1_16_SRO_ST_B:
+ gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
+ break;
+ case OPC1_16_SRO_ST_H:
+ gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
+ break;
+ case OPC1_16_SRO_ST_W:
+ gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
@@ -825,6 +903,49 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
case OPC1_16_SC_SUB_A:
decode_sc_opc(ctx, op1);
break;
+/* SLR-format */
+ case OPC1_16_SLR_LD_A:
+ case OPC1_16_SLR_LD_A_POSTINC:
+ case OPC1_16_SLR_LD_BU:
+ case OPC1_16_SLR_LD_BU_POSTINC:
+ case OPC1_16_SLR_LD_H:
+ case OPC1_16_SLR_LD_H_POSTINC:
+ case OPC1_16_SLR_LD_W:
+ case OPC1_16_SLR_LD_W_POSTINC:
+ decode_slr_opc(ctx, op1);
+ break;
+/* SRO-format */
+ case OPC1_16_SRO_LD_A:
+ case OPC1_16_SRO_LD_BU:
+ case OPC1_16_SRO_LD_H:
+ case OPC1_16_SRO_LD_W:
+ case OPC1_16_SRO_ST_A:
+ case OPC1_16_SRO_ST_B:
+ case OPC1_16_SRO_ST_H:
+ case OPC1_16_SRO_ST_W:
+ decode_sro_opc(ctx, op1);
+ break;
+/* SSRO-format */
+ case OPC1_16_SSRO_ST_A:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SSRO_ST_B:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
+ break;
+ case OPC1_16_SSRO_ST_H:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
+ break;
+ case OPC1_16_SSRO_ST_W:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v4 15/15] target-tricore: Add instructions of SR opcode format
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (13 preceding siblings ...)
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
@ 2014-08-07 14:34 ` Bastian Koppelmann
14 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-07 14:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v3 -> v4:
- Replace first movcond with tcg_gen_setcond and second with tcg_gen_or at RSUB insn.
- Add AV, SAV calculation to RSUB insn.
target-tricore/helper.h | 1 +
target-tricore/op_helper.c | 52 +++++++++++++++++++++
target-tricore/translate.c | 113 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 3c73234..7b7d74b 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -22,3 +22,4 @@ DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)
DEF_HELPER_2(bisr, void, env, i32)
+DEF_HELPER_1(rfe, void, env)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index c9cf0de..44bdb27 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -99,6 +99,21 @@ static int cdc_decrement(target_ulong *psw)
return 0;
}
+static bool cdc_zero(target_ulong *psw)
+{
+ int cdc = *psw & MASK_PSW_CDC;
+ /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
+ 7'b1111111, otherwise returns FALSE. */
+ if (cdc == 0x7f) {
+ return true;
+ }
+ /* find CDC.COUNT */
+ int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
+ int mask = (1u << (7 - lo)) - 1;
+ int count = *psw & mask;
+ return count == 0;
+}
+
static void save_context_upper(CPUTRICOREState *env, int ea,
target_ulong *new_FCX)
{
@@ -302,6 +317,43 @@ void helper_bisr(CPUTRICOREState *env, uint32_t const9)
}
}
+void helper_rfe(CPUTRICOREState *env)
+{
+ target_ulong ea;
+ target_ulong new_PCXI;
+ target_ulong new_PSW;
+ /* if (PCXI[19: 0] == 0) then trap(CSU); */
+ if ((env->PCXI & 0xfffff) == 0) {
+ /* raise csu trap */
+ }
+ /* if (PCXI.UL == 0) then trap(CTYP); */
+ if ((env->PCXI & MASK_PCXI_UL) == 0) {
+ /* raise CTYP trap */
+ }
+ /* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
+ if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
+ /* raise MNG trap */
+ }
+ /* ICR.IE = PCXI.PIE; */
+ env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
+ /* ICR.CCPN = PCXI.PCPN; */
+ env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
+ ((env->PCXI & MASK_PCXI_PCPN) >> 24);
+ /*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
+ ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
+ ((env->PCXI & MASK_PCXI_PCXO) << 6);
+ /*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
+ A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
+ M(EA, word) = FCX;*/
+ restore_context_upper(env, ea, &new_PCXI, &new_PSW);
+ /* FCX[19: 0] = PCXI[19: 0]; */
+ env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
+ /* PCXI = new_PCXI; */
+ env->PCXI = new_PCXI;
+ /* write psw */
+ psw_write(env, new_PSW);
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 0bb6ea1..2b95cd9 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -241,6 +241,29 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
tcg_temp_free(low);
}
+static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
+{
+ TCGv sat_neg = tcg_const_i32(low);
+ TCGv temp = tcg_const_i32(up);
+
+ /* sat_neg = (arg < low ) ? low : arg; */
+ tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, arg, sat_neg);
+
+ /* ret = (sat_neg > up ) ? up : sat_neg; */
+ tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
+
+ tcg_temp_free(sat_neg);
+ tcg_temp_free(temp);
+}
+
+static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
+{
+ TCGv temp = tcg_const_i32(up);
+ /* sat_neg = (arg > up ) ? up : arg; */
+ tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
+ tcg_temp_free(temp);
+}
+
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
{
if (shift_count == -32) {
@@ -444,6 +467,15 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
case OPC1_16_SBR_LOOP:
gen_loop(ctx, r1, offset * 2 - 32);
break;
+/* SR-format jumps */
+ case OPC1_16_SR_JI:
+ tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
+ tcg_gen_exit_tb(0);
+ break;
+ case OPC2_16_SR_RET:
+ gen_helper_ret(cpu_env);
+ tcg_gen_exit_tb(0);
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -760,6 +792,69 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
}
}
+static void decode_sr_system(CPUTRICOREState *env, DisasContext *ctx)
+{
+ uint32_t op2;
+ op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+ switch (op2) {
+ case OPC2_16_SR_NOP:
+ break;
+ case OPC2_16_SR_RET:
+ gen_compute_branch(ctx, op2, 0, 0, 0, 0);
+ break;
+ case OPC2_16_SR_RFE:
+ gen_helper_rfe(cpu_env);
+ tcg_gen_exit_tb(0);
+ ctx->bstate = BS_BRANCH;
+ break;
+ case OPC2_16_SR_DEBUG:
+ /* raise EXCP_DEBUG */
+ break;
+ }
+}
+
+static void decode_sr_accu(CPUTRICOREState *env, DisasContext *ctx)
+{
+ uint32_t op2;
+ uint32_t r1;
+ TCGv temp;
+
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+ switch (op2) {
+ case OPC2_16_SR_RSUB:
+ /* overflow only if r1 = -0x80000000 */
+ temp = tcg_const_i32(-0x80000000);
+ /* calc V bit */
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
+ /* calc SV bit */
+ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ /* sub */
+ tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ /* calc av */
+ tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
+ /* calc sav */
+ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_temp_free(temp);
+ break;
+ case OPC2_16_SR_SAT_B:
+ gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
+ break;
+ case OPC2_16_SR_SAT_BU:
+ gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
+ break;
+ case OPC2_16_SR_SAT_H:
+ gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
+ break;
+ case OPC2_16_SR_SAT_HU:
+ gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
@@ -946,6 +1041,24 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
+/* SR-format */
+ case OPCM_16_SR_SYSTEM:
+ decode_sr_system(env, ctx);
+ break;
+ case OPCM_16_SR_ACCU:
+ decode_sr_accu(env, ctx);
+ break;
+ case OPC1_16_SR_JI:
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, 0);
+ break;
+ case OPC1_16_SR_NOT:
+ if (MASK_OP_SR_OP2(ctx->opcode) == 0x0) {
+ break;
+ }
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ break;
}
}
--
2.0.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
@ 2014-08-08 2:28 ` Richard Henderson
2014-08-08 10:40 ` Bastian Koppelmann
2014-08-11 16:06 ` Bastian Koppelmann
0 siblings, 2 replies; 21+ messages in thread
From: Richard Henderson @ 2014-08-08 2:28 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
> + /* PSW flag cache for faster execution
> + if flag != 0 then flag is set. Else flag is not set.
> + */
> + target_ulong PSW_USB_C;
> + target_ulong PSW_USB_V;
> + target_ulong PSW_USB_SV;
> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
V and SV are also only set if bit 31 is set, the way we're computing overflow
from addition. Of course, overflow from saturation or multiplication isn't
being computed into bit 31, so there is a decision to make.
Depending on how important it is for ADDX+ADDC to be implemented efficiently,
vs how important is for SHA to be quick, you may wish to have C already set to
0/1 only.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
@ 2014-08-08 2:58 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2014-08-08 2:58 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
> +static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
> +{
> + TCGv t0 = tcg_temp_new_i32();
> + /* Addition and set V/SV bits */
> + tcg_gen_add_tl(ret, r1, r2);
> + /* calc V bit */
> + tcg_gen_xor_tl(cpu_PSW_V, ret, r1);
> + tcg_gen_xor_tl(t0, r1, r2);
> + tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
I'd prefer not to see a v5 until you've actually tested some of this. If that
requires that you implement some of the 32-bit instructions, so be it.
You cannot overwrite any of the inputs until you've computed overflow. Since
you're passing the cpu_gpr_d variables directly, which means that any insn that
computes a = a + b overwrites r1 before you've used it in either xor.
> +static inline void gen_cond_add(int cond, TCGv r1, TCGv r2, TCGv r3,
> + TCGv r4)
The type of cond should be TCGCond.
> + /* Calc PSW_V */
> + tcg_gen_xor_tl(temp, temp, r1);
> + tcg_gen_xor_tl(temp, r1, r2);
> + tcg_gen_andc_tl(temp2, temp, t0);
> + tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp2, cpu_PSW_V);
> + /* Set PSW_SV */
> + tcg_gen_or_tl(cpu_PSW_SV, temp2, cpu_PSW_SV);
> + /* calc AV bit */
> + tcg_gen_add_tl(temp2, temp2, temp);
> + tcg_gen_xor_tl(temp2, temp2, temp);
> + tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp2, cpu_PSW_AV);
> + /* calc SAV bit */
> + tcg_gen_or_tl(cpu_PSW_SAV, temp2, cpu_PSW_SAV);
The sticky bits still need a movcond. Or create a setcond mask like
mask = r4 cond 0
mask = mask << 31
temp2 &= mask
PSW_SV |= temp2;
...
temp2 &= mask
PSW_SAV |= temp2
> +static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
> +{
> + uint32_t msk, msk_start;
> + TCGv temp = tcg_temp_new();
> + TCGv temp2 = tcg_temp_new();
> + TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
> + TCGv t_min = tcg_const_i32(-(0x80000000L) >> shift_count);
These constants are only used in the shift_count > 0 case, and indeed cannot be
computed except within the shift_count > 0 case without provoking underined
behaviour.
> + if (shift_count == 0) {
> + /* Clear PSW.C */
> + tcg_gen_movi_tl(cpu_PSW_C, 0);
> + tcg_gen_mov_tl(ret, r1);
Also clear V.
> + } else if (shift_count == 32) {
> + /* fill ret completly with sign bit */
> + tcg_gen_sari_tl(ret, r1, 31);
Should be shift_count == -32; also clear V.
> + } else if (shift_count > 0) {
> + tcg_gen_shli_tl(ret, r1, shift_count);
> + /* calc carry */
> + msk_start = 32 - shift_count;
> + msk = ((1 << shift_count) - 1) << msk_start;
> + tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
> + /* calc v/sv bits */
> + tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
> + tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
> + tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
> + /* calc sv */
> + tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
You must compute C and V before overwriting r1.
> + } else {
> + tcg_gen_sari_tl(ret, r1, -(shift_count));
> + /* calc carry */
> + msk = (1 << (shift_count - 1)) - 1;
> + tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
Likewise, and clear V.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu
2014-08-08 2:28 ` Richard Henderson
@ 2014-08-08 10:40 ` Bastian Koppelmann
2014-08-08 11:35 ` Bastian Koppelmann
2014-08-11 16:06 ` Bastian Koppelmann
1 sibling, 1 reply; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-08 10:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 08/08/2014 03:28 AM, Richard Henderson wrote:
> On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
>> + /* PSW flag cache for faster execution
>> + if flag != 0 then flag is set. Else flag is not set.
>> + */
>> + target_ulong PSW_USB_C;
>> + target_ulong PSW_USB_V;
>> + target_ulong PSW_USB_SV;
>> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
>> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
> V and SV are also only set if bit 31 is set, the way we're computing overflow
> from addition. Of course, overflow from saturation or multiplication isn't
> being computed into bit 31, so there is a decision to make.
I would not define V and SV as bit 31. It would not change the
generation of add/sub insn, but adds additional tcg insn to mul and
saturation. It would just help the psw_write/_read helpers, which are
not that often called. But maybe I'm missing future insn that might
benefit :).
> Depending on how important it is for ADDX+ADDC to be implemented efficiently,
> vs how important is for SHA to be quick, you may wish to have C already set to
> 0/1 only.
>
>
> r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu
2014-08-08 10:40 ` Bastian Koppelmann
@ 2014-08-08 11:35 ` Bastian Koppelmann
0 siblings, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-08 11:35 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 08/08/2014 11:40 AM, Bastian Koppelmann wrote:
>
> On 08/08/2014 03:28 AM, Richard Henderson wrote:
>> On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
>>> + /* PSW flag cache for faster execution
>>> + if flag != 0 then flag is set. Else flag is not set.
>>> + */
>>> + target_ulong PSW_USB_C;
>>> + target_ulong PSW_USB_V;
>>> + target_ulong PSW_USB_SV;
>>> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is
>>> set. */
>>> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is
>>> set. */
>> V and SV are also only set if bit 31 is set, the way we're computing
>> overflow
>> from addition. Of course, overflow from saturation or multiplication
>> isn't
>> being computed into bit 31, so there is a decision to make.
> I would not define V and SV as bit 31. It would not change the
> generation of add/sub insn, but adds additional tcg insn to mul and
> saturation. It would just help the psw_write/_read helpers, which are
> not that often called. But maybe I'm missing future insn that might
> benefit :).
Never mind. I see the problem now. The computation of the V bit for
add/sub insn will set more than just the 31 bit.
So I would choose to define it as bit 31, to benefit the more common
add/sub insn.
>> Depending on how important it is for ADDX+ADDC to be implemented
>> efficiently,
>> vs how important is for SHA to be quick, you may wish to have C
>> already set to
>> 0/1 only.
>>
>>
>> r~
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu
2014-08-08 2:28 ` Richard Henderson
2014-08-08 10:40 ` Bastian Koppelmann
@ 2014-08-11 16:06 ` Bastian Koppelmann
1 sibling, 0 replies; 21+ messages in thread
From: Bastian Koppelmann @ 2014-08-11 16:06 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 08/08/2014 03:28 AM, Richard Henderson wrote:
> On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
>> + /* PSW flag cache for faster execution
>> + if flag != 0 then flag is set. Else flag is not set.
>> + */
>> + target_ulong PSW_USB_C;
>> + target_ulong PSW_USB_V;
>> + target_ulong PSW_USB_SV;
>> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
>> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
> V and SV are also only set if bit 31 is set, the way we're computing overflow
> from addition. Of course, overflow from saturation or multiplication isn't
> being computed into bit 31, so there is a decision to make.
>
> Depending on how important it is for ADDX+ADDC to be implemented efficiently,
> vs how important is for SHA to be quick, you may wish to have C already set to
> 0/1 only.
Since I don't have data, which instructions are more common, I would
choose the SHA instructions to be fast, because the manual states, that
the most commen instructions are also implemented as 16 bit instructions
and SHA is part of those. So I would leave the carry bit as is, unless
you are sure, that there is a benefit for ADDX+ADDC to be fast.
>
>
> r~
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2014-08-11 15:03 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-07 14:34 [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-08-08 2:28 ` Richard Henderson
2014-08-08 10:40 ` Bastian Koppelmann
2014-08-08 11:35 ` Bastian Koppelmann
2014-08-11 16:06 ` Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 03/15] target-tricore: Add softmmu support Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 04/15] target-tricore: Add initialization for translation and activate target Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
2014-08-08 2:58 ` Richard Henderson
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
2014-08-07 14:34 ` [Qemu-devel] [PATCH v4 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.