[U-Boot] [PATCH 1/4] ARM: mx5: Fix CHSCCDR name

[U-Boot] [PATCH 1/4] ARM: mx5: Fix CHSCCDR name

[Marek Vasut]

Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>
---
 arch/arm/include/asm/arch-mx5/crm_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index efe57e0..b61c7b9 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -40,7 +40,7 @@ struct mxc_ccm_reg {
 	u32 cs1cdr;
 	u32 cs2cdr;
 	u32 cdcdr;	/* 0x0030 */
-	u32 chscdr;
+	u32 chsccdr;
 	u32 cscdr2;
 	u32 cscdr3;
 	u32 cscdr4;	/* 0x0040 */
-- 
2.0.1

[U-Boot] [PATCH 2/4] ARM: mx6: Prevent overflow in DRAM size detection

[Marek Vasut]

The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
---
 arch/arm/imx-common/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 5a09107..0ec8b18 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -93,6 +93,11 @@ unsigned imx_ddr_size(void)
 	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
 	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
 	bits += ESD_MMDC_CTL_GET_CS1(ctl);
+
+	/* The MX6 can do only 3840 MiB of DRAM */
+	if (bits == 32)
+		return 0xf0000000;
+
 	return 1 << bits;
 }
 #endif
-- 
2.0.1

[U-Boot] [PATCH 3/4] ARM: mx6: Handle the MMDCx_MDCTL COL field caprices

[Marek Vasut]

The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
---
 arch/arm/cpu/armv7/mx6/ddr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 0434211..1ab69f6 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -197,6 +197,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
 	u16 CS0_END;
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+	u8 coladdr;
 	int clkper; /* clock period in picoseconds */
 	int clock; /* clock freq in mHz */
 	int cs;
@@ -422,8 +423,13 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	mmdc0->mdor = reg;
 
 	/* Step 5: Configure DDR physical parameters (density and burst len) */
+	coladdr = m->coladdr;
+	if (m->coladdr == 8)		/* 8-bit COL is 0x3 */
+		coladdr += 4;
+	else if (m->coladdr == 12)	/* 12-bit COL is 0x4 */
+		coladdr += 1;
 	reg = (m->rowaddr - 11) << 24 |		/* ROW */
-	      (m->coladdr - 9) << 20 |		/* COL */
+	      (coladdr - 9) << 20 |		/* COL */
 	      (1 << 19) |			/* Burst Length = 8 for DDR3 */
 	      (i->dsize << 16);			/* DDR data bus size */
 	mmdc0->mdctl = reg;
-- 
2.0.1

[U-Boot] [PATCH 4/4] ARM: mx6: Enable Thumb build for SPL

[Marek Vasut]

Building the SPL in Thumb mode saves roughly 30% in size of the
resulting SPL binary. As the size of SPL it limited on the MX6,
this helps a lot.

Signed-off-by: Marek Vasut <marex@denx.de>
---
 include/configs/imx6_spl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 6fdc438..970460d 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -24,6 +24,7 @@
  *    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
  *    or 64KB
  */
+#define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
 #define CONFIG_SPL_TEXT_BASE		0x00908000
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
-- 
2.0.1

[U-Boot] [PATCH 2/4] ARM: mx6: Prevent overflow in DRAM size detection

[Tim Harvey]

On Sun, Aug 3, 2014 at 4:47 PM, Marek Vasut <marex@denx.de> wrote:
> The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
> only 3840 MiB of that can be really used. In case the controller is
> configured to operate a 4GiB module, the imx_ddr_size() function will
> correctly compute that there is 4GiB of DRAM in the system. Firstly,
> the return value is 32-bit, so the function will effectively return
> zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
> of all that. Thus, clamp the returned size to 3840MiB in such case.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
>  arch/arm/imx-common/cpu.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 5a09107..0ec8b18 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -93,6 +93,11 @@ unsigned imx_ddr_size(void)
>         bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
>         bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
>         bits += ESD_MMDC_CTL_GET_CS1(ctl);
> +
> +       /* The MX6 can do only 3840 MiB of DRAM */
> +       if (bits == 32)
> +               return 0xf0000000;
> +
>         return 1 << bits;
>  }
>  #endif
> --
> 2.0.1
>

Acked-by: Tim Harvey <tharvey@gateworks.com>

Tim

[U-Boot] [PATCH 4/4] ARM: mx6: Enable Thumb build for SPL

[Tim Harvey]

On Sun, Aug 3, 2014 at 4:47 PM, Marek Vasut <marex@denx.de> wrote:
> Building the SPL in Thumb mode saves roughly 30% in size of the
> resulting SPL binary. As the size of SPL it limited on the MX6,
> this helps a lot.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
>  include/configs/imx6_spl.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
> index 6fdc438..970460d 100644
> --- a/include/configs/imx6_spl.h
> +++ b/include/configs/imx6_spl.h
> @@ -24,6 +24,7 @@
>   *    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
>   *    or 64KB
>   */
> +#define CONFIG_SYS_THUMB_BUILD
>  #define CONFIG_SPL_LDSCRIPT    "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
>  #define CONFIG_SPL_TEXT_BASE           0x00908000
>  #define CONFIG_SPL_MAX_SIZE            (64 * 1024)
> --
> 2.0.1
>

Marek,

Thanks for pointing this out - this indeed is a great space savings
where it matters.

Acked-by: Tim Harvey <tharvey@gateworks.com>

[U-Boot] [PATCH 1/4] ARM: mx5: Fix CHSCCDR name

[Stefano Babic]

Hi Marek,

On 04/08/2014 01:47, Marek Vasut wrote:
> Fix the name of the CCM CHSCCDR register.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 2/4] ARM: mx6: Prevent overflow in DRAM size detection

[Stefano Babic]

On 04/08/2014 01:47, Marek Vasut wrote:
> The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
> only 3840 MiB of that can be really used. In case the controller is
> configured to operate a 4GiB module, the imx_ddr_size() function will
> correctly compute that there is 4GiB of DRAM in the system. Firstly,
> the return value is 32-bit, so the function will effectively return
> zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
> of all that. Thus, clamp the returned size to 3840MiB in such case.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 3/4] ARM: mx6: Handle the MMDCx_MDCTL COL field caprices

[Stefano Babic]

Hi Marek,

On 04/08/2014 01:47, Marek Vasut wrote:
> The COL field value cannot be easily calculated from the desired
> column number. Instead, there are special cases for that, see the
> datasheet, MMDCx_MDCTL field description, field COL . Cater for
> those special cases.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 4/4] ARM: mx6: Enable Thumb build for SPL

[Stefano Babic]

Hi Marek,

On 04/08/2014 01:47, Marek Vasut wrote:
> Building the SPL in Thumb mode saves roughly 30% in size of the
> resulting SPL binary. As the size of SPL it limited on the MX6,
> this helps a lot.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================