[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Maxime Ripard]

The divider_get_val function that is used in our determine_rate callback
doesn't try to change the parent rate at all, while clk_divider_bestdiv,
used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_div.c | 12 ++++++++++++
 1 file changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 8659b4cb6c20..4057e6021aa9 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -77,6 +77,18 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
 {
 	struct ccu_div *cd = hw_to_ccu_div(hw);
 
+	if (clk_hw_get_num_parents(hw) == 1) {
+		req->rate = divider_round_rate(hw, req->rate,
+					       &req->best_parent_rate,
+					       cd->div.table,
+					       cd->div.width,
+					       cd->div.flags);
+
+		req->best_parent_hw = clk_hw_get_parent(hw);
+
+		return 0;
+	}
+
 	return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
 					     req, ccu_div_round_rate, cd);
 }

base-commit: 9181f40cede22bff9bc7f26830a4562373f30d73
-- 
git-series 0.8.11

[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Maxime Ripard]

The divider_get_val function that is used in our determine_rate callback
doesn't try to change the parent rate at all, while clk_divider_bestdiv,
used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_div.c | 12 ++++++++++++
 1 file changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 8659b4cb6c20..4057e6021aa9 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -77,6 +77,18 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
 {
 	struct ccu_div *cd = hw_to_ccu_div(hw);
 
+	if (clk_hw_get_num_parents(hw) == 1) {
+		req->rate = divider_round_rate(hw, req->rate,
+					       &req->best_parent_rate,
+					       cd->div.table,
+					       cd->div.width,
+					       cd->div.flags);
+
+		req->best_parent_hw = clk_hw_get_parent(hw);
+
+		return 0;
+	}
+
 	return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
 					     req, ccu_div_round_rate, cd);
 }

base-commit: 9181f40cede22bff9bc7f26830a4562373f30d73
-- 
git-series 0.8.11

[PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Maxime Ripard]

In order to achieve all the rates asked by the GPU, we might need to change
the parent frequency.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 0d513d2674cb..a7b3c08ed0e2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -468,7 +468,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 				       0x180, 0, 4, 24, 3, BIT(31), 0);
 
 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
-			     0x1a0, 0, 3, BIT(31), 0);
+			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
-- 
git-series 0.8.11

[PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Maxime Ripard]

In order to achieve all the rates asked by the GPU, we might need to change
the parent frequency.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 0d513d2674cb..a7b3c08ed0e2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -468,7 +468,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 				       0x180, 0, 4, 24, 3, BIT(31), 0);
 
 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
-			     0x1a0, 0, 3, BIT(31), 0);
+			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
-- 
git-series 0.8.11

Re: [PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Stephen Boyd]

On 01/24, Maxime Ripard wrote:
> The divider_get_val function that is used in our determine_rate callback
> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
> used in divider_round_rate, does.
> 
> If we have a single parent, call divider_round_rate.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Stephen Boyd]

On 01/24, Maxime Ripard wrote:
> The divider_get_val function that is used in our determine_rate callback
> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
> used in divider_round_rate, does.
> 
> If we have a single parent, call divider_round_rate.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Stephen Boyd]

On 01/24, Maxime Ripard wrote:
> In order to achieve all the rates asked by the GPU, we might need to change
> the parent frequency.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Stephen Boyd]

On 01/24, Maxime Ripard wrote:
> In order to achieve all the rates asked by the GPU, we might need to change
> the parent frequency.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Chen-Yu Tsai]

On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 01/24, Maxime Ripard wrote:
>> In order to achieve all the rates asked by the GPU, we might need to change
>> the parent frequency.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

[PATCH 2/2] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

[Chen-Yu Tsai]

On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 01/24, Maxime Ripard wrote:
>> In order to achieve all the rates asked by the GPU, we might need to change
>> the parent frequency.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

Re: [PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Chen-Yu Tsai]

On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 01/24, Maxime Ripard wrote:
>> The divider_get_val function that is used in our determine_rate callback
>> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
>> used in divider_round_rate, does.
>>
>> If we have a single parent, call divider_round_rate.

I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with
CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent
case? Still, the underlying clock type doesn't get to specify what
is considers to be the best parent rate.

>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Chen-Yu Tsai]

On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 01/24, Maxime Ripard wrote:
>> The divider_get_val function that is used in our determine_rate callback
>> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
>> used in divider_round_rate, does.
>>
>> If we have a single parent, call divider_round_rate.

I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with
CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent
case? Still, the underlying clock type doesn't get to specify what
is considers to be the best parent rate.

>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1106 bytes --]

On Fri, Jan 27, 2017 at 11:30:05AM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> > On 01/24, Maxime Ripard wrote:
> >> The divider_get_val function that is used in our determine_rate callback
> >> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
> >> used in divider_round_rate, does.
> >>
> >> If we have a single parent, call divider_round_rate.
> 
> I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with
> CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent
> case?

It looks like it does yes :)

> Still, the underlying clock type doesn't get to specify what
> is considers to be the best parent rate.
> 
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >
> > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Merged the two patches with Stephen and your Acked-bY.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH 1/2] clk: sunxi-ng: Call divider_round_rate if we only have a single parent

[Maxime Ripard]

On Fri, Jan 27, 2017 at 11:30:05AM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 27, 2017 at 8:12 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> > On 01/24, Maxime Ripard wrote:
> >> The divider_get_val function that is used in our determine_rate callback
> >> doesn't try to change the parent rate at all, while clk_divider_bestdiv,
> >> used in divider_round_rate, does.
> >>
> >> If we have a single parent, call divider_round_rate.
> 
> I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with
> CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent
> case?

It looks like it does yes :)

> Still, the underlying clock type doesn't get to specify what
> is considers to be the best parent rate.
> 
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >
> > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Merged the two patches with Stephen and your Acked-bY.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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