* [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
@ 2021-03-30 8:14 Emily Deng
2021-03-30 8:58 ` Nirmoy
0 siblings, 1 reply; 11+ messages in thread
From: Emily Deng @ 2021-03-30 8:14 UTC (permalink / raw)
To: amd-gfx; +Cc: Emily.Deng
From: "Emily.Deng" <Emily.Deng@amd.com>
After FLR, the msix will be cleared, so need to toggle it for sriov.
v2:
Change name with amdgpu_irq prefix, remove #ifdef.
Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 03412543427a..3045f52e613d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
return true;
}
+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev)
+{
+ u16 ctrl;
+
+ pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
+ ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+ ctrl |= PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+}
+
/**
* amdgpu_irq_init - initialize interrupt handling
*
@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
{
int i, j, k;
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_irq_restore_msix(adev);
+
for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
--
2.25.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 8:14 [PATCH] drm/amdgpu: Toggle msix after FLR for sriov Emily Deng
@ 2021-03-30 8:58 ` Nirmoy
2021-03-30 9:29 ` Deng, Emily
0 siblings, 1 reply; 11+ messages in thread
From: Nirmoy @ 2021-03-30 8:58 UTC (permalink / raw)
To: Emily Deng, amd-gfx
On 3/30/21 10:14 AM, Emily Deng wrote:
> From: "Emily.Deng" <Emily.Deng@amd.com>
>
> After FLR, the msix will be cleared, so need to toggle it for sriov.
>
> v2:
> Change name with amdgpu_irq prefix, remove #ifdef.
>
> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 03412543427a..3045f52e613d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
> return true;
> }
>
> +static void amdgpu_irq_restore_msix(struct amdgpu_device *adev)
> +{
> + u16 ctrl;
> +
> + pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
> + ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
> + ctrl |= PCI_MSIX_FLAGS_ENABLE;
> + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
Why write 1st clear and then set the msix flag if we know that msix is
already cleared.
> +}
> +
> /**
> * amdgpu_irq_init - initialize interrupt handling
> *
> @@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
> {
> int i, j, k;
>
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_irq_restore_msix(adev);
Is it possible to load amdgpu on guest without msix ? If so then we need
to probe if msix is enabled.
Nirmoy
> +
> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 8:58 ` Nirmoy
@ 2021-03-30 9:29 ` Deng, Emily
2021-03-30 9:33 ` Nirmoy
0 siblings, 1 reply; 11+ messages in thread
From: Deng, Emily @ 2021-03-30 9:29 UTC (permalink / raw)
To: Das, Nirmoy, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
>-----Original Message-----
>From: Das, Nirmoy <Nirmoy.Das@amd.com>
>Sent: Tuesday, March 30, 2021 4:59 PM
>To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>
>On 3/30/21 10:14 AM, Emily Deng wrote:
>> From: "Emily.Deng" <Emily.Deng@amd.com>
>>
>> After FLR, the msix will be cleared, so need to toggle it for sriov.
>>
>> v2:
>> Change name with amdgpu_irq prefix, remove #ifdef.
>>
>> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index 03412543427a..3045f52e613d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>*adev)
>> return true;
>> }
>>
>> +static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>> +u16 ctrl;
>> +
>> +pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, &ctrl);
>> +ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, ctrl);
>> +ctrl |= PCI_MSIX_FLAGS_ENABLE;
>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>> +PCI_MSIX_FLAGS, ctrl);
>
>
>Why write 1st clear and then set the msix flag if we know that msix is already
>cleared
For vf assigned to guest VM, after FLR, the msix table will be reset. As the flr is done on host driver. The qemu and vfio driver don't know
this, and the msix is still enable from qemu and vfio driver side. So if want to re-setup the msix table, first need to disable and re-enable the msix from guest VM side or the qemu will do nothing
as it thought the msix is already enabled.
>
>
>
>> +}
>> +
>> /**
>> * amdgpu_irq_init - initialize interrupt handling
>> *
>> @@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>amdgpu_device *adev)
>> {
>> int i, j, k;
>>
>> +if (amdgpu_sriov_vf(adev))
>> +amdgpu_irq_restore_msix(adev);
>
>
>Is it possible to load amdgpu on guest without msix ? If so then we need
>to probe if msix is enabled.
>
>
>Nirmoy
>
>
>> +
>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
>> if (!adev->irq.client[i].sources)
>> continue;
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 9:29 ` Deng, Emily
@ 2021-03-30 9:33 ` Nirmoy
2021-03-30 9:38 ` Deng, Emily
0 siblings, 1 reply; 11+ messages in thread
From: Nirmoy @ 2021-03-30 9:33 UTC (permalink / raw)
To: Deng, Emily, Das, Nirmoy, amd-gfx
On 3/30/21 11:29 AM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
>> -----Original Message-----
>> From: Das, Nirmoy <Nirmoy.Das@amd.com>
>> Sent: Tuesday, March 30, 2021 4:59 PM
>> To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>
>>
>> On 3/30/21 10:14 AM, Emily Deng wrote:
>>> From: "Emily.Deng" <Emily.Deng@amd.com>
>>>
>>> After FLR, the msix will be cleared, so need to toggle it for sriov.
>>>
>>> v2:
>>> Change name with amdgpu_irq prefix, remove #ifdef.
>>>
>>> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
>>> 1 file changed, 14 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>> index 03412543427a..3045f52e613d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>> @@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>> *adev)
>>> return true;
>>> }
>>>
>>> +static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>> +u16 ctrl;
>>> +
>>> +pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>> PCI_MSIX_FLAGS, &ctrl);
>>> +ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>> PCI_MSIX_FLAGS, ctrl);
>>> +ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>> +PCI_MSIX_FLAGS, ctrl);
>>
>> Why write 1st clear and then set the msix flag if we know that msix is already
>> cleared
> For vf assigned to guest VM, after FLR, the msix table will be reset. As the flr is done on host driver. The qemu and vfio driver don't know
> this, and the msix is still enable from qemu and vfio driver side. So if want to re-setup the msix table, first need to disable and re-enable the msix from guest VM side or the qemu will do nothing
> as it thought the msix is already enabled.
Thanks for the detailed explanation, Emily. Please add a comment so that
we know/remember why we are doing this.
Nirmoy
>>
>>
>>> +}
>>> +
>>> /**
>>> * amdgpu_irq_init - initialize interrupt handling
>>> *
>>> @@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>> amdgpu_device *adev)
>>> {
>>> int i, j, k;
>>>
>>> +if (amdgpu_sriov_vf(adev))
>>> +amdgpu_irq_restore_msix(adev);
>>
>> Is it possible to load amdgpu on guest without msix ? If so then we need
>> to probe if msix is enabled.
>>
>>
>> Nirmoy
>>
>>
>>> +
>>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
>>> if (!adev->irq.client[i].sources)
>>> continue;
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 9:33 ` Nirmoy
@ 2021-03-30 9:38 ` Deng, Emily
0 siblings, 0 replies; 11+ messages in thread
From: Deng, Emily @ 2021-03-30 9:38 UTC (permalink / raw)
To: Das, Nirmoy, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
>-----Original Message-----
>From: Das, Nirmoy <Nirmoy.Das@amd.com>
>Sent: Tuesday, March 30, 2021 5:34 PM
>To: Deng, Emily <Emily.Deng@amd.com>; Das, Nirmoy
><Nirmoy.Das@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>
>On 3/30/21 11:29 AM, Deng, Emily wrote:
>> [AMD Official Use Only - Internal Distribution Only]
>>
>>> -----Original Message-----
>>> From: Das, Nirmoy <Nirmoy.Das@amd.com>
>>> Sent: Tuesday, March 30, 2021 4:59 PM
>>> To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>>> Subject: Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>>
>>>
>>> On 3/30/21 10:14 AM, Emily Deng wrote:
>>>> From: "Emily.Deng" <Emily.Deng@amd.com>
>>>>
>>>> After FLR, the msix will be cleared, so need to toggle it for sriov.
>>>>
>>>> v2:
>>>> Change name with amdgpu_irq prefix, remove #ifdef.
>>>>
>>>> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
>>>> 1 file changed, 14 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> index 03412543427a..3045f52e613d 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> @@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct
>amdgpu_device
>>> *adev)
>>>> return true;
>>>> }
>>>>
>>>> +static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>>> +u16 ctrl;
>>>> +
>>>> +pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>>> PCI_MSIX_FLAGS, &ctrl);
>>>> +ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>> PCI_MSIX_FLAGS, ctrl);
>>>> +ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>>> +pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>>> +PCI_MSIX_FLAGS, ctrl);
>>>
>>> Why write 1st clear and then set the msix flag if we know that msix
>>> is already cleared
>> For vf assigned to guest VM, after FLR, the msix table will be reset.
>> As the flr is done on host driver. The qemu and vfio driver don't know
>> this, and the msix is still enable from qemu and vfio driver side. So if want to
>re-setup the msix table, first need to disable and re-enable the msix from
>guest VM side or the qemu will do nothing as it thought the msix is already
>enabled.
>
>
>Thanks for the detailed explanation, Emily. Please add a comment so that we
>know/remember why we are doing this.
Ok, will do this. Thanks.
>
>
>Nirmoy
>
>
>>>
>>>
>>>> +}
>>>> +
>>>> /**
>>>> * amdgpu_irq_init - initialize interrupt handling
>>>> *
>>>> @@ -558,6 +569,9 @@ void
>amdgpu_irq_gpu_reset_resume_helper(struct
>>> amdgpu_device *adev)
>>>> {
>>>> int i, j, k;
>>>>
>>>> +if (amdgpu_sriov_vf(adev))
>>>> +amdgpu_irq_restore_msix(adev);
>>>
>>> Is it possible to load amdgpu on guest without msix ? If so then we need
>>> to probe if msix is enabled.
It is decided by host driver, not guest driver.
>>>
>>>
>>> Nirmoy
>>>
>>>
>>>> +
>>>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
>>>> if (!adev->irq.client[i].sources)
>>>> continue;
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-04-01 6:03 ` Deng, Emily
@ 2021-04-01 8:35 ` Liu, Monk
0 siblings, 0 replies; 11+ messages in thread
From: Liu, Monk @ 2021-04-01 8:35 UTC (permalink / raw)
To: Deng, Emily; +Cc: amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Monk Liu <monk.liu@amd.com>
Thanks
------------------------------------------
Monk Liu | Cloud-GPU Core team
------------------------------------------
-----Original Message-----
From: Deng, Emily <Emily.Deng@amd.com>
Sent: Thursday, April 1, 2021 2:04 PM
To: Liu, Monk <Monk.Liu@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
[AMD Official Use Only - Internal Distribution Only]
Hi Monk,
Could you help to review this patch?
Best wishes
Emily Deng
>-----Original Message-----
>From: Deng, Emily <Emily.Deng@amd.com>
>Sent: Wednesday, March 31, 2021 5:02 PM
>To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping ......
>
>>-----Original Message-----
>>From: Emily Deng <Emily.Deng@amd.com>
>>Sent: Tuesday, March 30, 2021 5:43 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily <Emily.Deng@amd.com>
>>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>
>>From: "Emily.Deng" <Emily.Deng@amd.com>
>>
>>For vf assigned to guest VM, after FLR, the msix table will be reset.
>>As the flr is done on host driver. The qemu and vfio driver don't know
>>this, and the msix is still enable from qemu and vfio driver side.
>>So if want to re-setup the msix table, first need to disable and
>>re-enable the msix from guest VM side or the qemu will do nothing as
>>it thought the msix is already enabled.
>>
>>v2:
>>Change name with amdgpu_irq prefix, remove #ifdef.
>>
>>Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>>---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>index 03412543427a..3045f52e613d 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>>*adev)
>> return true;
>> }
>>
>>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>+u16 ctrl;
>>+
>>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, &ctrl);
>>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, ctrl);
>>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>+PCI_MSIX_FLAGS, ctrl); }
>>+
>> /**
>> * amdgpu_irq_init - initialize interrupt handling
>> *
>>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>>amdgpu_device *adev) {
>> int i, j, k;
>>
>>+if (amdgpu_sriov_vf(adev))
>>+amdgpu_irq_restore_msix(adev);
>>+
>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { if
>>(!adev->irq.client[i].sources) continue;
>>--
>>2.25.1
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 9:42 Emily Deng
2021-03-31 1:46 ` Deng, Emily
2021-03-31 9:01 ` Deng, Emily
@ 2021-04-01 7:39 ` Nirmoy
2 siblings, 0 replies; 11+ messages in thread
From: Nirmoy @ 2021-04-01 7:39 UTC (permalink / raw)
To: Emily Deng, amd-gfx
Acked-by: Nirmoy Das<nirmoy.das@amd.com>
On 3/30/21 11:42 AM, Emily Deng wrote:
> From: "Emily.Deng" <Emily.Deng@amd.com>
>
> For vf assigned to guest VM, after FLR, the msix table will be reset.
> As the flr is done on host driver. The qemu and vfio driver don't know
> this, and the msix is still enable from qemu and vfio driver side.
> So if want to re-setup the msix table, first need to disable and
> re-enable the msix from guest VM side or the qemu will do nothing as
> it thought the msix is already enabled.
>
> v2:
> Change name with amdgpu_irq prefix, remove #ifdef.
>
> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 03412543427a..3045f52e613d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
> return true;
> }
>
> +static void amdgpu_irq_restore_msix(struct amdgpu_device *adev)
> +{
> + u16 ctrl;
> +
> + pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
> + ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
> + ctrl |= PCI_MSIX_FLAGS_ENABLE;
> + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
> +}
> +
> /**
> * amdgpu_irq_init - initialize interrupt handling
> *
> @@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
> {
> int i, j, k;
>
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_irq_restore_msix(adev);
> +
> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-31 9:01 ` Deng, Emily
@ 2021-04-01 6:03 ` Deng, Emily
2021-04-01 8:35 ` Liu, Monk
0 siblings, 1 reply; 11+ messages in thread
From: Deng, Emily @ 2021-04-01 6:03 UTC (permalink / raw)
To: Liu, Monk; +Cc: amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Hi Monk,
Could you help to review this patch?
Best wishes
Emily Deng
>-----Original Message-----
>From: Deng, Emily <Emily.Deng@amd.com>
>Sent: Wednesday, March 31, 2021 5:02 PM
>To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping ......
>
>>-----Original Message-----
>>From: Emily Deng <Emily.Deng@amd.com>
>>Sent: Tuesday, March 30, 2021 5:43 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily <Emily.Deng@amd.com>
>>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>
>>From: "Emily.Deng" <Emily.Deng@amd.com>
>>
>>For vf assigned to guest VM, after FLR, the msix table will be reset.
>>As the flr is done on host driver. The qemu and vfio driver don't know
>>this, and the msix is still enable from qemu and vfio driver side.
>>So if want to re-setup the msix table, first need to disable and
>>re-enable the msix from guest VM side or the qemu will do nothing as it
>>thought the msix is already enabled.
>>
>>v2:
>>Change name with amdgpu_irq prefix, remove #ifdef.
>>
>>Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>>---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>index 03412543427a..3045f52e613d 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>>*adev)
>> return true;
>> }
>>
>>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>+u16 ctrl;
>>+
>>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, &ctrl);
>>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, ctrl);
>>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>+PCI_MSIX_FLAGS, ctrl); }
>>+
>> /**
>> * amdgpu_irq_init - initialize interrupt handling
>> *
>>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>>amdgpu_device *adev) {
>> int i, j, k;
>>
>>+if (amdgpu_sriov_vf(adev))
>>+amdgpu_irq_restore_msix(adev);
>>+
>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { if
>>(!adev->irq.client[i].sources) continue;
>>--
>>2.25.1
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 9:42 Emily Deng
2021-03-31 1:46 ` Deng, Emily
@ 2021-03-31 9:01 ` Deng, Emily
2021-04-01 6:03 ` Deng, Emily
2021-04-01 7:39 ` Nirmoy
2 siblings, 1 reply; 11+ messages in thread
From: Deng, Emily @ 2021-03-31 9:01 UTC (permalink / raw)
To: Deng, Emily, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Ping ......
>-----Original Message-----
>From: Emily Deng <Emily.Deng@amd.com>
>Sent: Tuesday, March 30, 2021 5:43 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily <Emily.Deng@amd.com>
>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>From: "Emily.Deng" <Emily.Deng@amd.com>
>
>For vf assigned to guest VM, after FLR, the msix table will be reset.
>As the flr is done on host driver. The qemu and vfio driver don't know this,
>and the msix is still enable from qemu and vfio driver side.
>So if want to re-setup the msix table, first need to disable and re-enable the
>msix from guest VM side or the qemu will do nothing as it thought the msix is
>already enabled.
>
>v2:
>Change name with amdgpu_irq prefix, remove #ifdef.
>
>Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>index 03412543427a..3045f52e613d 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>*adev)
> return true;
> }
>
>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>+u16 ctrl;
>+
>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, &ctrl);
>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, ctrl);
>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>+PCI_MSIX_FLAGS, ctrl); }
>+
> /**
> * amdgpu_irq_init - initialize interrupt handling
> *
>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>amdgpu_device *adev) {
> int i, j, k;
>
>+if (amdgpu_sriov_vf(adev))
>+amdgpu_irq_restore_msix(adev);
>+
> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
>--
>2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
2021-03-30 9:42 Emily Deng
@ 2021-03-31 1:46 ` Deng, Emily
2021-03-31 9:01 ` Deng, Emily
2021-04-01 7:39 ` Nirmoy
2 siblings, 0 replies; 11+ messages in thread
From: Deng, Emily @ 2021-03-31 1:46 UTC (permalink / raw)
To: Deng, Emily, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Ping ......
>-----Original Message-----
>From: Emily Deng <Emily.Deng@amd.com>
>Sent: Tuesday, March 30, 2021 5:43 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily <Emily.Deng@amd.com>
>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>From: "Emily.Deng" <Emily.Deng@amd.com>
>
>For vf assigned to guest VM, after FLR, the msix table will be reset.
>As the flr is done on host driver. The qemu and vfio driver don't know this,
>and the msix is still enable from qemu and vfio driver side.
>So if want to re-setup the msix table, first need to disable and re-enable the
>msix from guest VM side or the qemu will do nothing as it thought the msix is
>already enabled.
>
>v2:
>Change name with amdgpu_irq prefix, remove #ifdef.
>
>Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>index 03412543427a..3045f52e613d 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>*adev)
> return true;
> }
>
>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>+u16 ctrl;
>+
>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, &ctrl);
>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>PCI_MSIX_FLAGS, ctrl);
>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>+PCI_MSIX_FLAGS, ctrl); }
>+
> /**
> * amdgpu_irq_init - initialize interrupt handling
> *
>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>amdgpu_device *adev) {
> int i, j, k;
>
>+if (amdgpu_sriov_vf(adev))
>+amdgpu_irq_restore_msix(adev);
>+
> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
>--
>2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
@ 2021-03-30 9:42 Emily Deng
2021-03-31 1:46 ` Deng, Emily
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Emily Deng @ 2021-03-30 9:42 UTC (permalink / raw)
To: amd-gfx; +Cc: Emily.Deng
From: "Emily.Deng" <Emily.Deng@amd.com>
For vf assigned to guest VM, after FLR, the msix table will be reset.
As the flr is done on host driver. The qemu and vfio driver don't know
this, and the msix is still enable from qemu and vfio driver side.
So if want to re-setup the msix table, first need to disable and
re-enable the msix from guest VM side or the qemu will do nothing as
it thought the msix is already enabled.
v2:
Change name with amdgpu_irq prefix, remove #ifdef.
Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 03412543427a..3045f52e613d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
return true;
}
+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev)
+{
+ u16 ctrl;
+
+ pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
+ ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+ ctrl |= PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+}
+
/**
* amdgpu_irq_init - initialize interrupt handling
*
@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
{
int i, j, k;
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_irq_restore_msix(adev);
+
for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
--
2.25.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-04-01 8:36 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-30 8:14 [PATCH] drm/amdgpu: Toggle msix after FLR for sriov Emily Deng
2021-03-30 8:58 ` Nirmoy
2021-03-30 9:29 ` Deng, Emily
2021-03-30 9:33 ` Nirmoy
2021-03-30 9:38 ` Deng, Emily
2021-03-30 9:42 Emily Deng
2021-03-31 1:46 ` Deng, Emily
2021-03-31 9:01 ` Deng, Emily
2021-04-01 6:03 ` Deng, Emily
2021-04-01 8:35 ` Liu, Monk
2021-04-01 7:39 ` Nirmoy
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