[U-Boot] [PATCH 1/2] driver/ddr/fsl: Fix DDR4 driver

* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Fix DDR4 driver
@ 2014-09-11 20:32 York Sun
  2014-09-11 20:32 ` [U-Boot] [PATCH 2/2] board/ls1021aqds_d4: Add DDR4 support York Sun
  0 siblings, 1 reply; 4+ messages in thread
From: York Sun @ 2014-09-11 20:32 UTC (permalink / raw)
  To: u-boot

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 drivers/ddr/fsl/ctrl_regs.c    |    9 +++++++--
 drivers/ddr/fsl/fsl_ddr_gen4.c |    3 +--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index d9cac22..f3635ed 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1886,9 +1886,12 @@ static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
 	debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
 }
 
+/* This function needs to be called after set_ddr_sdram_cfg() is called */
 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
 			       const dimm_params_t *dimm_params)
 {
+	unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
+
 	ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
 			((dimm_params->dq_mapping[1] & 0x3F) << 20) |
 			((dimm_params->dq_mapping[2] & 0x3F) << 14) |
@@ -1907,9 +1910,11 @@ static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
 			((dimm_params->dq_mapping[15] & 0x3F) << 8) |
 			((dimm_params->dq_mapping[16] & 0x3F) << 2);
 
+	/* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
 	ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
 			((dimm_params->dq_mapping[8] & 0x3F) << 20) |
-			((dimm_params->dq_mapping[9] & 0x3F) << 14) |
+			(acc_ecc_en ? 0 :
+			 (dimm_params->dq_mapping[9] & 0x3F) << 14) |
 			dimm_params->dq_mapping_ors;
 
 	debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
@@ -2276,7 +2281,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
-	if (ip_rev > 0x40700)
+	if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
 		ddr->debug[18] = popts->cswl_override;
 
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index bfc76b3..e024db9 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -216,7 +216,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 2;
@@ -233,5 +233,4 @@ step2:
 
 	if (timeout <= 0)
 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
 }
-- 
1.7.9.5

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