[U-Boot] [PATCH v3 1/4] imx: mx6slevk: Add I2C1 support

[U-Boot] [PATCH v3 1/4] imx: mx6slevk: Add I2C1 support

[Ye.Li]

Add I2C1 pin and pad settings, and enable the MXC I2C driver.

Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes since v1:
- None

Changes since v2:
- None

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h |    5 +++++
 board/freescale/mx6slevk/mx6slevk.c        |   26 ++++++++++++++++++++++++++
 include/configs/mx6slevk.h                 |    6 ++++++
 3 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..ac84270 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
 	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
 	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+
+	MX6_PAD_I2C1_SDA__I2C1_SDA					= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+	MX6_PAD_I2C1_SDA__GPIO_3_13					= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__I2C1_SCL					= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+	MX6_PAD_I2C1_SCL__GPIO_3_12					= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index a990b4c..fedd5c3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,12 +13,14 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
 #include <netdev.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
 
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -162,6 +185,9 @@ int board_init(void)
 #ifdef	CONFIG_FEC_MXC
 	setup_fec();
 #endif
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+
 	return 0;
 }
 
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..bf5066f 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -60,6 +60,12 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
-- 
1.7.4.1

[U-Boot] [PATCH v3 2/4] imx: mx6slevk: Add PMIC Pfuze support

[Ye.Li]

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes since v1:
- None

Changes since v2:
- None

 board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
 include/configs/mx6slevk.h          |    7 ++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index fedd5c3..8b6a79c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -21,6 +21,8 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
 /* I2C1 for PMIC */
 struct i2c_pads_info i2c_pad_info0 = {
 	.sda = {
@@ -191,6 +195,59 @@ int board_init(void)
 	return 0;
 }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}
+
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index bf5066f..09d0896 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
@@ -66,6 +67,12 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
-- 
1.7.4.1

[U-Boot] [PATCH v3 3/4] imx: mx6sabresd: Add clear print for pfuze200

[Ye.Li]

Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.

Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes since v1:
- None

Changes since v2:
- None

 board/freescale/mx6sabresd/mx6sabresd.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 5f65f1b..72d6562 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -472,7 +472,8 @@ static int pfuze_init(void)
 		return ret;
 
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
 
 	/* Increase VGEN3 from 2.5 to 2.8V */
 	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
-- 
1.7.4.1

[U-Boot] [PATCH v3 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM

[Ye.Li]

Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.

Changes for boards:
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd

Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes since v1:
- Try to correct the return code per Fabio's comments, but send out a false patch 

Changes since v2:
- Correct the return code

 board/freescale/mx6qsabreauto/mx6qsabreauto.c |   41 +++++++++++++++++++++++++
 board/freescale/mx6sabresd/mx6sabresd.c       |   41 +++++++++++++++++++++++++
 board/freescale/mx6slevk/mx6slevk.c           |   41 +++++++++++++++++++++++++
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |   40 ++++++++++++++++++++++++
 4 files changed, 163 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 76b024b..df7f845 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -263,6 +263,41 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+	int ret;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	ret = pmic_reg_write(p, 0x23, value);
+	if (ret) {
+		printf("Set SW1AB mode error: %d!\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * 7, value);
+		if (ret) {
+			printf("Set switch%x mode error: %d!\n", offset, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+
 static int pfuze_init(void)
 {
 	struct pmic *p;
@@ -281,6 +316,12 @@ static int pfuze_init(void)
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	ret = pfuze_setup_mode(p, (reg & 0xf));
+	if (ret) {
+		printf("setup pfuze mode error: %d!\n", ret);
+		return ret;
+	}
+
 	/* Set SW1AB stanby volage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 72d6562..e0f0d2c 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -456,6 +456,41 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+	int ret;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	ret = pmic_reg_write(p, 0x23, value);
+	if (ret) {
+		printf("Set SW1AB mode error: %d!\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * 7, value);
+		if (ret) {
+			printf("Set switch%x mode error: %d!\n", offset, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+
 static int pfuze_init(void)
 {
 	struct pmic *p;
@@ -475,6 +510,12 @@ static int pfuze_init(void)
 	printf("PMIC:  PFUZE%s ID=0x%02x\n",
 		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	ret = pfuze_setup_mode(p, (reg & 0xf));
+	if (ret) {
+		printf("setup pfuze mode error: %d!\n", ret);
+		return ret;
+	}
+
 	/* Increase VGEN3 from 2.5 to 2.8V */
 	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 	reg &= ~0xf;
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 8b6a79c..8fa58c4 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -195,6 +195,41 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+	int ret;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	ret = pmic_reg_write(p, 0x23, value);
+	if (ret) {
+		printf("Set SW1AB mode error: %d!\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * 7, value);
+		if (ret) {
+			printf("Set switch%x mode error: %d!\n", offset, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+
 static int pfuze_init(void)
 {
 	struct pmic *p;
@@ -214,6 +249,12 @@ static int pfuze_init(void)
 	printf("PMIC:  PFUZE%s ID=0x%02x\n",
 		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	ret = pfuze_setup_mode(p, (reg & 0xf));
+	if (ret) {
+		printf("setup pfuze mode error: %d!\n", ret);
+		return ret;
+	}
+
 	/* Set SW1AB stanby volage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 80d2d99..a76a8ef 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -170,6 +170,40 @@ struct i2c_pads_info i2c_pad_info1 = {
 	},
 };
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+	int ret;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	ret = pmic_reg_write(p, 0x23, value);
+	if (ret) {
+		printf("Set SW1AB mode error: %d!\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * 7, value);
+		if (ret) {
+			printf("Set switch%x mode error: %d!\n", offset, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
 static int pfuze_init(void)
 {
 	struct pmic *p;
@@ -188,6 +222,12 @@ static int pfuze_init(void)
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	ret = pfuze_setup_mode(p, (reg & 0xf));
+	if (ret) {
+		printf("setup pfuze mode error: %d!\n", ret);
+		return ret;
+	}
+
 	/* Set SW1AB standby voltage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
-- 
1.7.4.1

[U-Boot] [PATCH v3 1/4] imx: mx6slevk: Add I2C1 support

[Stefano Babic]

Hi Ye,


On 11/09/2014 05:13, Ye.Li wrote:
> Add I2C1 pin and pad settings, and enable the MXC I2C driver.
> 

I see two different topics in this patch:

1. Add I2C1 pins to mx6sl pins. This is general, and not related to a
specific board.

2. Add I2C1 support to 6slevk board, as in subject.

Please spliut this patch to address ewach related issue.

Thanks,
Stefano Babic

> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
> Changes since v1:
> - None
> 
> Changes since v2:
> - None
> 
>  arch/arm/include/asm/arch-mx6/mx6sl_pins.h |    5 +++++
>  board/freescale/mx6slevk/mx6slevk.c        |   26 ++++++++++++++++++++++++++
>  include/configs/mx6slevk.h                 |    6 ++++++
>  3 files changed, 37 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
> index 045ccc4..ac84270 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
> @@ -34,5 +34,10 @@ enum {
>  	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
>  	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
>  	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
> +
> +	MX6_PAD_I2C1_SDA__I2C1_SDA					= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
> +	MX6_PAD_I2C1_SDA__GPIO_3_13					= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
> +	MX6_PAD_I2C1_SCL__I2C1_SCL					= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
> +	MX6_PAD_I2C1_SCL__GPIO_3_12					= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
>  };
>  #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
> index a990b4c..fedd5c3 100644
> --- a/board/freescale/mx6slevk/mx6slevk.c
> +++ b/board/freescale/mx6slevk/mx6slevk.c
> @@ -13,12 +13,14 @@
>  #include <asm/arch/sys_proto.h>
>  #include <asm/gpio.h>
>  #include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/mxc_i2c.h>
>  #include <asm/io.h>
>  #include <linux/sizes.h>
>  #include <common.h>
>  #include <fsl_esdhc.h>
>  #include <mmc.h>
>  #include <netdev.h>
> +#include <i2c.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
>  		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>  
> +#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
> +	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
> +	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
>  #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
>  
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +/* I2C1 for PMIC */
> +struct i2c_pads_info i2c_pad_info0 = {
> +	.sda = {
> +		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
> +		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
> +		.gp = IMX_GPIO_NR(3, 13),
> +	},
> +	.scl = {
> +		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
> +		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
> +		.gp = IMX_GPIO_NR(3, 12),
> +	},
> +};
> +
>  int dram_init(void)
>  {
>  	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -162,6 +185,9 @@ int board_init(void)
>  #ifdef	CONFIG_FEC_MXC
>  	setup_fec();
>  #endif
> +
> +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
> +
>  	return 0;
>  }
>  
> diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
> index 3d05a64..bf5066f 100644
> --- a/include/configs/mx6slevk.h
> +++ b/include/configs/mx6slevk.h
> @@ -60,6 +60,12 @@
>  #define CONFIG_PHYLIB
>  #define CONFIG_PHY_SMSC
>  
> +/* I2C Configs */
> +#define CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED		  100000
> +
>  /* allow to overwrite serial and ethaddr */
>  #define CONFIG_ENV_OVERWRITE
>  #define CONFIG_CONS_INDEX		1
> 


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 3/4] imx: mx6sabresd: Add clear print for pfuze200

[Stefano Babic]

Hi Ye,

On 11/09/2014 05:13, Ye.Li wrote:
> Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.
> 
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
> Changes since v1:
> - None
> 
> Changes since v2:
> - None
> 
>  board/freescale/mx6sabresd/mx6sabresd.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
> 
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
> index 5f65f1b..72d6562 100644
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -472,7 +472,8 @@ static int pfuze_init(void)
>  		return ret;
>  
>  	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
> -	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
> +	printf("PMIC:  PFUZE%s ID=0x%02x\n",
> +		((reg & 0xf) == 0) ? "100" : "200", reg);
>  
>  	/* Increase VGEN3 from 2.5 to 2.8V */
>  	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
> 

This is completely unrelated to the series - it can be applied
independently from the other patches. You do not need to resend this one
but please send in future patches belonging to the same series if they
are related to the same issue or to the same set of issues. This
simplifies review and merging - thanks !

Acked-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 1/4] imx: mx6slevk: Add I2C1 support

[Li Ye-B37916]

Hi Stefano,

On 9/12/2014 6:08 PM, Stefano Babic wrote:
> Hi Ye,
>
>
> On 11/09/2014 05:13, Ye.Li wrote:
>> Add I2C1 pin and pad settings, and enable the MXC I2C driver.
>>
> I see two different topics in this patch:
>
> 1. Add I2C1 pins to mx6sl pins. This is general, and not related to a
> specific board.
>
> 2. Add I2C1 support to 6slevk board, as in subject.
>
> Please spliut this patch to address ewach related issue.
>
> Thanks,
> Stefano Babic
>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>> Changes since v1:
>> - None
>>
>> Changes since v2:
>> - None
>>
>>  arch/arm/include/asm/arch-mx6/mx6sl_pins.h |    5 +++++
>>  board/freescale/mx6slevk/mx6slevk.c        |   26 ++++++++++++++++++++++++++
>>  include/configs/mx6slevk.h                 |    6 ++++++
>>  3 files changed, 37 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
>> index 045ccc4..ac84270 100644
>> --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
>> +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
>> @@ -34,5 +34,10 @@ enum {
>>  	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
>>  	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
>>  	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
>> +
>> +	MX6_PAD_I2C1_SDA__I2C1_SDA					= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
>> +	MX6_PAD_I2C1_SDA__GPIO_3_13					= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
>> +	MX6_PAD_I2C1_SCL__I2C1_SCL					= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
>> +	MX6_PAD_I2C1_SCL__GPIO_3_12					= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
>>  };
>>  #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
>> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
>> index a990b4c..fedd5c3 100644
>> --- a/board/freescale/mx6slevk/mx6slevk.c
>> +++ b/board/freescale/mx6slevk/mx6slevk.c
>> @@ -13,12 +13,14 @@
>>  #include <asm/arch/sys_proto.h>
>>  #include <asm/gpio.h>
>>  #include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/mxc_i2c.h>
>>  #include <asm/io.h>
>>  #include <linux/sizes.h>
>>  #include <common.h>
>>  #include <fsl_esdhc.h>
>>  #include <mmc.h>
>>  #include <netdev.h>
>> +#include <i2c.h>
>>  
>>  DECLARE_GLOBAL_DATA_PTR;
>>  
>> @@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
>>  #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
>>  		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>>  
>> +#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
>> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
>> +	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
>> +	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
>> +
>>  #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
>>  
>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +
>> +/* I2C1 for PMIC */
>> +struct i2c_pads_info i2c_pad_info0 = {
>> +	.sda = {
>> +		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
>> +		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
>> +		.gp = IMX_GPIO_NR(3, 13),
>> +	},
>> +	.scl = {
>> +		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
>> +		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
>> +		.gp = IMX_GPIO_NR(3, 12),
>> +	},
>> +};
>> +
>>  int dram_init(void)
>>  {
>>  	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
>> @@ -162,6 +185,9 @@ int board_init(void)
>>  #ifdef	CONFIG_FEC_MXC
>>  	setup_fec();
>>  #endif
>> +
>> +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
>> +
>>  	return 0;
>>  }
>>  
>> diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
>> index 3d05a64..bf5066f 100644
>> --- a/include/configs/mx6slevk.h
>> +++ b/include/configs/mx6slevk.h
>> @@ -60,6 +60,12 @@
>>  #define CONFIG_PHYLIB
>>  #define CONFIG_PHY_SMSC
>>  
>> +/* I2C Configs */
>> +#define CONFIG_CMD_I2C
>> +#define CONFIG_SYS_I2C
>> +#define CONFIG_SYS_I2C_MXC
>> +#define CONFIG_SYS_I2C_SPEED		  100000
>> +
>>  /* allow to overwrite serial and ethaddr */
>>  #define CONFIG_ENV_OVERWRITE
>>  #define CONFIG_CONS_INDEX		1
>>
>
I will split this patch to two in v4.

Best regards,
Ye Li

[U-Boot] [PATCH v3 3/4] imx: mx6sabresd: Add clear print for pfuze200

[Li Ye-B37916]

Hi Stefano,

On 9/12/2014 6:13 PM, Stefano Babic wrote:
> Hi Ye,
>
> On 11/09/2014 05:13, Ye.Li wrote:
>> Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.
>>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>> Changes since v1:
>> - None
>>
>> Changes since v2:
>> - None
>>
>>  board/freescale/mx6sabresd/mx6sabresd.c |    3 ++-
>>  1 files changed, 2 insertions(+), 1 deletions(-)
>>
>> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
>> index 5f65f1b..72d6562 100644
>> --- a/board/freescale/mx6sabresd/mx6sabresd.c
>> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
>> @@ -472,7 +472,8 @@ static int pfuze_init(void)
>>  		return ret;
>>  
>>  	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
>> -	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
>> +	printf("PMIC:  PFUZE%s ID=0x%02x\n",
>> +		((reg & 0xf) == 0) ? "100" : "200", reg);
>>  
>>  	/* Increase VGEN3 from 2.5 to 2.8V */
>>  	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
>>
> This is completely unrelated to the series - it can be applied
> independently from the other patches. You do not need to resend this one
> but please send in future patches belonging to the same series if they
> are related to the same issue or to the same set of issues. This
> simplifies review and merging - thanks !
>
> Acked-by: Stefano Babic <sbabic@denx.de>
>
> Best regards,
> Stefano Babic
>

Thanks for your comments. I feel this patch has somewhat relation with others, that in 4/4 the pfuze mode setup needs to consider the pfuze chip type. Of course, this patch can be applied independently.  I will be more careful about the patch set in future.

Best regards,
Ye Li