[PATCH 00/10] MIPS: ralink: various minor fixes and features

[PATCH 00/10] MIPS: ralink: various minor fixes and features

[John Crispin]

Over the last year these had been staged inside openwrt. These patches are a
pre-req for the following series which adds new mediatek SoCs.

John Crispin (10):
  MIPS: ralink: add verbose pmu info
  MIPS: ralink: add a helper for reading the ECO version
  MIPS: ralink: add rt_sysc_m32 helper
  MIPS: ralink: add a bootrom dumper module
  MIPS: ralink: add illegal access driver
  MIPS: ralink: allow manual memory override
  MIPS: ralink: add missing clk_set_rate() to clk.c
  MIPS: ralink: add rt2880 wmac clock
  MIPS: ralink: add rt3883 wmac clock
  MIPS: ralink: copy the commandline from the devicetree

 arch/mips/include/asm/mach-ralink/mt7620.h      |    5 ++
 arch/mips/include/asm/mach-ralink/ralink_regs.h |    7 ++
 arch/mips/ralink/Makefile                       |    4 ++
 arch/mips/ralink/bootrom.c                      |   48 +++++++++++++
 arch/mips/ralink/clk.c                          |    6 ++
 arch/mips/ralink/ill_acc.c                      |   87 +++++++++++++++++++++++
 arch/mips/ralink/mt7620.c                       |   26 +++++++
 arch/mips/ralink/of.c                           |   18 ++++-
 arch/mips/ralink/rt288x.c                       |    3 +-
 arch/mips/ralink/rt3883.c                       |    1 +
 10 files changed, 203 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/ralink/bootrom.c
 create mode 100644 arch/mips/ralink/ill_acc.c

-- 
1.7.10.4

[PATCH 01/10] MIPS: ralink: add verbose pmu info

[John Crispin]

Print the PMU and LDO settings on boot.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/mt7620.c |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index a3ad56c..5846817 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -20,6 +20,22 @@
 
 #include "common.h"
 
+/* analog */
+#define PMU0_CFG		0x88
+#define PMU_SW_SET		BIT(28)
+#define A_DCDC_EN		BIT(24)
+#define A_SSC_PERI		BIT(19)
+#define A_SSC_GEN		BIT(18)
+#define A_SSC_M			0x3
+#define A_SSC_S			16
+#define A_DLY_M			0x7
+#define A_DLY_S			8
+#define A_VTUNE_M		0xff
+
+/* digital */
+#define PMU1_CFG		0x8C
+#define DIG_SW_SEL		BIT(25)
+
 /* does the board have sdram or ddram */
 static int dram_type;
 
@@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 	u32 n1;
 	u32 rev;
 	u32 cfg0;
+	u32 pmu0;
+	u32 pmu1;
 
 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
@@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 		BUG();
 	}
 	soc_info->mem_base = MT7620_DRAM_BASE;
+
+	pmu0 = __raw_readl(sysc + PMU0_CFG);
+	pmu1 = __raw_readl(sysc + PMU1_CFG);
+
+	pr_info("Analog PMU set to %s control\n",
+		(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
+	pr_info("Digital PMU set to %s control\n",
+		(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 }
-- 
1.7.10.4

[PATCH 02/10] MIPS: ralink: add a helper for reading the ECO version

[John Crispin]

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/mt7620.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 6f9b24f..7ff9290 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -105,4 +105,9 @@
 #define MT7620_GPIO_MODE_EPHY		BIT(15)
 #define MT7620_GPIO_MODE_WDT		BIT(22)
 
+static inline int mt7620_get_eco(void)
+{
+	return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+}
+
 #endif
-- 
1.7.10.4

[PATCH 03/10] MIPS: ralink: add rt_sysc_m32 helper

[John Crispin]

We already have a read and write wrapper. This adds the missing mask wrapper.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/ralink_regs.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
index 5a508f9..bd93014 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned reg)
 	return __raw_readl(rt_sysc_membase + reg);
 }
 
+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
+{
+	u32 val = rt_sysc_r32(reg) & ~clr;
+
+	__raw_writel(val | set, rt_sysc_membase + reg);
+}
+
 static inline void rt_memc_w32(u32 val, unsigned reg)
 {
 	__raw_writel(val, rt_memc_membase + reg);
-- 
1.7.10.4

[PATCH 04/10] MIPS: ralink: add a bootrom dumper module

[John Crispin]

This patch adds a trivial driver that allows userland to extract the bootrom of
a SoC via debugfs.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/Makefile  |    2 ++
 arch/mips/ralink/bootrom.c |   48 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 arch/mips/ralink/bootrom.c

diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 98ae349..584a8d9 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
 
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 
+obj-$(CONFIG_DEBUG_FS) += bootrom.o
+
 obj-y += dts/
diff --git a/arch/mips/ralink/bootrom.c b/arch/mips/ralink/bootrom.c
new file mode 100644
index 0000000..5403468
--- /dev/null
+++ b/arch/mips/ralink/bootrom.c
@@ -0,0 +1,48 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#define BOOTROM_OFFSET	0x10118000
+#define BOOTROM_SIZE	0x8000
+
+static void __iomem *membase = (void __iomem *) KSEG1ADDR(BOOTROM_OFFSET);
+
+static int bootrom_show(struct seq_file *s, void *unused)
+{
+	seq_write(s, membase, BOOTROM_SIZE);
+
+	return 0;
+}
+
+static int bootrom_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, bootrom_show, NULL);
+}
+
+static const struct file_operations bootrom_file_ops = {
+	.open		= bootrom_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int bootrom_setup(void)
+{
+	if (!debugfs_create_file("bootrom", 0444,
+			NULL, NULL, &bootrom_file_ops)) {
+		pr_err("Failed to create bootrom debugfs file\n");
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+postcore_initcall(bootrom_setup);
-- 
1.7.10.4

[PATCH 05/10] MIPS: ralink: add illegal access driver

[John Crispin]

These SoCs have a special irq that fires upon an illegal memmory access.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/Makefile  |    2 +
 arch/mips/ralink/ill_acc.c |   87 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 arch/mips/ralink/ill_acc.c

diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 584a8d9..fc57c16 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 
 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 
+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+
 obj-$(CONFIG_SOC_RT288X) += rt288x.o
 obj-$(CONFIG_SOC_RT305X) += rt305x.o
 obj-$(CONFIG_SOC_RT3883) += rt3883.o
diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
new file mode 100644
index 0000000..e20b02e
--- /dev/null
+++ b/arch/mips/ralink/ill_acc.c
@@ -0,0 +1,87 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#define REG_ILL_ACC_ADDR	0x10
+#define REG_ILL_ACC_TYPE	0x14
+
+#define ILL_INT_STATUS		BIT(31)
+#define ILL_ACC_WRITE		BIT(30)
+#define ILL_ACC_LEN_M		0xff
+#define ILL_ACC_OFF_M		0xf
+#define ILL_ACC_OFF_S		16
+#define ILL_ACC_ID_M		0x7
+#define ILL_ACC_ID_S		8
+
+#define	DRV_NAME		"ill_acc"
+
+static const char * const ill_acc_ids[] = {
+	"cpu", "dma", "ppe", "pdma rx", "pdma tx", "pci/e", "wmac", "usb",
+};
+
+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
+{
+	struct device *dev = (struct device *) _priv;
+	u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
+	u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
+
+	dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
+		(type & ILL_ACC_WRITE) ? ("write") : ("read"),
+		ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
+		addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
+		type & ILL_ACC_LEN_M);
+
+	rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
+
+	return IRQ_HANDLED;
+}
+
+static int __init ill_acc_of_setup(void)
+{
+	struct platform_device *pdev;
+	struct device_node *np;
+	int irq;
+
+	/* somehow this driver breaks on RT5350 */
+	if (of_machine_is_compatible("ralink,rt5350-soc"))
+		return -EINVAL;
+
+	np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
+	if (!np)
+		return -EINVAL;
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev) {
+		pr_err("%s: failed to lookup pdev\n", np->name);
+		return -EINVAL;
+	}
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		return -EINVAL;
+	}
+
+	if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		return -EINVAL;
+	}
+
+	rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
+
+	dev_info(&pdev->dev, "irq registered\n");
+
+	return 0;
+}
+
+arch_initcall(ill_acc_of_setup);
-- 
1.7.10.4

[PATCH 06/10] MIPS: ralink: allow manual memory override

[John Crispin]

RT5350 relies on the bootloader setting up the memc correctly. On some boards
the setup is incorrect leading to 32 MB being available but only 16 MB being
recognized. Allow these boards to manually override the memory range.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/of.c |   16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 7c4598c..7b3aa68 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -53,6 +53,17 @@ void __init device_tree_init(void)
 	unflatten_and_copy_device_tree();
 }
 
+static int memory_dtb;
+
+static int __init early_init_dt_find_memory(unsigned long node,
+				const char *uname, int depth, void *data)
+{
+	if (depth == 1 && !strcmp(uname, "memory@0"))
+		memory_dtb = 1;
+
+	return 0;
+}
+
 void __init plat_mem_setup(void)
 {
 	set_io_port_base(KSEG1);
@@ -63,7 +74,10 @@ void __init plat_mem_setup(void)
 	 */
 	__dt_setup_arch(__dtb_start);
 
-	if (soc_info.mem_size)
+	of_scan_flat_dt(early_init_dt_find_memory, NULL);
+	if (memory_dtb)
+		of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+	else if (soc_info.mem_size)
 		add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
 				  BOOT_MEM_RAM);
 	else
-- 
1.7.10.4

[PATCH 07/10] MIPS: ralink: add missing clk_set_rate() to clk.c

[John Crispin]

This function was missing causing make allmod to fail.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/clk.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 5d0983d..feb5a9b 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(clk_get_rate);
 
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	return -1;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
 void __init plat_time_init(void)
 {
 	struct clk *clk;
-- 
1.7.10.4

[PATCH 08/10] MIPS: ralink: add rt2880 wmac clock

[John Crispin]

Register the wireleass mac clock on rt2880. This is required by the wifi driver.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/rt288x.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
index f87de1a..90e8934 100644
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
 
 void __init ralink_clk_init(void)
 {
-	unsigned long cpu_rate;
+	unsigned long cpu_rate, wmac_rate = 40000000;
 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
 
@@ -101,6 +101,7 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("300500.uart", cpu_rate / 2);
 	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
 	ralink_clk_add("400000.ethernet", cpu_rate / 2);
+	ralink_clk_add("480000.wmac", wmac_rate);
 }
 
 void __init ralink_of_remap(void)
-- 
1.7.10.4

[PATCH 09/10] MIPS: ralink: add rt3883 wmac clock

[John Crispin]

Register the wireless mac clock on rti3883. This is required by the wifi driver.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/rt3883.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
index b474ac2..58b5b9f 100644
--- a/arch/mips/ralink/rt3883.c
+++ b/arch/mips/ralink/rt3883.c
@@ -204,6 +204,7 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000b00.spi", sys_rate);
 	ralink_clk_add("10000c00.uartlite", 40000000);
 	ralink_clk_add("10100000.ethernet", sys_rate);
+	ralink_clk_add("10180000.wmac", 40000000);
 }
 
 void __init ralink_of_remap(void)
-- 
1.7.10.4

[PATCH 10/10] MIPS: ralink: copy the commandline from the devicetree

[John Crispin]

This is a regression caused by:
commit afb46f7996e91aeb36e07bc92cf96e8045bec00e
Author: Rob Herring <robh@kernel.org>
Date:   Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree

Make the of init code reuse the cmdline defined inside the dts.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/of.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 7b3aa68..e156eed 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -74,6 +74,8 @@ void __init plat_mem_setup(void)
 	 */
 	__dt_setup_arch(__dtb_start);
 
+	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+
 	of_scan_flat_dt(early_init_dt_find_memory, NULL);
 	if (memory_dtb)
 		of_scan_flat_dt(early_init_dt_scan_memory, NULL);
-- 
1.7.10.4

Re: [PATCH 05/10] MIPS: ralink: add illegal access driver

[Sergei Shtylyov]

Hello.

On 10/09/2014 03:53 AM, John Crispin wrote:

> These SoCs have a special irq that fires upon an illegal memmory access.

> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>   arch/mips/ralink/Makefile  |    2 +
>   arch/mips/ralink/ill_acc.c |   87 ++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 89 insertions(+)
>   create mode 100644 arch/mips/ralink/ill_acc.c

[...]
> diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
> new file mode 100644
> index 0000000..e20b02e
> --- /dev/null
> +++ b/arch/mips/ralink/ill_acc.c
> @@ -0,0 +1,87 @@
[...]
> +static const char * const ill_acc_ids[] = {
> +	"cpu", "dma", "ppe", "pdma rx", "pdma tx", "pci/e", "wmac", "usb",
> +};
> +
> +static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
> +{
> +	struct device *dev = (struct device *) _priv;
> +	u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
> +	u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
> +
> +	dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
> +		(type & ILL_ACC_WRITE) ? ("write") : ("read"),

    Hm, why these () around string literals? Not that the ones before ? are 
needed too...

WBR, Sergei

Re: [PATCH 08/10] MIPS: ralink: add rt2880 wmac clock

[Sergei Shtylyov]

On 10/09/2014 03:53 AM, John Crispin wrote:

> Register the wireleass mac clock on rt2880. This is required by the wifi driver.

> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>   arch/mips/ralink/rt288x.c |    3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)

> diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
> index f87de1a..90e8934 100644
> --- a/arch/mips/ralink/rt288x.c
> +++ b/arch/mips/ralink/rt288x.c
> @@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
>
>   void __init ralink_clk_init(void)
>   {
> -	unsigned long cpu_rate;
> +	unsigned long cpu_rate, wmac_rate = 40000000;

    Why you need this variable at all?

>   	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
>   	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
>
> @@ -101,6 +101,7 @@ void __init ralink_clk_init(void)
>   	ralink_clk_add("300500.uart", cpu_rate / 2);
>   	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
>   	ralink_clk_add("400000.ethernet", cpu_rate / 2);
> +	ralink_clk_add("480000.wmac", wmac_rate);
>   }

WBR, Sergei

Re: [PATCH 08/10] MIPS: ralink: add rt2880 wmac clock

[John Crispin]

On 09/10/2014 18:20, Sergei Shtylyov wrote:
> On 10/09/2014 03:53 AM, John Crispin wrote:
>
>> Register the wireleass mac clock on rt2880. This is required by the
>> wifi driver.
>
>> Signed-off-by: John Crispin <blogic@openwrt.org>
>> ---
>>   arch/mips/ralink/rt288x.c |    3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>
>> diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
>> index f87de1a..90e8934 100644
>> --- a/arch/mips/ralink/rt288x.c
>> +++ b/arch/mips/ralink/rt288x.c
>> @@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
>>
>>   void __init ralink_clk_init(void)
>>   {
>> -    unsigned long cpu_rate;
>> +    unsigned long cpu_rate, wmac_rate = 40000000;
>
>    Why you need this variable at all?
in theory there can be a 20mhz clock. the code follows the same pattern
as the other SoCs. due to lack of datasheet do however not know how to
read the clock register. if you see this as a problem we can change it.
   
    John