* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-16 16:58 ` Sonny Rao
0 siblings, 0 replies; 13+ messages in thread
From: Sonny Rao @ 2014-10-16 16:58 UTC (permalink / raw)
To: Alim Akhtar, linux-mmc
Cc: Heiko Stuebner, Seungwon Jeon, Jaehoon Chung, Ulf Hansson,
dianders, eddie.cai, addy.ke, linux-arm-kernel, linux-kernel,
Sonny Rao
We've already got a reset of DMA after it's done. Add one before we
start DMA too. This fixes a data corruption on Rockchip SoCs which
will get bad data when doing a DMA transfer after doing a PIO transfer.
We tested this on an Exynos 5800 with HS200 and didn't notice any
difference in sequential read throughput.
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
---
drivers/mmc/host/dw_mmc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 69f0cc6..ca67f69 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -83,6 +83,7 @@ struct idmac_desc {
#endif /* CONFIG_MMC_DW_IDMAC */
static bool dw_mci_reset(struct dw_mci *host);
+static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
#if defined(CONFIG_DEBUG_FS)
static int dw_mci_req_show(struct seq_file *s, void *v)
@@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
dw_mci_translate_sglist(host, host->data, sg_len);
+ /* Make sure to reset DMA in case we did PIO before this */
+ dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
+ dw_mci_idmac_reset(host);
+
/* Select IDMAC interface */
temp = mci_readl(host, CTRL);
temp |= SDMMC_CTRL_USE_IDMAC;
--
2.1.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-16 16:58 ` Sonny Rao
0 siblings, 0 replies; 13+ messages in thread
From: Sonny Rao @ 2014-10-16 16:58 UTC (permalink / raw)
To: linux-arm-kernel
We've already got a reset of DMA after it's done. Add one before we
start DMA too. This fixes a data corruption on Rockchip SoCs which
will get bad data when doing a DMA transfer after doing a PIO transfer.
We tested this on an Exynos 5800 with HS200 and didn't notice any
difference in sequential read throughput.
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
---
drivers/mmc/host/dw_mmc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 69f0cc6..ca67f69 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -83,6 +83,7 @@ struct idmac_desc {
#endif /* CONFIG_MMC_DW_IDMAC */
static bool dw_mci_reset(struct dw_mci *host);
+static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
#if defined(CONFIG_DEBUG_FS)
static int dw_mci_req_show(struct seq_file *s, void *v)
@@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
dw_mci_translate_sglist(host, host->data, sg_len);
+ /* Make sure to reset DMA in case we did PIO before this */
+ dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
+ dw_mci_idmac_reset(host);
+
/* Select IDMAC interface */
temp = mci_readl(host, CTRL);
temp |= SDMMC_CTRL_USE_IDMAC;
--
2.1.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
2014-10-16 16:58 ` Sonny Rao
@ 2014-10-17 8:26 ` Jaehoon Chung
-1 siblings, 0 replies; 13+ messages in thread
From: Jaehoon Chung @ 2014-10-17 8:26 UTC (permalink / raw)
To: Sonny Rao, Alim Akhtar, linux-mmc
Cc: Heiko Stuebner, Seungwon Jeon, Ulf Hansson, dianders, eddie.cai,
addy.ke, linux-arm-kernel, linux-kernel
Hi, Sonny.
On 10/17/2014 01:58 AM, Sonny Rao wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
Didn't affect the write throughput?
I tested this on exynos3/4 with DDR50 and HS200.
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-17 8:26 ` Jaehoon Chung
0 siblings, 0 replies; 13+ messages in thread
From: Jaehoon Chung @ 2014-10-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Sonny.
On 10/17/2014 01:58 AM, Sonny Rao wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
Didn't affect the write throughput?
I tested this on exynos3/4 with DDR50 and HS200.
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
2014-10-16 16:58 ` Sonny Rao
(?)
@ 2014-10-17 12:28 ` Alim Akhtar
-1 siblings, 0 replies; 13+ messages in thread
From: Alim Akhtar @ 2014-10-17 12:28 UTC (permalink / raw)
To: Sonny Rao
Cc: linux-mmc, Heiko Stuebner, Seungwon Jeon, Jaehoon Chung,
Ulf Hansson, Douglas Anderson, Eddie Cai, Addy Ke,
linux-arm-kernel, linux-kernel
Hi Sonny,
On Thu, Oct 16, 2014 at 10:28 PM, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
This looks fine.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
--
Regards,
Alim
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-17 12:28 ` Alim Akhtar
0 siblings, 0 replies; 13+ messages in thread
From: Alim Akhtar @ 2014-10-17 12:28 UTC (permalink / raw)
To: Sonny Rao
Cc: linux-mmc, Heiko Stuebner, Seungwon Jeon, Jaehoon Chung,
Ulf Hansson, Douglas Anderson, Eddie Cai, Addy Ke,
linux-arm-kernel, linux-kernel
Hi Sonny,
On Thu, Oct 16, 2014 at 10:28 PM, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
This looks fine.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
--
Regards,
Alim
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-17 12:28 ` Alim Akhtar
0 siblings, 0 replies; 13+ messages in thread
From: Alim Akhtar @ 2014-10-17 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sonny,
On Thu, Oct 16, 2014 at 10:28 PM, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
This looks fine.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
--
Regards,
Alim
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
2014-10-17 8:26 ` Jaehoon Chung
(?)
@ 2014-10-18 21:14 ` Sonny Rao
-1 siblings, 0 replies; 13+ messages in thread
From: Sonny Rao @ 2014-10-18 21:14 UTC (permalink / raw)
To: Jaehoon Chung
Cc: Alim Akhtar, linux-mmc, Heiko Stuebner, Seungwon Jeon,
Ulf Hansson, Douglas Anderson, Eddie Cai, Addy Ke,
linux-arm-kernel, linux-kernel
On Fri, Oct 17, 2014 at 1:26 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Sonny.
>
> On 10/17/2014 01:58 AM, Sonny Rao wrote:
>> We've already got a reset of DMA after it's done. Add one before we
>> start DMA too. This fixes a data corruption on Rockchip SoCs which
>> will get bad data when doing a DMA transfer after doing a PIO transfer.
>>
>> We tested this on an Exynos 5800 with HS200 and didn't notice any
>> difference in sequential read throughput.
>
> Didn't affect the write throughput?
Write is usually much slower than read, but I went ahead and re-tested
and saw no difference on writes.
> I tested this on exynos3/4 with DDR50 and HS200.
>
> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
>
>>
>> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
>> Signed-off-by: Doug Anderson <dianders@chromium.org>
>> Tested-by: Doug Anderson <dianders@chromium.org>
>> ---
>> drivers/mmc/host/dw_mmc.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 69f0cc6..ca67f69 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -83,6 +83,7 @@ struct idmac_desc {
>> #endif /* CONFIG_MMC_DW_IDMAC */
>>
>> static bool dw_mci_reset(struct dw_mci *host);
>> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>>
>> #if defined(CONFIG_DEBUG_FS)
>> static int dw_mci_req_show(struct seq_file *s, void *v)
>> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>>
>> dw_mci_translate_sglist(host, host->data, sg_len);
>>
>> + /* Make sure to reset DMA in case we did PIO before this */
>> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
>> + dw_mci_idmac_reset(host);
>> +
>> /* Select IDMAC interface */
>> temp = mci_readl(host, CTRL);
>> temp |= SDMMC_CTRL_USE_IDMAC;
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-18 21:14 ` Sonny Rao
0 siblings, 0 replies; 13+ messages in thread
From: Sonny Rao @ 2014-10-18 21:14 UTC (permalink / raw)
To: Jaehoon Chung
Cc: Alim Akhtar, linux-mmc, Heiko Stuebner, Seungwon Jeon,
Ulf Hansson, Douglas Anderson, Eddie Cai, Addy Ke,
linux-arm-kernel, linux-kernel
On Fri, Oct 17, 2014 at 1:26 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Sonny.
>
> On 10/17/2014 01:58 AM, Sonny Rao wrote:
>> We've already got a reset of DMA after it's done. Add one before we
>> start DMA too. This fixes a data corruption on Rockchip SoCs which
>> will get bad data when doing a DMA transfer after doing a PIO transfer.
>>
>> We tested this on an Exynos 5800 with HS200 and didn't notice any
>> difference in sequential read throughput.
>
> Didn't affect the write throughput?
Write is usually much slower than read, but I went ahead and re-tested
and saw no difference on writes.
> I tested this on exynos3/4 with DDR50 and HS200.
>
> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
>
>>
>> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
>> Signed-off-by: Doug Anderson <dianders@chromium.org>
>> Tested-by: Doug Anderson <dianders@chromium.org>
>> ---
>> drivers/mmc/host/dw_mmc.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 69f0cc6..ca67f69 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -83,6 +83,7 @@ struct idmac_desc {
>> #endif /* CONFIG_MMC_DW_IDMAC */
>>
>> static bool dw_mci_reset(struct dw_mci *host);
>> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>>
>> #if defined(CONFIG_DEBUG_FS)
>> static int dw_mci_req_show(struct seq_file *s, void *v)
>> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>>
>> dw_mci_translate_sglist(host, host->data, sg_len);
>>
>> + /* Make sure to reset DMA in case we did PIO before this */
>> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
>> + dw_mci_idmac_reset(host);
>> +
>> /* Select IDMAC interface */
>> temp = mci_readl(host, CTRL);
>> temp |= SDMMC_CTRL_USE_IDMAC;
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-18 21:14 ` Sonny Rao
0 siblings, 0 replies; 13+ messages in thread
From: Sonny Rao @ 2014-10-18 21:14 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Oct 17, 2014 at 1:26 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Sonny.
>
> On 10/17/2014 01:58 AM, Sonny Rao wrote:
>> We've already got a reset of DMA after it's done. Add one before we
>> start DMA too. This fixes a data corruption on Rockchip SoCs which
>> will get bad data when doing a DMA transfer after doing a PIO transfer.
>>
>> We tested this on an Exynos 5800 with HS200 and didn't notice any
>> difference in sequential read throughput.
>
> Didn't affect the write throughput?
Write is usually much slower than read, but I went ahead and re-tested
and saw no difference on writes.
> I tested this on exynos3/4 with DDR50 and HS200.
>
> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
>
>>
>> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
>> Signed-off-by: Doug Anderson <dianders@chromium.org>
>> Tested-by: Doug Anderson <dianders@chromium.org>
>> ---
>> drivers/mmc/host/dw_mmc.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 69f0cc6..ca67f69 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -83,6 +83,7 @@ struct idmac_desc {
>> #endif /* CONFIG_MMC_DW_IDMAC */
>>
>> static bool dw_mci_reset(struct dw_mci *host);
>> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>>
>> #if defined(CONFIG_DEBUG_FS)
>> static int dw_mci_req_show(struct seq_file *s, void *v)
>> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>>
>> dw_mci_translate_sglist(host, host->data, sg_len);
>>
>> + /* Make sure to reset DMA in case we did PIO before this */
>> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
>> + dw_mci_idmac_reset(host);
>> +
>> /* Select IDMAC interface */
>> temp = mci_readl(host, CTRL);
>> temp |= SDMMC_CTRL_USE_IDMAC;
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
2014-10-16 16:58 ` Sonny Rao
(?)
@ 2014-10-27 14:13 ` Ulf Hansson
-1 siblings, 0 replies; 13+ messages in thread
From: Ulf Hansson @ 2014-10-27 14:13 UTC (permalink / raw)
To: Sonny Rao
Cc: Alim Akhtar, linux-mmc, Heiko Stuebner, Seungwon Jeon,
Jaehoon Chung, Doug Anderson, eddie.cai, Addy Ke,
linux-arm-kernel, linux-kernel
On 16 October 2014 18:58, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
Thanks! Applied for next!
Kind regards
Uffe
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-27 14:13 ` Ulf Hansson
0 siblings, 0 replies; 13+ messages in thread
From: Ulf Hansson @ 2014-10-27 14:13 UTC (permalink / raw)
To: Sonny Rao
Cc: Alim Akhtar, linux-mmc, Heiko Stuebner, Seungwon Jeon,
Jaehoon Chung, Doug Anderson, eddie.cai, Addy Ke,
linux-arm-kernel, linux-kernel
On 16 October 2014 18:58, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
Thanks! Applied for next!
Kind regards
Uffe
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC
@ 2014-10-27 14:13 ` Ulf Hansson
0 siblings, 0 replies; 13+ messages in thread
From: Ulf Hansson @ 2014-10-27 14:13 UTC (permalink / raw)
To: linux-arm-kernel
On 16 October 2014 18:58, Sonny Rao <sonnyrao@chromium.org> wrote:
> We've already got a reset of DMA after it's done. Add one before we
> start DMA too. This fixes a data corruption on Rockchip SoCs which
> will get bad data when doing a DMA transfer after doing a PIO transfer.
>
> We tested this on an Exynos 5800 with HS200 and didn't notice any
> difference in sequential read throughput.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
Thanks! Applied for next!
Kind regards
Uffe
> ---
> drivers/mmc/host/dw_mmc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 69f0cc6..ca67f69 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -83,6 +83,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static bool dw_mci_reset(struct dw_mci *host);
> +static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> #if defined(CONFIG_DEBUG_FS)
> static int dw_mci_req_show(struct seq_file *s, void *v)
> @@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>
> dw_mci_translate_sglist(host, host->data, sg_len);
>
> + /* Make sure to reset DMA in case we did PIO before this */
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
> + dw_mci_idmac_reset(host);
> +
> /* Select IDMAC interface */
> temp = mci_readl(host, CTRL);
> temp |= SDMMC_CTRL_USE_IDMAC;
> --
> 2.1.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-10-27 14:13 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-16 16:58 [PATCH v2] mmc: dw_mmc: Reset DMA before enabling IDMAC Sonny Rao
2014-10-16 16:58 ` Sonny Rao
2014-10-17 8:26 ` Jaehoon Chung
2014-10-17 8:26 ` Jaehoon Chung
2014-10-18 21:14 ` Sonny Rao
2014-10-18 21:14 ` Sonny Rao
2014-10-18 21:14 ` Sonny Rao
2014-10-17 12:28 ` Alim Akhtar
2014-10-17 12:28 ` Alim Akhtar
2014-10-17 12:28 ` Alim Akhtar
2014-10-27 14:13 ` Ulf Hansson
2014-10-27 14:13 ` Ulf Hansson
2014-10-27 14:13 ` Ulf Hansson
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