* [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support
@ 2014-10-17 21:17 Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 01/21] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
` (21 more replies)
0 siblings, 22 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Version 14 of PV(H) PMU patches.
Changes in v14:
* Moved struct xen_pmu_regs to pmu.h
* Moved CHECK_pmu_* to an earlier patch (when structures are first introduced)
* Added PMU_SAMPLE_REAL flag to indicate whether the sample was taken in real mode
* Simplified slightly setting rules for xenpmu_data flags
* Rewrote vpmu_force_context_switch() to again use continuations. (Returning EAGAIN
to user would mean that VPMU mode may get into inconsistent state (across processors)
and dealing with that is more compicated than I'd like).
* Fixed msraddr_to_bitpos() and converted it into an inline
* Replaced address range check in vmpu_do_interrupt() with guest_mode()
* No error returns from __initcall
* Rebased on top of recent VPMU changes
* Various cleanups
Changes in v13:
* Rearranged data in xenpf_symdata to eliminate a hole (no change in
structure size)
* Removed unnecessary zeroing of last character in name string during
symbol read hypercall
* Updated comment in access_vectors for pmu_use operation
* Compute AMD MSR bank size at runtime
* Moved a couple of BUILD_BUG_ON later, to when the structures they are
checking are first used
* Added ss and eflags to xen_pmu_registers structure
* vpmu_force_context_switch() uses per-cpu tasklet pointers.
* Moved most of arch-specific VPMU initialization code into an __initcall()
to avoid re-calculating/re-checking things more than once (new patch, #12)
* Replaced is_*_domain() with is_*_vcpu()
* choose_hwdom_vcpu() will now assume that hardware_domain->vcpu[idx]
is always there (callers will still verify whether or not that's true)
* Fixed a couple of sampled vs. sampling tests in vpmu_do_interrupt()
* Pass CS to the guest unchanged, add pmu_flags's flag to indicate whether the
sample was for a user or kernel space. Move pmu_flags from xen_pmu_data into
xen_pmu_arch
* Removed local msr_content variable from vpmu_do_wrmsr()
* Re-arranged code in parse_vpmu_param()
* Made vpmu_interrupt_type checks test for value, not individual bits
* Moved PMU_SOFTIRQ definition into arch-specific header
* Moved vpmu*.c files into xen/arch/x86/cpu/ instead of xen/arch/x86/
* For hypervisor samples, report DOMID_XEN to the guest
* Changed logic to select which registers to report to the guest (include RIP
check to see whether we are in the hypervisor)
Changes in v12:
* Added XSM support
* Made a valifity check before writing MSR_CORE_PERF_GLOBAL_OVF_CTRL
* Updated documentation for 'vpmu=nmi' option
* Added more text to a bunch of commit messages (per Konrad's request)
Changes in v11:
* Replaced cpu_user_regs with new xen_pmu_regs (IP, SP, CS) in xen_pmu_arch.
- as part of this re-work noticed that CS registers were set in later patch then
needed. Moved those changes to appropriate place
* Added new VPMU mode (XENPMU_MODE_HV). Now XENPMU_MODE_SELF will only provide dom0
with its own samples only (i.e. no hypervisor data) and XENPMU_MODE_HV will be what
XENPMU_MODE_SELF used to be.
* Kept vmx_add_guest_msr()/vmx_add_host_load_msr() as wrappers around vmx_add_msr()
* Cleaned up VPMU context switch macros (moved 'if(prev!=next)' back to context_switch())
* Dropped hypercall continuation from vpmu_force_context_switch() and replaced it with
-EAGAIN error if hypercall_preempt_check() is true after 2ms.
* Kept vpmu_do_rdmsr()/vpmu_do_wrmsr as wrapperd for vpmu_do_msr()
* Move context switching patch (#13) earlier in the series (for proper bisection support)
* Various comment updates and cleanups
* Dropped a bunch of Reviewed-by and all Tested-by tags
Changes in v10:
* Swapped address and name fields of xenpf_symdata (to make it smaller on 32-bit)
* Dropped vmx_rm_guest_msr() as it requires refcountig which makes code more complicated.
* Cleaned up vlapic_reg_write()
* Call vpmu_destroy() for both HVM and PVH VCPUs
* Verify that (xen_pmu_data+PMU register bank) fit into a page
* Return error codes from arch-specific VPMU init code
* Moved VPMU-related context switch logic into inlines
* vpmu_force_context_switch() changes:
o Avoid greater than page-sized allocations
o Prevent another VCPU from starting VPMU sync while the first sync is in progress
* Avoid stack leak in do_xenpmu_op()
* Checked validity of Intel VPMU MSR values before they are committed
* Fixed MSR handling in traps.c (avoid potential accesses to Intel MSRs on AMD)
* Fixed VCPU selection in interrupt handler for 32-bit dom0 (sampled => sampling)
* Clarified commit messages (patches 2, 13, 18)
* Various cleanups
Changes in v9:
* Restore VPMU context after context_saved() is called in
context_switch(). This is needed because vpmu_load() may end up
calling vmx_vmcs_try_enter()->vcpu_pause() and that needs is_running
to be correctly set/cleared. (patch 18, dropped review acks)
* Added patch 2 to properly manage VPMU_CONTEXT_LOADED
* Addressed most of Jan's comments.
o Keep track of time in vpmu_force_context_switch() to properly break
out of a loop when using hypercall continuations
o Fixed logic in calling vpmu_do_msr() in emulate_privileged_op()
o Cleaned up vpmu_interrupt() wrt vcpu variable names to (hopefully)
make it more clear which vcpu we are using
o Cleaned up vpmu_do_wrmsr()
o Did *not* replace sizeof(uint64_t) with sizeof(variable) in
amd_vpmu_initialise(): throughout the code registers are declared as
uint64_t and if we are to add a new type (e.g. reg_t) this should be
done in a separate patch, unrelated to this series.
o Various more minor cleanups and code style fixes
Changes in v8:
* Cleaned up a bit definitions of struct xenpf_symdata and xen_pmu_params
* Added compat checks for vpmu structures
* Converted vpmu flag manipulation macros to inline routines
* Reimplemented vpmu_unload_all() to avoid long loops
* Reworked PMU fault generation and handling (new patch #12)
* Added checks for domain->vcpu[] non-NULLness
* Added more comments, renamed some routines and macros, code style cleanup
Changes in v7:
* When reading hypervisor symbols make the caller pass buffer length
(as opposed to having this length be part of the API). Make the
hypervisor buffer static, make xensyms_read() return zero-length
string on end-of-symbols. Make 'type' field of xenpf_symdata a char,
drop compat_pf_symdata definition.
* Spread PVH support across patches as opposed to lumping it into a
separate patch
* Rename vpmu_is_set_all() to vpmu_are_all_set()
* Split VPMU cleanup patch in two
* Use memmove when copying VMX guest and host MSRs
* Make padding of xen_arch_pmu's context union a constand that does not
depend on arch context size.
* Set interface version to 0.1
* Check pointer validity in pvpmu_init/destroy()
* Fixed crash in core2_vpmu_dump()
* Fixed crash in vmx_add_msr()
* Break handling of Intel and AMD MSRs in traps.c into separate cases
* Pass full CS selector to guests
* Add lock in pvpmu init code to prevent potential race
Changes in v6:
* Two new patches:
o Merge VMX MSR add/remove routines in vmcs.c (patch 5)
o Merge VPMU read/write MSR routines in vpmu.c (patch 14)
* Check for pending NMI softirq after saving VPMU context to prevent a newly-scheduled
guest from overwriting sampled_vcpu written by de-scheduled VPCU.
* Keep track of enabled counters on Intel. This was removed in earlier patches and
was a mistake. As result of this change struct vpmu will have a pointer to private
context data (i.e. data that is not exposed to a PV(H) guest). Use this private pointer
on SVM as well for storing MSR bitmap status (it was unnecessarily exposed to PV guests
earlier).
Dropped Reviewed-by: and Tested-by: tags from patch 4 since it needs to be reviewed
agan (core2_vpmu_do_wrmsr() routine, mostly)
* Replaced references to dom0 with hardware_domain (and is_control_domain with
is_hardware_domain for consistency)
* Prevent non-privileged domains from reading PMU MSRs in VPMU_PRIV_MODE
* Reverted unnecessary changes in vpmu_initialise()'s switch statement
* Fixed comment in vpmu_do_interrupt
Changes in v5:
* Dropped patch number 2 ("Stop AMD counters when called from vpmu_save_force()")
as no longer needed
* Added patch number 2 that marks context as loaded before PMU registers are
loaded. This prevents situation where a PMU interrupt may occur while context
is still viewed as not loaded. (This is really a bug fix for exsiting VPMU
code)
* Renamed xenpmu.h files to pmu.h
* More careful use of is_pv_domain(), is_hvm_domain(, is_pvh_domain and
has_hvm_container_domain(). Also explicitly disabled support for PVH until
patch 16 to make distinction between usage of the above macros more clear.
* Added support for disabling VPMU support during runtime.
* Disable VPMUs for non-privileged domains when switching to privileged
profiling mode
* Added ARM stub for xen_arch_pmu_t
* Separated vpmu_mode from vpmu_features
* Moved CS register query to make sure we use appropriate query mechanism for
various guest types.
* LVTPC is now set from value in shared area, not copied from dom0
* Various code and comments cleanup as suggested by Jan.
Changes in v4:
* Added support for PVH guests:
o changes in pvpmu_init() to accommodate both PV and PVH guests, still in patch 10
o more careful use of is_hvm_domain
o Additional patch (16)
* Moved HVM interrupt handling out of vpmu_do_interrupt() for NMI-safe handling
* Fixed dom0's VCPU selection in privileged mode
* Added a cast in register copy for 32-bit PV guests cpu_user_regs_t in vpmu_do_interrupt.
(don't want to expose compat_cpu_user_regs in a public header)
* Renamed public structures by prefixing them with "xen_"
* Added an entry for xenpf_symdata in xlat.lst
* Fixed pv_cpuid check for vpmu-specific cpuid adjustments
* Varios code style fixes
* Eliminated anonymous unions
* Added more verbiage to NMI patch description
Changes in v3:
* Moved PMU MSR banks out from architectural context data structures to allow
for future expansion without protocol changes
* PMU interrupts can be either NMIs or regular vector interrupts (the latter
is the default)
* Context is now marked as PMU_CACHED by the hypervisor code to avoid certain
race conditions with the guest
* Fixed races with PV guest in MSR access handlers
* More Intel VPMU cleanup
* Moved NMI-unsafe code from NMI handler
* Dropped changes to vcpu->is_running
* Added LVTPC apic handling (cached for PV guests)
* Separated privileged profiling mode into a standalone patch
* Separated NMI handling into a standalone patch
Changes in v2:
* Xen symbols are exported as data structure (as opoosed to a set of formatted
strings in v1). Even though one symbol per hypercall is returned performance
appears to be acceptable: reading whole file from dom0 userland takes on average
about twice as long as reading /proc/kallsyms
* More cleanup of Intel VPMU code to simplify publicly exported structures
* There is an architecture-independent and x86-specific public include files (ARM
has a stub)
* General cleanup of public include files to make them more presentable (and
to make auto doc generation better)
* Setting of vcpu->is_running is now done on ARM in schedule_tail as well (making
changes to common/schedule.c architecture-independent). Note that this is not
tested since I don't have access to ARM hardware.
* PCPU ID of interrupted processor is now passed to PV guest
The following patch series adds PMU support in Xen for PV(H)
guests. There is a companion patchset for Linux kernel. In addition,
another set of changes will be provided (later) for userland perf
code.
This version has following limitations:
* For accurate profiling of dom0/Xen dom0 VCPUs should be pinned.
* Hypervisor code is only profiled on processors that have running dom0 VCPUs
on them.
* No backtrace support.
A few notes that may help reviewing:
* A shared data structure (xenpmu_data_t) between each PV VPCU and hypervisor
CPU is used for passing registers' values as well as PMU state at the time of
PMU interrupt.
* PMU interrupts are taken by hypervisor either as NMIs or regular vector
interrupts for both HVM and PV(H). The interrupts are sent as NMIs to HVM guests
and as virtual interrupts to PV(H) guests
* PV guest's interrupt handler does not read/write PMU MSRs directly. Instead, it
accesses xenpmu_data_t and flushes it to HW it before returning.
* PMU mode is controlled at runtime via /sys/hypervisor/pmu/pmu/{pmu_mode,pmu_flags}
in addition to 'vpmu' boot option (which is preserved for back compatibility).
The following modes are provided:
* disable: VPMU is off
* enable: VPMU is on. Guests can profile themselves, dom0 profiles itself and Xen
* priv_enable: dom0 only profiling. dom0 collects samples for everyone. Sampling
in guests is suspended.
* /proc/xen/xensyms file exports hypervisor's symbols to dom0 (similar to
/proc/kallsyms)
* VPMU infrastructure is now used for HVM, PV and PVH and therefore has been moved
up from hvm subtree
Boris Ostrovsky (21):
common/symbols: Export hypervisor symbols to privileged guest
x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force()
x86/VPMU: Set MSR bitmaps only for HVM/PVH guests
x86/VPMU: Make vpmu macros a bit more efficient
intel/VPMU: Clean up Intel VPMU code
vmx: Merge MSR management routines
x86/VPMU: Handle APIC_LVTPC accesses
intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero
x86/VPMU: Add public xenpmu.h
x86/VPMU: Make vpmu not HVM-specific
x86/VPMU: Interface for setting PMU mode and flags
x86/VPMU: Initialize AMD and Intel VPMU with __initcall
x86/VPMU: Initialize PMU for PV(H) guests
x86/VPMU: Save VPMU state for PV guests during context switch
x86/VPMU: When handling MSR accesses, leave fault injection to callers
x86/VPMU: Add support for PMU register handling on PV guests
x86/VPMU: Handle PMU interrupts for PV guests
x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr
x86/VPMU: Add privileged PMU mode
x86/VPMU: NMI-based VPMU support
x86/VPMU: Move VPMU files up from hvm/ directory
docs/misc/xen-command-line.markdown | 8 +-
tools/flask/policy/policy/modules/xen/xen.te | 7 +
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/vpmu.c | 881 +++++++++++++++++++++
xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} | 248 +++---
.../x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} | 784 +++++++++---------
xen/arch/x86/domain.c | 23 +-
xen/arch/x86/hvm/Makefile | 1 -
xen/arch/x86/hvm/hvm.c | 3 +-
xen/arch/x86/hvm/svm/Makefile | 1 -
xen/arch/x86/hvm/svm/svm.c | 10 +-
xen/arch/x86/hvm/vlapic.c | 3 +
xen/arch/x86/hvm/vmx/Makefile | 1 -
xen/arch/x86/hvm/vmx/vmcs.c | 84 +-
xen/arch/x86/hvm/vmx/vmx.c | 28 +-
xen/arch/x86/hvm/vpmu.c | 263 ------
xen/arch/x86/oprofile/op_model_ppro.c | 8 +-
xen/arch/x86/platform_hypercall.c | 28 +
xen/arch/x86/traps.c | 62 +-
xen/arch/x86/x86_64/compat/entry.S | 4 +
xen/arch/x86/x86_64/entry.S | 4 +
xen/common/event_channel.c | 1 +
xen/common/symbols.c | 54 ++
xen/include/Makefile | 2 +
xen/include/asm-x86/domain.h | 2 +
xen/include/asm-x86/hvm/vcpu.h | 3 -
xen/include/asm-x86/hvm/vmx/vmcs.h | 18 +-
xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 51 --
xen/include/asm-x86/softirq.h | 3 +-
xen/include/asm-x86/{hvm => }/vpmu.h | 93 ++-
xen/include/public/arch-arm.h | 3 +
xen/include/public/arch-x86/pmu.h | 95 +++
xen/include/public/platform.h | 19 +
xen/include/public/pmu.h | 90 +++
xen/include/public/xen.h | 2 +
xen/include/xen/hypercall.h | 4 +
xen/include/xen/symbols.h | 3 +
xen/include/xlat.lst | 6 +
xen/include/xsm/dummy.h | 20 +
xen/include/xsm/xsm.h | 6 +
xen/xsm/dummy.c | 1 +
xen/xsm/flask/hooks.c | 28 +
xen/xsm/flask/policy/access_vectors | 6 +
43 files changed, 2028 insertions(+), 934 deletions(-)
create mode 100644 xen/arch/x86/cpu/vpmu.c
rename xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} (68%)
rename xen/arch/x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} (58%)
delete mode 100644 xen/arch/x86/hvm/vpmu.c
delete mode 100644 xen/include/asm-x86/hvm/vmx/vpmu_core2.h
rename xen/include/asm-x86/{hvm => }/vpmu.h (55%)
create mode 100644 xen/include/public/arch-x86/pmu.h
create mode 100644 xen/include/public/pmu.h
--
1.8.1.4
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 01/21] common/symbols: Export hypervisor symbols to privileged guest
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 02/21] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force() Boris Ostrovsky
` (20 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Export Xen's symbols as {<address><type><name>} triplet via new XENPF_get_symbol
hypercall
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Acked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/platform_hypercall.c | 28 +++++++++++++++++++
xen/common/symbols.c | 54 +++++++++++++++++++++++++++++++++++++
xen/include/public/platform.h | 19 +++++++++++++
xen/include/xen/symbols.h | 3 +++
xen/include/xlat.lst | 1 +
xen/xsm/flask/hooks.c | 4 +++
xen/xsm/flask/policy/access_vectors | 2 ++
7 files changed, 111 insertions(+)
diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 32f39b2..7b37960 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -23,6 +23,7 @@
#include <xen/cpu.h>
#include <xen/pmstat.h>
#include <xen/irq.h>
+#include <xen/symbols.h>
#include <asm/current.h>
#include <public/platform.h>
#include <acpi/cpufreq/processor_perf.h>
@@ -760,6 +761,33 @@ ret_t do_platform_op(XEN_GUEST_HANDLE_PARAM(xen_platform_op_t) u_xenpf_op)
}
break;
+ case XENPF_get_symbol:
+ {
+ static char name[KSYM_NAME_LEN + 1]; /* protected by xenpf_lock */
+ XEN_GUEST_HANDLE(char) nameh;
+ uint32_t namelen, copylen;
+
+ guest_from_compat_handle(nameh, op->u.symdata.name);
+
+ ret = xensyms_read(&op->u.symdata.symnum, &op->u.symdata.type,
+ &op->u.symdata.address, name);
+
+ namelen = strlen(name) + 1;
+
+ if ( namelen > op->u.symdata.namelen )
+ copylen = op->u.symdata.namelen;
+ else
+ copylen = namelen;
+
+ op->u.symdata.namelen = namelen;
+
+ if ( !ret && copy_to_guest(nameh, name, copylen) )
+ ret = -EFAULT;
+ if ( !ret && __copy_field_to_guest(u_xenpf_op, op, u.symdata) )
+ ret = -EFAULT;
+ }
+ break;
+
default:
ret = -ENOSYS;
break;
diff --git a/xen/common/symbols.c b/xen/common/symbols.c
index bc2fde6..2c0942d 100644
--- a/xen/common/symbols.c
+++ b/xen/common/symbols.c
@@ -17,6 +17,8 @@
#include <xen/lib.h>
#include <xen/string.h>
#include <xen/spinlock.h>
+#include <public/platform.h>
+#include <xen/guest_access.h>
#ifdef SYMBOLS_ORIGIN
extern const unsigned int symbols_offsets[1];
@@ -148,3 +150,55 @@ const char *symbols_lookup(unsigned long addr,
*offset = addr - symbols_address(low);
return namebuf;
}
+
+/*
+ * Get symbol type information. This is encoded as a single char at the
+ * beginning of the symbol name.
+ */
+static char symbols_get_symbol_type(unsigned int off)
+{
+ /*
+ * Get just the first code, look it up in the token table,
+ * and return the first char from this token.
+ */
+ return symbols_token_table[symbols_token_index[symbols_names[off + 1]]];
+}
+
+int xensyms_read(uint32_t *symnum, char *type,
+ uint64_t *address, char *name)
+{
+ /*
+ * Symbols are most likely accessed sequentially so we remember position
+ * from previous read. This can help us avoid the extra call to
+ * get_symbol_offset().
+ */
+ static uint64_t next_symbol, next_offset;
+ static DEFINE_SPINLOCK(symbols_mutex);
+
+ if ( *symnum > symbols_num_syms )
+ return -ERANGE;
+ if ( *symnum == symbols_num_syms )
+ {
+ /* No more symbols */
+ name[0] = '\0';
+ return 0;
+ }
+
+ spin_lock(&symbols_mutex);
+
+ if ( *symnum == 0 )
+ next_offset = next_symbol = 0;
+ if ( next_symbol != *symnum )
+ /* Non-sequential access */
+ next_offset = get_symbol_offset(*symnum);
+
+ *type = symbols_get_symbol_type(next_offset);
+ next_offset = symbols_expand_symbol(next_offset, name);
+ *address = symbols_offsets[*symnum] + SYMBOLS_ORIGIN;
+
+ next_symbol = ++*symnum;
+
+ spin_unlock(&symbols_mutex);
+
+ return 0;
+}
diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h
index 5c57615..6dd7732 100644
--- a/xen/include/public/platform.h
+++ b/xen/include/public/platform.h
@@ -560,6 +560,24 @@ struct xenpf_resource_op {
typedef struct xenpf_resource_op xenpf_resource_op_t;
DEFINE_XEN_GUEST_HANDLE(xenpf_resource_op_t);
+#define XENPF_get_symbol 62
+struct xenpf_symdata {
+ /* IN/OUT variables */
+ uint32_t namelen; /* IN: size of name buffer */
+ /* OUT: strlen(name) of hypervisor symbol (may be */
+ /* larger than what's been copied to guest) */
+ uint32_t symnum; /* IN: Symbol to read */
+ /* OUT: Next available symbol. If same as IN then */
+ /* we reached the end */
+
+ /* OUT variables */
+ XEN_GUEST_HANDLE(char) name;
+ uint64_t address;
+ char type;
+};
+typedef struct xenpf_symdata xenpf_symdata_t;
+DEFINE_XEN_GUEST_HANDLE(xenpf_symdata_t);
+
/*
* ` enum neg_errnoval
* ` HYPERVISOR_platform_op(const struct xen_platform_op*);
@@ -587,6 +605,7 @@ struct xen_platform_op {
struct xenpf_mem_hotadd mem_add;
struct xenpf_core_parking core_parking;
struct xenpf_resource_op resource_op;
+ struct xenpf_symdata symdata;
uint8_t pad[128];
} u;
};
diff --git a/xen/include/xen/symbols.h b/xen/include/xen/symbols.h
index 87cd77d..1fa0537 100644
--- a/xen/include/xen/symbols.h
+++ b/xen/include/xen/symbols.h
@@ -11,4 +11,7 @@ const char *symbols_lookup(unsigned long addr,
unsigned long *offset,
char *namebuf);
+int xensyms_read(uint32_t *symnum, char *type,
+ uint64_t *address, char *name);
+
#endif /*_XEN_SYMBOLS_H*/
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 234b668..4901573 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -86,6 +86,7 @@
? processor_px platform.h
! psd_package platform.h
? xenpf_enter_acpi_sleep platform.h
+! xenpf_symdata platform.h
? xenpf_pcpuinfo platform.h
? xenpf_pcpu_version platform.h
? xenpf_resource_entry platform.h
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 6d0fe72..41962b0 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -1405,6 +1405,10 @@ static int flask_platform_op(uint32_t op)
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
XEN2__RESOURCE_OP, NULL);
+ case XENPF_get_symbol:
+ return avc_has_perm(domain_sid(current->domain), SECINITSID_XEN,
+ SECCLASS_XEN2, XEN2__GET_SYMBOL, NULL);
+
default:
printk("flask_platform_op: Unknown op %d\n", op);
return -EPERM;
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index de0c707..23443e3 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -83,6 +83,8 @@ class xen2
resource_op
# XEN_SYSCTL_psr_cmt_op
psr_cmt_op
+# XENPF_get_symbol
+ get_symbol
}
# Classes domain and domain2 consist of operations that a domain performs on
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 02/21] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force()
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 01/21] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 03/21] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests Boris Ostrovsky
` (19 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
There is a possibility that we set VPMU_CONTEXT_SAVE on VPMU context in
vpmu_load() and never clear it (because vpmu_save_force() will see
VPMU_CONTEXT_LOADED bit clear, which is possible on AMD processors)
The problem is that amd_vpmu_save() assumes that if VPMU_CONTEXT_SAVE is set
then (1) we need to save counters and (2) we don't need to "stop" control
registers since they must have been stopped earlier. The latter may cause all
sorts of problem (like counters still running in a wrong guest and hypervisor
sending to that guest unexpected PMU interrupts).
Since setting this flag is currently always done prior to calling
vpmu_save_force() let's both set and clear it there.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
xen/arch/x86/hvm/vpmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index 265fc0e..e74c871 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -128,6 +128,8 @@ static void vpmu_save_force(void *arg)
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )
return;
+ vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
+
if ( vpmu->arch_vpmu_ops )
(void)vpmu->arch_vpmu_ops->arch_vpmu_save(v);
@@ -176,7 +178,6 @@ void vpmu_load(struct vcpu *v)
*/
if ( vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )
{
- vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
on_selected_cpus(cpumask_of(vpmu->last_pcpu),
vpmu_save_force, (void *)v, 1);
vpmu_reset(vpmu, VPMU_CONTEXT_LOADED);
@@ -193,7 +194,6 @@ void vpmu_load(struct vcpu *v)
vpmu = vcpu_vpmu(prev);
/* Someone ran here before us */
- vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
vpmu_save_force(prev);
vpmu_reset(vpmu, VPMU_CONTEXT_LOADED);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 03/21] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 01/21] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 02/21] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force() Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 04/21] x86/VPMU: Make vpmu macros a bit more efficient Boris Ostrovsky
` (18 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
In preparation for making VPMU code shared with PV make sure that we we update
MSR bitmaps only for HVM/PVH guests
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
xen/arch/x86/hvm/svm/vpmu.c | 21 +++++++++++++--------
xen/arch/x86/hvm/vmx/vpmu_core2.c | 8 +++++---
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index 8e07a98..f49af97 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -244,7 +244,8 @@ static int amd_vpmu_save(struct vcpu *v)
context_save(v);
- if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && ctx->msr_bitmap_set )
+ if ( !vpmu_is_set(vpmu, VPMU_RUNNING) &&
+ has_hvm_container_vcpu(v) && ctx->msr_bitmap_set )
amd_vpmu_unset_msr_bitmap(v);
return 1;
@@ -287,8 +288,9 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
ASSERT(!supported);
/* For all counters, enable guest only mode for HVM guest */
- if ( (get_pmu_reg_type(msr) == MSR_TYPE_CTRL) &&
- !(is_guest_mode(msr_content)) )
+ if ( has_hvm_container_vcpu(v) &&
+ (get_pmu_reg_type(msr) == MSR_TYPE_CTRL) &&
+ !is_guest_mode(msr_content) )
{
set_guest_mode(msr_content);
}
@@ -303,8 +305,9 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
apic_write(APIC_LVTPC, PMU_APIC_VECTOR);
vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR;
- if ( !((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
- amd_vpmu_set_msr_bitmap(v);
+ if ( has_hvm_container_vcpu(v) &&
+ !((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ amd_vpmu_set_msr_bitmap(v);
}
/* stop saving & restore if guest stops first counter */
@@ -314,8 +317,9 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
apic_write(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
vpmu_reset(vpmu, VPMU_RUNNING);
- if ( ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
- amd_vpmu_unset_msr_bitmap(v);
+ if ( has_hvm_container_vcpu(v) &&
+ ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ amd_vpmu_unset_msr_bitmap(v);
release_pmu_ownship(PMU_OWNER_HVM);
}
@@ -406,7 +410,8 @@ static void amd_vpmu_destroy(struct vcpu *v)
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
- if ( ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ if ( has_hvm_container_vcpu(v) &&
+ ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
amd_vpmu_unset_msr_bitmap(v);
xfree(vpmu->context);
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 68b6272..54e96b6 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -335,7 +335,8 @@ static int core2_vpmu_save(struct vcpu *v)
__core2_vpmu_save(v);
/* Unset PMU MSR bitmap to trap lazy load. */
- if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && cpu_has_vmx_msr_bitmap )
+ if ( !vpmu_is_set(vpmu, VPMU_RUNNING) &&
+ has_hvm_container_vcpu(v) && cpu_has_vmx_msr_bitmap )
core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
return 1;
@@ -448,7 +449,8 @@ static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
{
__core2_vpmu_load(current);
vpmu_set(vpmu, VPMU_CONTEXT_LOADED);
- if ( cpu_has_vmx_msr_bitmap )
+ if ( has_hvm_container_vcpu(current) &&
+ cpu_has_vmx_msr_bitmap )
core2_vpmu_set_msr_bitmap(current->arch.hvm_vmx.msr_bitmap);
}
return 1;
@@ -822,7 +824,7 @@ static void core2_vpmu_destroy(struct vcpu *v)
return;
xfree(core2_vpmu_cxt->pmu_enable);
xfree(vpmu->context);
- if ( cpu_has_vmx_msr_bitmap )
+ if ( has_hvm_container_vcpu(v) && cpu_has_vmx_msr_bitmap )
core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
release_pmu_ownship(PMU_OWNER_HVM);
vpmu_reset(vpmu, VPMU_CONTEXT_ALLOCATED);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 04/21] x86/VPMU: Make vpmu macros a bit more efficient
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (2 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 03/21] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 05/21] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
` (17 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Introduce vpmu_are_all_set that allows testing multiple bits at once. Convert macros
into inlines for better compiler checking.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 5 +----
xen/arch/x86/hvm/vpmu.c | 3 +--
xen/include/asm-x86/hvm/vpmu.h | 25 +++++++++++++++++++++----
3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 54e96b6..f2e9735 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -326,10 +326,7 @@ static int core2_vpmu_save(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_SAVE) )
- return 0;
-
- if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )
+ if ( !vpmu_are_all_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED) )
return 0;
__core2_vpmu_save(v);
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index e74c871..aec7b5f 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -143,8 +143,7 @@ void vpmu_save(struct vcpu *v)
struct vpmu_struct *vpmu = vcpu_vpmu(v);
int pcpu = smp_processor_id();
- if ( !(vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) &&
- vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED)) )
+ if ( !vpmu_are_all_set(vpmu, VPMU_CONTEXT_ALLOCATED | VPMU_CONTEXT_LOADED) )
return;
vpmu->last_pcpu = pcpu;
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 1f28bd8..ddc2748 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -82,10 +82,27 @@ struct vpmu_struct {
#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */
-#define vpmu_set(_vpmu, _x) ((_vpmu)->flags |= (_x))
-#define vpmu_reset(_vpmu, _x) ((_vpmu)->flags &= ~(_x))
-#define vpmu_is_set(_vpmu, _x) ((_vpmu)->flags & (_x))
-#define vpmu_clear(_vpmu) ((_vpmu)->flags = 0)
+static inline void vpmu_set(struct vpmu_struct *vpmu, const u32 mask)
+{
+ vpmu->flags |= mask;
+}
+static inline void vpmu_reset(struct vpmu_struct *vpmu, const u32 mask)
+{
+ vpmu->flags &= ~mask;
+}
+static inline void vpmu_clear(struct vpmu_struct *vpmu)
+{
+ vpmu->flags = 0;
+}
+static inline bool_t vpmu_is_set(const struct vpmu_struct *vpmu, const u32 mask)
+{
+ return !!(vpmu->flags & mask);
+}
+static inline bool_t vpmu_are_all_set(const struct vpmu_struct *vpmu,
+ const u32 mask)
+{
+ return !!((vpmu->flags & mask) == mask);
+}
int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported);
int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 05/21] intel/VPMU: Clean up Intel VPMU code
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (3 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 04/21] x86/VPMU: Make vpmu macros a bit more efficient Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 06/21] vmx: Merge MSR management routines Boris Ostrovsky
` (16 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Remove struct pmumsr and core2_pmu_enable. Replace static MSR structures with
fields in core2_vpmu_context.
Call core2_get_pmc_count() once, during initialization.
Properly clean up when core2_vpmu_alloc_resource() fails.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 381 ++++++++++++++-----------------
xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 19 --
2 files changed, 172 insertions(+), 228 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index f2e9735..09af846 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -69,6 +69,27 @@
static bool_t __read_mostly full_width_write;
/*
+ * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed
+ * counters. 4 bits for every counter.
+ */
+#define FIXED_CTR_CTRL_BITS 4
+#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
+
+#define VPMU_CORE2_MAX_FIXED_PMCS 4
+struct core2_vpmu_context {
+ u64 fixed_ctrl;
+ u64 ds_area;
+ u64 pebs_enable;
+ u64 global_ovf_status;
+ u64 enabled_cntrs; /* Follows PERF_GLOBAL_CTRL MSR format */
+ u64 fix_counters[VPMU_CORE2_MAX_FIXED_PMCS];
+ struct arch_msr_pair arch_msr_pair[1];
+};
+
+/* Number of general-purpose and fixed performance counters */
+static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
+
+/*
* QUIRK to workaround an issue on various family 6 cpus.
* The issue leads to endless PMC interrupt loops on the processor.
* If the interrupt handler is running and a pmc reaches the value 0, this
@@ -88,11 +109,8 @@ static void check_pmc_quirk(void)
is_pmc_quirk = 0;
}
-static int core2_get_pmc_count(void);
static void handle_pmc_quirk(u64 msr_content)
{
- int num_gen_pmc = core2_get_pmc_count();
- int num_fix_pmc = 3;
int i;
u64 val;
@@ -100,7 +118,7 @@ static void handle_pmc_quirk(u64 msr_content)
return;
val = msr_content;
- for ( i = 0; i < num_gen_pmc; i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
{
if ( val & 0x1 )
{
@@ -112,7 +130,7 @@ static void handle_pmc_quirk(u64 msr_content)
val >>= 1;
}
val = msr_content >> 32;
- for ( i = 0; i < num_fix_pmc; i++ )
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
{
if ( val & 0x1 )
{
@@ -125,128 +143,91 @@ static void handle_pmc_quirk(u64 msr_content)
}
}
-static const u32 core2_fix_counters_msr[] = {
- MSR_CORE_PERF_FIXED_CTR0,
- MSR_CORE_PERF_FIXED_CTR1,
- MSR_CORE_PERF_FIXED_CTR2
-};
-
/*
- * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed
- * counters. 4 bits for every counter.
+ * Read the number of general counters via CPUID.EAX[0xa].EAX[8..15]
*/
-#define FIXED_CTR_CTRL_BITS 4
-#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
-
-/* The index into the core2_ctrls_msr[] of this MSR used in core2_vpmu_dump() */
-#define MSR_CORE_PERF_FIXED_CTR_CTRL_IDX 0
-
-/* Core 2 Non-architectual Performance Control MSRs. */
-static const u32 core2_ctrls_msr[] = {
- MSR_CORE_PERF_FIXED_CTR_CTRL,
- MSR_IA32_PEBS_ENABLE,
- MSR_IA32_DS_AREA
-};
-
-struct pmumsr {
- unsigned int num;
- const u32 *msr;
-};
-
-static const struct pmumsr core2_fix_counters = {
- VPMU_CORE2_NUM_FIXED,
- core2_fix_counters_msr
-};
+static int core2_get_arch_pmc_count(void)
+{
+ u32 eax;
-static const struct pmumsr core2_ctrls = {
- VPMU_CORE2_NUM_CTRLS,
- core2_ctrls_msr
-};
-static int arch_pmc_cnt;
+ eax = cpuid_eax(0xa);
+ return MASK_EXTR(eax, PMU_GENERAL_NR_MASK);
+}
/*
- * Read the number of general counters via CPUID.EAX[0xa].EAX[8..15]
+ * Read the number of fixed counters via CPUID.EDX[0xa].EDX[0..4]
*/
-static int core2_get_pmc_count(void)
+static int core2_get_fixed_pmc_count(void)
{
- u32 eax, ebx, ecx, edx;
+ u32 eax;
- if ( arch_pmc_cnt == 0 )
- {
- cpuid(0xa, &eax, &ebx, &ecx, &edx);
- arch_pmc_cnt = (eax & PMU_GENERAL_NR_MASK) >> PMU_GENERAL_NR_SHIFT;
- }
-
- return arch_pmc_cnt;
+ eax = cpuid_eax(0xa);
+ return MASK_EXTR(eax, PMU_FIXED_NR_MASK);
}
static u64 core2_calc_intial_glb_ctrl_msr(void)
{
- int arch_pmc_bits = (1 << core2_get_pmc_count()) - 1;
- u64 fix_pmc_bits = (1 << 3) - 1;
- return ((fix_pmc_bits << 32) | arch_pmc_bits);
+ int arch_pmc_bits = (1 << arch_pmc_cnt) - 1;
+ u64 fix_pmc_bits = (1 << fixed_pmc_cnt) - 1;
+
+ return (fix_pmc_bits << 32) | arch_pmc_bits;
}
/* edx bits 5-12: Bit width of fixed-function performance counters */
static int core2_get_bitwidth_fix_count(void)
{
- u32 eax, ebx, ecx, edx;
+ u32 edx;
- cpuid(0xa, &eax, &ebx, &ecx, &edx);
- return ((edx & PMU_FIXED_WIDTH_MASK) >> PMU_FIXED_WIDTH_SHIFT);
+ edx = cpuid_edx(0xa);
+ return MASK_EXTR(edx, PMU_FIXED_WIDTH_MASK);
}
static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
{
- int i;
u32 msr_index_pmc;
- for ( i = 0; i < core2_fix_counters.num; i++ )
+ switch ( msr_index )
{
- if ( core2_fix_counters.msr[i] == msr_index )
+ case MSR_CORE_PERF_FIXED_CTR_CTRL:
+ case MSR_IA32_DS_AREA:
+ case MSR_IA32_PEBS_ENABLE:
+ *type = MSR_TYPE_CTRL;
+ return 1;
+
+ case MSR_CORE_PERF_GLOBAL_CTRL:
+ case MSR_CORE_PERF_GLOBAL_STATUS:
+ case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ *type = MSR_TYPE_GLOBAL;
+ return 1;
+
+ default:
+
+ if ( (msr_index >= MSR_CORE_PERF_FIXED_CTR0) &&
+ (msr_index < MSR_CORE_PERF_FIXED_CTR0 + fixed_pmc_cnt) )
{
+ *index = msr_index - MSR_CORE_PERF_FIXED_CTR0;
*type = MSR_TYPE_COUNTER;
- *index = i;
return 1;
}
- }
- for ( i = 0; i < core2_ctrls.num; i++ )
- {
- if ( core2_ctrls.msr[i] == msr_index )
+ if ( (msr_index >= MSR_P6_EVNTSEL(0)) &&
+ (msr_index < MSR_P6_EVNTSEL(arch_pmc_cnt)) )
{
- *type = MSR_TYPE_CTRL;
- *index = i;
+ *index = msr_index - MSR_P6_EVNTSEL(0);
+ *type = MSR_TYPE_ARCH_CTRL;
return 1;
}
- }
-
- if ( (msr_index == MSR_CORE_PERF_GLOBAL_CTRL) ||
- (msr_index == MSR_CORE_PERF_GLOBAL_STATUS) ||
- (msr_index == MSR_CORE_PERF_GLOBAL_OVF_CTRL) )
- {
- *type = MSR_TYPE_GLOBAL;
- return 1;
- }
-
- msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
- if ( (msr_index_pmc >= MSR_IA32_PERFCTR0) &&
- (msr_index_pmc < (MSR_IA32_PERFCTR0 + core2_get_pmc_count())) )
- {
- *type = MSR_TYPE_ARCH_COUNTER;
- *index = msr_index_pmc - MSR_IA32_PERFCTR0;
- return 1;
- }
- if ( (msr_index >= MSR_P6_EVNTSEL(0)) &&
- (msr_index < (MSR_P6_EVNTSEL(core2_get_pmc_count()))) )
- {
- *type = MSR_TYPE_ARCH_CTRL;
- *index = msr_index - MSR_P6_EVNTSEL(0);
- return 1;
+ msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
+ if ( (msr_index_pmc >= MSR_IA32_PERFCTR0) &&
+ (msr_index_pmc < (MSR_IA32_PERFCTR0 + arch_pmc_cnt)) )
+ {
+ *type = MSR_TYPE_ARCH_COUNTER;
+ *index = msr_index_pmc - MSR_IA32_PERFCTR0;
+ return 1;
+ }
+ return 0;
}
-
- return 0;
}
static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap)
@@ -254,13 +235,13 @@ static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap)
int i;
/* Allow Read/Write PMU Counters MSR Directly. */
- for ( i = 0; i < core2_fix_counters.num; i++ )
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
{
- clear_bit(msraddr_to_bitpos(core2_fix_counters.msr[i]), msr_bitmap);
- clear_bit(msraddr_to_bitpos(core2_fix_counters.msr[i]),
+ clear_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR0 + i), msr_bitmap);
+ clear_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR0 + i),
msr_bitmap + 0x800/BYTES_PER_LONG);
}
- for ( i = 0; i < core2_get_pmc_count(); i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
{
clear_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap);
clear_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i),
@@ -275,26 +256,28 @@ static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap)
}
/* Allow Read PMU Non-global Controls Directly. */
- for ( i = 0; i < core2_ctrls.num; i++ )
- clear_bit(msraddr_to_bitpos(core2_ctrls.msr[i]), msr_bitmap);
- for ( i = 0; i < core2_get_pmc_count(); i++ )
- clear_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL(i)), msr_bitmap);
+ for ( i = 0; i < arch_pmc_cnt; i++ )
+ clear_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL(i)), msr_bitmap);
+
+ clear_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR_CTRL), msr_bitmap);
+ clear_bit(msraddr_to_bitpos(MSR_IA32_PEBS_ENABLE), msr_bitmap);
+ clear_bit(msraddr_to_bitpos(MSR_IA32_DS_AREA), msr_bitmap);
}
static void core2_vpmu_unset_msr_bitmap(unsigned long *msr_bitmap)
{
int i;
- for ( i = 0; i < core2_fix_counters.num; i++ )
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
{
- set_bit(msraddr_to_bitpos(core2_fix_counters.msr[i]), msr_bitmap);
- set_bit(msraddr_to_bitpos(core2_fix_counters.msr[i]),
+ set_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR0 + i), msr_bitmap);
+ set_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR0 + i),
msr_bitmap + 0x800/BYTES_PER_LONG);
}
- for ( i = 0; i < core2_get_pmc_count(); i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
{
- set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap);
- set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i),
+ set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0 + i), msr_bitmap);
+ set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0 + i),
msr_bitmap + 0x800/BYTES_PER_LONG);
if ( full_width_write )
@@ -305,10 +288,12 @@ static void core2_vpmu_unset_msr_bitmap(unsigned long *msr_bitmap)
}
}
- for ( i = 0; i < core2_ctrls.num; i++ )
- set_bit(msraddr_to_bitpos(core2_ctrls.msr[i]), msr_bitmap);
- for ( i = 0; i < core2_get_pmc_count(); i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
set_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL(i)), msr_bitmap);
+
+ set_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR_CTRL), msr_bitmap);
+ set_bit(msraddr_to_bitpos(MSR_IA32_PEBS_ENABLE), msr_bitmap);
+ set_bit(msraddr_to_bitpos(MSR_IA32_DS_AREA), msr_bitmap);
}
static inline void __core2_vpmu_save(struct vcpu *v)
@@ -316,10 +301,10 @@ static inline void __core2_vpmu_save(struct vcpu *v)
int i;
struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
- for ( i = 0; i < core2_fix_counters.num; i++ )
- rdmsrl(core2_fix_counters.msr[i], core2_vpmu_cxt->fix_counters[i]);
- for ( i = 0; i < core2_get_pmc_count(); i++ )
- rdmsrl(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
+ rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, core2_vpmu_cxt->fix_counters[i]);
+ for ( i = 0; i < arch_pmc_cnt; i++ )
+ rdmsrl(MSR_IA32_PERFCTR0 + i, core2_vpmu_cxt->arch_msr_pair[i].counter);
}
static int core2_vpmu_save(struct vcpu *v)
@@ -344,20 +329,22 @@ static inline void __core2_vpmu_load(struct vcpu *v)
unsigned int i, pmc_start;
struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
- for ( i = 0; i < core2_fix_counters.num; i++ )
- wrmsrl(core2_fix_counters.msr[i], core2_vpmu_cxt->fix_counters[i]);
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
+ wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, core2_vpmu_cxt->fix_counters[i]);
if ( full_width_write )
pmc_start = MSR_IA32_A_PERFCTR0;
else
pmc_start = MSR_IA32_PERFCTR0;
- for ( i = 0; i < core2_get_pmc_count(); i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
+ {
wrmsrl(pmc_start + i, core2_vpmu_cxt->arch_msr_pair[i].counter);
-
- for ( i = 0; i < core2_ctrls.num; i++ )
- wrmsrl(core2_ctrls.msr[i], core2_vpmu_cxt->ctrls[i]);
- for ( i = 0; i < core2_get_pmc_count(); i++ )
wrmsrl(MSR_P6_EVNTSEL(i), core2_vpmu_cxt->arch_msr_pair[i].control);
+ }
+
+ wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, core2_vpmu_cxt->fixed_ctrl);
+ wrmsrl(MSR_IA32_DS_AREA, core2_vpmu_cxt->ds_area);
+ wrmsrl(MSR_IA32_PEBS_ENABLE, core2_vpmu_cxt->pebs_enable);
}
static void core2_vpmu_load(struct vcpu *v)
@@ -376,56 +363,37 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
struct core2_vpmu_context *core2_vpmu_cxt;
- struct core2_pmu_enable *pmu_enable;
if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
return 0;
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
if ( vmx_add_host_load_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
- return 0;
+ goto out_err;
if ( vmx_add_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
- return 0;
+ goto out_err;
vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
core2_calc_intial_glb_ctrl_msr());
- pmu_enable = xzalloc_bytes(sizeof(struct core2_pmu_enable) +
- core2_get_pmc_count() - 1);
- if ( !pmu_enable )
- goto out1;
-
core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
- (core2_get_pmc_count()-1)*sizeof(struct arch_msr_pair));
+ (arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
if ( !core2_vpmu_cxt )
- goto out2;
- core2_vpmu_cxt->pmu_enable = pmu_enable;
+ goto out_err;
+
vpmu->context = (void *)core2_vpmu_cxt;
+ vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
+
return 1;
- out2:
- xfree(pmu_enable);
- out1:
- gdprintk(XENLOG_WARNING, "Insufficient memory for PMU, PMU feature is "
- "unavailable on domain %d vcpu %d.\n",
- v->vcpu_id, v->domain->domain_id);
- return 0;
-}
-static void core2_vpmu_save_msr_context(struct vcpu *v, int type,
- int index, u64 msr_data)
-{
- struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
+out_err:
+ release_pmu_ownship(PMU_OWNER_HVM);
- switch ( type )
- {
- case MSR_TYPE_CTRL:
- core2_vpmu_cxt->ctrls[index] = msr_data;
- break;
- case MSR_TYPE_ARCH_CTRL:
- core2_vpmu_cxt->arch_msr_pair[index].control = msr_data;
- break;
- }
+ printk("Failed to allocate VPMU resources for domain %u vcpu %u\n",
+ v->vcpu_id, v->domain->domain_id);
+
+ return 0;
}
static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
@@ -436,10 +404,8 @@ static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
return 0;
if ( unlikely(!vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED)) &&
- (vpmu->context != NULL ||
- !core2_vpmu_alloc_resource(current)) )
+ !core2_vpmu_alloc_resource(current) )
return 0;
- vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
/* Do the lazy load staff. */
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )
@@ -456,8 +422,7 @@ static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
uint64_t supported)
{
- u64 global_ctrl, non_global_ctrl;
- char pmu_enable = 0;
+ u64 global_ctrl;
int i, tmp;
int type = -1, index = -1;
struct vcpu *v = current;
@@ -504,6 +469,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( msr_content & 1 )
gdprintk(XENLOG_WARNING, "Guest is trying to enable PEBS, "
"which is not supported.\n");
+ core2_vpmu_cxt->pebs_enable = msr_content;
return 1;
case MSR_IA32_DS_AREA:
if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) )
@@ -516,57 +482,48 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
hvm_inject_hw_exception(TRAP_gp_fault, 0);
return 1;
}
- core2_vpmu_cxt->pmu_enable->ds_area_enable = msr_content ? 1 : 0;
+ core2_vpmu_cxt->ds_area = msr_content;
break;
}
gdprintk(XENLOG_WARNING, "Guest setting of DTS is ignored.\n");
return 1;
case MSR_CORE_PERF_GLOBAL_CTRL:
global_ctrl = msr_content;
- for ( i = 0; i < core2_get_pmc_count(); i++ )
- {
- rdmsrl(MSR_P6_EVNTSEL(i), non_global_ctrl);
- core2_vpmu_cxt->pmu_enable->arch_pmc_enable[i] =
- global_ctrl & (non_global_ctrl >> 22) & 1;
- global_ctrl >>= 1;
- }
-
- rdmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, non_global_ctrl);
- global_ctrl = msr_content >> 32;
- for ( i = 0; i < core2_fix_counters.num; i++ )
- {
- core2_vpmu_cxt->pmu_enable->fixed_ctr_enable[i] =
- (global_ctrl & 1) & ((non_global_ctrl & 0x3)? 1: 0);
- non_global_ctrl >>= FIXED_CTR_CTRL_BITS;
- global_ctrl >>= 1;
- }
break;
case MSR_CORE_PERF_FIXED_CTR_CTRL:
- non_global_ctrl = msr_content;
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
- global_ctrl >>= 32;
- for ( i = 0; i < core2_fix_counters.num; i++ )
+ core2_vpmu_cxt->enabled_cntrs &=
+ ~(((1ULL << VPMU_CORE2_MAX_FIXED_PMCS) - 1) << 32);
+ if ( msr_content != 0 )
{
- core2_vpmu_cxt->pmu_enable->fixed_ctr_enable[i] =
- (global_ctrl & 1) & ((non_global_ctrl & 0x3)? 1: 0);
- non_global_ctrl >>= 4;
- global_ctrl >>= 1;
+ u64 val = msr_content;
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
+ {
+ if ( val & 3 )
+ core2_vpmu_cxt->enabled_cntrs |= (1ULL << 32) << i;
+ val >>= FIXED_CTR_CTRL_BITS;
+ }
}
+
+ core2_vpmu_cxt->fixed_ctrl = msr_content;
break;
default:
tmp = msr - MSR_P6_EVNTSEL(0);
- vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
- if ( tmp >= 0 && tmp < core2_get_pmc_count() )
- core2_vpmu_cxt->pmu_enable->arch_pmc_enable[tmp] =
- (global_ctrl >> tmp) & (msr_content >> 22) & 1;
+ if ( tmp >= 0 && tmp < arch_pmc_cnt )
+ {
+ vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
+
+ if ( msr_content & (1ULL << 22) )
+ core2_vpmu_cxt->enabled_cntrs |= 1ULL << tmp;
+ else
+ core2_vpmu_cxt->enabled_cntrs &= ~(1ULL << tmp);
+
+ core2_vpmu_cxt->arch_msr_pair[tmp].control = msr_content;
+ }
}
- for ( i = 0; i < core2_fix_counters.num; i++ )
- pmu_enable |= core2_vpmu_cxt->pmu_enable->fixed_ctr_enable[i];
- for ( i = 0; i < core2_get_pmc_count(); i++ )
- pmu_enable |= core2_vpmu_cxt->pmu_enable->arch_pmc_enable[i];
- pmu_enable |= core2_vpmu_cxt->pmu_enable->ds_area_enable;
- if ( pmu_enable )
+ if ( (global_ctrl & core2_vpmu_cxt->enabled_cntrs) ||
+ (core2_vpmu_cxt->ds_area != 0) )
vpmu_set(vpmu, VPMU_RUNNING);
else
vpmu_reset(vpmu, VPMU_RUNNING);
@@ -584,7 +541,6 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
}
- core2_vpmu_save_msr_context(v, type, index, msr_content);
if ( type != MSR_TYPE_GLOBAL )
{
u64 mask;
@@ -600,7 +556,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( msr == MSR_IA32_DS_AREA )
break;
/* 4 bits per counter, currently 3 fixed counters implemented. */
- mask = ~((1ull << (VPMU_CORE2_NUM_FIXED * FIXED_CTR_CTRL_BITS)) - 1);
+ mask = ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1);
if (msr_content & mask)
inject_gp = 1;
break;
@@ -685,7 +641,7 @@ static void core2_vpmu_do_cpuid(unsigned int input,
static void core2_vpmu_dump(const struct vcpu *v)
{
const struct vpmu_struct *vpmu = vcpu_vpmu(v);
- int i, num;
+ unsigned int i;
const struct core2_vpmu_context *core2_vpmu_cxt = NULL;
u64 val;
@@ -703,27 +659,25 @@ static void core2_vpmu_dump(const struct vcpu *v)
printk(" vPMU running\n");
core2_vpmu_cxt = vpmu->context;
- num = core2_get_pmc_count();
+
/* Print the contents of the counter and its configuration msr. */
- for ( i = 0; i < num; i++ )
+ for ( i = 0; i < arch_pmc_cnt; i++ )
{
const struct arch_msr_pair *msr_pair = core2_vpmu_cxt->arch_msr_pair;
- if ( core2_vpmu_cxt->pmu_enable->arch_pmc_enable[i] )
- printk(" general_%d: 0x%016lx ctrl: 0x%016lx\n",
- i, msr_pair[i].counter, msr_pair[i].control);
+ printk(" general_%d: 0x%016lx ctrl: 0x%016lx\n",
+ i, msr_pair[i].counter, msr_pair[i].control);
}
/*
* The configuration of the fixed counter is 4 bits each in the
* MSR_CORE_PERF_FIXED_CTR_CTRL.
*/
- val = core2_vpmu_cxt->ctrls[MSR_CORE_PERF_FIXED_CTR_CTRL_IDX];
- for ( i = 0; i < core2_fix_counters.num; i++ )
+ val = core2_vpmu_cxt->fixed_ctrl;
+ for ( i = 0; i < fixed_pmc_cnt; i++ )
{
- if ( core2_vpmu_cxt->pmu_enable->fixed_ctr_enable[i] )
- printk(" fixed_%d: 0x%016lx ctrl: %#lx\n",
- i, core2_vpmu_cxt->fix_counters[i],
- val & FIXED_CTR_CTRL_MASK);
+ printk(" fixed_%d: 0x%016lx ctrl: %#lx\n",
+ i, core2_vpmu_cxt->fix_counters[i],
+ val & FIXED_CTR_CTRL_MASK);
val >>= FIXED_CTR_CTRL_BITS;
}
}
@@ -741,7 +695,7 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
if ( is_pmc_quirk )
handle_pmc_quirk(msr_content);
core2_vpmu_cxt->global_ovf_status |= msr_content;
- msr_content = 0xC000000700000000 | ((1 << core2_get_pmc_count()) - 1);
+ msr_content = 0xC000000700000000 | ((1 << arch_pmc_cnt) - 1);
wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
}
else
@@ -808,6 +762,16 @@ static int core2_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
}
ds_warned = 1;
func_out:
+
+ arch_pmc_cnt = core2_get_arch_pmc_count();
+ fixed_pmc_cnt = core2_get_fixed_pmc_count();
+ if ( fixed_pmc_cnt > VPMU_CORE2_MAX_FIXED_PMCS )
+ {
+ fixed_pmc_cnt = VPMU_CORE2_MAX_FIXED_PMCS;
+ printk(XENLOG_G_WARNING "Limiting number of fixed counters to %d\n",
+ fixed_pmc_cnt);
+ }
+
check_pmc_quirk();
return 0;
}
@@ -815,11 +779,10 @@ static int core2_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
static void core2_vpmu_destroy(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct core2_vpmu_context *core2_vpmu_cxt = vpmu->context;
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
- xfree(core2_vpmu_cxt->pmu_enable);
+
xfree(vpmu->context);
if ( has_hvm_container_vcpu(v) && cpu_has_vmx_msr_bitmap )
core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
diff --git a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h b/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
index 60b05fd..410372d 100644
--- a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
+++ b/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
@@ -23,29 +23,10 @@
#ifndef __ASM_X86_HVM_VPMU_CORE_H_
#define __ASM_X86_HVM_VPMU_CORE_H_
-/* Currently only 3 fixed counters are supported. */
-#define VPMU_CORE2_NUM_FIXED 3
-/* Currently only 3 Non-architectual Performance Control MSRs */
-#define VPMU_CORE2_NUM_CTRLS 3
-
struct arch_msr_pair {
u64 counter;
u64 control;
};
-struct core2_pmu_enable {
- char ds_area_enable;
- char fixed_ctr_enable[VPMU_CORE2_NUM_FIXED];
- char arch_pmc_enable[1];
-};
-
-struct core2_vpmu_context {
- struct core2_pmu_enable *pmu_enable;
- u64 fix_counters[VPMU_CORE2_NUM_FIXED];
- u64 ctrls[VPMU_CORE2_NUM_CTRLS];
- u64 global_ovf_status;
- struct arch_msr_pair arch_msr_pair[1];
-};
-
#endif /* __ASM_X86_HVM_VPMU_CORE_H_ */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 06/21] vmx: Merge MSR management routines
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (4 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 05/21] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 07/21] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
` (15 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
vmx_add_host_load_msr() and vmx_add_guest_msr() share fair amount of code. Merge
them to simplify code maintenance.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
---
xen/arch/x86/hvm/vmx/vmcs.c | 84 +++++++++++++++++++-------------------
xen/include/asm-x86/hvm/vmx/vmcs.h | 16 +++++++-
2 files changed, 55 insertions(+), 45 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 9d8033e..b9e3ef8 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -1201,64 +1201,62 @@ int vmx_write_guest_msr(u32 msr, u64 val)
return -ESRCH;
}
-int vmx_add_guest_msr(u32 msr)
+int vmx_add_msr(u32 msr, int type)
{
struct vcpu *curr = current;
- unsigned int i, msr_count = curr->arch.hvm_vmx.msr_count;
- struct vmx_msr_entry *msr_area = curr->arch.hvm_vmx.msr_area;
+ unsigned int idx, *msr_count;
+ struct vmx_msr_entry **msr_area, *msr_area_elem;
+
+ if ( type == VMX_GUEST_MSR )
+ {
+ msr_count = &curr->arch.hvm_vmx.msr_count;
+ msr_area = &curr->arch.hvm_vmx.msr_area;
+ }
+ else
+ {
+ ASSERT(type == VMX_HOST_MSR);
+ msr_count = &curr->arch.hvm_vmx.host_msr_count;
+ msr_area = &curr->arch.hvm_vmx.host_msr_area;
+ }
- if ( msr_area == NULL )
+ if ( *msr_area == NULL )
{
- if ( (msr_area = alloc_xenheap_page()) == NULL )
+ if ( (*msr_area = alloc_xenheap_page()) == NULL )
return -ENOMEM;
- curr->arch.hvm_vmx.msr_area = msr_area;
- __vmwrite(VM_EXIT_MSR_STORE_ADDR, virt_to_maddr(msr_area));
- __vmwrite(VM_ENTRY_MSR_LOAD_ADDR, virt_to_maddr(msr_area));
+
+ if ( type == VMX_GUEST_MSR )
+ {
+ __vmwrite(VM_EXIT_MSR_STORE_ADDR, virt_to_maddr(*msr_area));
+ __vmwrite(VM_ENTRY_MSR_LOAD_ADDR, virt_to_maddr(*msr_area));
+ }
+ else
+ __vmwrite(VM_EXIT_MSR_LOAD_ADDR, virt_to_maddr(*msr_area));
}
- for ( i = 0; i < msr_count; i++ )
- if ( msr_area[i].index == msr )
+ for ( idx = 0; idx < *msr_count; idx++ )
+ if ( (*msr_area)[idx].index == msr )
return 0;
- if ( msr_count == (PAGE_SIZE / sizeof(struct vmx_msr_entry)) )
+ if ( *msr_count == (PAGE_SIZE / sizeof(struct vmx_msr_entry)) )
return -ENOSPC;
- msr_area[msr_count].index = msr;
- msr_area[msr_count].mbz = 0;
- msr_area[msr_count].data = 0;
- curr->arch.hvm_vmx.msr_count = ++msr_count;
- __vmwrite(VM_EXIT_MSR_STORE_COUNT, msr_count);
- __vmwrite(VM_ENTRY_MSR_LOAD_COUNT, msr_count);
+ msr_area_elem = *msr_area + *msr_count;
+ msr_area_elem->index = msr;
+ msr_area_elem->mbz = 0;
- return 0;
-}
+ ++*msr_count;
-int vmx_add_host_load_msr(u32 msr)
-{
- struct vcpu *curr = current;
- unsigned int i, msr_count = curr->arch.hvm_vmx.host_msr_count;
- struct vmx_msr_entry *msr_area = curr->arch.hvm_vmx.host_msr_area;
-
- if ( msr_area == NULL )
+ if ( type == VMX_GUEST_MSR )
{
- if ( (msr_area = alloc_xenheap_page()) == NULL )
- return -ENOMEM;
- curr->arch.hvm_vmx.host_msr_area = msr_area;
- __vmwrite(VM_EXIT_MSR_LOAD_ADDR, virt_to_maddr(msr_area));
+ msr_area_elem->data = 0;
+ __vmwrite(VM_EXIT_MSR_STORE_COUNT, *msr_count);
+ __vmwrite(VM_ENTRY_MSR_LOAD_COUNT, *msr_count);
+ }
+ else
+ {
+ rdmsrl(msr, msr_area_elem->data);
+ __vmwrite(VM_EXIT_MSR_LOAD_COUNT, *msr_count);
}
-
- for ( i = 0; i < msr_count; i++ )
- if ( msr_area[i].index == msr )
- return 0;
-
- if ( msr_count == (PAGE_SIZE / sizeof(struct vmx_msr_entry)) )
- return -ENOSPC;
-
- msr_area[msr_count].index = msr;
- msr_area[msr_count].mbz = 0;
- rdmsrl(msr, msr_area[msr_count].data);
- curr->arch.hvm_vmx.host_msr_count = ++msr_count;
- __vmwrite(VM_EXIT_MSR_LOAD_COUNT, msr_count);
return 0;
}
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 6a99dca..949884b 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -482,12 +482,15 @@ extern const unsigned int vmx_introspection_force_enabled_msrs_size;
#define MSR_TYPE_R 1
#define MSR_TYPE_W 2
+
+#define VMX_GUEST_MSR 0
+#define VMX_HOST_MSR 1
+
void vmx_disable_intercept_for_msr(struct vcpu *v, u32 msr, int type);
void vmx_enable_intercept_for_msr(struct vcpu *v, u32 msr, int type);
int vmx_read_guest_msr(u32 msr, u64 *val);
int vmx_write_guest_msr(u32 msr, u64 val);
-int vmx_add_guest_msr(u32 msr);
-int vmx_add_host_load_msr(u32 msr);
+int vmx_add_msr(u32 msr, int type);
void vmx_vmcs_switch(struct vmcs_struct *from, struct vmcs_struct *to);
void vmx_set_eoi_exit_bitmap(struct vcpu *v, u8 vector);
void vmx_clear_eoi_exit_bitmap(struct vcpu *v, u8 vector);
@@ -497,6 +500,15 @@ void virtual_vmcs_exit(void *vvmcs);
u64 virtual_vmcs_vmread(void *vvmcs, u32 vmcs_encoding);
void virtual_vmcs_vmwrite(void *vvmcs, u32 vmcs_encoding, u64 val);
+static inline int vmx_add_guest_msr(u32 msr)
+{
+ return vmx_add_msr(msr, VMX_GUEST_MSR);
+}
+static inline int vmx_add_host_load_msr(u32 msr)
+{
+ return vmx_add_msr(msr, VMX_HOST_MSR);
+}
+
DECLARE_PER_CPU(bool_t, vmxon);
#endif /* ASM_X86_HVM_VMX_VMCS_H__ */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 07/21] x86/VPMU: Handle APIC_LVTPC accesses
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (5 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 06/21] vmx: Merge MSR management routines Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 08/21] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
` (14 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Don't have the hypervisor update APIC_LVTPC when _it_ thinks the vector should
be updated. Instead, handle guest's APIC_LVTPC accesses and write what the guest
explicitly wanted.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/svm/vpmu.c | 4 ----
xen/arch/x86/hvm/vlapic.c | 3 +++
xen/arch/x86/hvm/vmx/vpmu_core2.c | 17 -----------------
xen/arch/x86/hvm/vpmu.c | 8 ++++++++
xen/include/asm-x86/hvm/vpmu.h | 1 +
5 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index f49af97..af3cdb2 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -302,8 +302,6 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
return 1;
vpmu_set(vpmu, VPMU_RUNNING);
- apic_write(APIC_LVTPC, PMU_APIC_VECTOR);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR;
if ( has_hvm_container_vcpu(v) &&
!((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
@@ -314,8 +312,6 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( (get_pmu_reg_type(msr) == MSR_TYPE_CTRL) &&
(is_pmu_enabled(msr_content) == 0) && vpmu_is_set(vpmu, VPMU_RUNNING) )
{
- apic_write(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
vpmu_reset(vpmu, VPMU_RUNNING);
if ( has_hvm_container_vcpu(v) &&
((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 089d13f..c4ae505 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -38,6 +38,7 @@
#include <asm/hvm/support.h>
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/nestedhvm.h>
+#include <asm/hvm/vpmu.h>
#include <public/hvm/ioreq.h>
#include <public/hvm/params.h>
@@ -770,6 +771,8 @@ static int vlapic_reg_write(struct vcpu *v,
}
if ( (offset == APIC_LVTT) && !(val & APIC_LVT_MASKED) )
pt_may_unmask_irq(NULL, &vlapic->pt);
+ if ( offset == APIC_LVTPC )
+ vpmu_lvtpc_update(val);
break;
case APIC_TMICT:
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 09af846..f44847f 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -528,19 +528,6 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
else
vpmu_reset(vpmu, VPMU_RUNNING);
- /* Setup LVTPC in local apic */
- if ( vpmu_is_set(vpmu, VPMU_RUNNING) &&
- is_vlapic_lvtpc_enabled(vcpu_vlapic(v)) )
- {
- apic_write_around(APIC_LVTPC, PMU_APIC_VECTOR);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR;
- }
- else
- {
- apic_write_around(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
- }
-
if ( type != MSR_TYPE_GLOBAL )
{
u64 mask;
@@ -706,10 +693,6 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
return 0;
}
- /* HW sets the MASK bit when performance counter interrupt occurs*/
- vpmu->hw_lapic_lvtpc = apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED;
- apic_write_around(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
-
return 1;
}
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index aec7b5f..29d9fde 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -64,6 +64,14 @@ static void __init parse_vpmu_param(char *s)
}
}
+void vpmu_lvtpc_update(uint32_t val)
+{
+ struct vpmu_struct *vpmu = vcpu_vpmu(current);
+
+ vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
+}
+
int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported)
{
struct vpmu_struct *vpmu = vcpu_vpmu(current);
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index ddc2748..9c4e65a 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -104,6 +104,7 @@ static inline bool_t vpmu_are_all_set(const struct vpmu_struct *vpmu,
return !!((vpmu->flags & mask) == mask);
}
+void vpmu_lvtpc_update(uint32_t val);
int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported);
int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content);
void vpmu_do_interrupt(struct cpu_user_regs *regs);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 08/21] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (6 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 07/21] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
` (13 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
MSR_CORE_PERF_GLOBAL_CTRL register should be set zero initially. It is up to
the guest to set it so that counters are enabled.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index f44847f..e7fffcf 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -165,14 +165,6 @@ static int core2_get_fixed_pmc_count(void)
return MASK_EXTR(eax, PMU_FIXED_NR_MASK);
}
-static u64 core2_calc_intial_glb_ctrl_msr(void)
-{
- int arch_pmc_bits = (1 << arch_pmc_cnt) - 1;
- u64 fix_pmc_bits = (1 << fixed_pmc_cnt) - 1;
-
- return (fix_pmc_bits << 32) | arch_pmc_bits;
-}
-
/* edx bits 5-12: Bit width of fixed-function performance counters */
static int core2_get_bitwidth_fix_count(void)
{
@@ -373,8 +365,7 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
if ( vmx_add_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
goto out_err;
- vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
- core2_calc_intial_glb_ctrl_msr());
+ vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
(arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (7 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 08/21] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-24 16:00 ` Jan Beulich
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 10/21] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
` (12 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Add pmu.h header files, move various macros and structures that will be
shared between hypervisor and PV guests to it.
Move MSR banks out of architectural PMU structures to allow for larger sizes
in the future. The banks are allocated immediately after the context and
PMU structures store offsets to them.
Also, while updating vpmu.h, remove unused vpmu_domain() macro.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
---
xen/arch/x86/hvm/svm/vpmu.c | 83 +++++++++++----------
xen/arch/x86/hvm/vmx/vpmu_core2.c | 123 +++++++++++++++++--------------
xen/arch/x86/hvm/vpmu.c | 10 +++
xen/arch/x86/oprofile/op_model_ppro.c | 6 +-
xen/include/Makefile | 2 +
xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 32 --------
xen/include/asm-x86/hvm/vpmu.h | 16 ++--
xen/include/public/arch-arm.h | 3 +
xen/include/public/arch-x86/pmu.h | 90 ++++++++++++++++++++++
xen/include/public/pmu.h | 38 ++++++++++
xen/include/xlat.lst | 4 +
11 files changed, 274 insertions(+), 133 deletions(-)
delete mode 100644 xen/include/asm-x86/hvm/vmx/vpmu_core2.h
create mode 100644 xen/include/public/arch-x86/pmu.h
create mode 100644 xen/include/public/pmu.h
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index af3cdb2..f68c020 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -30,10 +30,7 @@
#include <asm/apic.h>
#include <asm/hvm/vlapic.h>
#include <asm/hvm/vpmu.h>
-
-#define F10H_NUM_COUNTERS 4
-#define F15H_NUM_COUNTERS 6
-#define MAX_NUM_COUNTERS F15H_NUM_COUNTERS
+#include <public/pmu.h>
#define MSR_F10H_EVNTSEL_GO_SHIFT 40
#define MSR_F10H_EVNTSEL_EN_SHIFT 22
@@ -49,6 +46,9 @@ static const u32 __read_mostly *counters;
static const u32 __read_mostly *ctrls;
static bool_t __read_mostly k7_counters_mirrored;
+#define F10H_NUM_COUNTERS 4
+#define F15H_NUM_COUNTERS 6
+
/* PMU Counter MSRs. */
static const u32 AMD_F10H_COUNTERS[] = {
MSR_K7_PERFCTR0,
@@ -83,12 +83,14 @@ static const u32 AMD_F15H_CTRLS[] = {
MSR_AMD_FAM15H_EVNTSEL5
};
-/* storage for context switching */
-struct amd_vpmu_context {
- u64 counters[MAX_NUM_COUNTERS];
- u64 ctrls[MAX_NUM_COUNTERS];
- bool_t msr_bitmap_set;
-};
+/* Use private context as a flag for MSR bitmap */
+#define msr_bitmap_on(vpmu) do { \
+ (vpmu)->priv_context = (void *)-1L; \
+ } while (0)
+#define msr_bitmap_off(vpmu) do { \
+ (vpmu)->priv_context = NULL; \
+ } while (0)
+#define is_msr_bitmap_on(vpmu) ((vpmu)->priv_context != NULL)
static inline int get_pmu_reg_type(u32 addr)
{
@@ -142,7 +144,6 @@ static void amd_vpmu_set_msr_bitmap(struct vcpu *v)
{
unsigned int i;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
for ( i = 0; i < num_counters; i++ )
{
@@ -150,14 +151,13 @@ static void amd_vpmu_set_msr_bitmap(struct vcpu *v)
svm_intercept_msr(v, ctrls[i], MSR_INTERCEPT_WRITE);
}
- ctxt->msr_bitmap_set = 1;
+ msr_bitmap_on(vpmu);
}
static void amd_vpmu_unset_msr_bitmap(struct vcpu *v)
{
unsigned int i;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
for ( i = 0; i < num_counters; i++ )
{
@@ -165,7 +165,7 @@ static void amd_vpmu_unset_msr_bitmap(struct vcpu *v)
svm_intercept_msr(v, ctrls[i], MSR_INTERCEPT_RW);
}
- ctxt->msr_bitmap_set = 0;
+ msr_bitmap_off(vpmu);
}
static int amd_vpmu_do_interrupt(struct cpu_user_regs *regs)
@@ -177,19 +177,22 @@ static inline void context_load(struct vcpu *v)
{
unsigned int i;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
+ struct xen_pmu_amd_ctxt *ctxt = vpmu->context;
+ uint64_t *counter_regs = vpmu_reg_pointer(ctxt, counters);
+ uint64_t *ctrl_regs = vpmu_reg_pointer(ctxt, ctrls);
for ( i = 0; i < num_counters; i++ )
{
- wrmsrl(counters[i], ctxt->counters[i]);
- wrmsrl(ctrls[i], ctxt->ctrls[i]);
+ wrmsrl(counters[i], counter_regs[i]);
+ wrmsrl(ctrls[i], ctrl_regs[i]);
}
}
static void amd_vpmu_load(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
+ struct xen_pmu_amd_ctxt *ctxt = vpmu->context;
+ uint64_t *ctrl_regs = vpmu_reg_pointer(ctxt, ctrls);
vpmu_reset(vpmu, VPMU_FROZEN);
@@ -198,7 +201,7 @@ static void amd_vpmu_load(struct vcpu *v)
unsigned int i;
for ( i = 0; i < num_counters; i++ )
- wrmsrl(ctrls[i], ctxt->ctrls[i]);
+ wrmsrl(ctrls[i], ctrl_regs[i]);
return;
}
@@ -212,17 +215,17 @@ static inline void context_save(struct vcpu *v)
{
unsigned int i;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
+ struct xen_pmu_amd_ctxt *ctxt = vpmu->context;
+ uint64_t *counter_regs = vpmu_reg_pointer(ctxt, counters);
/* No need to save controls -- they are saved in amd_vpmu_do_wrmsr */
for ( i = 0; i < num_counters; i++ )
- rdmsrl(counters[i], ctxt->counters[i]);
+ rdmsrl(counters[i], counter_regs[i]);
}
static int amd_vpmu_save(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctx = vpmu->context;
unsigned int i;
/*
@@ -245,7 +248,7 @@ static int amd_vpmu_save(struct vcpu *v)
context_save(v);
if ( !vpmu_is_set(vpmu, VPMU_RUNNING) &&
- has_hvm_container_vcpu(v) && ctx->msr_bitmap_set )
+ has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
amd_vpmu_unset_msr_bitmap(v);
return 1;
@@ -256,7 +259,9 @@ static void context_update(unsigned int msr, u64 msr_content)
unsigned int i;
struct vcpu *v = current;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct amd_vpmu_context *ctxt = vpmu->context;
+ struct xen_pmu_amd_ctxt *ctxt = vpmu->context;
+ uint64_t *counter_regs = vpmu_reg_pointer(ctxt, counters);
+ uint64_t *ctrl_regs = vpmu_reg_pointer(ctxt, ctrls);
if ( k7_counters_mirrored &&
((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)) )
@@ -268,12 +273,12 @@ static void context_update(unsigned int msr, u64 msr_content)
{
if ( msr == ctrls[i] )
{
- ctxt->ctrls[i] = msr_content;
+ ctrl_regs[i] = msr_content;
return;
}
else if (msr == counters[i] )
{
- ctxt->counters[i] = msr_content;
+ counter_regs[i] = msr_content;
return;
}
}
@@ -303,8 +308,7 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
return 1;
vpmu_set(vpmu, VPMU_RUNNING);
- if ( has_hvm_container_vcpu(v) &&
- !((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ if ( has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
amd_vpmu_set_msr_bitmap(v);
}
@@ -313,8 +317,7 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
(is_pmu_enabled(msr_content) == 0) && vpmu_is_set(vpmu, VPMU_RUNNING) )
{
vpmu_reset(vpmu, VPMU_RUNNING);
- if ( has_hvm_container_vcpu(v) &&
- ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ if ( has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
amd_vpmu_unset_msr_bitmap(v);
release_pmu_ownship(PMU_OWNER_HVM);
}
@@ -355,7 +358,7 @@ static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
static int amd_vpmu_initialise(struct vcpu *v)
{
- struct amd_vpmu_context *ctxt;
+ struct xen_pmu_amd_ctxt *ctxt;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
uint8_t family = current_cpu_data.x86;
@@ -385,7 +388,8 @@ static int amd_vpmu_initialise(struct vcpu *v)
}
}
- ctxt = xzalloc(struct amd_vpmu_context);
+ ctxt = xzalloc_bytes(sizeof(struct xen_pmu_amd_ctxt) +
+ 2 * sizeof(uint64_t) * num_counters);
if ( !ctxt )
{
gdprintk(XENLOG_WARNING, "Insufficient memory for PMU, "
@@ -394,7 +398,11 @@ static int amd_vpmu_initialise(struct vcpu *v)
return -ENOMEM;
}
+ ctxt->counters = sizeof(struct xen_pmu_amd_ctxt);
+ ctxt->ctrls = ctxt->counters + sizeof(uint64_t) * num_counters;
+
vpmu->context = ctxt;
+ vpmu->priv_context = NULL;
vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
return 0;
}
@@ -406,8 +414,7 @@ static void amd_vpmu_destroy(struct vcpu *v)
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
- if ( has_hvm_container_vcpu(v) &&
- ((struct amd_vpmu_context *)vpmu->context)->msr_bitmap_set )
+ if ( has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
amd_vpmu_unset_msr_bitmap(v);
xfree(vpmu->context);
@@ -424,7 +431,9 @@ static void amd_vpmu_destroy(struct vcpu *v)
static void amd_vpmu_dump(const struct vcpu *v)
{
const struct vpmu_struct *vpmu = vcpu_vpmu(v);
- const struct amd_vpmu_context *ctxt = vpmu->context;
+ const struct xen_pmu_amd_ctxt *ctxt = vpmu->context;
+ const uint64_t *counter_regs = vpmu_reg_pointer(ctxt, counters);
+ const uint64_t *ctrl_regs = vpmu_reg_pointer(ctxt, ctrls);
unsigned int i;
printk(" VPMU state: 0x%x ", vpmu->flags);
@@ -454,8 +463,8 @@ static void amd_vpmu_dump(const struct vcpu *v)
rdmsrl(ctrls[i], ctrl);
rdmsrl(counters[i], cntr);
printk(" %#x: %#lx (%#lx in HW) %#x: %#lx (%#lx in HW)\n",
- ctrls[i], ctxt->ctrls[i], ctrl,
- counters[i], ctxt->counters[i], cntr);
+ ctrls[i], ctrl_regs[i], ctrl,
+ counters[i], counter_regs[i], cntr);
}
}
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index e7fffcf..f74a3f1 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -35,8 +35,8 @@
#include <asm/hvm/vmx/vmcs.h>
#include <public/sched.h>
#include <public/hvm/save.h>
+#include <public/pmu.h>
#include <asm/hvm/vpmu.h>
-#include <asm/hvm/vmx/vpmu_core2.h>
/*
* See Intel SDM Vol 2a Instruction Set Reference chapter 3 for CPUID
@@ -68,6 +68,10 @@
#define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_A_PERFCTR0))
static bool_t __read_mostly full_width_write;
+/* Intel-specific VPMU features */
+#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */
+#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */
+
/*
* MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed
* counters. 4 bits for every counter.
@@ -75,17 +79,6 @@ static bool_t __read_mostly full_width_write;
#define FIXED_CTR_CTRL_BITS 4
#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
-#define VPMU_CORE2_MAX_FIXED_PMCS 4
-struct core2_vpmu_context {
- u64 fixed_ctrl;
- u64 ds_area;
- u64 pebs_enable;
- u64 global_ovf_status;
- u64 enabled_cntrs; /* Follows PERF_GLOBAL_CTRL MSR format */
- u64 fix_counters[VPMU_CORE2_MAX_FIXED_PMCS];
- struct arch_msr_pair arch_msr_pair[1];
-};
-
/* Number of general-purpose and fixed performance counters */
static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
@@ -222,6 +215,12 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
}
}
+static inline int msraddr_to_bitpos(int x)
+{
+ ASSERT(x == (x & 0x1fff));
+ return x;
+}
+
static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap)
{
int i;
@@ -291,12 +290,15 @@ static void core2_vpmu_unset_msr_bitmap(unsigned long *msr_bitmap)
static inline void __core2_vpmu_save(struct vcpu *v)
{
int i;
- struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt = vcpu_vpmu(v)->context;
+ uint64_t *fixed_counters = vpmu_reg_pointer(core2_vpmu_cxt, fixed_counters);
+ struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
+ vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
for ( i = 0; i < fixed_pmc_cnt; i++ )
- rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, core2_vpmu_cxt->fix_counters[i]);
+ rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, fixed_counters[i]);
for ( i = 0; i < arch_pmc_cnt; i++ )
- rdmsrl(MSR_IA32_PERFCTR0 + i, core2_vpmu_cxt->arch_msr_pair[i].counter);
+ rdmsrl(MSR_IA32_PERFCTR0 + i, xen_pmu_cntr_pair[i].counter);
}
static int core2_vpmu_save(struct vcpu *v)
@@ -319,10 +321,13 @@ static int core2_vpmu_save(struct vcpu *v)
static inline void __core2_vpmu_load(struct vcpu *v)
{
unsigned int i, pmc_start;
- struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt = vcpu_vpmu(v)->context;
+ uint64_t *fixed_counters = vpmu_reg_pointer(core2_vpmu_cxt, fixed_counters);
+ struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
+ vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
for ( i = 0; i < fixed_pmc_cnt; i++ )
- wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, core2_vpmu_cxt->fix_counters[i]);
+ wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, fixed_counters[i]);
if ( full_width_write )
pmc_start = MSR_IA32_A_PERFCTR0;
@@ -330,8 +335,8 @@ static inline void __core2_vpmu_load(struct vcpu *v)
pmc_start = MSR_IA32_PERFCTR0;
for ( i = 0; i < arch_pmc_cnt; i++ )
{
- wrmsrl(pmc_start + i, core2_vpmu_cxt->arch_msr_pair[i].counter);
- wrmsrl(MSR_P6_EVNTSEL(i), core2_vpmu_cxt->arch_msr_pair[i].control);
+ wrmsrl(pmc_start + i, xen_pmu_cntr_pair[i].counter);
+ wrmsrl(MSR_P6_EVNTSEL(i), xen_pmu_cntr_pair[i].control);
}
wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, core2_vpmu_cxt->fixed_ctrl);
@@ -354,7 +359,8 @@ static void core2_vpmu_load(struct vcpu *v)
static int core2_vpmu_alloc_resource(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct core2_vpmu_context *core2_vpmu_cxt;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt = NULL;
+ uint64_t *p = NULL;
if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
return 0;
@@ -367,12 +373,20 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
goto out_err;
vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
- core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
- (arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
- if ( !core2_vpmu_cxt )
+ core2_vpmu_cxt = xzalloc_bytes(sizeof(*core2_vpmu_cxt) +
+ sizeof(uint64_t) * fixed_pmc_cnt +
+ sizeof(struct xen_pmu_cntr_pair) *
+ arch_pmc_cnt);
+ p = xzalloc(uint64_t);
+ if ( !core2_vpmu_cxt || !p )
goto out_err;
- vpmu->context = (void *)core2_vpmu_cxt;
+ core2_vpmu_cxt->fixed_counters = sizeof(struct xen_pmu_intel_ctxt);
+ core2_vpmu_cxt->arch_counters = core2_vpmu_cxt->fixed_counters +
+ sizeof(uint64_t) * fixed_pmc_cnt;
+
+ vpmu->context = core2_vpmu_cxt;
+ vpmu->priv_context = p;
vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
@@ -381,6 +395,9 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
out_err:
release_pmu_ownship(PMU_OWNER_HVM);
+ xfree(core2_vpmu_cxt);
+ xfree(p);
+
printk("Failed to allocate VPMU resources for domain %u vcpu %u\n",
v->vcpu_id, v->domain->domain_id);
@@ -418,7 +435,8 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
int type = -1, index = -1;
struct vcpu *v = current;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct core2_vpmu_context *core2_vpmu_cxt = NULL;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt;
+ uint64_t *enabled_cntrs;
if ( !core2_vpmu_msr_common_check(msr, &type, &index) )
{
@@ -446,10 +464,11 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
ASSERT(!supported);
core2_vpmu_cxt = vpmu->context;
+ enabled_cntrs = vpmu->priv_context;
switch ( msr )
{
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
- core2_vpmu_cxt->global_ovf_status &= ~msr_content;
+ core2_vpmu_cxt->global_status &= ~msr_content;
return 1;
case MSR_CORE_PERF_GLOBAL_STATUS:
gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
@@ -483,15 +502,14 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
break;
case MSR_CORE_PERF_FIXED_CTR_CTRL:
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
- core2_vpmu_cxt->enabled_cntrs &=
- ~(((1ULL << VPMU_CORE2_MAX_FIXED_PMCS) - 1) << 32);
+ *enabled_cntrs &= ~(((1ULL << fixed_pmc_cnt) - 1) << 32);
if ( msr_content != 0 )
{
u64 val = msr_content;
for ( i = 0; i < fixed_pmc_cnt; i++ )
{
if ( val & 3 )
- core2_vpmu_cxt->enabled_cntrs |= (1ULL << 32) << i;
+ *enabled_cntrs |= (1ULL << 32) << i;
val >>= FIXED_CTR_CTRL_BITS;
}
}
@@ -502,19 +520,21 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
tmp = msr - MSR_P6_EVNTSEL(0);
if ( tmp >= 0 && tmp < arch_pmc_cnt )
{
+ struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
+ vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
+
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
if ( msr_content & (1ULL << 22) )
- core2_vpmu_cxt->enabled_cntrs |= 1ULL << tmp;
+ *enabled_cntrs |= 1ULL << tmp;
else
- core2_vpmu_cxt->enabled_cntrs &= ~(1ULL << tmp);
+ *enabled_cntrs &= ~(1ULL << tmp);
- core2_vpmu_cxt->arch_msr_pair[tmp].control = msr_content;
+ xen_pmu_cntr_pair[tmp].control = msr_content;
}
}
- if ( (global_ctrl & core2_vpmu_cxt->enabled_cntrs) ||
- (core2_vpmu_cxt->ds_area != 0) )
+ if ( (global_ctrl & *enabled_cntrs) || (core2_vpmu_cxt->ds_area != 0) )
vpmu_set(vpmu, VPMU_RUNNING);
else
vpmu_reset(vpmu, VPMU_RUNNING);
@@ -560,7 +580,7 @@ static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
int type = -1, index = -1;
struct vcpu *v = current;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct core2_vpmu_context *core2_vpmu_cxt = NULL;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt;
if ( core2_vpmu_msr_common_check(msr, &type, &index) )
{
@@ -571,7 +591,7 @@ static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
*msr_content = 0;
break;
case MSR_CORE_PERF_GLOBAL_STATUS:
- *msr_content = core2_vpmu_cxt->global_ovf_status;
+ *msr_content = core2_vpmu_cxt->global_status;
break;
case MSR_CORE_PERF_GLOBAL_CTRL:
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
@@ -620,10 +640,12 @@ static void core2_vpmu_dump(const struct vcpu *v)
{
const struct vpmu_struct *vpmu = vcpu_vpmu(v);
unsigned int i;
- const struct core2_vpmu_context *core2_vpmu_cxt = NULL;
+ const struct xen_pmu_intel_ctxt *core2_vpmu_cxt = vpmu->context;
u64 val;
+ uint64_t *fixed_counters;
+ struct xen_pmu_cntr_pair *cntr_pair;
- if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
+ if ( !core2_vpmu_cxt || !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
if ( !vpmu_is_set(vpmu, VPMU_RUNNING) )
@@ -636,16 +658,15 @@ static void core2_vpmu_dump(const struct vcpu *v)
}
printk(" vPMU running\n");
- core2_vpmu_cxt = vpmu->context;
+
+ cntr_pair = vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
+ fixed_counters = vpmu_reg_pointer(core2_vpmu_cxt, fixed_counters);
/* Print the contents of the counter and its configuration msr. */
for ( i = 0; i < arch_pmc_cnt; i++ )
- {
- const struct arch_msr_pair *msr_pair = core2_vpmu_cxt->arch_msr_pair;
-
printk(" general_%d: 0x%016lx ctrl: 0x%016lx\n",
- i, msr_pair[i].counter, msr_pair[i].control);
- }
+ i, cntr_pair[i].counter, cntr_pair[i].control);
+
/*
* The configuration of the fixed counter is 4 bits each in the
* MSR_CORE_PERF_FIXED_CTR_CTRL.
@@ -654,7 +675,7 @@ static void core2_vpmu_dump(const struct vcpu *v)
for ( i = 0; i < fixed_pmc_cnt; i++ )
{
printk(" fixed_%d: 0x%016lx ctrl: %#lx\n",
- i, core2_vpmu_cxt->fix_counters[i],
+ i, fixed_counters[i],
val & FIXED_CTR_CTRL_MASK);
val >>= FIXED_CTR_CTRL_BITS;
}
@@ -665,14 +686,14 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
struct vcpu *v = current;
u64 msr_content;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- struct core2_vpmu_context *core2_vpmu_cxt = vpmu->context;
+ struct xen_pmu_intel_ctxt *core2_vpmu_cxt = vpmu->context;
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, msr_content);
if ( msr_content )
{
if ( is_pmc_quirk )
handle_pmc_quirk(msr_content);
- core2_vpmu_cxt->global_ovf_status |= msr_content;
+ core2_vpmu_cxt->global_status |= msr_content;
msr_content = 0xC000000700000000 | ((1 << arch_pmc_cnt) - 1);
wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
}
@@ -739,13 +760,6 @@ static int core2_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
arch_pmc_cnt = core2_get_arch_pmc_count();
fixed_pmc_cnt = core2_get_fixed_pmc_count();
- if ( fixed_pmc_cnt > VPMU_CORE2_MAX_FIXED_PMCS )
- {
- fixed_pmc_cnt = VPMU_CORE2_MAX_FIXED_PMCS;
- printk(XENLOG_G_WARNING "Limiting number of fixed counters to %d\n",
- fixed_pmc_cnt);
- }
-
check_pmc_quirk();
return 0;
}
@@ -758,6 +772,7 @@ static void core2_vpmu_destroy(struct vcpu *v)
return;
xfree(vpmu->context);
+ xfree(vpmu->priv_context);
if ( has_hvm_container_vcpu(v) && cpu_has_vmx_msr_bitmap )
core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
release_pmu_ownship(PMU_OWNER_HVM);
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index 29d9fde..f96b530 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -31,6 +31,13 @@
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
+#include <public/pmu.h>
+
+#include <compat/pmu.h>
+CHECK_pmu_intel_ctxt;
+CHECK_pmu_amd_ctxt;
+CHECK_pmu_cntr_pair;
+CHECK_pmu_regs;
/*
* "vpmu" : vpmu generally enabled
@@ -226,6 +233,9 @@ void vpmu_initialise(struct vcpu *v)
struct vpmu_struct *vpmu = vcpu_vpmu(v);
uint8_t vendor = current_cpu_data.x86_vendor;
+ BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ);
+ BUILD_BUG_ON(sizeof(struct xen_pmu_amd_ctxt) > XENPMU_CTXT_PAD_SZ);
+
if ( vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
vpmu_destroy(v);
vpmu_clear(vpmu);
diff --git a/xen/arch/x86/oprofile/op_model_ppro.c b/xen/arch/x86/oprofile/op_model_ppro.c
index aa99e4d..ca429a1 100644
--- a/xen/arch/x86/oprofile/op_model_ppro.c
+++ b/xen/arch/x86/oprofile/op_model_ppro.c
@@ -20,11 +20,15 @@
#include <asm/regs.h>
#include <asm/current.h>
#include <asm/hvm/vpmu.h>
-#include <asm/hvm/vmx/vpmu_core2.h>
#include "op_x86_model.h"
#include "op_counter.h"
+struct arch_msr_pair {
+ u64 counter;
+ u64 control;
+};
+
/*
* Intel "Architectural Performance Monitoring" CPUID
* detection/enumeration details:
diff --git a/xen/include/Makefile b/xen/include/Makefile
index f7ccbc9..f97733a 100644
--- a/xen/include/Makefile
+++ b/xen/include/Makefile
@@ -26,7 +26,9 @@ headers-y := \
headers-$(CONFIG_X86) += compat/arch-x86/xen-mca.h
headers-$(CONFIG_X86) += compat/arch-x86/xen.h
headers-$(CONFIG_X86) += compat/arch-x86/xen-$(compat-arch-y).h
+headers-$(CONFIG_X86) += compat/arch-x86/pmu.h
headers-y += compat/arch-$(compat-arch-y).h compat/xlat.h
+headers-y += compat/pmu.h
headers-$(FLASK_ENABLE) += compat/xsm/flask_op.h
cppflags-y := -include public/xen-compat.h
diff --git a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h b/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
deleted file mode 100644
index 410372d..0000000
--- a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
+++ /dev/null
@@ -1,32 +0,0 @@
-
-/*
- * vpmu_core2.h: CORE 2 specific PMU virtualization for HVM domain.
- *
- * Copyright (c) 2007, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Author: Haitao Shan <haitao.shan@intel.com>
- */
-
-#ifndef __ASM_X86_HVM_VPMU_CORE_H_
-#define __ASM_X86_HVM_VPMU_CORE_H_
-
-struct arch_msr_pair {
- u64 counter;
- u64 control;
-};
-
-#endif /* __ASM_X86_HVM_VPMU_CORE_H_ */
-
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 9c4e65a..83eea7e 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -22,6 +22,8 @@
#ifndef __ASM_X86_HVM_VPMU_H_
#define __ASM_X86_HVM_VPMU_H_
+#include <public/pmu.h>
+
/*
* Flag bits given as a string on the hypervisor boot parameter 'vpmu'.
* See arch/x86/hvm/vpmu.c.
@@ -29,12 +31,9 @@
#define VPMU_BOOT_ENABLED 0x1 /* vpmu generally enabled. */
#define VPMU_BOOT_BTS 0x2 /* Intel BTS feature wanted. */
-
-#define msraddr_to_bitpos(x) (((x)&0xffff) + ((x)>>31)*0x2000)
#define vcpu_vpmu(vcpu) (&((vcpu)->arch.hvm_vcpu.vpmu))
#define vpmu_vcpu(vpmu) (container_of((vpmu), struct vcpu, \
arch.hvm_vcpu.vpmu))
-#define vpmu_domain(vpmu) (vpmu_vcpu(vpmu)->domain)
#define MSR_TYPE_COUNTER 0
#define MSR_TYPE_CTRL 1
@@ -42,6 +41,9 @@
#define MSR_TYPE_ARCH_COUNTER 3
#define MSR_TYPE_ARCH_CTRL 4
+/* Start of PMU register bank */
+#define vpmu_reg_pointer(ctxt, offset) ((void *)((uintptr_t)ctxt + \
+ (uintptr_t)ctxt->offset))
/* Arch specific operations shared by all vpmus */
struct arch_vpmu_ops {
@@ -65,7 +67,8 @@ struct vpmu_struct {
u32 flags;
u32 last_pcpu;
u32 hw_lapic_lvtpc;
- void *context;
+ void *context; /* May be shared with PV guest */
+ void *priv_context; /* hypervisor-only */
struct arch_vpmu_ops *arch_vpmu_ops;
};
@@ -77,11 +80,6 @@ struct vpmu_struct {
#define VPMU_FROZEN 0x10 /* Stop counters while VCPU is not running */
#define VPMU_PASSIVE_DOMAIN_ALLOCATED 0x20
-/* VPMU features */
-#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */
-#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */
-
-
static inline void vpmu_set(struct vpmu_struct *vpmu, const u32 mask)
{
vpmu->flags |= mask;
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index ac54cd6..9de6d66 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -407,6 +407,9 @@ typedef uint64_t xen_callback_t;
#endif
+/* Stub definition of PMU structure */
+typedef struct xen_pmu_arch {} xen_pmu_arch_t;
+
#endif /* __XEN_PUBLIC_ARCH_ARM_H__ */
/*
diff --git a/xen/include/public/arch-x86/pmu.h b/xen/include/public/arch-x86/pmu.h
new file mode 100644
index 0000000..b0f9100
--- /dev/null
+++ b/xen/include/public/arch-x86/pmu.h
@@ -0,0 +1,90 @@
+#ifndef __XEN_PUBLIC_ARCH_X86_PMU_H__
+#define __XEN_PUBLIC_ARCH_X86_PMU_H__
+
+/* x86-specific PMU definitions */
+
+/* AMD PMU registers and structures */
+struct xen_pmu_amd_ctxt {
+ /* Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd) */
+ uint32_t counters;
+ uint32_t ctrls;
+};
+typedef struct xen_pmu_amd_ctxt xen_pmu_amd_ctxt_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_amd_ctxt_t);
+
+/* Intel PMU registers and structures */
+struct xen_pmu_cntr_pair {
+ uint64_t counter;
+ uint64_t control;
+};
+typedef struct xen_pmu_cntr_pair xen_pmu_cntr_pair_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_cntr_pair_t);
+
+struct xen_pmu_intel_ctxt {
+ uint64_t global_ctrl;
+ uint64_t global_ovf_ctrl;
+ uint64_t global_status;
+ uint64_t fixed_ctrl;
+ uint64_t ds_area;
+ uint64_t pebs_enable;
+ uint64_t debugctl;
+ /*
+ * Offsets to fixed and architectural counter MSRs (relative to
+ * xen_pmu_arch.c.intel)
+ */
+ uint32_t fixed_counters;
+ uint32_t arch_counters;
+};
+typedef struct xen_pmu_intel_ctxt xen_pmu_intel_ctxt_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_intel_ctxt_t);
+
+/* Sampled domain's registers */
+struct xen_pmu_regs {
+ uint64_t ip;
+ uint64_t sp;
+ uint64_t flags;
+ uint16_t cs;
+ uint16_t ss;
+ uint32_t pad;
+};
+typedef struct xen_pmu_regs xen_pmu_regs_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_regs_t);
+
+struct xen_pmu_arch {
+ union {
+ struct xen_pmu_regs regs;
+ /* Padding for adding new registers to xen_pmu_regs in the future */
+#define XENPMU_REGS_PAD_SZ 64
+ uint8_t pad[XENPMU_REGS_PAD_SZ];
+ } r;
+ uint64_t pmu_flags;
+ union {
+ uint32_t lapic_lvtpc;
+ uint64_t pad;
+ } l;
+ union {
+ struct xen_pmu_amd_ctxt amd;
+ struct xen_pmu_intel_ctxt intel;
+
+ /*
+ * Padding for contexts (fixed parts only, does not include MSR banks
+ * that are specified by offsets
+ */
+#define XENPMU_CTXT_PAD_SZ 128
+ uint8_t pad[XENPMU_CTXT_PAD_SZ];
+ } c;
+};
+typedef struct xen_pmu_arch xen_pmu_arch_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t);
+
+#endif /* __XEN_PUBLIC_ARCH_X86_PMU_H__ */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
+
diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h
new file mode 100644
index 0000000..f97106d
--- /dev/null
+++ b/xen/include/public/pmu.h
@@ -0,0 +1,38 @@
+#ifndef __XEN_PUBLIC_PMU_H__
+#define __XEN_PUBLIC_PMU_H__
+
+#include "xen.h"
+#if defined(__i386__) || defined(__x86_64__)
+#include "arch-x86/pmu.h"
+#elif defined (__arm__) || defined (__aarch64__)
+#include "arch-arm.h"
+#else
+#error "Unsupported architecture"
+#endif
+
+#define XENPMU_VER_MAJ 0
+#define XENPMU_VER_MIN 1
+
+
+/* Shared between hypervisor and PV domain */
+struct xen_pmu_data {
+ uint32_t domain_id;
+ uint32_t vcpu_id;
+ uint32_t pcpu_id;
+
+ uint32_t pad;
+
+ xen_pmu_arch_t pmu;
+};
+
+#endif /* __XEN_PUBLIC_PMU_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 4901573..a9e1769 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -102,6 +102,10 @@
! vcpu_set_singleshot_timer vcpu.h
? xenoprof_init xenoprof.h
? xenoprof_passive xenoprof.h
+? pmu_intel_ctxt arch-x86/pmu.h
+? pmu_amd_ctxt arch-x86/pmu.h
+? pmu_cntr_pair arch-x86/pmu.h
+? pmu_regs arch-x86/pmu.h
? flask_access xsm/flask_op.h
! flask_boolean xsm/flask_op.h
? flask_cache_stats xsm/flask_op.h
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 10/21] x86/VPMU: Make vpmu not HVM-specific
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (8 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
` (11 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
vpmu structure will be used for both HVM and PV guests. Move it from
hvm_vcpu to arch_vcpu.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/include/asm-x86/domain.h | 2 ++
xen/include/asm-x86/hvm/vcpu.h | 3 ---
xen/include/asm-x86/hvm/vpmu.h | 5 ++---
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domain.h
index 6a77a93..be4d1dc 100644
--- a/xen/include/asm-x86/domain.h
+++ b/xen/include/asm-x86/domain.h
@@ -426,6 +426,8 @@ struct arch_vcpu
void (*ctxt_switch_from) (struct vcpu *);
void (*ctxt_switch_to) (struct vcpu *);
+ struct vpmu_struct vpmu;
+
/* Virtual Machine Extensions */
union {
struct pv_vcpu pv_vcpu;
diff --git a/xen/include/asm-x86/hvm/vcpu.h b/xen/include/asm-x86/hvm/vcpu.h
index 01e0665..71a5b15 100644
--- a/xen/include/asm-x86/hvm/vcpu.h
+++ b/xen/include/asm-x86/hvm/vcpu.h
@@ -151,9 +151,6 @@ struct hvm_vcpu {
u32 msr_tsc_aux;
u64 msr_tsc_adjust;
- /* VPMU */
- struct vpmu_struct vpmu;
-
union {
struct arch_vmx_struct vmx;
struct arch_svm_struct svm;
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 83eea7e..82bfa0e 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -31,9 +31,8 @@
#define VPMU_BOOT_ENABLED 0x1 /* vpmu generally enabled. */
#define VPMU_BOOT_BTS 0x2 /* Intel BTS feature wanted. */
-#define vcpu_vpmu(vcpu) (&((vcpu)->arch.hvm_vcpu.vpmu))
-#define vpmu_vcpu(vpmu) (container_of((vpmu), struct vcpu, \
- arch.hvm_vcpu.vpmu))
+#define vcpu_vpmu(vcpu) (&(vcpu)->arch.vpmu)
+#define vpmu_vcpu(vpmu) container_of((vpmu), struct vcpu, arch.vpmu)
#define MSR_TYPE_COUNTER 0
#define MSR_TYPE_CTRL 1
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (9 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 10/21] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
@ 2014-10-17 21:17 ` Boris Ostrovsky
2014-10-27 16:24 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 12/21] x86/VPMU: Initialize AMD and Intel VPMU with __initcall Boris Ostrovsky
` (10 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:17 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Add runtime interface for setting PMU mode and flags. Three main modes are
provided:
* XENPMU_MODE_OFF: PMU is not virtualized
* XENPMU_MODE_SELF: Guests can access PMU MSRs and receive PMU interrupts.
* XENPMU_MODE_HV: Same as XENPMU_MODE_SELF for non-proviledged guests, dom0
can profile itself and the hypervisor.
Note that PMU modes are different from what can be provided at Xen's boot line
with 'vpmu' argument. An 'off' (or '0') value is equivalent to XENPMU_MODE_OFF.
Any other value, on the other hand, will cause VPMU mode to be set to
XENPMU_MODE_SELF during boot.
For feature flags only Intel's BTS is currently supported.
Mode and flags are set via HYPERVISOR_xenpmu_op hypercall.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
---
tools/flask/policy/policy/modules/xen/xen.te | 3 +
xen/arch/x86/domain.c | 6 +-
xen/arch/x86/hvm/svm/vpmu.c | 4 +-
xen/arch/x86/hvm/vmx/vpmu_core2.c | 10 +-
xen/arch/x86/hvm/vpmu.c | 223 ++++++++++++++++++++++++++-
xen/arch/x86/x86_64/compat/entry.S | 4 +
xen/arch/x86/x86_64/entry.S | 4 +
xen/include/asm-x86/hvm/vpmu.h | 27 ++--
xen/include/public/pmu.h | 45 ++++++
xen/include/public/xen.h | 1 +
xen/include/xen/hypercall.h | 4 +
xen/include/xlat.lst | 1 +
xen/include/xsm/dummy.h | 15 ++
xen/include/xsm/xsm.h | 6 +
xen/xsm/dummy.c | 1 +
xen/xsm/flask/hooks.c | 18 +++
xen/xsm/flask/policy/access_vectors | 2 +
17 files changed, 347 insertions(+), 27 deletions(-)
diff --git a/tools/flask/policy/policy/modules/xen/xen.te b/tools/flask/policy/policy/modules/xen/xen.te
index d214470..ae7bf3c 100644
--- a/tools/flask/policy/policy/modules/xen/xen.te
+++ b/tools/flask/policy/policy/modules/xen/xen.te
@@ -68,6 +68,9 @@ allow dom0_t xen_t:xen2 {
resource_op
psr_cmt_op
};
+allow dom0_t xen_t:xen2 {
+ pmu_ctrl
+};
allow dom0_t xen_t:mmu memorymap;
# Allow dom0 to use these domctls on itself. For domctls acting on other
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 558d8d5..0681c56 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1525,7 +1525,7 @@ void context_switch(struct vcpu *prev, struct vcpu *next)
if ( is_hvm_vcpu(prev) )
{
if (prev != next)
- vpmu_save(prev);
+ vpmu_switch_from(prev, next);
if ( !list_empty(&prev->arch.hvm_vcpu.tm_list) )
pt_save_timer(prev);
@@ -1568,9 +1568,9 @@ void context_switch(struct vcpu *prev, struct vcpu *next)
!is_hardware_domain(next->domain));
}
- if (is_hvm_vcpu(next) && (prev != next) )
+ if ( is_hvm_vcpu(prev) && (prev != next) )
/* Must be done with interrupts enabled */
- vpmu_load(next);
+ vpmu_switch_to(prev, next);
context_saved(prev);
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index f68c020..1ae4c1e 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -478,14 +478,14 @@ struct arch_vpmu_ops amd_vpmu_ops = {
.arch_vpmu_dump = amd_vpmu_dump
};
-int svm_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
+int svm_vpmu_initialise(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
uint8_t family = current_cpu_data.x86;
int ret = 0;
/* vpmu enabled? */
- if ( !vpmu_flags )
+ if ( vpmu_mode == XENPMU_MODE_OFF )
return 0;
switch ( family )
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index f74a3f1..9b422c3 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -708,13 +708,13 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
return 1;
}
-static int core2_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
+static int core2_vpmu_initialise(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
u64 msr_content;
static bool_t ds_warned;
- if ( !(vpmu_flags & VPMU_BOOT_BTS) )
+ if ( !(vpmu_features & XENPMU_FEATURE_INTEL_BTS) )
goto func_out;
/* Check the 'Debug Store' feature in the CPUID.EAX[1]:EDX[21] */
while ( boot_cpu_has(X86_FEATURE_DS) )
@@ -829,7 +829,7 @@ struct arch_vpmu_ops core2_no_vpmu_ops = {
.do_cpuid = core2_no_vpmu_do_cpuid,
};
-int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
+int vmx_vpmu_initialise(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
uint8_t family = current_cpu_data.x86;
@@ -837,7 +837,7 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
int ret = 0;
vpmu->arch_vpmu_ops = &core2_no_vpmu_ops;
- if ( !vpmu_flags )
+ if ( vpmu_mode == XENPMU_MODE_OFF )
return 0;
if ( family == 6 )
@@ -880,7 +880,7 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
/* future: */
case 0x3d:
case 0x4e:
- ret = core2_vpmu_initialise(v, vpmu_flags);
+ ret = core2_vpmu_initialise(v);
if ( !ret )
vpmu->arch_vpmu_ops = &core2_vpmu_ops;
return ret;
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index f96b530..d21c3c7 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -21,6 +21,8 @@
#include <xen/config.h>
#include <xen/sched.h>
#include <xen/xenoprof.h>
+#include <xen/event.h>
+#include <xen/guest_access.h>
#include <asm/regs.h>
#include <asm/types.h>
#include <asm/msr.h>
@@ -32,8 +34,11 @@
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
#include <public/pmu.h>
+#include <xen/tasklet.h>
+#include <xsm/xsm.h>
#include <compat/pmu.h>
+CHECK_pmu_params;
CHECK_pmu_intel_ctxt;
CHECK_pmu_amd_ctxt;
CHECK_pmu_cntr_pair;
@@ -44,7 +49,8 @@ CHECK_pmu_regs;
* "vpmu=off" : vpmu generally disabled
* "vpmu=bts" : vpmu enabled and Intel BTS feature switched on.
*/
-static unsigned int __read_mostly opt_vpmu_enabled;
+uint64_t __read_mostly vpmu_mode = XENPMU_MODE_OFF;
+uint64_t __read_mostly vpmu_features = 0;
static void parse_vpmu_param(char *s);
custom_param("vpmu", parse_vpmu_param);
@@ -58,7 +64,7 @@ static void __init parse_vpmu_param(char *s)
break;
default:
if ( !strcmp(s, "bts") )
- opt_vpmu_enabled |= VPMU_BOOT_BTS;
+ vpmu_features |= XENPMU_FEATURE_INTEL_BTS;
else if ( *s )
{
printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
@@ -66,7 +72,8 @@ static void __init parse_vpmu_param(char *s)
}
/* fall through */
case 1:
- opt_vpmu_enabled |= VPMU_BOOT_ENABLED;
+ /* Default VPMU mode */
+ vpmu_mode = XENPMU_MODE_SELF;
break;
}
}
@@ -83,6 +90,9 @@ int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported)
{
struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
+ return 0;
+
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_wrmsr )
return vpmu->arch_vpmu_ops->do_wrmsr(msr, msr_content, supported);
return 0;
@@ -92,6 +102,9 @@ int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
{
struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
+ return 0;
+
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_rdmsr )
return vpmu->arch_vpmu_ops->do_rdmsr(msr, msr_content);
return 0;
@@ -244,19 +257,19 @@ void vpmu_initialise(struct vcpu *v)
switch ( vendor )
{
case X86_VENDOR_AMD:
- if ( svm_vpmu_initialise(v, opt_vpmu_enabled) != 0 )
- opt_vpmu_enabled = 0;
+ if ( svm_vpmu_initialise(v) != 0 )
+ vpmu_mode = XENPMU_MODE_OFF;
break;
case X86_VENDOR_INTEL:
- if ( vmx_vpmu_initialise(v, opt_vpmu_enabled) != 0 )
- opt_vpmu_enabled = 0;
+ if ( vmx_vpmu_initialise(v) != 0 )
+ vpmu_mode = XENPMU_MODE_OFF;
break;
default:
printk("VPMU: Initialization failed. "
"Unknown CPU vendor %d\n", vendor);
- opt_vpmu_enabled = 0;
+ vpmu_mode = XENPMU_MODE_OFF;
break;
}
}
@@ -278,3 +291,197 @@ void vpmu_dump(struct vcpu *v)
vpmu->arch_vpmu_ops->arch_vpmu_dump(v);
}
+static atomic_t vpmu_sched_counter;
+static struct vcpu *sync_vcpu;
+
+static void vpmu_sched_checkin(unsigned long unused)
+{
+ atomic_inc(&vpmu_sched_counter);
+}
+
+static int vpmu_force_context_switch(void)
+{
+ unsigned i, numcpus, mycpu;
+ static s_time_t start;
+ struct vcpu *curr_vcpu = current;
+ static DEFINE_PER_CPU(struct tasklet *, sync_task);
+ int ret = 0;
+
+ numcpus = num_online_cpus();
+ mycpu = smp_processor_id();
+
+ if ( sync_vcpu != NULL ) /* if set, we may be in hypercall continuation */
+ {
+ if (sync_vcpu != curr_vcpu )
+ /* We are not the original caller */
+ return -EAGAIN;
+ goto cont_wait;
+ }
+
+ for_each_online_cpu ( i )
+ {
+ if ( i == mycpu )
+ continue;
+
+ per_cpu(sync_task, i) = xmalloc(struct tasklet);
+ if ( per_cpu(sync_task, i) == NULL )
+ {
+ printk(XENLOG_WARNING "vpmu_force_context_switch: out of memory\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+ tasklet_init(per_cpu(sync_task, i), vpmu_sched_checkin, 0);
+ }
+
+ /* First count is for self */
+ atomic_set(&vpmu_sched_counter, 1);
+
+ for_each_online_cpu ( i )
+ {
+ if ( i != mycpu )
+ tasklet_schedule_on_cpu(per_cpu(sync_task, i), i);
+ }
+
+ vpmu_save(current);
+
+ sync_vcpu = curr_vcpu;
+ start = NOW();
+
+ cont_wait:
+ /*
+ * Note that we may fail here if a CPU is hot-plugged while we are
+ * waiting. We will then time out.
+ */
+ while ( atomic_read(&vpmu_sched_counter) != numcpus )
+ {
+ s_time_t now;
+
+ cpu_relax();
+
+ now = NOW();
+
+ /* Give up after (arbitrarily chosen) 5 seconds */
+ if ( now > start + SECONDS(5) )
+ {
+ printk(XENLOG_WARNING
+ "vpmu_force_context_switch: failed to sync\n");
+ ret = -EBUSY;
+ break;
+ }
+
+ if ( hypercall_preempt_check() )
+ return hypercall_create_continuation(
+ __HYPERVISOR_xenpmu_op, "i", XENPMU_mode_set);
+ }
+
+ out:
+ for ( i = 0; i < numcpus; i++ )
+ {
+ if ( per_cpu(sync_task, i) )
+ {
+ tasklet_kill(per_cpu(sync_task, i));
+ xfree(per_cpu(sync_task, i));
+ per_cpu(sync_task, i) = NULL;
+ }
+ }
+
+ sync_vcpu = NULL;
+ return ret;
+}
+
+long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
+{
+ int ret;
+ struct xen_pmu_params pmu_params;
+ static DEFINE_SPINLOCK(xenpmu_mode_lock);
+
+ ret = xsm_pmu_op(XSM_OTHER, current->domain, op);
+ if ( ret )
+ return ret;
+
+ switch ( op )
+ {
+ case XENPMU_mode_set:
+ {
+ uint32_t current_mode;
+
+ if ( copy_from_guest(&pmu_params, arg, 1) )
+ return -EFAULT;
+
+ if ( pmu_params.val & ~(XENPMU_MODE_SELF | XENPMU_MODE_HV) )
+ return -EINVAL;
+
+ /* 32-bit dom0 can only sample itself */
+ if ( is_pv_32bit_vcpu(current) && (pmu_params.val & XENPMU_MODE_HV) )
+ return -EINVAL;
+
+ /*
+ * Return error is someone else is in the middle of changing mode ---
+ * this is most likely indication of two system administrators
+ * working against each other.
+ * If continuation from vpmu_force_context_switch() is still pending
+ * we can proceed here without getting the lock:
+ * vpmu_force_context_switch() will check whether we are the vcpu that
+ * initialted it.
+ */
+ if ( (sync_vcpu == NULL) && !spin_trylock(&xenpmu_mode_lock) )
+ return -EAGAIN;
+
+ current_mode = vpmu_mode;
+ vpmu_mode = pmu_params.val;
+
+ if ( vpmu_mode == XENPMU_MODE_OFF )
+ {
+ /*
+ * Make sure all (non-dom0) VCPUs have unloaded their VPMUs. This
+ * can be achieved by having all physical processors go through
+ * context_switch().
+ */
+ ret = vpmu_force_context_switch();
+ if ( ret )
+ vpmu_mode = current_mode;
+ }
+
+ if ( spin_is_locked(&xenpmu_mode_lock) )
+ spin_unlock(&xenpmu_mode_lock);
+ break;
+ }
+
+ case XENPMU_mode_get:
+ /* See whether we are in the middle of mode change */
+ if ( (sync_vcpu != NULL) || !spin_trylock(&xenpmu_mode_lock) )
+ return -EAGAIN;
+
+ memset(&pmu_params, 0, sizeof(pmu_params));
+ pmu_params.val = vpmu_mode;
+ spin_unlock(&xenpmu_mode_lock);
+
+ pmu_params.version.maj = XENPMU_VER_MAJ;
+ pmu_params.version.min = XENPMU_VER_MIN;
+
+ if ( copy_to_guest(arg, &pmu_params, 1) )
+ return -EFAULT;
+ break;
+
+ case XENPMU_feature_set:
+ if ( copy_from_guest(&pmu_params, arg, 1) )
+ return -EFAULT;
+
+ if ( pmu_params.val & ~XENPMU_FEATURE_INTEL_BTS )
+ return -EINVAL;
+
+ vpmu_features = pmu_params.val;
+ break;
+
+ case XENPMU_feature_get:
+ pmu_params.val = vpmu_features;
+ if ( copy_field_to_guest(arg, &pmu_params, val) )
+ return -EFAULT;
+ break;
+
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compat/entry.S
index 5b0af61..7691a79 100644
--- a/xen/arch/x86/x86_64/compat/entry.S
+++ b/xen/arch/x86/x86_64/compat/entry.S
@@ -417,6 +417,8 @@ ENTRY(compat_hypercall_table)
.quad do_domctl
.quad compat_kexec_op
.quad do_tmem_op
+ .quad do_ni_hypercall /* reserved for XenClient */
+ .quad do_xenpmu_op /* 40 */
.rept __HYPERVISOR_arch_0-((.-compat_hypercall_table)/8)
.quad compat_ni_hypercall
.endr
@@ -466,6 +468,8 @@ ENTRY(compat_hypercall_args_table)
.byte 1 /* do_domctl */
.byte 2 /* compat_kexec_op */
.byte 1 /* do_tmem_op */
+ .byte 0 /* reserved for XenClient */
+ .byte 2 /* do_xenpmu_op */ /* 40 */
.rept __HYPERVISOR_arch_0-(.-compat_hypercall_args_table)
.byte 0 /* compat_ni_hypercall */
.endr
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index b3d6e32..aa842ac 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -772,6 +772,8 @@ ENTRY(hypercall_table)
.quad do_domctl
.quad do_kexec_op
.quad do_tmem_op
+ .quad do_ni_hypercall /* reserved for XenClient */
+ .quad do_xenpmu_op /* 40 */
.rept __HYPERVISOR_arch_0-((.-hypercall_table)/8)
.quad do_ni_hypercall
.endr
@@ -821,6 +823,8 @@ ENTRY(hypercall_args_table)
.byte 1 /* do_domctl */
.byte 2 /* do_kexec */
.byte 1 /* do_tmem_op */
+ .byte 0 /* reserved for XenClient */
+ .byte 2 /* do_xenpmu_op */ /* 40 */
.rept __HYPERVISOR_arch_0-(.-hypercall_args_table)
.byte 0 /* do_ni_hypercall */
.endr
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 82bfa0e..cb430e0 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -24,13 +24,6 @@
#include <public/pmu.h>
-/*
- * Flag bits given as a string on the hypervisor boot parameter 'vpmu'.
- * See arch/x86/hvm/vpmu.c.
- */
-#define VPMU_BOOT_ENABLED 0x1 /* vpmu generally enabled. */
-#define VPMU_BOOT_BTS 0x2 /* Intel BTS feature wanted. */
-
#define vcpu_vpmu(vcpu) (&(vcpu)->arch.vpmu)
#define vpmu_vcpu(vpmu) container_of((vpmu), struct vcpu, arch.vpmu)
@@ -59,8 +52,8 @@ struct arch_vpmu_ops {
void (*arch_vpmu_dump)(const struct vcpu *);
};
-int vmx_vpmu_initialise(struct vcpu *, unsigned int flags);
-int svm_vpmu_initialise(struct vcpu *, unsigned int flags);
+int vmx_vpmu_initialise(struct vcpu *);
+int svm_vpmu_initialise(struct vcpu *);
struct vpmu_struct {
u32 flags;
@@ -116,5 +109,21 @@ void vpmu_dump(struct vcpu *v);
extern int acquire_pmu_ownership(int pmu_ownership);
extern void release_pmu_ownership(int pmu_ownership);
+extern uint64_t vpmu_mode;
+extern uint64_t vpmu_features;
+
+/* Context switch */
+inline void vpmu_switch_from(struct vcpu *prev, struct vcpu *next)
+{
+ if ( vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV) )
+ vpmu_save(prev);
+}
+
+inline void vpmu_switch_to(struct vcpu *prev, struct vcpu *next)
+{
+ if ( vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV) )
+ vpmu_load(next);
+}
+
#endif /* __ASM_X86_HVM_VPMU_H_*/
diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h
index f97106d..66cc494 100644
--- a/xen/include/public/pmu.h
+++ b/xen/include/public/pmu.h
@@ -13,6 +13,51 @@
#define XENPMU_VER_MAJ 0
#define XENPMU_VER_MIN 1
+/*
+ * ` enum neg_errnoval
+ * ` HYPERVISOR_xenpmu_op(enum xenpmu_op cmd, struct xenpmu_params *args);
+ *
+ * @cmd == XENPMU_* (PMU operation)
+ * @args == struct xenpmu_params
+ */
+/* ` enum xenpmu_op { */
+#define XENPMU_mode_get 0 /* Also used for getting PMU version */
+#define XENPMU_mode_set 1
+#define XENPMU_feature_get 2
+#define XENPMU_feature_set 3
+/* ` } */
+
+/* Parameters structure for HYPERVISOR_xenpmu_op call */
+struct xen_pmu_params {
+ /* IN/OUT parameters */
+ struct {
+ uint32_t maj;
+ uint32_t min;
+ } version;
+ uint64_t val;
+
+ /* IN parameters */
+ uint32_t vcpu;
+ uint32_t pad;
+};
+typedef struct xen_pmu_params xen_pmu_params_t;
+DEFINE_XEN_GUEST_HANDLE(xen_pmu_params_t);
+
+/* PMU modes:
+ * - XENPMU_MODE_OFF: No PMU virtualization
+ * - XENPMU_MODE_SELF: Guests can profile themselves
+ * - XENPMU_MODE_HV: Guests can profile themselves, dom0 profiles
+ * itself and Xen
+ */
+#define XENPMU_MODE_OFF 0
+#define XENPMU_MODE_SELF (1<<0)
+#define XENPMU_MODE_HV (1<<1)
+
+/*
+ * PMU features:
+ * - XENPMU_FEATURE_INTEL_BTS: Intel BTS support (ignored on AMD)
+ */
+#define XENPMU_FEATURE_INTEL_BTS 1
/* Shared between hypervisor and PV domain */
struct xen_pmu_data {
diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index a6a2092..0766790 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -101,6 +101,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t);
#define __HYPERVISOR_kexec_op 37
#define __HYPERVISOR_tmem_op 38
#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */
+#define __HYPERVISOR_xenpmu_op 40
/* Architecture-specific hypercall definitions. */
#define __HYPERVISOR_arch_0 48
diff --git a/xen/include/xen/hypercall.h b/xen/include/xen/hypercall.h
index a9e5229..cf34547 100644
--- a/xen/include/xen/hypercall.h
+++ b/xen/include/xen/hypercall.h
@@ -14,6 +14,7 @@
#include <public/event_channel.h>
#include <public/tmem.h>
#include <public/version.h>
+#include <public/pmu.h>
#include <asm/hypercall.h>
#include <xsm/xsm.h>
@@ -139,6 +140,9 @@ do_tmem_op(
extern long
do_xenoprof_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg);
+extern long
+do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg);
+
#ifdef CONFIG_COMPAT
extern int
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index a9e1769..74abebf 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -102,6 +102,7 @@
! vcpu_set_singleshot_timer vcpu.h
? xenoprof_init xenoprof.h
? xenoprof_passive xenoprof.h
+? pmu_params pmu.h
? pmu_intel_ctxt arch-x86/pmu.h
? pmu_amd_ctxt arch-x86/pmu.h
? pmu_cntr_pair arch-x86/pmu.h
diff --git a/xen/include/xsm/dummy.h b/xen/include/xsm/dummy.h
index f20e89c..c637454 100644
--- a/xen/include/xsm/dummy.h
+++ b/xen/include/xsm/dummy.h
@@ -655,4 +655,19 @@ static XSM_INLINE int xsm_ioport_mapping(XSM_DEFAULT_ARG struct domain *d, uint3
return xsm_default_action(action, current->domain, d);
}
+static XSM_INLINE int xsm_pmu_op (XSM_DEFAULT_ARG struct domain *d, int op)
+{
+ XSM_ASSERT_ACTION(XSM_OTHER);
+ switch ( op )
+ {
+ case XENPMU_mode_set:
+ case XENPMU_mode_get:
+ case XENPMU_feature_set:
+ case XENPMU_feature_get:
+ return xsm_default_action(XSM_PRIV, d, current->domain);
+ default:
+ return -EPERM;
+ }
+}
+
#endif /* CONFIG_X86 */
diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h
index 4ce089f..0e39dfe 100644
--- a/xen/include/xsm/xsm.h
+++ b/xen/include/xsm/xsm.h
@@ -173,6 +173,7 @@ struct xsm_operations {
int (*unbind_pt_irq) (struct domain *d, struct xen_domctl_bind_pt_irq *bind);
int (*ioport_permission) (struct domain *d, uint32_t s, uint32_t e, uint8_t allow);
int (*ioport_mapping) (struct domain *d, uint32_t s, uint32_t e, uint8_t allow);
+ int (*pmu_op) (struct domain *d, int op);
#endif
};
@@ -665,6 +666,11 @@ static inline int xsm_ioport_mapping (xsm_default_t def, struct domain *d, uint3
return xsm_ops->ioport_mapping(d, s, e, allow);
}
+static inline int xsm_pmu_op (xsm_default_t def, struct domain *d, int op)
+{
+ return xsm_ops->pmu_op(d, op);
+}
+
#endif /* CONFIG_X86 */
#endif /* XSM_NO_WRAPPERS */
diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c
index 8eb3050..94f1cf0 100644
--- a/xen/xsm/dummy.c
+++ b/xen/xsm/dummy.c
@@ -144,5 +144,6 @@ void xsm_fixup_ops (struct xsm_operations *ops)
set_to_dummy_if_null(ops, unbind_pt_irq);
set_to_dummy_if_null(ops, ioport_permission);
set_to_dummy_if_null(ops, ioport_mapping);
+ set_to_dummy_if_null(ops, pmu_op);
#endif
}
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 41962b0..fecbc5c 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -1499,6 +1499,23 @@ static int flask_unbind_pt_irq (struct domain *d, struct xen_domctl_bind_pt_irq
{
return current_has_perm(d, SECCLASS_RESOURCE, RESOURCE__REMOVE);
}
+
+static int flask_pmu_op (struct domain *d, int op)
+{
+ u32 dsid = domain_sid(d);
+
+ switch ( op )
+ {
+ case XENPMU_mode_set:
+ case XENPMU_mode_get:
+ case XENPMU_feature_set:
+ case XENPMU_feature_get:
+ return avc_has_perm(dsid, SECINITSID_XEN, SECCLASS_XEN2,
+ XEN2__PMU_CTRL, NULL);
+ default:
+ return -EPERM;
+ }
+}
#endif /* CONFIG_X86 */
long do_flask_op(XEN_GUEST_HANDLE_PARAM(xsm_op_t) u_flask_op);
@@ -1621,6 +1638,7 @@ static struct xsm_operations flask_ops = {
.unbind_pt_irq = flask_unbind_pt_irq,
.ioport_permission = flask_ioport_permission,
.ioport_mapping = flask_ioport_mapping,
+ .pmu_op = flask_pmu_op,
#endif
};
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 23443e3..3c0465d 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -85,6 +85,8 @@ class xen2
psr_cmt_op
# XENPF_get_symbol
get_symbol
+# PMU control
+ pmu_ctrl
}
# Classes domain and domain2 consist of operations that a domain performs on
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 12/21] x86/VPMU: Initialize AMD and Intel VPMU with __initcall
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (10 preceding siblings ...)
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
` (9 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Move some VPMU initilization operations into __initcalls to avoid performing
same tests and calculations for each vcpu.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
xen/arch/x86/hvm/svm/vpmu.c | 117 +++++++++++++---------------
xen/arch/x86/hvm/vmx/vpmu_core2.c | 157 ++++++++++++++++++++------------------
2 files changed, 133 insertions(+), 141 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index 1ae4c1e..e8bb4e2 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -356,57 +356,6 @@ static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
return 1;
}
-static int amd_vpmu_initialise(struct vcpu *v)
-{
- struct xen_pmu_amd_ctxt *ctxt;
- struct vpmu_struct *vpmu = vcpu_vpmu(v);
- uint8_t family = current_cpu_data.x86;
-
- if ( vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
- return 0;
-
- if ( counters == NULL )
- {
- switch ( family )
- {
- case 0x15:
- num_counters = F15H_NUM_COUNTERS;
- counters = AMD_F15H_COUNTERS;
- ctrls = AMD_F15H_CTRLS;
- k7_counters_mirrored = 1;
- break;
- case 0x10:
- case 0x12:
- case 0x14:
- case 0x16:
- default:
- num_counters = F10H_NUM_COUNTERS;
- counters = AMD_F10H_COUNTERS;
- ctrls = AMD_F10H_CTRLS;
- k7_counters_mirrored = 0;
- break;
- }
- }
-
- ctxt = xzalloc_bytes(sizeof(struct xen_pmu_amd_ctxt) +
- 2 * sizeof(uint64_t) * num_counters);
- if ( !ctxt )
- {
- gdprintk(XENLOG_WARNING, "Insufficient memory for PMU, "
- " PMU feature is unavailable on domain %d vcpu %d.\n",
- v->vcpu_id, v->domain->domain_id);
- return -ENOMEM;
- }
-
- ctxt->counters = sizeof(struct xen_pmu_amd_ctxt);
- ctxt->ctrls = ctxt->counters + sizeof(uint64_t) * num_counters;
-
- vpmu->context = ctxt;
- vpmu->priv_context = NULL;
- vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
- return 0;
-}
-
static void amd_vpmu_destroy(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
@@ -480,30 +429,66 @@ struct arch_vpmu_ops amd_vpmu_ops = {
int svm_vpmu_initialise(struct vcpu *v)
{
+ struct xen_pmu_amd_ctxt *ctxt;
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- uint8_t family = current_cpu_data.x86;
- int ret = 0;
- /* vpmu enabled? */
- if ( vpmu_mode == XENPMU_MODE_OFF )
+ if ( (vpmu_mode == XENPMU_MODE_OFF) ||
+ vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return 0;
- switch ( family )
+ if ( !counters )
+ return -EINVAL;
+
+ ctxt = xzalloc_bytes(sizeof(struct xen_pmu_amd_ctxt) +
+ 2 * sizeof(uint64_t) * num_counters);
+ if ( !ctxt )
{
+ printk(XENLOG_G_WARNING "Insufficient memory for PMU, "
+ " PMU feature is unavailable on domain %d vcpu %d.\n",
+ v->vcpu_id, v->domain->domain_id);
+ return -ENOMEM;
+ }
+
+ ctxt->counters = sizeof(struct xen_pmu_amd_ctxt);
+ ctxt->ctrls = ctxt->counters + sizeof(uint64_t) * num_counters;
+
+ vpmu->context = ctxt;
+ vpmu->priv_context = NULL;
+
+ vpmu->arch_vpmu_ops = &amd_vpmu_ops;
+
+ vpmu_set(vpmu, VPMU_CONTEXT_ALLOCATED);
+ return 0;
+}
+
+static int __init amd_vpmu_init(void)
+{
+ if ( current_cpu_data.x86_vendor != X86_VENDOR_AMD )
+ return 0;
+
+ switch ( current_cpu_data.x86 )
+ {
+ case 0x15:
+ num_counters = F15H_NUM_COUNTERS;
+ counters = AMD_F15H_COUNTERS;
+ ctrls = AMD_F15H_CTRLS;
+ k7_counters_mirrored = 1;
+ break;
case 0x10:
case 0x12:
case 0x14:
- case 0x15:
case 0x16:
- ret = amd_vpmu_initialise(v);
- if ( !ret )
- vpmu->arch_vpmu_ops = &amd_vpmu_ops;
- return ret;
+ num_counters = F10H_NUM_COUNTERS;
+ counters = AMD_F10H_COUNTERS;
+ ctrls = AMD_F10H_CTRLS;
+ k7_counters_mirrored = 0;
+ break;
+ default:
+ printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n",
+ current_cpu_data.x86);
+ vpmu_mode = XENPMU_MODE_OFF;
}
- printk("VPMU: Initialization failed. "
- "AMD processor family %d has not "
- "been supported\n", family);
- return -EINVAL;
+ return 0;
}
-
+__initcall(amd_vpmu_init);
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 9b422c3..0933c67 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -708,62 +708,6 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
return 1;
}
-static int core2_vpmu_initialise(struct vcpu *v)
-{
- struct vpmu_struct *vpmu = vcpu_vpmu(v);
- u64 msr_content;
- static bool_t ds_warned;
-
- if ( !(vpmu_features & XENPMU_FEATURE_INTEL_BTS) )
- goto func_out;
- /* Check the 'Debug Store' feature in the CPUID.EAX[1]:EDX[21] */
- while ( boot_cpu_has(X86_FEATURE_DS) )
- {
- if ( !boot_cpu_has(X86_FEATURE_DTES64) )
- {
- if ( !ds_warned )
- printk(XENLOG_G_WARNING "CPU doesn't support 64-bit DS Area"
- " - Debug Store disabled for guests\n");
- break;
- }
- vpmu_set(vpmu, VPMU_CPU_HAS_DS);
- rdmsrl(MSR_IA32_MISC_ENABLE, msr_content);
- if ( msr_content & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL )
- {
- /* If BTS_UNAVAIL is set reset the DS feature. */
- vpmu_reset(vpmu, VPMU_CPU_HAS_DS);
- if ( !ds_warned )
- printk(XENLOG_G_WARNING "CPU has set BTS_UNAVAIL"
- " - Debug Store disabled for guests\n");
- break;
- }
-
- vpmu_set(vpmu, VPMU_CPU_HAS_BTS);
- if ( !ds_warned )
- {
- if ( !boot_cpu_has(X86_FEATURE_DSCPL) )
- printk(XENLOG_G_INFO
- "vpmu: CPU doesn't support CPL-Qualified BTS\n");
- printk("******************************************************\n");
- printk("** WARNING: Emulation of BTS Feature is switched on **\n");
- printk("** Using this processor feature in a virtualized **\n");
- printk("** environment is not 100%% safe. **\n");
- printk("** Setting the DS buffer address with wrong values **\n");
- printk("** may lead to hypervisor hangs or crashes. **\n");
- printk("** It is NOT recommended for production use! **\n");
- printk("******************************************************\n");
- }
- break;
- }
- ds_warned = 1;
- func_out:
-
- arch_pmc_cnt = core2_get_arch_pmc_count();
- fixed_pmc_cnt = core2_get_fixed_pmc_count();
- check_pmc_quirk();
- return 0;
-}
-
static void core2_vpmu_destroy(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
@@ -832,23 +776,81 @@ struct arch_vpmu_ops core2_no_vpmu_ops = {
int vmx_vpmu_initialise(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
- uint8_t family = current_cpu_data.x86;
- uint8_t cpu_model = current_cpu_data.x86_model;
- int ret = 0;
+ u64 msr_content;
+ static bool_t ds_warned;
vpmu->arch_vpmu_ops = &core2_no_vpmu_ops;
if ( vpmu_mode == XENPMU_MODE_OFF )
return 0;
- if ( family == 6 )
- {
- u64 caps;
+ if ( (arch_pmc_cnt + fixed_pmc_cnt) == 0 )
+ return -EINVAL;
- rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps);
- full_width_write = (caps >> 13) & 1;
+ if ( !(vpmu_features & XENPMU_FEATURE_INTEL_BTS) )
+ goto func_out;
+ /* Check the 'Debug Store' feature in the CPUID.EAX[1]:EDX[21] */
+ while ( boot_cpu_has(X86_FEATURE_DS) )
+ {
+ if ( !boot_cpu_has(X86_FEATURE_DTES64) )
+ {
+ if ( !ds_warned )
+ printk(XENLOG_G_WARNING "CPU doesn't support 64-bit DS Area"
+ " - Debug Store disabled for guests\n");
+ break;
+ }
+ vpmu_set(vpmu, VPMU_CPU_HAS_DS);
+ rdmsrl(MSR_IA32_MISC_ENABLE, msr_content);
+ if ( msr_content & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL )
+ {
+ /* If BTS_UNAVAIL is set reset the DS feature. */
+ vpmu_reset(vpmu, VPMU_CPU_HAS_DS);
+ if ( !ds_warned )
+ printk(XENLOG_G_WARNING "CPU has set BTS_UNAVAIL"
+ " - Debug Store disabled for guests\n");
+ break;
+ }
- switch ( cpu_model )
+ vpmu_set(vpmu, VPMU_CPU_HAS_BTS);
+ if ( !ds_warned )
{
+ if ( !boot_cpu_has(X86_FEATURE_DSCPL) )
+ printk(XENLOG_G_INFO
+ "vpmu: CPU doesn't support CPL-Qualified BTS\n");
+ printk("******************************************************\n");
+ printk("** WARNING: Emulation of BTS Feature is switched on **\n");
+ printk("** Using this processor feature in a virtualized **\n");
+ printk("** environment is not 100%% safe. **\n");
+ printk("** Setting the DS buffer address with wrong values **\n");
+ printk("** may lead to hypervisor hangs or crashes. **\n");
+ printk("** It is NOT recommended for production use! **\n");
+ printk("******************************************************\n");
+ }
+ break;
+ }
+ ds_warned = 1;
+ func_out:
+
+ vpmu->arch_vpmu_ops = &core2_vpmu_ops;
+
+ return 0;
+}
+
+static int __init core2_vpmu_init(void)
+{
+ u64 caps;
+
+ if ( current_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+ return 0;
+
+ if ( current_cpu_data.x86 != 6 )
+ {
+ printk(XENLOG_WARNING "VPMU: only family 6 is supported\n");
+ vpmu_mode = XENPMU_MODE_OFF;
+ return 0;
+ }
+
+ switch ( current_cpu_data.x86_model )
+ {
/* Core2: */
case 0x0f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
case 0x16: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
@@ -880,16 +882,21 @@ int vmx_vpmu_initialise(struct vcpu *v)
/* future: */
case 0x3d:
case 0x4e:
- ret = core2_vpmu_initialise(v);
- if ( !ret )
- vpmu->arch_vpmu_ops = &core2_vpmu_ops;
- return ret;
- }
+ break;
+ default:
+ printk(XENLOG_WARNING "VPMU: Unsupported CPU model %#x\n",
+ current_cpu_data.x86_model);
+ vpmu_mode = XENPMU_MODE_OFF;
+ return 0;
}
- printk("VPMU: Initialization failed. "
- "Intel processor family %d model %d has not "
- "been supported\n", family, cpu_model);
- return -EINVAL;
-}
+ arch_pmc_cnt = core2_get_arch_pmc_count();
+ fixed_pmc_cnt = core2_get_fixed_pmc_count();
+ rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps);
+ full_width_write = (caps >> 13) & 1;
+ check_pmc_quirk();
+
+ return 0;
+}
+__initcall(core2_vpmu_init);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (11 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 12/21] x86/VPMU: Initialize AMD and Intel VPMU with __initcall Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-27 16:38 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 14/21] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
` (8 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Code for initializing/tearing down PMU for PV guests
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
---
tools/flask/policy/policy/modules/xen/xen.te | 4 ++
xen/arch/x86/hvm/hvm.c | 3 +-
xen/arch/x86/hvm/svm/svm.c | 4 +-
xen/arch/x86/hvm/svm/vpmu.c | 45 ++++++++++-----
xen/arch/x86/hvm/vmx/vmx.c | 4 +-
xen/arch/x86/hvm/vmx/vpmu_core2.c | 82 ++++++++++++++++++++--------
xen/arch/x86/hvm/vpmu.c | 79 +++++++++++++++++++++++++++
xen/common/event_channel.c | 1 +
xen/include/asm-x86/hvm/vpmu.h | 1 +
xen/include/public/pmu.h | 2 +
xen/include/public/xen.h | 1 +
xen/include/xsm/dummy.h | 3 +
xen/xsm/flask/hooks.c | 4 ++
xen/xsm/flask/policy/access_vectors | 2 +
14 files changed, 194 insertions(+), 41 deletions(-)
diff --git a/tools/flask/policy/policy/modules/xen/xen.te b/tools/flask/policy/policy/modules/xen/xen.te
index ae7bf3c..9d84004 100644
--- a/tools/flask/policy/policy/modules/xen/xen.te
+++ b/tools/flask/policy/policy/modules/xen/xen.te
@@ -120,6 +120,10 @@ domain_comms(dom0_t, dom0_t)
# Allow all domains to use (unprivileged parts of) the tmem hypercall
allow domain_type xen_t:xen tmem_op;
+# Allow all domains to use PMU (but not to change its settings --- that's what
+# pmu_ctrl is for)
+allow domain_type xen_t:xen2 pmu_use;
+
###############################################################################
#
# Domain creation
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index f0e1edc..19ff9e6 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4811,7 +4811,8 @@ static hvm_hypercall_t *const pvh_hypercall64_table[NR_hypercalls] = {
HYPERCALL(hvm_op),
HYPERCALL(sysctl),
HYPERCALL(domctl),
- [ __HYPERVISOR_arch_1 ] = (hvm_hypercall_t *)paging_domctl_continuation
+ [ __HYPERVISOR_arch_1 ] = (hvm_hypercall_t *)paging_domctl_continuation,
+ HYPERCALL(xenpmu_op)
};
int hvm_do_hypercall(struct cpu_user_regs *regs)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index e3e1565..d73b4f9 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1157,7 +1157,9 @@ static int svm_vcpu_initialise(struct vcpu *v)
return rc;
}
- vpmu_initialise(v);
+ /* PVH's VPMU is initialized via hypercall */
+ if ( is_hvm_vcpu(v) )
+ vpmu_initialise(v);
svm_guest_osvw_init(v);
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index e8bb4e2..07509c8 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -363,17 +363,19 @@ static void amd_vpmu_destroy(struct vcpu *v)
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
- if ( has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
- amd_vpmu_unset_msr_bitmap(v);
+ if ( has_hvm_container_vcpu(v) )
+ {
+ if ( is_msr_bitmap_on(vpmu) )
+ amd_vpmu_unset_msr_bitmap(v);
- xfree(vpmu->context);
- vpmu_reset(vpmu, VPMU_CONTEXT_ALLOCATED);
+ if ( is_hvm_vcpu(v) )
+ xfree(vpmu->context);
- if ( vpmu_is_set(vpmu, VPMU_RUNNING) )
- {
- vpmu_reset(vpmu, VPMU_RUNNING);
release_pmu_ownship(PMU_OWNER_HVM);
}
+
+ vpmu->context = NULL;
+ vpmu_clear(vpmu);
}
/* VPMU part of the 'q' keyhandler */
@@ -439,15 +441,19 @@ int svm_vpmu_initialise(struct vcpu *v)
if ( !counters )
return -EINVAL;
- ctxt = xzalloc_bytes(sizeof(struct xen_pmu_amd_ctxt) +
- 2 * sizeof(uint64_t) * num_counters);
- if ( !ctxt )
+ if ( is_hvm_vcpu(v) )
{
- printk(XENLOG_G_WARNING "Insufficient memory for PMU, "
- " PMU feature is unavailable on domain %d vcpu %d.\n",
- v->vcpu_id, v->domain->domain_id);
- return -ENOMEM;
+ ctxt = xzalloc_bytes(sizeof(struct xen_pmu_amd_ctxt) +
+ 2 * sizeof(uint64_t) * num_counters);
+ if ( !ctxt )
+ {
+ printk(XENLOG_G_WARNING "%pv: Insufficient memory for PMU, "
+ " PMU feature is unavailable\n", v);
+ return -ENOMEM;
+ }
}
+ else
+ ctxt = &v->arch.vpmu.xenpmu_data->pmu.c.amd;
ctxt->counters = sizeof(struct xen_pmu_amd_ctxt);
ctxt->ctrls = ctxt->counters + sizeof(uint64_t) * num_counters;
@@ -489,6 +495,17 @@ static int __init amd_vpmu_init(void)
vpmu_mode = XENPMU_MODE_OFF;
}
+ if ( sizeof(struct xen_pmu_data) +
+ 2 * sizeof(uint64_t) * num_counters > PAGE_SIZE )
+ {
+ printk(XENLOG_WARNING
+ "VPMU: Register bank does not fit into VPMU shared page. "
+ "VPMU will be disabled\n");
+ counters = ctrls = NULL;
+ num_counters = 0;
+ vpmu_mode = XENPMU_MODE_OFF;
+ }
+
return 0;
}
__initcall(amd_vpmu_init);
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 304aeea..438a007 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -116,7 +116,9 @@ static int vmx_vcpu_initialise(struct vcpu *v)
return rc;
}
- vpmu_initialise(v);
+ /* PVH's VPMU is initialized via hypercall */
+ if ( is_hvm_vcpu(v) )
+ vpmu_initialise(v);
vmx_install_vlapic_mapping(v);
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 0933c67..6fd0942 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -362,24 +362,34 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
struct xen_pmu_intel_ctxt *core2_vpmu_cxt = NULL;
uint64_t *p = NULL;
- if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
- return 0;
-
- wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
- if ( vmx_add_host_load_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
+ p = xzalloc_bytes(sizeof(uint64_t));
+ if ( !p )
goto out_err;
- if ( vmx_add_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
- goto out_err;
- vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
-
- core2_vpmu_cxt = xzalloc_bytes(sizeof(*core2_vpmu_cxt) +
- sizeof(uint64_t) * fixed_pmc_cnt +
- sizeof(struct xen_pmu_cntr_pair) *
- arch_pmc_cnt);
- p = xzalloc(uint64_t);
- if ( !core2_vpmu_cxt || !p )
- goto out_err;
+ if ( has_hvm_container_vcpu(v) )
+ {
+ if ( is_hvm_vcpu(v) && !acquire_pmu_ownership(PMU_OWNER_HVM) )
+ goto out_err;
+
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+ if ( vmx_add_host_load_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
+ goto out_err_hvm;
+ if ( vmx_add_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
+ goto out_err_hvm;
+ vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+ }
+
+ if ( is_hvm_vcpu(v) )
+ {
+ core2_vpmu_cxt = xzalloc_bytes(sizeof(struct xen_pmu_intel_ctxt) +
+ sizeof(uint64_t) * fixed_pmc_cnt +
+ sizeof(struct xen_pmu_cntr_pair) *
+ arch_pmc_cnt);
+ if ( !core2_vpmu_cxt )
+ goto out_err_hvm;
+ }
+ else
+ core2_vpmu_cxt = &v->arch.vpmu.xenpmu_data->pmu.c.intel;
core2_vpmu_cxt->fixed_counters = sizeof(struct xen_pmu_intel_ctxt);
core2_vpmu_cxt->arch_counters = core2_vpmu_cxt->fixed_counters +
@@ -392,10 +402,12 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
return 1;
-out_err:
- release_pmu_ownship(PMU_OWNER_HVM);
-
+ out_err_hvm:
xfree(core2_vpmu_cxt);
+ if ( is_hvm_vcpu(v) )
+ release_pmu_ownship(PMU_OWNER_HVM);
+
+ out_err:
xfree(p);
printk("Failed to allocate VPMU resources for domain %u vcpu %u\n",
@@ -715,12 +727,20 @@ static void core2_vpmu_destroy(struct vcpu *v)
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
return;
- xfree(vpmu->context);
+ if ( has_hvm_container_vcpu(v) )
+ {
+ if ( cpu_has_vmx_msr_bitmap )
+ core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
+
+ if ( is_hvm_vcpu(v) )
+ xfree(vpmu->context);
+
+ release_pmu_ownship(PMU_OWNER_HVM);
+ }
+
xfree(vpmu->priv_context);
- if ( has_hvm_container_vcpu(v) && cpu_has_vmx_msr_bitmap )
- core2_vpmu_unset_msr_bitmap(v->arch.hvm_vmx.msr_bitmap);
- release_pmu_ownship(PMU_OWNER_HVM);
- vpmu_reset(vpmu, VPMU_CONTEXT_ALLOCATED);
+ vpmu->context = NULL;
+ vpmu_clear(vpmu);
}
struct arch_vpmu_ops core2_vpmu_ops = {
@@ -830,6 +850,10 @@ int vmx_vpmu_initialise(struct vcpu *v)
ds_warned = 1;
func_out:
+ /* PV domains can allocate resources immediately */
+ if ( is_pv_vcpu(v) && !core2_vpmu_alloc_resource(v) )
+ return -EIO;
+
vpmu->arch_vpmu_ops = &core2_vpmu_ops;
return 0;
@@ -897,6 +921,16 @@ static int __init core2_vpmu_init(void)
check_pmc_quirk();
+ if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt +
+ sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > PAGE_SIZE )
+ {
+ printk(XENLOG_WARNING
+ "VPMU: Register bank does not fit into VPMU share page. "
+ "VPMU will be disabled\n");
+ vpmu_mode = XENPMU_MODE_OFF;
+ arch_pmc_cnt = fixed_pmc_cnt = 0;
+ }
+
return 0;
}
__initcall(core2_vpmu_init);
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index d21c3c7..f086156 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -26,6 +26,7 @@
#include <asm/regs.h>
#include <asm/types.h>
#include <asm/msr.h>
+#include <asm/p2m.h>
#include <asm/hvm/support.h>
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/vmx/vmcs.h>
@@ -253,6 +254,7 @@ void vpmu_initialise(struct vcpu *v)
vpmu_destroy(v);
vpmu_clear(vpmu);
vpmu->context = NULL;
+ vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
switch ( vendor )
{
@@ -279,7 +281,72 @@ void vpmu_destroy(struct vcpu *v)
struct vpmu_struct *vpmu = vcpu_vpmu(v);
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->arch_vpmu_destroy )
+ {
+ /* Unload VPMU first. This will stop counters */
+ on_selected_cpus(cpumask_of(vcpu_vpmu(v)->last_pcpu),
+ vpmu_save_force, v, 1);
+
vpmu->arch_vpmu_ops->arch_vpmu_destroy(v);
+ }
+}
+
+static int pvpmu_init(struct domain *d, xen_pmu_params_t *params)
+{
+ struct vcpu *v;
+ struct page_info *page;
+ uint64_t gfn = params->val;
+
+ if ( (params->vcpu >= d->max_vcpus) || (d->vcpu == NULL) ||
+ (d->vcpu[params->vcpu] == NULL) )
+ return -EINVAL;
+
+ page = get_page_from_gfn(d, gfn, NULL, P2M_ALLOC);
+ if ( !page )
+ return -EINVAL;
+
+ if ( !get_page_type(page, PGT_writable_page) )
+ {
+ put_page(page);
+ return -EINVAL;
+ }
+
+ v = d->vcpu[params->vcpu];
+ v->arch.vpmu.xenpmu_data = __map_domain_page_global(page);
+ if ( !v->arch.vpmu.xenpmu_data )
+ {
+ put_page_and_type(page);
+ return -EINVAL;
+ }
+
+ vpmu_initialise(v);
+
+ return 0;
+}
+
+static void pvpmu_finish(struct domain *d, xen_pmu_params_t *params)
+{
+ struct vcpu *v;
+ uint64_t mfn;
+
+ if ( (params->vcpu >= d->max_vcpus) || (d->vcpu == NULL) ||
+ (d->vcpu[params->vcpu] == NULL) )
+ return;
+
+ v = d->vcpu[params->vcpu];
+ if ( v != current )
+ vcpu_pause(v);
+
+ if ( v->arch.vpmu.xenpmu_data )
+ {
+ mfn = domain_page_map_to_mfn(v->arch.vpmu.xenpmu_data);
+ ASSERT(mfn != 0);
+ unmap_domain_page_global(v->arch.vpmu.xenpmu_data);
+ put_page_and_type(mfn_to_page(mfn));
+ }
+ vpmu_destroy(v);
+
+ if ( v != current )
+ vcpu_unpause(v);
}
/* Dump some vpmu informations on console. Used in keyhandler dump_domains(). */
@@ -479,6 +546,18 @@ long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
return -EFAULT;
break;
+ case XENPMU_init:
+ if ( copy_from_guest(&pmu_params, arg, 1) )
+ return -EFAULT;
+ ret = pvpmu_init(current->domain, &pmu_params);
+ break;
+
+ case XENPMU_finish:
+ if ( copy_from_guest(&pmu_params, arg, 1) )
+ return -EFAULT;
+ pvpmu_finish(current->domain, &pmu_params);
+ break;
+
default:
ret = -EINVAL;
}
diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 7d6de54..a991b2d 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -108,6 +108,7 @@ static int virq_is_global(uint32_t virq)
case VIRQ_TIMER:
case VIRQ_DEBUG:
case VIRQ_XENOPROF:
+ case VIRQ_XENPMU:
rc = 0;
break;
case VIRQ_ARCH_0 ... VIRQ_ARCH_7:
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index cb430e0..8a9a337 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -62,6 +62,7 @@ struct vpmu_struct {
void *context; /* May be shared with PV guest */
void *priv_context; /* hypervisor-only */
struct arch_vpmu_ops *arch_vpmu_ops;
+ struct xen_pmu_data *xenpmu_data;
};
/* VPMU states */
diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h
index 66cc494..afb4ca1 100644
--- a/xen/include/public/pmu.h
+++ b/xen/include/public/pmu.h
@@ -25,6 +25,8 @@
#define XENPMU_mode_set 1
#define XENPMU_feature_get 2
#define XENPMU_feature_set 3
+#define XENPMU_init 4
+#define XENPMU_finish 5
/* ` } */
/* Parameters structure for HYPERVISOR_xenpmu_op call */
diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 0766790..e4d0b79 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -161,6 +161,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t);
#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */
#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */
#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */
+#define VIRQ_XENPMU 13 /* V. PMC interrupt */
/* Architecture-specific VIRQ definitions. */
#define VIRQ_ARCH_0 16
diff --git a/xen/include/xsm/dummy.h b/xen/include/xsm/dummy.h
index c637454..ae47135 100644
--- a/xen/include/xsm/dummy.h
+++ b/xen/include/xsm/dummy.h
@@ -665,6 +665,9 @@ static XSM_INLINE int xsm_pmu_op (XSM_DEFAULT_ARG struct domain *d, int op)
case XENPMU_feature_set:
case XENPMU_feature_get:
return xsm_default_action(XSM_PRIV, d, current->domain);
+ case XENPMU_init:
+ case XENPMU_finish:
+ return xsm_default_action(XSM_HOOK, d, current->domain);
default:
return -EPERM;
}
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index fecbc5c..d927ee0 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -1512,6 +1512,10 @@ static int flask_pmu_op (struct domain *d, int op)
case XENPMU_feature_get:
return avc_has_perm(dsid, SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PMU_CTRL, NULL);
+ case XENPMU_init:
+ case XENPMU_finish:
+ return avc_has_perm(dsid, SECINITSID_XEN, SECCLASS_XEN2,
+ XEN2__PMU_USE, NULL);
default:
return -EPERM;
}
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 3c0465d..5018167 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -87,6 +87,8 @@ class xen2
get_symbol
# PMU control
pmu_ctrl
+# PMU use (domains, including unprivileged ones, will be using this operation)
+ pmu_use
}
# Classes domain and domain2 consist of operations that a domain performs on
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 14/21] x86/VPMU: Save VPMU state for PV guests during context switch
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (12 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 15/21] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
` (7 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Save VPMU state during context switch for both HVM and PV(H) guests.
A subsequent patch ("x86/VPMU: NMI-based VPMU support") will make it possible
for vpmu_switch_to() to call vmx_vmcs_try_enter()->vcpu_pause() which needs
is_running to be correctly set/cleared. To prepare for that, call context_saved()
before vpmu_switch_to() is executed. (Note that while this change could have
been dalayed until that later patch, the changes are harmless to existing code
and so we do it here)
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/domain.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 0681c56..bffae81 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1520,16 +1520,13 @@ void context_switch(struct vcpu *prev, struct vcpu *next)
}
if ( prev != next )
- _update_runstate_area(prev);
-
- if ( is_hvm_vcpu(prev) )
{
- if (prev != next)
- vpmu_switch_from(prev, next);
+ _update_runstate_area(prev);
+ vpmu_switch_from(prev, next);
+ }
- if ( !list_empty(&prev->arch.hvm_vcpu.tm_list) )
+ if ( is_hvm_vcpu(prev) && !list_empty(&prev->arch.hvm_vcpu.tm_list) )
pt_save_timer(prev);
- }
local_irq_disable();
@@ -1568,15 +1565,16 @@ void context_switch(struct vcpu *prev, struct vcpu *next)
!is_hardware_domain(next->domain));
}
- if ( is_hvm_vcpu(prev) && (prev != next) )
- /* Must be done with interrupts enabled */
- vpmu_switch_to(prev, next);
-
context_saved(prev);
if ( prev != next )
+ {
_update_runstate_area(next);
+ /* Must be done with interrupts enabled */
+ vpmu_switch_to(prev, next);
+ }
+
/* Ensure that the vcpu has an up-to-date time base. */
update_vcpu_system_time(next);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 15/21] x86/VPMU: When handling MSR accesses, leave fault injection to callers
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (13 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 14/21] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 16/21] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
` (6 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
With this patch return value of 1 of vpmu_do_msr() will now indicate whether an
error was encountered during MSR processing (instead of stating that the access
was to a VPMU register).
As part of this patch we also check for validity of certain MSR accesses right
when we determine which register is being written, as opposed to postponing this
until later.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/svm/svm.c | 6 ++-
xen/arch/x86/hvm/svm/vpmu.c | 6 +--
xen/arch/x86/hvm/vmx/vmx.c | 24 +++++++++---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 78 ++++++++++++++-------------------------
4 files changed, 53 insertions(+), 61 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index d73b4f9..16a3b52 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1700,7 +1700,8 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
case MSR_AMD_FAM15H_EVNTSEL3:
case MSR_AMD_FAM15H_EVNTSEL4:
case MSR_AMD_FAM15H_EVNTSEL5:
- vpmu_do_rdmsr(msr, msr_content);
+ if ( vpmu_do_rdmsr(msr, msr_content) )
+ goto gpf;
break;
case MSR_AMD64_DR0_ADDRESS_MASK:
@@ -1851,7 +1852,8 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
case MSR_AMD_FAM15H_EVNTSEL3:
case MSR_AMD_FAM15H_EVNTSEL4:
case MSR_AMD_FAM15H_EVNTSEL5:
- vpmu_do_wrmsr(msr, msr_content, 0);
+ if ( vpmu_do_wrmsr(msr, msr_content, 0) )
+ goto gpf;
break;
case MSR_IA32_MCx_MISC(4): /* Threshold register */
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index 07509c8..9e0a457 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -305,7 +305,7 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
is_pmu_enabled(msr_content) && !vpmu_is_set(vpmu, VPMU_RUNNING) )
{
if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
- return 1;
+ return 0;
vpmu_set(vpmu, VPMU_RUNNING);
if ( has_hvm_container_vcpu(v) && is_msr_bitmap_on(vpmu) )
@@ -335,7 +335,7 @@ static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
/* Write to hw counters */
wrmsrl(msr, msr_content);
- return 1;
+ return 0;
}
static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
@@ -353,7 +353,7 @@ static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
rdmsrl(msr, *msr_content);
- return 1;
+ return 0;
}
static void amd_vpmu_destroy(struct vcpu *v)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 438a007..4dc76df 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2088,12 +2088,17 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
*msr_content |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
/* Perhaps vpmu will change some bits. */
+ /* FALLTHROUGH */
+ case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
+ case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
+ case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
+ case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ case MSR_IA32_PEBS_ENABLE:
+ case MSR_IA32_DS_AREA:
if ( vpmu_do_rdmsr(msr, msr_content) )
- goto done;
+ goto gp_fault;
break;
default:
- if ( vpmu_do_rdmsr(msr, msr_content) )
- break;
if ( passive_domain_do_rdmsr(msr, msr_content) )
goto done;
switch ( long_mode_do_msr_read(msr, msr_content) )
@@ -2265,7 +2270,7 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
if ( msr_content & ~supported )
{
/* Perhaps some other bits are supported in vpmu. */
- if ( !vpmu_do_wrmsr(msr, msr_content, supported) )
+ if ( vpmu_do_wrmsr(msr, msr_content, supported) )
break;
}
if ( msr_content & IA32_DEBUGCTLMSR_LBR )
@@ -2293,9 +2298,16 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
if ( !nvmx_msr_write_intercept(msr, msr_content) )
goto gp_fault;
break;
+ case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
+ case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(7):
+ case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
+ case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ case MSR_IA32_PEBS_ENABLE:
+ case MSR_IA32_DS_AREA:
+ if ( vpmu_do_wrmsr(msr, msr_content, 0) )
+ goto gp_fault;
+ break;
default:
- if ( vpmu_do_wrmsr(msr, msr_content, 0) )
- return X86EMUL_OKAY;
if ( passive_domain_do_wrmsr(msr, msr_content) )
return X86EMUL_OKAY;
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 6fd0942..774ad9b 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -463,36 +463,41 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
IA32_DEBUGCTLMSR_BTS_OFF_USR;
if ( !(msr_content & ~supported) &&
vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
- return 1;
+ return 0;
if ( (msr_content & supported) &&
!vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
printk(XENLOG_G_WARNING
"%pv: Debug Store unsupported on this CPU\n",
current);
}
- return 0;
+ return 1;
}
ASSERT(!supported);
+ if ( type == MSR_TYPE_COUNTER &&
+ (msr_content &
+ ~((1ull << core2_get_bitwidth_fix_count()) - 1)) )
+ /* Writing unsupported bits to a fixed counter */
+ return 1;
+
core2_vpmu_cxt = vpmu->context;
enabled_cntrs = vpmu->priv_context;
switch ( msr )
{
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
core2_vpmu_cxt->global_status &= ~msr_content;
- return 1;
+ return 0;
case MSR_CORE_PERF_GLOBAL_STATUS:
gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
"MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
- hvm_inject_hw_exception(TRAP_gp_fault, 0);
return 1;
case MSR_IA32_PEBS_ENABLE:
if ( msr_content & 1 )
gdprintk(XENLOG_WARNING, "Guest is trying to enable PEBS, "
"which is not supported.\n");
core2_vpmu_cxt->pebs_enable = msr_content;
- return 1;
+ return 0;
case MSR_IA32_DS_AREA:
if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) )
{
@@ -501,18 +506,21 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
gdprintk(XENLOG_WARNING,
"Illegal address for IA32_DS_AREA: %#" PRIx64 "x\n",
msr_content);
- hvm_inject_hw_exception(TRAP_gp_fault, 0);
return 1;
}
core2_vpmu_cxt->ds_area = msr_content;
break;
}
gdprintk(XENLOG_WARNING, "Guest setting of DTS is ignored.\n");
- return 1;
+ return 0;
case MSR_CORE_PERF_GLOBAL_CTRL:
global_ctrl = msr_content;
break;
case MSR_CORE_PERF_FIXED_CTR_CTRL:
+ if ( msr_content &
+ ( ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1)) )
+ return 1;
+
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
*enabled_cntrs &= ~(((1ULL << fixed_pmc_cnt) - 1) << 32);
if ( msr_content != 0 )
@@ -535,6 +543,9 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
+ if ( msr_content & (~((1ull << 32) - 1)) )
+ return 1;
+
vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
if ( msr_content & (1ULL << 22) )
@@ -546,45 +557,17 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
}
}
+ if ( type != MSR_TYPE_GLOBAL )
+ wrmsrl(msr, msr_content);
+ else
+ vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+
if ( (global_ctrl & *enabled_cntrs) || (core2_vpmu_cxt->ds_area != 0) )
vpmu_set(vpmu, VPMU_RUNNING);
else
vpmu_reset(vpmu, VPMU_RUNNING);
- if ( type != MSR_TYPE_GLOBAL )
- {
- u64 mask;
- int inject_gp = 0;
- switch ( type )
- {
- case MSR_TYPE_ARCH_CTRL: /* MSR_P6_EVNTSEL[0,...] */
- mask = ~((1ull << 32) - 1);
- if (msr_content & mask)
- inject_gp = 1;
- break;
- case MSR_TYPE_CTRL: /* IA32_FIXED_CTR_CTRL */
- if ( msr == MSR_IA32_DS_AREA )
- break;
- /* 4 bits per counter, currently 3 fixed counters implemented. */
- mask = ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1);
- if (msr_content & mask)
- inject_gp = 1;
- break;
- case MSR_TYPE_COUNTER: /* IA32_FIXED_CTR[0-2] */
- mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1);
- if (msr_content & mask)
- inject_gp = 1;
- break;
- }
- if (inject_gp)
- hvm_inject_hw_exception(TRAP_gp_fault, 0);
- else
- wrmsrl(msr, msr_content);
- }
- else
- vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
-
- return 1;
+ return 0;
}
static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
@@ -612,19 +595,14 @@ static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
rdmsrl(msr, *msr_content);
}
}
- else
+ else if ( msr == MSR_IA32_MISC_ENABLE )
{
/* Extension for BTS */
- if ( msr == MSR_IA32_MISC_ENABLE )
- {
- if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
- *msr_content &= ~MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
- }
- else
- return 0;
+ if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
+ *msr_content &= ~MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
}
- return 1;
+ return 0;
}
static void core2_vpmu_do_cpuid(unsigned int input,
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 16/21] x86/VPMU: Add support for PMU register handling on PV guests
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (14 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 15/21] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
` (5 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Intercept accesses to PMU MSRs and process them in VPMU module.
Dump VPMU state for all domains (HVM and PV) when requested.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
---
xen/arch/x86/domain.c | 3 +--
xen/arch/x86/hvm/vmx/vpmu_core2.c | 49 ++++++++++++++++++++++++++++++++------
xen/arch/x86/traps.c | 50 ++++++++++++++++++++++++++++++++++++++-
3 files changed, 92 insertions(+), 10 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index bffae81..7260766 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -2054,8 +2054,7 @@ void arch_dump_vcpu_info(struct vcpu *v)
{
paging_dump_vcpu_info(v);
- if ( is_hvm_vcpu(v) )
- vpmu_dump(v);
+ vpmu_dump(v);
}
void domain_cpuid(
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 774ad9b..8d6002c 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -27,6 +27,7 @@
#include <asm/regs.h>
#include <asm/types.h>
#include <asm/apic.h>
+#include <asm/traps.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
#include <asm/hvm/support.h>
@@ -299,12 +300,18 @@ static inline void __core2_vpmu_save(struct vcpu *v)
rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, fixed_counters[i]);
for ( i = 0; i < arch_pmc_cnt; i++ )
rdmsrl(MSR_IA32_PERFCTR0 + i, xen_pmu_cntr_pair[i].counter);
+
+ if ( !has_hvm_container_vcpu(v) )
+ rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status);
}
static int core2_vpmu_save(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
+ if ( !has_hvm_container_vcpu(v) )
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+
if ( !vpmu_are_all_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED) )
return 0;
@@ -342,6 +349,13 @@ static inline void __core2_vpmu_load(struct vcpu *v)
wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, core2_vpmu_cxt->fixed_ctrl);
wrmsrl(MSR_IA32_DS_AREA, core2_vpmu_cxt->ds_area);
wrmsrl(MSR_IA32_PEBS_ENABLE, core2_vpmu_cxt->pebs_enable);
+
+ if ( !has_hvm_container_vcpu(v) )
+ {
+ wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, core2_vpmu_cxt->global_ovf_ctrl);
+ core2_vpmu_cxt->global_ovf_ctrl = 0;
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl);
+ }
}
static void core2_vpmu_load(struct vcpu *v)
@@ -442,7 +456,6 @@ static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
uint64_t supported)
{
- u64 global_ctrl;
int i, tmp;
int type = -1, index = -1;
struct vcpu *v = current;
@@ -486,7 +499,12 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
switch ( msr )
{
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ if ( msr_content & ~(0xC000000000000000 |
+ (((1ULL << fixed_pmc_cnt) - 1) << 32) |
+ ((1ULL << arch_pmc_cnt) - 1)) )
+ return 1;
core2_vpmu_cxt->global_status &= ~msr_content;
+ wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
return 0;
case MSR_CORE_PERF_GLOBAL_STATUS:
gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
@@ -514,14 +532,18 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
gdprintk(XENLOG_WARNING, "Guest setting of DTS is ignored.\n");
return 0;
case MSR_CORE_PERF_GLOBAL_CTRL:
- global_ctrl = msr_content;
+ core2_vpmu_cxt->global_ctrl = msr_content;
break;
case MSR_CORE_PERF_FIXED_CTR_CTRL:
if ( msr_content &
( ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1)) )
return 1;
- vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
+ if ( has_hvm_container_vcpu(v) )
+ vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
+ &core2_vpmu_cxt->global_ctrl);
+ else
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl);
*enabled_cntrs &= ~(((1ULL << fixed_pmc_cnt) - 1) << 32);
if ( msr_content != 0 )
{
@@ -546,7 +568,11 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( msr_content & (~((1ull << 32) - 1)) )
return 1;
- vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, &global_ctrl);
+ if ( has_hvm_container_vcpu(v) )
+ vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
+ &core2_vpmu_cxt->global_ctrl);
+ else
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl);
if ( msr_content & (1ULL << 22) )
*enabled_cntrs |= 1ULL << tmp;
@@ -560,9 +586,15 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
if ( type != MSR_TYPE_GLOBAL )
wrmsrl(msr, msr_content);
else
- vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+ {
+ if ( has_hvm_container_vcpu(v) )
+ vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+ else
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+ }
- if ( (global_ctrl & *enabled_cntrs) || (core2_vpmu_cxt->ds_area != 0) )
+ if ( (core2_vpmu_cxt->global_ctrl & *enabled_cntrs) ||
+ (core2_vpmu_cxt->ds_area != 0) )
vpmu_set(vpmu, VPMU_RUNNING);
else
vpmu_reset(vpmu, VPMU_RUNNING);
@@ -589,7 +621,10 @@ static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
*msr_content = core2_vpmu_cxt->global_status;
break;
case MSR_CORE_PERF_GLOBAL_CTRL:
- vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+ if ( has_hvm_container_vcpu(v) )
+ vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
+ else
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content);
break;
default:
rdmsrl(msr, *msr_content);
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 10fc2ca..70477b2 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -72,6 +72,7 @@
#include <asm/apic.h>
#include <asm/mc146818rtc.h>
#include <asm/hpet.h>
+#include <asm/hvm/vpmu.h>
#include <public/arch-x86/cpuid.h>
#include <xsm/xsm.h>
@@ -896,8 +897,10 @@ void pv_cpuid(struct cpu_user_regs *regs)
__clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
break;
+ case 0x0000000a: /* Architectural Performance Monitor Features (Intel) */
+ break;
+
case 0x00000005: /* MONITOR/MWAIT */
- case 0x0000000a: /* Architectural Performance Monitor Features */
case 0x0000000b: /* Extended Topology Enumeration */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
@@ -913,6 +916,9 @@ void pv_cpuid(struct cpu_user_regs *regs)
}
out:
+ /* VPMU may decide to modify some of the leaves */
+ vpmu_do_cpuid(regs->eax, &a, &b, &c, &d);
+
regs->eax = a;
regs->ebx = b;
regs->ecx = c;
@@ -1935,6 +1941,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
char io_emul_stub[32];
void (*io_emul)(struct cpu_user_regs *) __attribute__((__regparm__(1)));
uint64_t val, msr_content;
+ bool_t vpmu_msr;
if ( !read_descriptor(regs->cs, v, regs,
&code_base, &code_limit, &ar,
@@ -2425,6 +2432,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
uint32_t eax = regs->eax;
uint32_t edx = regs->edx;
msr_content = ((uint64_t)edx << 32) | eax;
+ vpmu_msr = 0;
switch ( (u32)regs->ecx )
{
case MSR_FS_BASE:
@@ -2561,6 +2569,22 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
if ( v->arch.debugreg[7] & DR7_ACTIVE_MASK )
wrmsrl(regs->_ecx, msr_content);
break;
+ case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
+ case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
+ case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
+ case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ vpmu_msr = 1;
+ case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
+ if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+ {
+ if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
+ goto fail;
+ }
+ break;
+ }
+ /*FALLTHROUGH*/
default:
if ( wrmsr_hypervisor_regs(regs->ecx, msr_content) == 1 )
@@ -2593,6 +2617,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
break;
case 0x32: /* RDMSR */
+ vpmu_msr = 0;
switch ( (u32)regs->ecx )
{
case MSR_FS_BASE:
@@ -2663,6 +2688,29 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
[regs->_ecx - MSR_AMD64_DR1_ADDRESS_MASK + 1];
regs->edx = 0;
break;
+ case MSR_IA32_PERF_CAPABILITIES:
+ /* No extra capabilities are supported */
+ regs->eax = regs->edx = 0;
+ break;
+ case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
+ case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
+ case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
+ case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ vpmu_msr = 1;
+ case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
+ if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+ {
+ if ( vpmu_do_rdmsr(regs->ecx, &msr_content) )
+ goto fail;
+
+ regs->eax = (uint32_t)msr_content;
+ regs->edx = (uint32_t)(msr_content >> 32);
+ }
+ break;
+ }
+ /*FALLTHROUGH*/
default:
if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (15 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 16/21] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-27 16:54 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 18/21] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
` (4 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Add support for handling PMU interrupts for PV guests.
VPMU for the interrupted VCPU is unloaded until the guest issues XENPMU_flush
hypercall. This allows the guest to access PMU MSR values that are stored in
VPMU context which is shared between hypervisor and domain, thus avoiding
traps to hypervisor.
Since the interrupt handler may now force VPMU context save (i.e. set
VPMU_CONTEXT_SAVE flag) we need to make changes to amd_vpmu_save() which
until now expected this flag to be set only when the counters were stopped.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/svm/vpmu.c | 11 +-
xen/arch/x86/hvm/vpmu.c | 206 ++++++++++++++++++++++++++++++++++++--
xen/include/public/arch-x86/pmu.h | 5 +
xen/include/public/pmu.h | 2 +
xen/include/xsm/dummy.h | 4 +-
xen/xsm/flask/hooks.c | 2 +
6 files changed, 210 insertions(+), 20 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index 9e0a457..654930a 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -228,17 +228,12 @@ static int amd_vpmu_save(struct vcpu *v)
struct vpmu_struct *vpmu = vcpu_vpmu(v);
unsigned int i;
- /*
- * Stop the counters. If we came here via vpmu_save_force (i.e.
- * when VPMU_CONTEXT_SAVE is set) counters are already stopped.
- */
+ for ( i = 0; i < num_counters; i++ )
+ wrmsrl(ctrls[i], 0);
+
if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_SAVE) )
{
vpmu_set(vpmu, VPMU_FROZEN);
-
- for ( i = 0; i < num_counters; i++ )
- wrmsrl(ctrls[i], 0);
-
return 0;
}
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index f086156..0bd95ee 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
void vpmu_lvtpc_update(uint32_t val)
{
- struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ struct vcpu *curr = current;
+ struct vpmu_struct *vpmu = vcpu_vpmu(curr);
vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
- apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
+
+ /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending */
+ if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
+ !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
+ apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
}
int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported)
{
- struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ struct vcpu *curr = current;
+ struct vpmu_struct *vpmu = vcpu_vpmu(curr);
if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
return 0;
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_wrmsr )
- return vpmu->arch_vpmu_ops->do_wrmsr(msr, msr_content, supported);
+ {
+ int ret = vpmu->arch_vpmu_ops->do_wrmsr(msr, msr_content, supported);
+
+ /*
+ * We may have received a PMU interrupt during WRMSR handling
+ * and since do_wrmsr may load VPMU context we should save
+ * (and unload) it again.
+ */
+ if ( !is_hvm_vcpu(curr) && vpmu->xenpmu_data &&
+ (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
+ {
+ vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
+ vpmu->arch_vpmu_ops->arch_vpmu_save(curr);
+ vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
+ }
+ return ret;
+ }
return 0;
}
int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
{
- struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ struct vcpu *curr = current;
+ struct vpmu_struct *vpmu = vcpu_vpmu(curr);
if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
return 0;
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_rdmsr )
- return vpmu->arch_vpmu_ops->do_rdmsr(msr, msr_content);
+ {
+ int ret = vpmu->arch_vpmu_ops->do_rdmsr(msr, msr_content);
+
+ if ( !is_hvm_vcpu(curr) && vpmu->xenpmu_data &&
+ (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
+ {
+ vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
+ vpmu->arch_vpmu_ops->arch_vpmu_save(curr);
+ vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
+ }
+ return ret;
+ }
return 0;
}
+static struct vcpu *choose_hwdom_vcpu(void)
+{
+ unsigned idx = smp_processor_id() % hardware_domain->max_vcpus;
+
+ if ( hardware_domain->vcpu == NULL )
+ return NULL;
+
+ return hardware_domain->vcpu[idx];
+}
+
void vpmu_do_interrupt(struct cpu_user_regs *regs)
{
- struct vcpu *v = current;
- struct vpmu_struct *vpmu = vcpu_vpmu(v);
+ struct vcpu *sampled = current, *sampling;
+ struct vpmu_struct *vpmu;
+
+ /* dom0 will handle interrupt for special domains (e.g. idle domain) */
+ if ( sampled->domain->domain_id >= DOMID_FIRST_RESERVED )
+ {
+ sampling = choose_hwdom_vcpu();
+ if ( !sampling )
+ return;
+ }
+ else
+ sampling = sampled;
+
+ vpmu = vcpu_vpmu(sampling);
+ if ( !is_hvm_vcpu(sampling) )
+ {
+ /* PV(H) guest */
+ const struct cpu_user_regs *cur_regs;
+ uint64_t *flags = &vpmu->xenpmu_data->pmu.pmu_flags;
+ uint32_t domid = DOMID_SELF;
+
+ if ( !vpmu->xenpmu_data )
+ return;
+
+ if ( *flags & PMU_CACHED )
+ return;
+
+ if ( is_pvh_vcpu(sampling) &&
+ !vpmu->arch_vpmu_ops->do_interrupt(regs) )
+ return;
+
+ /* PV guest will be reading PMU MSRs from xenpmu_data */
+ vpmu_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
+ vpmu->arch_vpmu_ops->arch_vpmu_save(sampling);
+ vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
+
+ *flags = 0;
+
+ /* Store appropriate registers in xenpmu_data */
+ /* FIXME: 32-bit PVH should go here as well */
+ if ( is_pv_32bit_vcpu(sampling) )
+ {
+ /*
+ * 32-bit dom0 cannot process Xen's addresses (which are 64 bit)
+ * and therefore we treat it the same way as a non-privileged
+ * PV 32-bit domain.
+ */
+ struct compat_pmu_regs *cmp;
+
+ cur_regs = guest_cpu_user_regs();
+
+ cmp = (void *)&vpmu->xenpmu_data->pmu.r.regs;
+ cmp->ip = cur_regs->rip;
+ cmp->sp = cur_regs->rsp;
+ cmp->flags = cur_regs->eflags;
+ cmp->ss = cur_regs->ss;
+ cmp->cs = cur_regs->cs;
+ if ( (cmp->cs & 3) != 1 )
+ *flags |= PMU_SAMPLE_USER;
+ }
+ else
+ {
+ struct xen_pmu_regs *r = &vpmu->xenpmu_data->pmu.r.regs;
+
+ if ( (vpmu_mode & XENPMU_MODE_SELF) )
+ cur_regs = guest_cpu_user_regs();
+ else if ( (regs->rip >= XEN_VIRT_START) &&
+ (regs->rip < XEN_VIRT_END) &&
+ is_hardware_domain(sampling->domain))
+ {
+ cur_regs = regs;
+ domid = DOMID_XEN;
+ }
+ else
+ cur_regs = guest_cpu_user_regs();
+
+ r->ip = cur_regs->rip;
+ r->sp = cur_regs->rsp;
+ r->flags = cur_regs->eflags;
+
+ if ( !has_hvm_container_vcpu(sampled) )
+ {
+ r->ss = cur_regs->ss;
+ r->cs = cur_regs->cs;
+ if ( !(sampled->arch.flags & TF_kernel_mode) )
+ *flags |= PMU_SAMPLE_USER;
+ }
+ else
+ {
+ struct segment_register seg;
+
+ hvm_get_segment_register(sampled, x86_seg_cs, &seg);
+ r->cs = seg.sel;
+ if ( (r->cs & 3) != 0 )
+ *flags |= PMU_SAMPLE_USER;
+ if ( !(sampled->arch.hvm_vcpu.guest_cr[0] & X86_CR0_PE) )
+ *flags |= PMU_SAMPLE_REAL;
+
+ hvm_get_segment_register(sampled, x86_seg_ss, &seg);
+ r->ss = seg.sel;
+ }
+ }
+
+ vpmu->xenpmu_data->domain_id = domid;
+ vpmu->xenpmu_data->vcpu_id = sampled->vcpu_id;
+ vpmu->xenpmu_data->pcpu_id = smp_processor_id();
+
+ *flags |= PMU_CACHED;
+ vpmu->hw_lapic_lvtpc |= APIC_LVT_MASKED;
+ apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
+
+ send_guest_vcpu_virq(sampling, VIRQ_XENPMU);
+
+ return;
+ }
if ( vpmu->arch_vpmu_ops )
{
- struct vlapic *vlapic = vcpu_vlapic(v);
+ struct vlapic *vlapic = vcpu_vlapic(sampling);
u32 vlapic_lvtpc;
+ /* We don't support (yet) HVM dom0 */
+ ASSERT(sampling == sampled);
+
if ( !vpmu->arch_vpmu_ops->do_interrupt(regs) ||
!is_vlapic_lvtpc_enabled(vlapic) )
return;
@@ -133,7 +293,7 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
vlapic_set_irq(vlapic, vlapic_lvtpc & APIC_VECTOR_MASK, 0);
break;
case APIC_MODE_NMI:
- v->nmi_pending = 1;
+ sampling->nmi_pending = 1;
break;
}
}
@@ -231,7 +391,9 @@ void vpmu_load(struct vcpu *v)
local_irq_enable();
/* Only when PMU is counting, we load PMU context immediately. */
- if ( !vpmu_is_set(vpmu, VPMU_RUNNING) )
+ if ( !vpmu_is_set(vpmu, VPMU_RUNNING) ||
+ (!is_hvm_vcpu(v) &&
+ (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED)) )
return;
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->arch_vpmu_load )
@@ -249,6 +411,8 @@ void vpmu_initialise(struct vcpu *v)
BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ);
BUILD_BUG_ON(sizeof(struct xen_pmu_amd_ctxt) > XENPMU_CTXT_PAD_SZ);
+ BUILD_BUG_ON(sizeof(struct xen_pmu_regs) > XENPMU_REGS_PAD_SZ);
+ BUILD_BUG_ON(sizeof(struct compat_pmu_regs) > XENPMU_REGS_PAD_SZ);
if ( vpmu_is_set(vpmu, VPMU_CONTEXT_ALLOCATED) )
vpmu_destroy(v);
@@ -459,7 +623,9 @@ static int vpmu_force_context_switch(void)
long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
{
int ret;
+ struct vcpu *curr;
struct xen_pmu_params pmu_params;
+ struct xen_pmu_data *xenpmu_data;
static DEFINE_SPINLOCK(xenpmu_mode_lock);
ret = xsm_pmu_op(XSM_OTHER, current->domain, op);
@@ -558,6 +724,24 @@ long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
pvpmu_finish(current->domain, &pmu_params);
break;
+ case XENPMU_lvtpc_set:
+ curr = current;
+ xenpmu_data = curr->arch.vpmu.xenpmu_data;
+ if ( xenpmu_data == NULL )
+ return -EINVAL;
+ vpmu_lvtpc_update(xenpmu_data->pmu.l.lapic_lvtpc);
+ break;
+
+ case XENPMU_flush:
+ curr = current;
+ xenpmu_data = curr->arch.vpmu.xenpmu_data;
+ if ( xenpmu_data == NULL )
+ return -EINVAL;
+ xenpmu_data->pmu.pmu_flags &= ~PMU_CACHED;
+ vpmu_lvtpc_update(xenpmu_data->pmu.l.lapic_lvtpc);
+ vpmu_load(curr);
+ break;
+
default:
ret = -EINVAL;
}
diff --git a/xen/include/public/arch-x86/pmu.h b/xen/include/public/arch-x86/pmu.h
index b0f9100..d795594 100644
--- a/xen/include/public/arch-x86/pmu.h
+++ b/xen/include/public/arch-x86/pmu.h
@@ -50,6 +50,11 @@ struct xen_pmu_regs {
typedef struct xen_pmu_regs xen_pmu_regs_t;
DEFINE_XEN_GUEST_HANDLE(xen_pmu_regs_t);
+/* PMU flags */
+#define PMU_CACHED (1<<0) /* PMU MSRs are cached in the context */
+#define PMU_SAMPLE_USER (1<<1) /* Sample is from user or kernel mode */
+#define PMU_SAMPLE_REAL (1<<2) /* Sample is from realmode */
+
struct xen_pmu_arch {
union {
struct xen_pmu_regs regs;
diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h
index afb4ca1..db5321a 100644
--- a/xen/include/public/pmu.h
+++ b/xen/include/public/pmu.h
@@ -27,6 +27,8 @@
#define XENPMU_feature_set 3
#define XENPMU_init 4
#define XENPMU_finish 5
+#define XENPMU_lvtpc_set 6
+#define XENPMU_flush 7 /* Write cached MSR values to HW */
/* ` } */
/* Parameters structure for HYPERVISOR_xenpmu_op call */
diff --git a/xen/include/xsm/dummy.h b/xen/include/xsm/dummy.h
index ae47135..1ad4ecc 100644
--- a/xen/include/xsm/dummy.h
+++ b/xen/include/xsm/dummy.h
@@ -666,7 +666,9 @@ static XSM_INLINE int xsm_pmu_op (XSM_DEFAULT_ARG struct domain *d, int op)
case XENPMU_feature_get:
return xsm_default_action(XSM_PRIV, d, current->domain);
case XENPMU_init:
- case XENPMU_finish:
+ case XENPMU_finish:
+ case XENPMU_lvtpc_set:
+ case XENPMU_flush:
return xsm_default_action(XSM_HOOK, d, current->domain);
default:
return -EPERM;
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index d927ee0..6cd76fa 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -1514,6 +1514,8 @@ static int flask_pmu_op (struct domain *d, int op)
XEN2__PMU_CTRL, NULL);
case XENPMU_init:
case XENPMU_finish:
+ case XENPMU_lvtpc_set:
+ case XENPMU_flush:
return avc_has_perm(dsid, SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PMU_USE, NULL);
default:
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 18/21] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (16 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 19/21] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
` (3 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
The two routines share most of their logic.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/hvm/vpmu.c | 69 +++++++++++++++++-------------------------
xen/include/asm-x86/hvm/vpmu.h | 14 +++++++--
2 files changed, 39 insertions(+), 44 deletions(-)
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index 0bd95ee..14f969c 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -92,57 +92,42 @@ void vpmu_lvtpc_update(uint32_t val)
apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
}
-int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported)
+int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
+ uint64_t supported, bool_t is_write)
{
- struct vcpu *curr = current;
- struct vpmu_struct *vpmu = vcpu_vpmu(curr);
+ struct vcpu *curr;
+ struct vpmu_struct *vpmu;
+ struct arch_vpmu_ops *ops;
+ int ret = 0;
if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
return 0;
- if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_wrmsr )
- {
- int ret = vpmu->arch_vpmu_ops->do_wrmsr(msr, msr_content, supported);
-
- /*
- * We may have received a PMU interrupt during WRMSR handling
- * and since do_wrmsr may load VPMU context we should save
- * (and unload) it again.
- */
- if ( !is_hvm_vcpu(curr) && vpmu->xenpmu_data &&
- (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
- {
- vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
- vpmu->arch_vpmu_ops->arch_vpmu_save(curr);
- vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
- }
- return ret;
- }
- return 0;
-}
-
-int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
-{
- struct vcpu *curr = current;
- struct vpmu_struct *vpmu = vcpu_vpmu(curr);
-
- if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
+ curr = current;
+ vpmu = vcpu_vpmu(curr);
+ ops = vpmu->arch_vpmu_ops;
+ if ( !ops )
return 0;
- if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->do_rdmsr )
- {
- int ret = vpmu->arch_vpmu_ops->do_rdmsr(msr, msr_content);
+ if ( is_write && ops->do_wrmsr )
+ ret = ops->do_wrmsr(msr, *msr_content, supported);
+ else if ( !is_write && ops->do_rdmsr )
+ ret = ops->do_rdmsr(msr, msr_content);
- if ( !is_hvm_vcpu(curr) && vpmu->xenpmu_data &&
- (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
- {
- vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
- vpmu->arch_vpmu_ops->arch_vpmu_save(curr);
- vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
- }
- return ret;
+ /*
+ * We may have received a PMU interrupt while handling MSR access
+ * and since do_wr/rdmsr may load VPMU context we should save
+ * (and unload) it again.
+ */
+ if ( !is_hvm_vcpu(curr) &&
+ vpmu->xenpmu_data && (vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
+ {
+ vpmu_set(vpmu, VPMU_CONTEXT_SAVE);
+ ops->arch_vpmu_save(curr);
+ vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
}
- return 0;
+
+ return ret;
}
static struct vcpu *choose_hwdom_vcpu(void)
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 8a9a337..3efba21 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -96,8 +96,8 @@ static inline bool_t vpmu_are_all_set(const struct vpmu_struct *vpmu,
}
void vpmu_lvtpc_update(uint32_t val);
-int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, uint64_t supported);
-int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content);
+int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
+ uint64_t supported, bool_t is_write);
void vpmu_do_interrupt(struct cpu_user_regs *regs);
void vpmu_do_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx);
@@ -107,6 +107,16 @@ void vpmu_save(struct vcpu *v);
void vpmu_load(struct vcpu *v);
void vpmu_dump(struct vcpu *v);
+static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
+ uint64_t supported)
+{
+ return vpmu_do_msr(msr, &msr_content, supported, 1);
+}
+static inline int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
+{
+ return vpmu_do_msr(msr, msr_content, 0, 0);
+}
+
extern int acquire_pmu_ownership(int pmu_ownership);
extern void release_pmu_ownership(int pmu_ownership);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 19/21] x86/VPMU: Add privileged PMU mode
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (17 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 18/21] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
` (2 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Add support for privileged PMU mode (XENPMU_MODE_ALL) which allows privileged
domain (dom0) profile both itself (and the hypervisor) and the guests. While
this mode is on profiling in guests is disabled.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
xen/arch/x86/hvm/vpmu.c | 30 ++++++++++++++++++++++--------
xen/arch/x86/traps.c | 12 ++++++++++++
xen/include/public/pmu.h | 3 +++
3 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index 14f969c..a987dbd 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -100,7 +100,9 @@ int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
struct arch_vpmu_ops *ops;
int ret = 0;
- if ( !(vpmu_mode & (XENPMU_MODE_SELF | XENPMU_MODE_HV)) )
+ if ( (vpmu_mode == XENPMU_MODE_OFF) ||
+ ((vpmu_mode & XENPMU_MODE_ALL) &&
+ !is_hardware_domain(current->domain)) )
return 0;
curr = current;
@@ -145,8 +147,12 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
struct vcpu *sampled = current, *sampling;
struct vpmu_struct *vpmu;
- /* dom0 will handle interrupt for special domains (e.g. idle domain) */
- if ( sampled->domain->domain_id >= DOMID_FIRST_RESERVED )
+ /*
+ * dom0 will handle interrupt for special domains (e.g. idle domain) or,
+ * in XENPMU_MODE_ALL, for everyone.
+ */
+ if ( (vpmu_mode & XENPMU_MODE_ALL) ||
+ (sampled->domain->domain_id >= DOMID_FIRST_RESERVED) )
{
sampling = choose_hwdom_vcpu();
if ( !sampling )
@@ -156,12 +162,12 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
sampling = sampled;
vpmu = vcpu_vpmu(sampling);
- if ( !is_hvm_vcpu(sampling) )
+ if ( !is_hvm_vcpu(sampling) || (vpmu_mode & XENPMU_MODE_ALL) )
{
/* PV(H) guest */
const struct cpu_user_regs *cur_regs;
uint64_t *flags = &vpmu->xenpmu_data->pmu.pmu_flags;
- uint32_t domid = DOMID_SELF;
+ uint32_t domid;
if ( !vpmu->xenpmu_data )
return;
@@ -170,6 +176,7 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
return;
if ( is_pvh_vcpu(sampling) &&
+ !(vpmu_mode & XENPMU_MODE_ALL) &&
!vpmu->arch_vpmu_ops->do_interrupt(regs) )
return;
@@ -180,6 +187,11 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
*flags = 0;
+ if ( sampled == sampling )
+ domid = DOMID_SELF;
+ else
+ domid = sampled->domain->domain_id;
+
/* Store appropriate registers in xenpmu_data */
/* FIXME: 32-bit PVH should go here as well */
if ( is_pv_32bit_vcpu(sampling) )
@@ -626,11 +638,13 @@ long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
if ( copy_from_guest(&pmu_params, arg, 1) )
return -EFAULT;
- if ( pmu_params.val & ~(XENPMU_MODE_SELF | XENPMU_MODE_HV) )
+ if ( pmu_params.val & ~(XENPMU_MODE_SELF | XENPMU_MODE_HV |
+ XENPMU_MODE_ALL) )
return -EINVAL;
/* 32-bit dom0 can only sample itself */
- if ( is_pv_32bit_vcpu(current) && (pmu_params.val & XENPMU_MODE_HV) )
+ if ( is_pv_32bit_vcpu(current) &&
+ (pmu_params.val & (XENPMU_MODE_HV | XENPMU_MODE_ALL)) )
return -EINVAL;
/*
@@ -648,7 +662,7 @@ long do_xenpmu_op(int op, XEN_GUEST_HANDLE_PARAM(xen_pmu_params_t) arg)
current_mode = vpmu_mode;
vpmu_mode = pmu_params.val;
- if ( vpmu_mode == XENPMU_MODE_OFF )
+ if ( (vpmu_mode == XENPMU_MODE_OFF) || (vpmu_mode == XENPMU_MODE_ALL) )
{
/*
* Make sure all (non-dom0) VCPUs have unloaded their VPMUs. This
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 70477b2..663b44f 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2579,6 +2579,10 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
{
+ if ( (vpmu_mode & XENPMU_MODE_ALL) &&
+ !is_hardware_domain(v->domain) )
+ break;
+
if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
goto fail;
}
@@ -2702,6 +2706,14 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
{
+ if ( (vpmu_mode & XENPMU_MODE_ALL) &&
+ !is_hardware_domain(v->domain) )
+ {
+ /* Don't leak PMU MSRs to unprivileged domains */
+ regs->eax = regs->edx = 0;
+ break;
+ }
+
if ( vpmu_do_rdmsr(regs->ecx, &msr_content) )
goto fail;
diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h
index db5321a..a83ae71 100644
--- a/xen/include/public/pmu.h
+++ b/xen/include/public/pmu.h
@@ -52,10 +52,13 @@ DEFINE_XEN_GUEST_HANDLE(xen_pmu_params_t);
* - XENPMU_MODE_SELF: Guests can profile themselves
* - XENPMU_MODE_HV: Guests can profile themselves, dom0 profiles
* itself and Xen
+ * - XENPMU_MODE_ALL: Only dom0 has access to VPMU and it profiles
+ * everyone: itself, the hypervisor and the guests.
*/
#define XENPMU_MODE_OFF 0
#define XENPMU_MODE_SELF (1<<0)
#define XENPMU_MODE_HV (1<<1)
+#define XENPMU_MODE_ALL (1<<2)
/*
* PMU features:
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (18 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 19/21] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-28 10:51 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-10-27 7:38 ` [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Dietmar Hahn
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Add support for using NMIs as PMU interrupts to allow profiling hypervisor
when interrupts are disabled.
Most of processing is still performed by vpmu_do_interrupt(). However, since
certain operations are not NMI-safe we defer them to a softint that vpmu_do_interrupt()
will schedule:
* For PV guests that would be send_guest_vcpu_virq()
* For HVM guests it's VLAPIC accesses and hvm_get_segment_register() (the later
can be called in privileged profiling mode when the interrupted guest is an HVM one).
With send_guest_vcpu_virq() and hvm_get_segment_register() for PV(H) and vlapic
accesses for HVM moved to sofint, the only routines/macros that vpmu_do_interrupt()
calls in NMI mode are:
* memcpy()
* querying domain type (is_XX_domain())
* guest_cpu_user_regs()
* XLAT_cpu_user_regs()
* raise_softirq()
* vcpu_vpmu()
* vpmu_ops->arch_vpmu_save()
* vpmu_ops->do_interrupt()
The latter two only access PMU MSRs with {rd,wr}msrl() (not the _safe versions
which would not be NMI-safe).
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
docs/misc/xen-command-line.markdown | 8 +-
xen/arch/x86/hvm/svm/vpmu.c | 3 +-
xen/arch/x86/hvm/vmx/vpmu_core2.c | 3 +-
xen/arch/x86/hvm/vpmu.c | 232 ++++++++++++++++++++++++++++--------
xen/include/asm-x86/hvm/vpmu.h | 4 +-
xen/include/asm-x86/softirq.h | 3 +-
6 files changed, 196 insertions(+), 57 deletions(-)
diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown
index 28bbaaf..0f87572 100644
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -1259,11 +1259,11 @@ Use Virtual Processor ID support if available. This prevents the need for TLB
flushes on VM entry and exit, increasing performance.
### vpmu
-> `= ( bts )`
+> `= ( [nmi,][bts] )`
> Default: `off`
-Switch on the virtualized performance monitoring unit for HVM guests.
+Switch on the virtualized performance monitoring unit.
If the current cpu isn't supported a message like
'VPMU: Initialization failed. ...'
@@ -1275,6 +1275,10 @@ wrong behaviour (see handle\_pmc\_quirk()).
If 'vpmu=bts' is specified the virtualisation of the Branch Trace Store (BTS)
feature is switched on on Intel processors supporting this feature.
+If 'vpmu=nmi' is specified the PMU interrupt will cause an NMI instead of a
+regular vector interrupt (which is the default). This can be useful for sampling
+hypervisor code that is executed with interrupts disabled.
+
*Warning:*
As the BTS virtualisation is not 100% safe and because of the nehalem quirk
don't use the vpmu flag on production systems with Intel cpus!
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index 654930a..547fc30 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -168,7 +168,7 @@ static void amd_vpmu_unset_msr_bitmap(struct vcpu *v)
msr_bitmap_off(vpmu);
}
-static int amd_vpmu_do_interrupt(struct cpu_user_regs *regs)
+static int amd_vpmu_do_interrupt(const struct cpu_user_regs *regs)
{
return 1;
}
@@ -223,6 +223,7 @@ static inline void context_save(struct vcpu *v)
rdmsrl(counters[i], counter_regs[i]);
}
+/* Must be NMI-safe */
static int amd_vpmu_save(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 8d6002c..5607ec9 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -305,6 +305,7 @@ static inline void __core2_vpmu_save(struct vcpu *v)
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status);
}
+/* Must be NMI-safe */
static int core2_vpmu_save(struct vcpu *v)
{
struct vpmu_struct *vpmu = vcpu_vpmu(v);
@@ -706,7 +707,7 @@ static void core2_vpmu_dump(const struct vcpu *v)
}
}
-static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs)
+static int core2_vpmu_do_interrupt(const struct cpu_user_regs *regs)
{
struct vcpu *v = current;
u64 msr_content;
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index a987dbd..4f443f2 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -34,6 +34,7 @@
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
+#include <asm/nmi.h>
#include <public/pmu.h>
#include <xen/tasklet.h>
#include <xsm/xsm.h>
@@ -55,36 +56,54 @@ uint64_t __read_mostly vpmu_features = 0;
static void parse_vpmu_param(char *s);
custom_param("vpmu", parse_vpmu_param);
+static void pmu_softnmi(void);
+
static DEFINE_PER_CPU(struct vcpu *, last_vcpu);
+static DEFINE_PER_CPU(struct vcpu *, sampled_vcpu);
+
+static uint32_t __read_mostly vpmu_interrupt_type = PMU_APIC_VECTOR;
static void __init parse_vpmu_param(char *s)
{
- switch ( parse_bool(s) )
- {
- case 0:
- break;
- default:
- if ( !strcmp(s, "bts") )
- vpmu_features |= XENPMU_FEATURE_INTEL_BTS;
- else if ( *s )
+ char *ss;
+
+ vpmu_mode = XENPMU_MODE_SELF;
+ if (*s == '\0')
+ return;
+
+ do {
+ ss = strchr(s, ',');
+ if ( ss )
+ *ss = '\0';
+
+ switch ( parse_bool(s) )
{
- printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
- break;
+ default:
+ if ( !strcmp(s, "nmi") )
+ vpmu_interrupt_type = APIC_DM_NMI;
+ else if ( !strcmp(s, "bts") )
+ vpmu_features |= XENPMU_FEATURE_INTEL_BTS;
+ else
+ {
+ printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
+ case 0:
+ vpmu_mode = XENPMU_MODE_OFF;
+ case 1:
+ return;
+ }
}
- /* fall through */
- case 1:
- /* Default VPMU mode */
- vpmu_mode = XENPMU_MODE_SELF;
- break;
- }
+
+ s = ss + 1;
+ } while ( ss );
}
+
void vpmu_lvtpc_update(uint32_t val)
{
struct vcpu *curr = current;
struct vpmu_struct *vpmu = vcpu_vpmu(curr);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
+ vpmu->hw_lapic_lvtpc = vpmu_interrupt_type | (val & APIC_LVT_MASKED);
/* Postpone APIC updates for PV(H) guests if PMU interrupt is pending */
if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
@@ -92,6 +111,30 @@ void vpmu_lvtpc_update(uint32_t val)
apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
}
+static void vpmu_send_interrupt(struct vcpu *v)
+{
+ struct vlapic *vlapic;
+ u32 vlapic_lvtpc;
+
+ ASSERT(is_hvm_vcpu(v));
+
+ vlapic = vcpu_vlapic(v);
+ if ( !is_vlapic_lvtpc_enabled(vlapic) )
+ return;
+
+ vlapic_lvtpc = vlapic_get_reg(vlapic, APIC_LVTPC);
+
+ switch ( GET_APIC_DELIVERY_MODE(vlapic_lvtpc) )
+ {
+ case APIC_MODE_FIXED:
+ vlapic_set_irq(vlapic, vlapic_lvtpc & APIC_VECTOR_MASK, 0);
+ break;
+ case APIC_MODE_NMI:
+ v->nmi_pending = 1;
+ break;
+ }
+}
+
int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
uint64_t supported, bool_t is_write)
{
@@ -142,7 +185,7 @@ static struct vcpu *choose_hwdom_vcpu(void)
return hardware_domain->vcpu[idx];
}
-void vpmu_do_interrupt(struct cpu_user_regs *regs)
+int vpmu_do_interrupt(const struct cpu_user_regs *regs)
{
struct vcpu *sampled = current, *sampling;
struct vpmu_struct *vpmu;
@@ -156,7 +199,7 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
{
sampling = choose_hwdom_vcpu();
if ( !sampling )
- return;
+ return 0;
}
else
sampling = sampled;
@@ -170,15 +213,15 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
uint32_t domid;
if ( !vpmu->xenpmu_data )
- return;
+ return 0;
if ( *flags & PMU_CACHED )
- return;
+ return 0;
if ( is_pvh_vcpu(sampling) &&
!(vpmu_mode & XENPMU_MODE_ALL) &&
!vpmu->arch_vpmu_ops->do_interrupt(regs) )
- return;
+ return 0;
/* PV guest will be reading PMU MSRs from xenpmu_data */
vpmu_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
@@ -243,17 +286,22 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
}
else
{
- struct segment_register seg;
-
- hvm_get_segment_register(sampled, x86_seg_cs, &seg);
- r->cs = seg.sel;
- if ( (r->cs & 3) != 0 )
- *flags |= PMU_SAMPLE_USER;
- if ( !(sampled->arch.hvm_vcpu.guest_cr[0] & X86_CR0_PE) )
+ if ( !(sampled->arch.hvm_vcpu.guest_cr[0] & X86_CR0_PE) )
*flags |= PMU_SAMPLE_REAL;
- hvm_get_segment_register(sampled, x86_seg_ss, &seg);
- r->ss = seg.sel;
+ /* Unsafe in NMI context, defer to softint later */
+ if ( vpmu_interrupt_type != APIC_DM_NMI )
+ {
+ struct segment_register seg;
+
+ hvm_get_segment_register(sampled, x86_seg_cs, &seg);
+ r->cs = seg.sel;
+ if ( (r->cs & 3) != 0 )
+ *flags |= PMU_SAMPLE_USER;
+
+ hvm_get_segment_register(sampled, x86_seg_ss, &seg);
+ r->ss = seg.sel;
+ }
}
}
@@ -265,35 +313,37 @@ void vpmu_do_interrupt(struct cpu_user_regs *regs)
vpmu->hw_lapic_lvtpc |= APIC_LVT_MASKED;
apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
- send_guest_vcpu_virq(sampling, VIRQ_XENPMU);
+ if ( vpmu_interrupt_type == APIC_DM_NMI )
+ {
+ this_cpu(sampled_vcpu) = sampled;
+ raise_softirq(PMU_SOFTIRQ);
+ }
+ else
+ send_guest_vcpu_virq(sampling, VIRQ_XENPMU);
- return;
+ return 1;
}
if ( vpmu->arch_vpmu_ops )
{
- struct vlapic *vlapic = vcpu_vlapic(sampling);
- u32 vlapic_lvtpc;
-
/* We don't support (yet) HVM dom0 */
ASSERT(sampling == sampled);
- if ( !vpmu->arch_vpmu_ops->do_interrupt(regs) ||
- !is_vlapic_lvtpc_enabled(vlapic) )
- return;
-
- vlapic_lvtpc = vlapic_get_reg(vlapic, APIC_LVTPC);
+ if ( !vpmu->arch_vpmu_ops->do_interrupt(regs) )
+ return 0;
- switch ( GET_APIC_DELIVERY_MODE(vlapic_lvtpc) )
+ if ( vpmu_interrupt_type == APIC_DM_NMI )
{
- case APIC_MODE_FIXED:
- vlapic_set_irq(vlapic, vlapic_lvtpc & APIC_VECTOR_MASK, 0);
- break;
- case APIC_MODE_NMI:
- sampling->nmi_pending = 1;
- break;
+ this_cpu(sampled_vcpu) = sampled;
+ raise_softirq(PMU_SOFTIRQ);
}
+ else
+ vpmu_send_interrupt(sampling);
+
+ return 1;
}
+
+ return 0;
}
void vpmu_do_cpuid(unsigned int input,
@@ -322,6 +372,9 @@ static void vpmu_save_force(void *arg)
vpmu_reset(vpmu, VPMU_CONTEXT_SAVE);
per_cpu(last_vcpu, smp_processor_id()) = NULL;
+
+ /* Make sure there are no outstanding PMU NMIs */
+ pmu_softnmi();
}
void vpmu_save(struct vcpu *v)
@@ -339,7 +392,10 @@ void vpmu_save(struct vcpu *v)
if ( vpmu->arch_vpmu_ops->arch_vpmu_save(v) )
vpmu_reset(vpmu, VPMU_CONTEXT_LOADED);
- apic_write(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, vpmu_interrupt_type | APIC_LVT_MASKED);
+
+ /* Make sure there are no outstanding PMU NMIs */
+ pmu_softnmi();
}
void vpmu_load(struct vcpu *v)
@@ -393,6 +449,9 @@ void vpmu_load(struct vcpu *v)
(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED)) )
return;
+ /* Make sure there are no outstanding PMU NMIs from previous vcpu */
+ pmu_softnmi();
+
if ( vpmu->arch_vpmu_ops && vpmu->arch_vpmu_ops->arch_vpmu_load )
{
apic_write_around(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
@@ -415,7 +474,7 @@ void vpmu_initialise(struct vcpu *v)
vpmu_destroy(v);
vpmu_clear(vpmu);
vpmu->context = NULL;
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | APIC_LVT_MASKED;
+ vpmu->hw_lapic_lvtpc = vpmu_interrupt_type | APIC_LVT_MASKED;
switch ( vendor )
{
@@ -451,11 +510,63 @@ void vpmu_destroy(struct vcpu *v)
}
}
+/* Process the softirq set by PMU NMI handler */
+static void pmu_softnmi(void)
+{
+ unsigned int cpu = smp_processor_id();
+ struct vcpu *v, *sampled = per_cpu(sampled_vcpu, cpu);
+
+ if ( sampled == NULL )
+ return;
+
+ per_cpu(sampled_vcpu, cpu) = NULL;
+
+ if ( (vpmu_mode & XENPMU_MODE_ALL) ||
+ (sampled->domain->domain_id >= DOMID_FIRST_RESERVED) )
+ {
+ v = choose_hwdom_vcpu();
+ if ( !v )
+ return;
+ }
+ else
+ {
+ if ( is_hvm_vcpu(sampled) )
+ {
+ vpmu_send_interrupt(sampled);
+ return;
+ }
+ v = sampled;
+ }
+
+ if ( has_hvm_container_vcpu(sampled) )
+ {
+ struct segment_register seg;
+ struct xen_pmu_arch *pmu = &v->arch.vpmu.xenpmu_data->pmu;
+ struct xen_pmu_regs *r = &pmu->r.regs;
+
+ hvm_get_segment_register(sampled, x86_seg_cs, &seg);
+ r->cs = seg.sel;
+ if ( (r->cs & 3) != 0 )
+ pmu->pmu_flags |= PMU_SAMPLE_USER;
+ hvm_get_segment_register(sampled, x86_seg_ss, &seg);
+ r->ss = seg.sel;
+ }
+
+ send_guest_vcpu_virq(v, VIRQ_XENPMU);
+}
+
+int pmu_nmi_interrupt(const struct cpu_user_regs *regs, int cpu)
+{
+ return vpmu_do_interrupt(regs);
+}
+
static int pvpmu_init(struct domain *d, xen_pmu_params_t *params)
{
struct vcpu *v;
struct page_info *page;
uint64_t gfn = params->val;
+ static bool_t __read_mostly pvpmu_init_done;
+ static DEFINE_SPINLOCK(init_lock);
if ( (params->vcpu >= d->max_vcpus) || (d->vcpu == NULL) ||
(d->vcpu[params->vcpu] == NULL) )
@@ -479,6 +590,27 @@ static int pvpmu_init(struct domain *d, xen_pmu_params_t *params)
return -EINVAL;
}
+ spin_lock(&init_lock);
+
+ if ( !pvpmu_init_done )
+ {
+ if ( reserve_lapic_nmi() != 0 )
+ {
+ spin_unlock(&init_lock);
+ printk(XENLOG_G_ERR "Failed to reserve PMU NMI\n");
+ put_page(page);
+ return -EBUSY;
+ }
+
+ set_nmi_callback(pmu_nmi_interrupt);
+
+ open_softirq(PMU_SOFTIRQ, pmu_softnmi);
+
+ pvpmu_init_done = 1;
+ }
+
+ spin_unlock(&init_lock);
+
vpmu_initialise(v);
return 0;
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 3efba21..faeeaf6 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -42,7 +42,7 @@ struct arch_vpmu_ops {
int (*do_wrmsr)(unsigned int msr, uint64_t msr_content,
uint64_t supported);
int (*do_rdmsr)(unsigned int msr, uint64_t *msr_content);
- int (*do_interrupt)(struct cpu_user_regs *regs);
+ int (*do_interrupt)(const struct cpu_user_regs *regs);
void (*do_cpuid)(unsigned int input,
unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx);
@@ -98,7 +98,7 @@ static inline bool_t vpmu_are_all_set(const struct vpmu_struct *vpmu,
void vpmu_lvtpc_update(uint32_t val);
int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
uint64_t supported, bool_t is_write);
-void vpmu_do_interrupt(struct cpu_user_regs *regs);
+int vpmu_do_interrupt(const struct cpu_user_regs *regs);
void vpmu_do_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx);
void vpmu_initialise(struct vcpu *v);
diff --git a/xen/include/asm-x86/softirq.h b/xen/include/asm-x86/softirq.h
index 7225dea..ef24056 100644
--- a/xen/include/asm-x86/softirq.h
+++ b/xen/include/asm-x86/softirq.h
@@ -7,7 +7,8 @@
#define MACHINE_CHECK_SOFTIRQ (NR_COMMON_SOFTIRQS + 3)
#define PCI_SERR_SOFTIRQ (NR_COMMON_SOFTIRQS + 4)
-#define NR_ARCH_SOFTIRQS 5
+#define PMU_SOFTIRQ (NR_COMMON_SOFTIRQS + 5)
+#define NR_ARCH_SOFTIRQS 6
bool_t arch_skip_send_event_check(unsigned int cpu);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (19 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
@ 2014-10-17 21:18 ` Boris Ostrovsky
2014-10-28 10:52 ` Jan Beulich
2014-10-27 7:38 ` [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Dietmar Hahn
21 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-17 21:18 UTC (permalink / raw)
To: JBeulich, kevin.tian, suravee.suthikulpanit,
Aravind.Gopalakrishnan, dietmar.hahn, dgdegra, konrad.wilk
Cc: keir, andrew.cooper3, tim, xen-devel, jun.nakajima, boris.ostrovsky
Since PMU is now not HVM specific we can move VPMU-related files up from
arch/x86/hvm/ directory.
Specifically:
arch/x86/hvm/vpmu.c -> arch/x86/cpu/vpmu.c
arch/x86/hvm/svm/vpmu.c -> arch/x86/cpu/vpmu_amd.c
arch/x86/hvm/vmx/vpmu_core2.c -> arch/x86/cpu/vpmu_intel.c
include/asm-x86/hvm/vpmu.h -> include/asm-x86/vpmu.h
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/{hvm => cpu}/vpmu.c | 2 +-
xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} | 2 +-
xen/arch/x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} | 2 +-
xen/arch/x86/hvm/Makefile | 1 -
xen/arch/x86/hvm/svm/Makefile | 1 -
xen/arch/x86/hvm/vlapic.c | 2 +-
xen/arch/x86/hvm/vmx/Makefile | 1 -
xen/arch/x86/oprofile/op_model_ppro.c | 2 +-
xen/arch/x86/traps.c | 2 +-
xen/include/asm-x86/hvm/vmx/vmcs.h | 2 +-
xen/include/asm-x86/{hvm => }/vpmu.h | 0
12 files changed, 8 insertions(+), 10 deletions(-)
rename xen/arch/x86/{hvm => cpu}/vpmu.c (99%)
rename xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} (99%)
rename xen/arch/x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} (99%)
rename xen/include/asm-x86/{hvm => }/vpmu.h (100%)
diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index d73d93a..74f23ae 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -7,3 +7,4 @@ obj-y += common.o
obj-y += intel.o
obj-y += intel_cacheinfo.o
obj-y += mwait-idle.o
+obj-y += vpmu.o vpmu_amd.o vpmu_intel.o
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/cpu/vpmu.c
similarity index 99%
rename from xen/arch/x86/hvm/vpmu.c
rename to xen/arch/x86/cpu/vpmu.c
index 4f443f2..f2b422a 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -27,10 +27,10 @@
#include <asm/types.h>
#include <asm/msr.h>
#include <asm/p2m.h>
+#include <asm/vpmu.h>
#include <asm/hvm/support.h>
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/vmx/vmcs.h>
-#include <asm/hvm/vpmu.h>
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/cpu/vpmu_amd.c
similarity index 99%
rename from xen/arch/x86/hvm/svm/vpmu.c
rename to xen/arch/x86/cpu/vpmu_amd.c
index 547fc30..9c1e2a9 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -28,8 +28,8 @@
#include <xen/sched.h>
#include <xen/irq.h>
#include <asm/apic.h>
+#include <asm/vpmu.h>
#include <asm/hvm/vlapic.h>
-#include <asm/hvm/vpmu.h>
#include <public/pmu.h>
#define MSR_F10H_EVNTSEL_GO_SHIFT 40
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/cpu/vpmu_intel.c
similarity index 99%
rename from xen/arch/x86/hvm/vmx/vpmu_core2.c
rename to xen/arch/x86/cpu/vpmu_intel.c
index 5607ec9..7d0574d 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -30,6 +30,7 @@
#include <asm/traps.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
+#include <asm/vpmu.h>
#include <asm/hvm/support.h>
#include <asm/hvm/vlapic.h>
#include <asm/hvm/vmx/vmx.h>
@@ -37,7 +38,6 @@
#include <public/sched.h>
#include <public/hvm/save.h>
#include <public/pmu.h>
-#include <asm/hvm/vpmu.h>
/*
* See Intel SDM Vol 2a Instruction Set Reference chapter 3 for CPUID
diff --git a/xen/arch/x86/hvm/Makefile b/xen/arch/x86/hvm/Makefile
index eea5555..742b83b 100644
--- a/xen/arch/x86/hvm/Makefile
+++ b/xen/arch/x86/hvm/Makefile
@@ -22,4 +22,3 @@ obj-y += vlapic.o
obj-y += vmsi.o
obj-y += vpic.o
obj-y += vpt.o
-obj-y += vpmu.o
\ No newline at end of file
diff --git a/xen/arch/x86/hvm/svm/Makefile b/xen/arch/x86/hvm/svm/Makefile
index a10a55e..760d295 100644
--- a/xen/arch/x86/hvm/svm/Makefile
+++ b/xen/arch/x86/hvm/svm/Makefile
@@ -6,4 +6,3 @@ obj-y += nestedsvm.o
obj-y += svm.o
obj-y += svmdebug.o
obj-y += vmcb.o
-obj-y += vpmu.o
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index c4ae505..c676e78 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -38,7 +38,7 @@
#include <asm/hvm/support.h>
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/nestedhvm.h>
-#include <asm/hvm/vpmu.h>
+#include <asm/vpmu.h>
#include <public/hvm/ioreq.h>
#include <public/hvm/params.h>
diff --git a/xen/arch/x86/hvm/vmx/Makefile b/xen/arch/x86/hvm/vmx/Makefile
index 373b3d9..04a29ce 100644
--- a/xen/arch/x86/hvm/vmx/Makefile
+++ b/xen/arch/x86/hvm/vmx/Makefile
@@ -3,5 +3,4 @@ obj-y += intr.o
obj-y += realmode.o
obj-y += vmcs.o
obj-y += vmx.o
-obj-y += vpmu_core2.o
obj-y += vvmx.o
diff --git a/xen/arch/x86/oprofile/op_model_ppro.c b/xen/arch/x86/oprofile/op_model_ppro.c
index ca429a1..89649d0 100644
--- a/xen/arch/x86/oprofile/op_model_ppro.c
+++ b/xen/arch/x86/oprofile/op_model_ppro.c
@@ -19,7 +19,7 @@
#include <asm/processor.h>
#include <asm/regs.h>
#include <asm/current.h>
-#include <asm/hvm/vpmu.h>
+#include <asm/vpmu.h>
#include "op_x86_model.h"
#include "op_counter.h"
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 663b44f..33f0fc5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -72,7 +72,7 @@
#include <asm/apic.h>
#include <asm/mc146818rtc.h>
#include <asm/hpet.h>
-#include <asm/hvm/vpmu.h>
+#include <asm/vpmu.h>
#include <public/arch-x86/cpuid.h>
#include <xsm/xsm.h>
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 949884b..dcf2d31 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -20,7 +20,7 @@
#define __ASM_X86_HVM_VMX_VMCS_H__
#include <asm/hvm/io.h>
-#include <asm/hvm/vpmu.h>
+#include <asm/vpmu.h>
#include <irq_vectors.h>
extern void vmcs_dump_vcpu(struct vcpu *v);
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/vpmu.h
similarity index 100%
rename from xen/include/asm-x86/hvm/vpmu.h
rename to xen/include/asm-x86/vpmu.h
--
1.8.1.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
@ 2014-10-24 16:00 ` Jan Beulich
0 siblings, 0 replies; 41+ messages in thread
From: Jan Beulich @ 2014-10-24 16:00 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:17, <boris.ostrovsky@oracle.com> wrote:
> @@ -222,6 +215,12 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
> }
> }
>
> +static inline int msraddr_to_bitpos(int x)
> +{
> + ASSERT(x == (x & 0x1fff));
> + return x;
> +}
Now this is interesting: I indeed asked you to fix this while you move
it, but (a) should such a fix be mentioned in the commit message and
(b) even more so when you outright drop support for the other half
of the possible MSR ranges.
> @@ -367,12 +373,20 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
> goto out_err;
> vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
>
> - core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
> - (arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
> - if ( !core2_vpmu_cxt )
> + core2_vpmu_cxt = xzalloc_bytes(sizeof(*core2_vpmu_cxt) +
Okay, you switched this one as I had asked for. But you don't
really expect that I repeat this comment in various places, do you?
I.e. I would have expected you to fix this uniformly, not just here.
> + sizeof(uint64_t) * fixed_pmc_cnt +
> + sizeof(struct xen_pmu_cntr_pair) *
> + arch_pmc_cnt);
> + p = xzalloc(uint64_t);
> + if ( !core2_vpmu_cxt || !p )
> goto out_err;
>
> - vpmu->context = (void *)core2_vpmu_cxt;
> + core2_vpmu_cxt->fixed_counters = sizeof(struct xen_pmu_intel_ctxt);
I.e. here as well as in the AMD code as well as wherever else.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
` (20 preceding siblings ...)
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
@ 2014-10-27 7:38 ` Dietmar Hahn
2014-10-27 13:47 ` Boris Ostrovsky
21 siblings, 1 reply; 41+ messages in thread
From: Dietmar Hahn @ 2014-10-27 7:38 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, keir, JBeulich, jun.nakajima, andrew.cooper3, tim,
Aravind.Gopalakrishnan, suravee.suthikulpanit, dgdegra,
Boris Ostrovsky
Hi Boris,
Am Freitag 17 Oktober 2014, 17:17:48 schrieb Boris Ostrovsky:
> Version 14 of PV(H) PMU patches.
>
> Changes in v14:
>
> * Moved struct xen_pmu_regs to pmu.h
> * Moved CHECK_pmu_* to an earlier patch (when structures are first introduced)
> * Added PMU_SAMPLE_REAL flag to indicate whether the sample was taken in real mode
> * Simplified slightly setting rules for xenpmu_data flags
> * Rewrote vpmu_force_context_switch() to again use continuations. (Returning EAGAIN
> to user would mean that VPMU mode may get into inconsistent state (across processors)
> and dealing with that is more compicated than I'd like).
> * Fixed msraddr_to_bitpos() and converted it into an inline
> * Replaced address range check in vmpu_do_interrupt() with guest_mode()
> * No error returns from __initcall
> * Rebased on top of recent VPMU changes
> * Various cleanups
I did some tests with the Intel part and all went fine, so
Tested-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Btw. you use different names for the same structure in the linux kernel driver
part "struct xen_arch_pmu" and in the xen part "struct xen_pmu_arch". This is a
little bit confusing when searching through the code. So when possible ... ;-)
Many thanks!
Dietmar.
>
> Changes in v13:
>
> * Rearranged data in xenpf_symdata to eliminate a hole (no change in
> structure size)
> * Removed unnecessary zeroing of last character in name string during
> symbol read hypercall
> * Updated comment in access_vectors for pmu_use operation
> * Compute AMD MSR bank size at runtime
> * Moved a couple of BUILD_BUG_ON later, to when the structures they are
> checking are first used
> * Added ss and eflags to xen_pmu_registers structure
> * vpmu_force_context_switch() uses per-cpu tasklet pointers.
> * Moved most of arch-specific VPMU initialization code into an __initcall()
> to avoid re-calculating/re-checking things more than once (new patch, #12)
> * Replaced is_*_domain() with is_*_vcpu()
> * choose_hwdom_vcpu() will now assume that hardware_domain->vcpu[idx]
> is always there (callers will still verify whether or not that's true)
> * Fixed a couple of sampled vs. sampling tests in vpmu_do_interrupt()
> * Pass CS to the guest unchanged, add pmu_flags's flag to indicate whether the
> sample was for a user or kernel space. Move pmu_flags from xen_pmu_data into
> xen_pmu_arch
> * Removed local msr_content variable from vpmu_do_wrmsr()
> * Re-arranged code in parse_vpmu_param()
> * Made vpmu_interrupt_type checks test for value, not individual bits
> * Moved PMU_SOFTIRQ definition into arch-specific header
> * Moved vpmu*.c files into xen/arch/x86/cpu/ instead of xen/arch/x86/
> * For hypervisor samples, report DOMID_XEN to the guest
> * Changed logic to select which registers to report to the guest (include RIP
> check to see whether we are in the hypervisor)
>
> Changes in v12:
>
> * Added XSM support
> * Made a valifity check before writing MSR_CORE_PERF_GLOBAL_OVF_CTRL
> * Updated documentation for 'vpmu=nmi' option
> * Added more text to a bunch of commit messages (per Konrad's request)
>
> Changes in v11:
>
> * Replaced cpu_user_regs with new xen_pmu_regs (IP, SP, CS) in xen_pmu_arch.
> - as part of this re-work noticed that CS registers were set in later patch then
> needed. Moved those changes to appropriate place
> * Added new VPMU mode (XENPMU_MODE_HV). Now XENPMU_MODE_SELF will only provide dom0
> with its own samples only (i.e. no hypervisor data) and XENPMU_MODE_HV will be what
> XENPMU_MODE_SELF used to be.
> * Kept vmx_add_guest_msr()/vmx_add_host_load_msr() as wrappers around vmx_add_msr()
> * Cleaned up VPMU context switch macros (moved 'if(prev!=next)' back to context_switch())
> * Dropped hypercall continuation from vpmu_force_context_switch() and replaced it with
> -EAGAIN error if hypercall_preempt_check() is true after 2ms.
> * Kept vpmu_do_rdmsr()/vpmu_do_wrmsr as wrapperd for vpmu_do_msr()
> * Move context switching patch (#13) earlier in the series (for proper bisection support)
> * Various comment updates and cleanups
> * Dropped a bunch of Reviewed-by and all Tested-by tags
>
> Changes in v10:
>
> * Swapped address and name fields of xenpf_symdata (to make it smaller on 32-bit)
> * Dropped vmx_rm_guest_msr() as it requires refcountig which makes code more complicated.
> * Cleaned up vlapic_reg_write()
> * Call vpmu_destroy() for both HVM and PVH VCPUs
> * Verify that (xen_pmu_data+PMU register bank) fit into a page
> * Return error codes from arch-specific VPMU init code
> * Moved VPMU-related context switch logic into inlines
> * vpmu_force_context_switch() changes:
> o Avoid greater than page-sized allocations
> o Prevent another VCPU from starting VPMU sync while the first sync is in progress
> * Avoid stack leak in do_xenpmu_op()
> * Checked validity of Intel VPMU MSR values before they are committed
> * Fixed MSR handling in traps.c (avoid potential accesses to Intel MSRs on AMD)
> * Fixed VCPU selection in interrupt handler for 32-bit dom0 (sampled => sampling)
> * Clarified commit messages (patches 2, 13, 18)
> * Various cleanups
>
> Changes in v9:
>
> * Restore VPMU context after context_saved() is called in
> context_switch(). This is needed because vpmu_load() may end up
> calling vmx_vmcs_try_enter()->vcpu_pause() and that needs is_running
> to be correctly set/cleared. (patch 18, dropped review acks)
> * Added patch 2 to properly manage VPMU_CONTEXT_LOADED
> * Addressed most of Jan's comments.
> o Keep track of time in vpmu_force_context_switch() to properly break
> out of a loop when using hypercall continuations
> o Fixed logic in calling vpmu_do_msr() in emulate_privileged_op()
> o Cleaned up vpmu_interrupt() wrt vcpu variable names to (hopefully)
> make it more clear which vcpu we are using
> o Cleaned up vpmu_do_wrmsr()
> o Did *not* replace sizeof(uint64_t) with sizeof(variable) in
> amd_vpmu_initialise(): throughout the code registers are declared as
> uint64_t and if we are to add a new type (e.g. reg_t) this should be
> done in a separate patch, unrelated to this series.
> o Various more minor cleanups and code style fixes
>
> Changes in v8:
>
> * Cleaned up a bit definitions of struct xenpf_symdata and xen_pmu_params
> * Added compat checks for vpmu structures
> * Converted vpmu flag manipulation macros to inline routines
> * Reimplemented vpmu_unload_all() to avoid long loops
> * Reworked PMU fault generation and handling (new patch #12)
> * Added checks for domain->vcpu[] non-NULLness
> * Added more comments, renamed some routines and macros, code style cleanup
>
>
> Changes in v7:
>
> * When reading hypervisor symbols make the caller pass buffer length
> (as opposed to having this length be part of the API). Make the
> hypervisor buffer static, make xensyms_read() return zero-length
> string on end-of-symbols. Make 'type' field of xenpf_symdata a char,
> drop compat_pf_symdata definition.
> * Spread PVH support across patches as opposed to lumping it into a
> separate patch
> * Rename vpmu_is_set_all() to vpmu_are_all_set()
> * Split VPMU cleanup patch in two
> * Use memmove when copying VMX guest and host MSRs
> * Make padding of xen_arch_pmu's context union a constand that does not
> depend on arch context size.
> * Set interface version to 0.1
> * Check pointer validity in pvpmu_init/destroy()
> * Fixed crash in core2_vpmu_dump()
> * Fixed crash in vmx_add_msr()
> * Break handling of Intel and AMD MSRs in traps.c into separate cases
> * Pass full CS selector to guests
> * Add lock in pvpmu init code to prevent potential race
>
>
> Changes in v6:
>
> * Two new patches:
> o Merge VMX MSR add/remove routines in vmcs.c (patch 5)
> o Merge VPMU read/write MSR routines in vpmu.c (patch 14)
> * Check for pending NMI softirq after saving VPMU context to prevent a newly-scheduled
> guest from overwriting sampled_vcpu written by de-scheduled VPCU.
> * Keep track of enabled counters on Intel. This was removed in earlier patches and
> was a mistake. As result of this change struct vpmu will have a pointer to private
> context data (i.e. data that is not exposed to a PV(H) guest). Use this private pointer
> on SVM as well for storing MSR bitmap status (it was unnecessarily exposed to PV guests
> earlier).
> Dropped Reviewed-by: and Tested-by: tags from patch 4 since it needs to be reviewed
> agan (core2_vpmu_do_wrmsr() routine, mostly)
> * Replaced references to dom0 with hardware_domain (and is_control_domain with
> is_hardware_domain for consistency)
> * Prevent non-privileged domains from reading PMU MSRs in VPMU_PRIV_MODE
> * Reverted unnecessary changes in vpmu_initialise()'s switch statement
> * Fixed comment in vpmu_do_interrupt
>
>
> Changes in v5:
>
> * Dropped patch number 2 ("Stop AMD counters when called from vpmu_save_force()")
> as no longer needed
> * Added patch number 2 that marks context as loaded before PMU registers are
> loaded. This prevents situation where a PMU interrupt may occur while context
> is still viewed as not loaded. (This is really a bug fix for exsiting VPMU
> code)
> * Renamed xenpmu.h files to pmu.h
> * More careful use of is_pv_domain(), is_hvm_domain(, is_pvh_domain and
> has_hvm_container_domain(). Also explicitly disabled support for PVH until
> patch 16 to make distinction between usage of the above macros more clear.
> * Added support for disabling VPMU support during runtime.
> * Disable VPMUs for non-privileged domains when switching to privileged
> profiling mode
> * Added ARM stub for xen_arch_pmu_t
> * Separated vpmu_mode from vpmu_features
> * Moved CS register query to make sure we use appropriate query mechanism for
> various guest types.
> * LVTPC is now set from value in shared area, not copied from dom0
> * Various code and comments cleanup as suggested by Jan.
>
> Changes in v4:
>
> * Added support for PVH guests:
> o changes in pvpmu_init() to accommodate both PV and PVH guests, still in patch 10
> o more careful use of is_hvm_domain
> o Additional patch (16)
> * Moved HVM interrupt handling out of vpmu_do_interrupt() for NMI-safe handling
> * Fixed dom0's VCPU selection in privileged mode
> * Added a cast in register copy for 32-bit PV guests cpu_user_regs_t in vpmu_do_interrupt.
> (don't want to expose compat_cpu_user_regs in a public header)
> * Renamed public structures by prefixing them with "xen_"
> * Added an entry for xenpf_symdata in xlat.lst
> * Fixed pv_cpuid check for vpmu-specific cpuid adjustments
> * Varios code style fixes
> * Eliminated anonymous unions
> * Added more verbiage to NMI patch description
>
>
> Changes in v3:
>
> * Moved PMU MSR banks out from architectural context data structures to allow
> for future expansion without protocol changes
> * PMU interrupts can be either NMIs or regular vector interrupts (the latter
> is the default)
> * Context is now marked as PMU_CACHED by the hypervisor code to avoid certain
> race conditions with the guest
> * Fixed races with PV guest in MSR access handlers
> * More Intel VPMU cleanup
> * Moved NMI-unsafe code from NMI handler
> * Dropped changes to vcpu->is_running
> * Added LVTPC apic handling (cached for PV guests)
> * Separated privileged profiling mode into a standalone patch
> * Separated NMI handling into a standalone patch
>
>
> Changes in v2:
>
> * Xen symbols are exported as data structure (as opoosed to a set of formatted
> strings in v1). Even though one symbol per hypercall is returned performance
> appears to be acceptable: reading whole file from dom0 userland takes on average
> about twice as long as reading /proc/kallsyms
> * More cleanup of Intel VPMU code to simplify publicly exported structures
> * There is an architecture-independent and x86-specific public include files (ARM
> has a stub)
> * General cleanup of public include files to make them more presentable (and
> to make auto doc generation better)
> * Setting of vcpu->is_running is now done on ARM in schedule_tail as well (making
> changes to common/schedule.c architecture-independent). Note that this is not
> tested since I don't have access to ARM hardware.
> * PCPU ID of interrupted processor is now passed to PV guest
>
>
> The following patch series adds PMU support in Xen for PV(H)
> guests. There is a companion patchset for Linux kernel. In addition,
> another set of changes will be provided (later) for userland perf
> code.
>
> This version has following limitations:
> * For accurate profiling of dom0/Xen dom0 VCPUs should be pinned.
> * Hypervisor code is only profiled on processors that have running dom0 VCPUs
> on them.
> * No backtrace support.
>
> A few notes that may help reviewing:
>
> * A shared data structure (xenpmu_data_t) between each PV VPCU and hypervisor
> CPU is used for passing registers' values as well as PMU state at the time of
> PMU interrupt.
> * PMU interrupts are taken by hypervisor either as NMIs or regular vector
> interrupts for both HVM and PV(H). The interrupts are sent as NMIs to HVM guests
> and as virtual interrupts to PV(H) guests
> * PV guest's interrupt handler does not read/write PMU MSRs directly. Instead, it
> accesses xenpmu_data_t and flushes it to HW it before returning.
> * PMU mode is controlled at runtime via /sys/hypervisor/pmu/pmu/{pmu_mode,pmu_flags}
> in addition to 'vpmu' boot option (which is preserved for back compatibility).
> The following modes are provided:
> * disable: VPMU is off
> * enable: VPMU is on. Guests can profile themselves, dom0 profiles itself and Xen
> * priv_enable: dom0 only profiling. dom0 collects samples for everyone. Sampling
> in guests is suspended.
> * /proc/xen/xensyms file exports hypervisor's symbols to dom0 (similar to
> /proc/kallsyms)
> * VPMU infrastructure is now used for HVM, PV and PVH and therefore has been moved
> up from hvm subtree
>
>
> Boris Ostrovsky (21):
> common/symbols: Export hypervisor symbols to privileged guest
> x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force()
> x86/VPMU: Set MSR bitmaps only for HVM/PVH guests
> x86/VPMU: Make vpmu macros a bit more efficient
> intel/VPMU: Clean up Intel VPMU code
> vmx: Merge MSR management routines
> x86/VPMU: Handle APIC_LVTPC accesses
> intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero
> x86/VPMU: Add public xenpmu.h
> x86/VPMU: Make vpmu not HVM-specific
> x86/VPMU: Interface for setting PMU mode and flags
> x86/VPMU: Initialize AMD and Intel VPMU with __initcall
> x86/VPMU: Initialize PMU for PV(H) guests
> x86/VPMU: Save VPMU state for PV guests during context switch
> x86/VPMU: When handling MSR accesses, leave fault injection to callers
> x86/VPMU: Add support for PMU register handling on PV guests
> x86/VPMU: Handle PMU interrupts for PV guests
> x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr
> x86/VPMU: Add privileged PMU mode
> x86/VPMU: NMI-based VPMU support
> x86/VPMU: Move VPMU files up from hvm/ directory
>
> docs/misc/xen-command-line.markdown | 8 +-
> tools/flask/policy/policy/modules/xen/xen.te | 7 +
> xen/arch/x86/cpu/Makefile | 1 +
> xen/arch/x86/cpu/vpmu.c | 881 +++++++++++++++++++++
> xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} | 248 +++---
> .../x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} | 784 +++++++++---------
> xen/arch/x86/domain.c | 23 +-
> xen/arch/x86/hvm/Makefile | 1 -
> xen/arch/x86/hvm/hvm.c | 3 +-
> xen/arch/x86/hvm/svm/Makefile | 1 -
> xen/arch/x86/hvm/svm/svm.c | 10 +-
> xen/arch/x86/hvm/vlapic.c | 3 +
> xen/arch/x86/hvm/vmx/Makefile | 1 -
> xen/arch/x86/hvm/vmx/vmcs.c | 84 +-
> xen/arch/x86/hvm/vmx/vmx.c | 28 +-
> xen/arch/x86/hvm/vpmu.c | 263 ------
> xen/arch/x86/oprofile/op_model_ppro.c | 8 +-
> xen/arch/x86/platform_hypercall.c | 28 +
> xen/arch/x86/traps.c | 62 +-
> xen/arch/x86/x86_64/compat/entry.S | 4 +
> xen/arch/x86/x86_64/entry.S | 4 +
> xen/common/event_channel.c | 1 +
> xen/common/symbols.c | 54 ++
> xen/include/Makefile | 2 +
> xen/include/asm-x86/domain.h | 2 +
> xen/include/asm-x86/hvm/vcpu.h | 3 -
> xen/include/asm-x86/hvm/vmx/vmcs.h | 18 +-
> xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 51 --
> xen/include/asm-x86/softirq.h | 3 +-
> xen/include/asm-x86/{hvm => }/vpmu.h | 93 ++-
> xen/include/public/arch-arm.h | 3 +
> xen/include/public/arch-x86/pmu.h | 95 +++
> xen/include/public/platform.h | 19 +
> xen/include/public/pmu.h | 90 +++
> xen/include/public/xen.h | 2 +
> xen/include/xen/hypercall.h | 4 +
> xen/include/xen/symbols.h | 3 +
> xen/include/xlat.lst | 6 +
> xen/include/xsm/dummy.h | 20 +
> xen/include/xsm/xsm.h | 6 +
> xen/xsm/dummy.c | 1 +
> xen/xsm/flask/hooks.c | 28 +
> xen/xsm/flask/policy/access_vectors | 6 +
> 43 files changed, 2028 insertions(+), 934 deletions(-)
> create mode 100644 xen/arch/x86/cpu/vpmu.c
> rename xen/arch/x86/{hvm/svm/vpmu.c => cpu/vpmu_amd.c} (68%)
> rename xen/arch/x86/{hvm/vmx/vpmu_core2.c => cpu/vpmu_intel.c} (58%)
> delete mode 100644 xen/arch/x86/hvm/vpmu.c
> delete mode 100644 xen/include/asm-x86/hvm/vmx/vpmu_core2.h
> rename xen/include/asm-x86/{hvm => }/vpmu.h (55%)
> create mode 100644 xen/include/public/arch-x86/pmu.h
> create mode 100644 xen/include/public/pmu.h
>
>
--
Company details: http://ts.fujitsu.com/imprint.html
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support
2014-10-27 7:38 ` [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Dietmar Hahn
@ 2014-10-27 13:47 ` Boris Ostrovsky
0 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-27 13:47 UTC (permalink / raw)
To: Dietmar Hahn, xen-devel
Cc: kevin.tian, keir, JBeulich, jun.nakajima, andrew.cooper3, tim,
Aravind.Gopalakrishnan, suravee.suthikulpanit, dgdegra
On 10/27/2014 03:38 AM, Dietmar Hahn wrote:
> Hi Boris,
>
> Am Freitag 17 Oktober 2014, 17:17:48 schrieb Boris Ostrovsky:
>> Version 14 of PV(H) PMU patches.
>>
>> Changes in v14:
>>
>> * Moved struct xen_pmu_regs to pmu.h
>> * Moved CHECK_pmu_* to an earlier patch (when structures are first introduced)
>> * Added PMU_SAMPLE_REAL flag to indicate whether the sample was taken in real mode
>> * Simplified slightly setting rules for xenpmu_data flags
>> * Rewrote vpmu_force_context_switch() to again use continuations. (Returning EAGAIN
>> to user would mean that VPMU mode may get into inconsistent state (across processors)
>> and dealing with that is more compicated than I'd like).
>> * Fixed msraddr_to_bitpos() and converted it into an inline
>> * Replaced address range check in vmpu_do_interrupt() with guest_mode()
>> * No error returns from __initcall
>> * Rebased on top of recent VPMU changes
>> * Various cleanups
> I did some tests with the Intel part and all went fine, so
>
> Tested-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Excellent, thanks!
> Btw. you use different names for the same structure in the linux kernel driver
> part "struct xen_arch_pmu" and in the xen part "struct xen_pmu_arch". This is a
> little bit confusing when searching through the code. So when possible ... ;-)
> Many thanks!
Linux driver had quite a few changes since I posted it last time (mostly
due to requested API changes on Xen side) so the header files will need
to be copied anew anyway. And structure names will be updated at that time.
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
@ 2014-10-27 16:24 ` Jan Beulich
2014-10-27 18:52 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-27 16:24 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:17, <boris.ostrovsky@oracle.com> wrote:
> --- a/xen/arch/x86/hvm/vpmu.c
> +++ b/xen/arch/x86/hvm/vpmu.c
> @@ -21,6 +21,8 @@
> #include <xen/config.h>
> #include <xen/sched.h>
> #include <xen/xenoprof.h>
> +#include <xen/event.h>
> +#include <xen/guest_access.h>
> #include <asm/regs.h>
> #include <asm/types.h>
> #include <asm/msr.h>
> @@ -32,8 +34,11 @@
> #include <asm/hvm/svm/vmcb.h>
> #include <asm/apic.h>
> #include <public/pmu.h>
> +#include <xen/tasklet.h>
> +#include <xsm/xsm.h>
Please put the xen/ one alongside the other xen/ ones.
> +static int vpmu_force_context_switch(void)
> +{
> + unsigned i, numcpus, mycpu;
> + static s_time_t start;
> + struct vcpu *curr_vcpu = current;
> + static DEFINE_PER_CPU(struct tasklet *, sync_task);
> + int ret = 0;
> +
> + numcpus = num_online_cpus();
I think you'd be better off counting these as you schedule the tasklets.
> + mycpu = smp_processor_id();
> +
> + if ( sync_vcpu != NULL ) /* if set, we may be in hypercall continuation */
> + {
> + if (sync_vcpu != curr_vcpu )
Coding style.
> + /* We are not the original caller */
> + return -EAGAIN;
That would seem to be the wrong return value then. Also, the HAP
side fix for XSA-97 taught us that identifying a caller by vCPU is
problematic - in the course of the retries the kernel's scheduler
may move the calling process to a different vCPU, yet it's still the
legitimate original caller.
> + goto cont_wait;
> + }
> +
> + for_each_online_cpu ( i )
> + {
> + if ( i == mycpu )
> + continue;
> +
> + per_cpu(sync_task, i) = xmalloc(struct tasklet);
> + if ( per_cpu(sync_task, i) == NULL )
> + {
> + printk(XENLOG_WARNING "vpmu_force_context_switch: out of memory\n");
> + ret = -ENOMEM;
> + goto out;
> + }
> + tasklet_init(per_cpu(sync_task, i), vpmu_sched_checkin, 0);
> + }
> +
> + /* First count is for self */
> + atomic_set(&vpmu_sched_counter, 1);
> +
> + for_each_online_cpu ( i )
> + {
> + if ( i != mycpu )
> + tasklet_schedule_on_cpu(per_cpu(sync_task, i), i);
> + }
> +
> + vpmu_save(current);
> +
> + sync_vcpu = curr_vcpu;
> + start = NOW();
> +
> + cont_wait:
> + /*
> + * Note that we may fail here if a CPU is hot-plugged while we are
> + * waiting. We will then time out.
> + */
And I continue to miss the handling of the hot-unplug case (or at the
very least a note on this being unimplemented [and going to crash],
to at least clarify matters to the curious reader).
> + while ( atomic_read(&vpmu_sched_counter) != numcpus )
> + {
> + s_time_t now;
> +
> + cpu_relax();
> +
> + now = NOW();
> +
> + /* Give up after (arbitrarily chosen) 5 seconds */
> + if ( now > start + SECONDS(5) )
> + {
> + printk(XENLOG_WARNING
> + "vpmu_force_context_switch: failed to sync\n");
> + ret = -EBUSY;
> + break;
> + }
> +
> + if ( hypercall_preempt_check() )
> + return hypercall_create_continuation(
> + __HYPERVISOR_xenpmu_op, "i", XENPMU_mode_set);
Did you test this code path? I don't see how with the missing second
hypercall argument the continuation could reliably succeed.
> + case XENPMU_mode_set:
> + {
> + uint32_t current_mode;
> +
> + if ( copy_from_guest(&pmu_params, arg, 1) )
> + return -EFAULT;
> +
> + if ( pmu_params.val & ~(XENPMU_MODE_SELF | XENPMU_MODE_HV) )
> + return -EINVAL;
> +
> + /* 32-bit dom0 can only sample itself */
> + if ( is_pv_32bit_vcpu(current) && (pmu_params.val & XENPMU_MODE_HV) )
> + return -EINVAL;
> +
> + /*
> + * Return error is someone else is in the middle of changing mode ---
> + * this is most likely indication of two system administrators
> + * working against each other.
> + * If continuation from vpmu_force_context_switch() is still pending
> + * we can proceed here without getting the lock:
> + * vpmu_force_context_switch() will check whether we are the vcpu that
> + * initialted it.
> + */
> + if ( (sync_vcpu == NULL) && !spin_trylock(&xenpmu_mode_lock) )
> + return -EAGAIN;
Continuing without holding the lock when sync_vcpu != NULL is
bogus: What if sync_vcpu got cleared by the time
vpmu_force_context_switch() gets around to look at it?
> +
> + current_mode = vpmu_mode;
> + vpmu_mode = pmu_params.val;
> +
> + if ( vpmu_mode == XENPMU_MODE_OFF )
> + {
> + /*
> + * Make sure all (non-dom0) VCPUs have unloaded their VPMUs. This
> + * can be achieved by having all physical processors go through
> + * context_switch().
> + */
> + ret = vpmu_force_context_switch();
> + if ( ret )
> + vpmu_mode = current_mode;
> + }
> +
> + if ( spin_is_locked(&xenpmu_mode_lock) )
> + spin_unlock(&xenpmu_mode_lock);
spin_is_locked() only tells you that _someone_ holds the lock - that
isn't necessarily the current vCPU.
> + break;
> + }
> +
> + case XENPMU_mode_get:
> + /* See whether we are in the middle of mode change */
Please make your comments conform to ./CODING_STYLE.
> + if ( (sync_vcpu != NULL) || !spin_trylock(&xenpmu_mode_lock) )
> + return -EAGAIN;
> +
> + memset(&pmu_params, 0, sizeof(pmu_params));
> + pmu_params.val = vpmu_mode;
> + spin_unlock(&xenpmu_mode_lock);
Is it really meaningful to do this under lock? By the time the caller
gets to see it it's stale anyway.
> @@ -116,5 +109,21 @@ void vpmu_dump(struct vcpu *v);
> extern int acquire_pmu_ownership(int pmu_ownership);
> extern void release_pmu_ownership(int pmu_ownership);
>
> +extern uint64_t vpmu_mode;
> +extern uint64_t vpmu_features;
Any particular reason for these to not be unsigned int?
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
@ 2014-10-27 16:38 ` Jan Beulich
2014-10-27 19:21 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-27 16:38 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -4811,7 +4811,8 @@ static hvm_hypercall_t *const pvh_hypercall64_table[NR_hypercalls] = {
> HYPERCALL(hvm_op),
> HYPERCALL(sysctl),
> HYPERCALL(domctl),
> - [ __HYPERVISOR_arch_1 ] = (hvm_hypercall_t *)paging_domctl_continuation
> + [ __HYPERVISOR_arch_1 ] = (hvm_hypercall_t *)paging_domctl_continuation,
> + HYPERCALL(xenpmu_op)
> };
At least the operations visible in the patch context are all sorted
by hypercall number - please don't break this.
> +static void pvpmu_finish(struct domain *d, xen_pmu_params_t *params)
> +{
> + struct vcpu *v;
> + uint64_t mfn;
> +
> + if ( (params->vcpu >= d->max_vcpus) || (d->vcpu == NULL) ||
> + (d->vcpu[params->vcpu] == NULL) )
> + return;
> +
> + v = d->vcpu[params->vcpu];
> + if ( v != current )
> + vcpu_pause(v);
> +
> + if ( v->arch.vpmu.xenpmu_data )
> + {
> + mfn = domain_page_map_to_mfn(v->arch.vpmu.xenpmu_data);
> + ASSERT(mfn != 0);
> + unmap_domain_page_global(v->arch.vpmu.xenpmu_data);
> + put_page_and_type(mfn_to_page(mfn));
I think you absolutely need to clear v->arch.vpmu.xenpmu_data
here, or else another call will (likely) crash the hypervisor. Even
more, I think this actually needs serialization (and pvpmu_init() as
well), especially with ...
> --- a/xen/include/xsm/dummy.h
> +++ b/xen/include/xsm/dummy.h
> @@ -665,6 +665,9 @@ static XSM_INLINE int xsm_pmu_op (XSM_DEFAULT_ARG struct
> domain *d, int op)
> case XENPMU_feature_set:
> case XENPMU_feature_get:
> return xsm_default_action(XSM_PRIV, d, current->domain);
> + case XENPMU_init:
> + case XENPMU_finish:
> + return xsm_default_action(XSM_HOOK, d, current->domain);
... this being XSM_HOOK rather than XSM_TARGET.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
@ 2014-10-27 16:54 ` Jan Beulich
2014-10-27 19:43 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-27 16:54 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
> --- a/xen/arch/x86/hvm/vpmu.c
> +++ b/xen/arch/x86/hvm/vpmu.c
> @@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
>
> void vpmu_lvtpc_update(uint32_t val)
> {
> - struct vpmu_struct *vpmu = vcpu_vpmu(current);
> + struct vcpu *curr = current;
> + struct vpmu_struct *vpmu = vcpu_vpmu(curr);
>
> vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
> - apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
> +
> + /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending */
> + if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
> + !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
Isn't this the pointer that pvpmu_finish() deallocates (and needs to
clear? If so, there's a race between it being cleared and used. If you
need it in places like this, perhaps you'd be better off never clearing
it and leaving the MFN allocated?
> void vpmu_do_interrupt(struct cpu_user_regs *regs)
> {
> - struct vcpu *v = current;
> - struct vpmu_struct *vpmu = vcpu_vpmu(v);
> + struct vcpu *sampled = current, *sampling;
> + struct vpmu_struct *vpmu;
> +
> + /* dom0 will handle interrupt for special domains (e.g. idle domain) */
> + if ( sampled->domain->domain_id >= DOMID_FIRST_RESERVED )
> + {
> + sampling = choose_hwdom_vcpu();
> + if ( !sampling )
> + return;
> + }
> + else
> + sampling = sampled;
> +
> + vpmu = vcpu_vpmu(sampling);
> + if ( !is_hvm_vcpu(sampling) )
> + {
> + /* PV(H) guest */
> + const struct cpu_user_regs *cur_regs;
> + uint64_t *flags = &vpmu->xenpmu_data->pmu.pmu_flags;
> + uint32_t domid = DOMID_SELF;
> +
> + if ( !vpmu->xenpmu_data )
> + return;
> +
> + if ( *flags & PMU_CACHED )
> + return;
> +
> + if ( is_pvh_vcpu(sampling) &&
> + !vpmu->arch_vpmu_ops->do_interrupt(regs) )
> + return;
> +
> + /* PV guest will be reading PMU MSRs from xenpmu_data */
> + vpmu_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
> + vpmu->arch_vpmu_ops->arch_vpmu_save(sampling);
> + vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
> +
> + *flags = 0;
> +
> + /* Store appropriate registers in xenpmu_data */
> + /* FIXME: 32-bit PVH should go here as well */
> + if ( is_pv_32bit_vcpu(sampling) )
> + {
> + /*
> + * 32-bit dom0 cannot process Xen's addresses (which are 64 bit)
> + * and therefore we treat it the same way as a non-privileged
> + * PV 32-bit domain.
> + */
> + struct compat_pmu_regs *cmp;
> +
> + cur_regs = guest_cpu_user_regs();
> +
> + cmp = (void *)&vpmu->xenpmu_data->pmu.r.regs;
> + cmp->ip = cur_regs->rip;
> + cmp->sp = cur_regs->rsp;
> + cmp->flags = cur_regs->eflags;
> + cmp->ss = cur_regs->ss;
> + cmp->cs = cur_regs->cs;
> + if ( (cmp->cs & 3) != 1 )
> + *flags |= PMU_SAMPLE_USER;
> + }
> + else
> + {
> + struct xen_pmu_regs *r = &vpmu->xenpmu_data->pmu.r.regs;
> +
> + if ( (vpmu_mode & XENPMU_MODE_SELF) )
> + cur_regs = guest_cpu_user_regs();
> + else if ( (regs->rip >= XEN_VIRT_START) &&
> + (regs->rip < XEN_VIRT_END) &&
> + is_hardware_domain(sampling->domain))
I'm pretty sure that already on the previous round I said that using
only RIP for determining whether the sample occurred in hypervisor
context is not enough.
> + {
> + cur_regs = regs;
> + domid = DOMID_XEN;
> + }
> + else
> + cur_regs = guest_cpu_user_regs();
> +
> + r->ip = cur_regs->rip;
> + r->sp = cur_regs->rsp;
> + r->flags = cur_regs->eflags;
> +
> + if ( !has_hvm_container_vcpu(sampled) )
> + {
> + r->ss = cur_regs->ss;
> + r->cs = cur_regs->cs;
> + if ( !(sampled->arch.flags & TF_kernel_mode) )
> + *flags |= PMU_SAMPLE_USER;
> + }
> + else
> + {
> + struct segment_register seg;
> +
> + hvm_get_segment_register(sampled, x86_seg_cs, &seg);
> + r->cs = seg.sel;
> + if ( (r->cs & 3) != 0 )
> + *flags |= PMU_SAMPLE_USER;
So is the VM86 mode case here intentionally being ignored? And is
there a particular reason you look at the selector's RPL instead of
DPL, and CS instead of SS?
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-27 16:24 ` Jan Beulich
@ 2014-10-27 18:52 ` Boris Ostrovsky
2014-10-28 8:29 ` Jan Beulich
0 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-27 18:52 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/27/2014 12:24 PM, Jan Beulich wrote:
>>>> On 17.10.14 at 23:17, <boris.ostrovsky@oracle.com> wrote:
>>
>> +static int vpmu_force_context_switch(void)
>> +{
>> + unsigned i, numcpus, mycpu;
>> + static s_time_t start;
>> + struct vcpu *curr_vcpu = current;
>> + static DEFINE_PER_CPU(struct tasklet *, sync_task);
>> + int ret = 0;
>> +
>> + numcpus = num_online_cpus();
> I think you'd be better off counting these as you schedule the tasklets.
>
>> + mycpu = smp_processor_id();
>> +
>> + if ( sync_vcpu != NULL ) /* if set, we may be in hypercall continuation */
>> + {
>> + if (sync_vcpu != curr_vcpu )
> Coding style.
>
>> + /* We are not the original caller */
>> + return -EAGAIN;
> That would seem to be the wrong return value then. Also, the HAP
> side fix for XSA-97 taught us that identifying a caller by vCPU is
> problematic - in the course of the retries the kernel's scheduler
> may move the calling process to a different vCPU, yet it's still the
> legitimate original caller.
If the process is rescheduled then we will time out operation.
I suppose I can set a bit in the argument's val to mark that particular
argument as pending a continuation completion (I don't think we need to
worry about malicious domain here since this is a privileged operation).
>
>> + goto cont_wait;
>> + }
>> +
>> + for_each_online_cpu ( i )
>> + {
>> + if ( i == mycpu )
>> + continue;
>> +
>> + per_cpu(sync_task, i) = xmalloc(struct tasklet);
>> + if ( per_cpu(sync_task, i) == NULL )
>> + {
>> + printk(XENLOG_WARNING "vpmu_force_context_switch: out of memory\n");
>> + ret = -ENOMEM;
>> + goto out;
>> + }
>> + tasklet_init(per_cpu(sync_task, i), vpmu_sched_checkin, 0);
>> + }
>> +
>> + /* First count is for self */
>> + atomic_set(&vpmu_sched_counter, 1);
>> +
>> + for_each_online_cpu ( i )
>> + {
>> + if ( i != mycpu )
>> + tasklet_schedule_on_cpu(per_cpu(sync_task, i), i);
>> + }
>> +
>> + vpmu_save(current);
>> +
>> + sync_vcpu = curr_vcpu;
>> + start = NOW();
>> +
>> + cont_wait:
>> + /*
>> + * Note that we may fail here if a CPU is hot-plugged while we are
>> + * waiting. We will then time out.
>> + */
> And I continue to miss the handling of the hot-unplug case (or at the
> very least a note on this being unimplemented [and going to crash],
> to at least clarify matters to the curious reader).
Where would we crash? I have no interest in that.
>
>> + while ( atomic_read(&vpmu_sched_counter) != numcpus )
>> + {
>> + s_time_t now;
>> +
>> + cpu_relax();
>> +
>> + now = NOW();
>> +
>> + /* Give up after (arbitrarily chosen) 5 seconds */
>> + if ( now > start + SECONDS(5) )
>> + {
>> + printk(XENLOG_WARNING
>> + "vpmu_force_context_switch: failed to sync\n");
>> + ret = -EBUSY;
>> + break;
>> + }
>> +
>> + if ( hypercall_preempt_check() )
>> + return hypercall_create_continuation(
>> + __HYPERVISOR_xenpmu_op, "i", XENPMU_mode_set);
> Did you test this code path? I don't see how with the missing second
> hypercall argument the continuation could reliably succeed.
I did test it (and retested it now) and it works. I guess it may be
picking the same value from the stack during continuation which is why
it does not fail.
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests
2014-10-27 16:38 ` Jan Beulich
@ 2014-10-27 19:21 ` Boris Ostrovsky
0 siblings, 0 replies; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-27 19:21 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/27/2014 12:38 PM, Jan Beulich wrote:
>
>> +static void pvpmu_finish(struct domain *d, xen_pmu_params_t *params)
>> +{
>> + struct vcpu *v;
>> + uint64_t mfn;
>> +
>> + if ( (params->vcpu >= d->max_vcpus) || (d->vcpu == NULL) ||
>> + (d->vcpu[params->vcpu] == NULL) )
>> + return;
>> +
>> + v = d->vcpu[params->vcpu];
>> + if ( v != current )
>> + vcpu_pause(v);
>> +
>> + if ( v->arch.vpmu.xenpmu_data )
>> + {
>> + mfn = domain_page_map_to_mfn(v->arch.vpmu.xenpmu_data);
>> + ASSERT(mfn != 0);
>> + unmap_domain_page_global(v->arch.vpmu.xenpmu_data);
>> + put_page_and_type(mfn_to_page(mfn));
> I think you absolutely need to clear v->arch.vpmu.xenpmu_data
> here, or else another call will (likely) crash the hypervisor. Even
> more, I think this actually needs serialization (and pvpmu_init() as
> well), especially with ...
What I should do is to destroy vpmu *before* everything else. And add
tests for VPMU_CONTEXT_ALLOCATED at a couple of entry points to
arch-specific code (I will need to rework Intel VPMU allocation to
happen at initialization time as opposed to current lazy allocation).
Then noone will be touching xenpmu_data whine it's not available.
Including pvpmu_init().
-boris
>
>> --- a/xen/include/xsm/dummy.h
>> +++ b/xen/include/xsm/dummy.h
>> @@ -665,6 +665,9 @@ static XSM_INLINE int xsm_pmu_op (XSM_DEFAULT_ARG struct
>> domain *d, int op)
>> case XENPMU_feature_set:
>> case XENPMU_feature_get:
>> return xsm_default_action(XSM_PRIV, d, current->domain);
>> + case XENPMU_init:
>> + case XENPMU_finish:
>> + return xsm_default_action(XSM_HOOK, d, current->domain);
> ... this being XSM_HOOK rather than XSM_TARGET.
>
> Jan
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-27 16:54 ` Jan Beulich
@ 2014-10-27 19:43 ` Boris Ostrovsky
2014-10-28 9:30 ` Jan Beulich
0 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-27 19:43 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/27/2014 12:54 PM, Jan Beulich wrote:
>>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
>> --- a/xen/arch/x86/hvm/vpmu.c
>> +++ b/xen/arch/x86/hvm/vpmu.c
>> @@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
>>
>> void vpmu_lvtpc_update(uint32_t val)
>> {
>> - struct vpmu_struct *vpmu = vcpu_vpmu(current);
>> + struct vcpu *curr = current;
>> + struct vpmu_struct *vpmu = vcpu_vpmu(curr);
>>
>> vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
>> - apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
>> +
>> + /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending */
>> + if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
>> + !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
> Isn't this the pointer that pvpmu_finish() deallocates (and needs to
> clear? If so, there's a race between it being cleared and used. If you
> need it in places like this, perhaps you'd be better off never clearing
> it and leaving the MFN allocated?
This will be one of the places that check for VPMU_CONTEXT_ALLOCATED.
>
>> void vpmu_do_interrupt(struct cpu_user_regs *regs)
>> {
>> - struct vcpu *v = current;
>> - struct vpmu_struct *vpmu = vcpu_vpmu(v);
>> + struct vcpu *sampled = current, *sampling;
>> + struct vpmu_struct *vpmu;
>> +
>> + /* dom0 will handle interrupt for special domains (e.g. idle domain) */
>> + if ( sampled->domain->domain_id >= DOMID_FIRST_RESERVED )
>> + {
>> + sampling = choose_hwdom_vcpu();
>> + if ( !sampling )
>> + return;
>> + }
>> + else
>> + sampling = sampled;
>> +
>> + vpmu = vcpu_vpmu(sampling);
>> + if ( !is_hvm_vcpu(sampling) )
>> + {
>> + /* PV(H) guest */
>> + const struct cpu_user_regs *cur_regs;
>> + uint64_t *flags = &vpmu->xenpmu_data->pmu.pmu_flags;
>> + uint32_t domid = DOMID_SELF;
>> +
>> + if ( !vpmu->xenpmu_data )
>> + return;
>> +
>> + if ( *flags & PMU_CACHED )
>> + return;
>> +
>> + if ( is_pvh_vcpu(sampling) &&
>> + !vpmu->arch_vpmu_ops->do_interrupt(regs) )
>> + return;
>> +
>> + /* PV guest will be reading PMU MSRs from xenpmu_data */
>> + vpmu_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
>> + vpmu->arch_vpmu_ops->arch_vpmu_save(sampling);
>> + vpmu_reset(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED);
>> +
>> + *flags = 0;
>> +
>> + /* Store appropriate registers in xenpmu_data */
>> + /* FIXME: 32-bit PVH should go here as well */
>> + if ( is_pv_32bit_vcpu(sampling) )
>> + {
>> + /*
>> + * 32-bit dom0 cannot process Xen's addresses (which are 64 bit)
>> + * and therefore we treat it the same way as a non-privileged
>> + * PV 32-bit domain.
>> + */
>> + struct compat_pmu_regs *cmp;
>> +
>> + cur_regs = guest_cpu_user_regs();
>> +
>> + cmp = (void *)&vpmu->xenpmu_data->pmu.r.regs;
>> + cmp->ip = cur_regs->rip;
>> + cmp->sp = cur_regs->rsp;
>> + cmp->flags = cur_regs->eflags;
>> + cmp->ss = cur_regs->ss;
>> + cmp->cs = cur_regs->cs;
>> + if ( (cmp->cs & 3) != 1 )
>> + *flags |= PMU_SAMPLE_USER;
>> + }
>> + else
>> + {
>> + struct xen_pmu_regs *r = &vpmu->xenpmu_data->pmu.r.regs;
>> +
>> + if ( (vpmu_mode & XENPMU_MODE_SELF) )
>> + cur_regs = guest_cpu_user_regs();
>> + else if ( (regs->rip >= XEN_VIRT_START) &&
>> + (regs->rip < XEN_VIRT_END) &&
>> + is_hardware_domain(sampling->domain))
> I'm pretty sure that already on the previous round I said that using
> only RIP for determining whether the sample occurred in hypervisor
> context is not enough.
Hmm, I did change this to !guest_mode(). But must have reverted it when
doing rebasing.
>
>> + {
>> + cur_regs = regs;
>> + domid = DOMID_XEN;
>> + }
>> + else
>> + cur_regs = guest_cpu_user_regs();
>> +
>> + r->ip = cur_regs->rip;
>> + r->sp = cur_regs->rsp;
>> + r->flags = cur_regs->eflags;
>> +
>> + if ( !has_hvm_container_vcpu(sampled) )
>> + {
>> + r->ss = cur_regs->ss;
>> + r->cs = cur_regs->cs;
>> + if ( !(sampled->arch.flags & TF_kernel_mode) )
>> + *flags |= PMU_SAMPLE_USER;
>> + }
>> + else
>> + {
>> + struct segment_register seg;
>> +
>> + hvm_get_segment_register(sampled, x86_seg_cs, &seg);
>> + r->cs = seg.sel;
>> + if ( (r->cs & 3) != 0 )
>> + *flags |= PMU_SAMPLE_USER;
> So is the VM86 mode case here intentionally being ignored?
We pass EFLAGS so the guest can check the VM bit. Is this not sufficient?
> And is
> there a particular reason you look at the selector's RPL instead of
> DPL, and CS instead of SS?
Should be DPL indeed. But why is SS better than CS?
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-27 18:52 ` Boris Ostrovsky
@ 2014-10-28 8:29 ` Jan Beulich
2014-10-28 16:56 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-28 8:29 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 27.10.14 at 19:52, <boris.ostrovsky@oracle.com> wrote:
> On 10/27/2014 12:24 PM, Jan Beulich wrote:
>>>>> On 17.10.14 at 23:17, <boris.ostrovsky@oracle.com> wrote:
>>> + mycpu = smp_processor_id();
>>> +
>>> + if ( sync_vcpu != NULL ) /* if set, we may be in hypercall continuation */
>>> + {
>>> + if (sync_vcpu != curr_vcpu )
>>> + /* We are not the original caller */
>>> + return -EAGAIN;
>> That would seem to be the wrong return value then. Also, the HAP
>> side fix for XSA-97 taught us that identifying a caller by vCPU is
>> problematic - in the course of the retries the kernel's scheduler
>> may move the calling process to a different vCPU, yet it's still the
>> legitimate original caller.
>
> If the process is rescheduled then we will time out operation.
And potentially never be able to complete it. Not an acceptable
model imo.
> I suppose I can set a bit in the argument's val to mark that particular
> argument as pending a continuation completion (I don't think we need to
> worry about malicious domain here since this is a privileged operation).
Privileged in the sense that it (conceptually) will always be restricted
to the hardware domain (or one granted equivalent privileges)?
Please don't forget about disaggregation - newly added code will not
get exceptions granted along the lines of XSA-77.
Also "I can set a bit in ..." is too vague to say whether that would end
up being an acceptable approach. The rationale behind the final
behavior we gave the XSA-97 fix was that if the operation is privileged
enough, it is okay for any vCPU of the originating domain to continue
the current one (including the non-determinism of which of them will
see the final successful completion of the hypercall, should more than
one of them race). I think you ought to follow that model here and
store/check the domain rather than the vCPU, in which case I don't
think you'll need any extra bit(s).
>>> + goto cont_wait;
>>> + }
>>> +
>>> + for_each_online_cpu ( i )
>>> + {
>>> + if ( i == mycpu )
>>> + continue;
>>> +
>>> + per_cpu(sync_task, i) = xmalloc(struct tasklet);
>>> + if ( per_cpu(sync_task, i) == NULL )
>>> + {
>>> + printk(XENLOG_WARNING "vpmu_force_context_switch: out of memory\n");
>>> + ret = -ENOMEM;
>>> + goto out;
>>> + }
>>> + tasklet_init(per_cpu(sync_task, i), vpmu_sched_checkin, 0);
>>> + }
>>> +
>>> + /* First count is for self */
>>> + atomic_set(&vpmu_sched_counter, 1);
>>> +
>>> + for_each_online_cpu ( i )
>>> + {
>>> + if ( i != mycpu )
>>> + tasklet_schedule_on_cpu(per_cpu(sync_task, i), i);
>>> + }
>>> +
>>> + vpmu_save(current);
>>> +
>>> + sync_vcpu = curr_vcpu;
>>> + start = NOW();
>>> +
>>> + cont_wait:
>>> + /*
>>> + * Note that we may fail here if a CPU is hot-plugged while we are
>>> + * waiting. We will then time out.
>>> + */
>> And I continue to miss the handling of the hot-unplug case (or at the
>> very least a note on this being unimplemented [and going to crash],
>> to at least clarify matters to the curious reader).
>
> Where would we crash? I have no interest in that.
per_cpu() accesses are invalid for offline CPUs.
>>> + while ( atomic_read(&vpmu_sched_counter) != numcpus )
>>> + {
>>> + s_time_t now;
>>> +
>>> + cpu_relax();
>>> +
>>> + now = NOW();
>>> +
>>> + /* Give up after (arbitrarily chosen) 5 seconds */
>>> + if ( now > start + SECONDS(5) )
>>> + {
>>> + printk(XENLOG_WARNING
>>> + "vpmu_force_context_switch: failed to sync\n");
>>> + ret = -EBUSY;
>>> + break;
>>> + }
>>> +
>>> + if ( hypercall_preempt_check() )
>>> + return hypercall_create_continuation(
>>> + __HYPERVISOR_xenpmu_op, "i", XENPMU_mode_set);
>> Did you test this code path? I don't see how with the missing second
>> hypercall argument the continuation could reliably succeed.
>
> I did test it (and retested it now) and it works. I guess it may be
> picking the same value from the stack during continuation which is why
> it does not fail.
Oh, right, hypercall argument clobbering (in debug builds) gets
skipped for continuations (and no clobbering is being done for
HVM/PVH at all). But I don't think you should rely on this, i.e. the
invocation above should get fixed in any event.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-27 19:43 ` Boris Ostrovsky
@ 2014-10-28 9:30 ` Jan Beulich
2014-10-28 17:08 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-28 9:30 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 27.10.14 at 20:43, <boris.ostrovsky@oracle.com> wrote:
> On 10/27/2014 12:54 PM, Jan Beulich wrote:
>>>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
>>> --- a/xen/arch/x86/hvm/vpmu.c
>>> +++ b/xen/arch/x86/hvm/vpmu.c
>>> @@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
>>>
>>> void vpmu_lvtpc_update(uint32_t val)
>>> {
>>> - struct vpmu_struct *vpmu = vcpu_vpmu(current);
>>> + struct vcpu *curr = current;
>>> + struct vpmu_struct *vpmu = vcpu_vpmu(curr);
>>>
>>> vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
>>> - apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
>>> +
>>> + /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending
> */
>>> + if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
>>> + !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
>> Isn't this the pointer that pvpmu_finish() deallocates (and needs to
>> clear? If so, there's a race between it being cleared and used. If you
>> need it in places like this, perhaps you'd be better off never clearing
>> it and leaving the MFN allocated?
>
> This will be one of the places that check for VPMU_CONTEXT_ALLOCATED.
But how will adding this check make this race free?
>>> + if ( !has_hvm_container_vcpu(sampled) )
>>> + {
>>> + r->ss = cur_regs->ss;
>>> + r->cs = cur_regs->cs;
>>> + if ( !(sampled->arch.flags & TF_kernel_mode) )
>>> + *flags |= PMU_SAMPLE_USER;
>>> + }
>>> + else
>>> + {
>>> + struct segment_register seg;
>>> +
>>> + hvm_get_segment_register(sampled, x86_seg_cs, &seg);
>>> + r->cs = seg.sel;
>>> + if ( (r->cs & 3) != 0 )
>>> + *flags |= PMU_SAMPLE_USER;
>> So is the VM86 mode case here intentionally being ignored?
>
> We pass EFLAGS so the guest can check the VM bit. Is this not sufficient?
The PMU_SAMPLE_USER flag is misleading in that case the way you
have things coded currently. But that'll get addressed by switching
to use SS.DPL (see below) anyway.
>> And is
>> there a particular reason you look at the selector's RPL instead of
>> DPL, and CS instead of SS?
>
> Should be DPL indeed. But why is SS better than CS?
Because SS.DPL is the canonical source for determining CPL.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
@ 2014-10-28 10:51 ` Jan Beulich
0 siblings, 0 replies; 41+ messages in thread
From: Jan Beulich @ 2014-10-28 10:51 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
> + if ( has_hvm_container_vcpu(sampled) )
> + {
> + struct segment_register seg;
> + struct xen_pmu_arch *pmu = &v->arch.vpmu.xenpmu_data->pmu;
> + struct xen_pmu_regs *r = &pmu->r.regs;
> +
> + hvm_get_segment_register(sampled, x86_seg_cs, &seg);
> + r->cs = seg.sel;
> + if ( (r->cs & 3) != 0 )
> + pmu->pmu_flags |= PMU_SAMPLE_USER;
> + hvm_get_segment_register(sampled, x86_seg_ss, &seg);
> + r->ss = seg.sel;
> + }
With this adjusted along what was outlined for an earlier patch,
feel free to add my ack to this one.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
@ 2014-10-28 10:52 ` Jan Beulich
0 siblings, 0 replies; 41+ messages in thread
From: Jan Beulich @ 2014-10-28 10:52 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
> Since PMU is now not HVM specific we can move VPMU-related files up from
> arch/x86/hvm/ directory.
>
> Specifically:
> arch/x86/hvm/vpmu.c -> arch/x86/cpu/vpmu.c
> arch/x86/hvm/svm/vpmu.c -> arch/x86/cpu/vpmu_amd.c
> arch/x86/hvm/vmx/vpmu_core2.c -> arch/x86/cpu/vpmu_intel.c
> include/asm-x86/hvm/vpmu.h -> include/asm-x86/vpmu.h
>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Jan Beulich <jbeulcih@suse.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-28 8:29 ` Jan Beulich
@ 2014-10-28 16:56 ` Boris Ostrovsky
2014-10-29 8:14 ` Jan Beulich
0 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-28 16:56 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/28/2014 04:29 AM, Jan Beulich wrote:
>>>> On 27.10.14 at 19:52, <boris.ostrovsky@oracle.com> wrote:
>> On 10/27/2014 12:24 PM, Jan Beulich wrote:
>>>>>> On 17.10.14 at 23:17, <boris.ostrovsky@oracle.com> wrote:
>>>> + mycpu = smp_processor_id();
>>>> +
>>>> + if ( sync_vcpu != NULL ) /* if set, we may be in hypercall continuation */
>>>> + {
>>>> + if (sync_vcpu != curr_vcpu )
>>>> + /* We are not the original caller */
>>>> + return -EAGAIN;
>>> That would seem to be the wrong return value then. Also, the HAP
>>> side fix for XSA-97 taught us that identifying a caller by vCPU is
>>> problematic - in the course of the retries the kernel's scheduler
>>> may move the calling process to a different vCPU, yet it's still the
>>> legitimate original caller.
>> If the process is rescheduled then we will time out operation.
> And potentially never be able to complete it. Not an acceptable
> model imo.
>
>> I suppose I can set a bit in the argument's val to mark that particular
>> argument as pending a continuation completion (I don't think we need to
>> worry about malicious domain here since this is a privileged operation).
> Privileged in the sense that it (conceptually) will always be restricted
> to the hardware domain (or one granted equivalent privileges)?
> Please don't forget about disaggregation - newly added code will not
> get exceptions granted along the lines of XSA-77.
>
> Also "I can set a bit in ..." is too vague to say whether that would end
> up being an acceptable approach. The rationale behind the final
> behavior we gave the XSA-97 fix was that if the operation is privileged
> enough, it is okay for any vCPU of the originating domain to continue
> the current one (including the non-determinism of which of them will
> see the final successful completion of the hypercall, should more than
> one of them race). I think you ought to follow that model here and
> store/check the domain rather than the vCPU, in which case I don't
> think you'll need any extra bit(s).
I am not sure just keeping domainID is sufficient in this case. True, it
doesn't matter which VCPU completes the operation but what we want to
avoid is to have two simultaneous (and possibly different) requests from
the same domain. If we keep it as some sort of a static variable (like I
do now with sync_vcpu) then it will be difficult to distinguish which
request is the continuation and which is a new one.
What I was suggesting is keeping some sort of state in the hypercall
argument making it unique to the call. I said "a bit" but it can be, for
example, setting the pad value in xen_pmu_params to some cookie
(although that's probably not a particularly good idea since then the
caller/domain would have to clear it before making the hypercall). So,
if we set, say, the upper bit in xen_pmu_params.val before creating
continuation then when we come back we will know for sure that this is
indeed the continuation and not a new call.
The comment about privileged domain was to mean that we don't need to
worry that the caller may maliciously try setting this bit in the hope
of causing trouble. The caller can only be a privileged guest (even if
it is the "disaggregated" guest that is responsible for VPMU management)
and if it does it --- well, it will break VPMUs but nothing else. As far
as I can tell, that is.
>
>>>> + goto cont_wait;
>>>> + }
>>>> +
>>>> + for_each_online_cpu ( i )
>>>> + {
>>>> + if ( i == mycpu )
>>>> + continue;
>>>> +
>>>> + per_cpu(sync_task, i) = xmalloc(struct tasklet);
>>>> + if ( per_cpu(sync_task, i) == NULL )
>>>> + {
>>>> + printk(XENLOG_WARNING "vpmu_force_context_switch: out of memory\n");
>>>> + ret = -ENOMEM;
>>>> + goto out;
>>>> + }
>>>> + tasklet_init(per_cpu(sync_task, i), vpmu_sched_checkin, 0);
>>>> + }
>>>> +
>>>> + /* First count is for self */
>>>> + atomic_set(&vpmu_sched_counter, 1);
>>>> +
>>>> + for_each_online_cpu ( i )
>>>> + {
>>>> + if ( i != mycpu )
>>>> + tasklet_schedule_on_cpu(per_cpu(sync_task, i), i);
>>>> + }
>>>> +
>>>> + vpmu_save(current);
>>>> +
>>>> + sync_vcpu = curr_vcpu;
>>>> + start = NOW();
>>>> +
>>>> + cont_wait:
>>>> + /*
>>>> + * Note that we may fail here if a CPU is hot-plugged while we are
>>>> + * waiting. We will then time out.
>>>> + */
>>> And I continue to miss the handling of the hot-unplug case (or at the
>>> very least a note on this being unimplemented [and going to crash],
>>> to at least clarify matters to the curious reader).
>> Where would we crash? I have no interest in that.
> per_cpu() accesses are invalid for offline CPUs.
Right.
How about I get/put_cpu_maps() to prevent hotplug/unplug while we are
doing this?
>
>>>> + while ( atomic_read(&vpmu_sched_counter) != numcpus )
>>>> + {
>>>> + s_time_t now;
>>>> +
>>>> + cpu_relax();
>>>> +
>>>> + now = NOW();
>>>> +
>>>> + /* Give up after (arbitrarily chosen) 5 seconds */
>>>> + if ( now > start + SECONDS(5) )
>>>> + {
>>>> + printk(XENLOG_WARNING
>>>> + "vpmu_force_context_switch: failed to sync\n");
>>>> + ret = -EBUSY;
>>>> + break;
>>>> + }
>>>> +
>>>> + if ( hypercall_preempt_check() )
>>>> + return hypercall_create_continuation(
>>>> + __HYPERVISOR_xenpmu_op, "i", XENPMU_mode_set);
>>> Did you test this code path? I don't see how with the missing second
>>> hypercall argument the continuation could reliably succeed.
>> I did test it (and retested it now) and it works. I guess it may be
>> picking the same value from the stack during continuation which is why
>> it does not fail.
> Oh, right, hypercall argument clobbering (in debug builds) gets
> skipped for continuations (and no clobbering is being done for
> HVM/PVH at all). But I don't think you should rely on this, i.e. the
> invocation above should get fixed in any event.
Of course. I was simply saying why the tests passed, not why it should
stay this way.
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-28 9:30 ` Jan Beulich
@ 2014-10-28 17:08 ` Boris Ostrovsky
2014-10-29 8:19 ` Jan Beulich
0 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-28 17:08 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/28/2014 05:30 AM, Jan Beulich wrote:
>>>> On 27.10.14 at 20:43, <boris.ostrovsky@oracle.com> wrote:
>> On 10/27/2014 12:54 PM, Jan Beulich wrote:
>>>>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
>>>> --- a/xen/arch/x86/hvm/vpmu.c
>>>> +++ b/xen/arch/x86/hvm/vpmu.c
>>>> @@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
>>>>
>>>> void vpmu_lvtpc_update(uint32_t val)
>>>> {
>>>> - struct vpmu_struct *vpmu = vcpu_vpmu(current);
>>>> + struct vcpu *curr = current;
>>>> + struct vpmu_struct *vpmu = vcpu_vpmu(curr);
>>>>
>>>> vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
>>>> - apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
>>>> +
>>>> + /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending
>> */
>>>> + if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
>>>> + !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
>>> Isn't this the pointer that pvpmu_finish() deallocates (and needs to
>>> clear? If so, there's a race between it being cleared and used. If you
>>> need it in places like this, perhaps you'd be better off never clearing
>>> it and leaving the MFN allocated?
>> This will be one of the places that check for VPMU_CONTEXT_ALLOCATED.
> But how will adding this check make this race free?
>
This VCPU is paused while we are tearing down its pvpmu so we can't be
in the middle if this (or other, such as vpmu_do_msr()) hypercall, can we?
Or it's not paused if the VCPU is the same one that is doing the
teardown. In which case we certainly are not in this hypercall.
So, in fact, the check for VPMU_CONTEXT_ALLOCATED may not be needed at all.
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-28 16:56 ` Boris Ostrovsky
@ 2014-10-29 8:14 ` Jan Beulich
2014-10-29 14:22 ` Boris Ostrovsky
0 siblings, 1 reply; 41+ messages in thread
From: Jan Beulich @ 2014-10-29 8:14 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 28.10.14 at 17:56, <boris.ostrovsky@oracle.com> wrote:
> On 10/28/2014 04:29 AM, Jan Beulich wrote:
>> Also "I can set a bit in ..." is too vague to say whether that would end
>> up being an acceptable approach. The rationale behind the final
>> behavior we gave the XSA-97 fix was that if the operation is privileged
>> enough, it is okay for any vCPU of the originating domain to continue
>> the current one (including the non-determinism of which of them will
>> see the final successful completion of the hypercall, should more than
>> one of them race). I think you ought to follow that model here and
>> store/check the domain rather than the vCPU, in which case I don't
>> think you'll need any extra bit(s).
>
> I am not sure just keeping domainID is sufficient in this case. True, it
> doesn't matter which VCPU completes the operation but what we want to
> avoid is to have two simultaneous (and possibly different) requests from
> the same domain. If we keep it as some sort of a static variable (like I
> do now with sync_vcpu) then it will be difficult to distinguish which
> request is the continuation and which is a new one.
A static variable may indeed be insufficient here. Did you look at
the XSA-97 change at all, trying to mirror its logic here?
> What I was suggesting is keeping some sort of state in the hypercall
> argument making it unique to the call. I said "a bit" but it can be, for
> example, setting the pad value in xen_pmu_params to some cookie
> (although that's probably not a particularly good idea since then the
> caller/domain would have to clear it before making the hypercall). So,
> if we set, say, the upper bit in xen_pmu_params.val before creating
> continuation then when we come back we will know for sure that this is
> indeed the continuation and not a new call.
Whatever state in the hypercall arguments you alter, a malicious or
buggy caller could do the same to an original request.
However, I wonder whether a model without continuations (and
hence not along the lines of what we did for XSA-97) might not be
better here after all:
1) Considering that you don't need access to the hypercall
arguments after initial evaluation, continue_hypercall_on_cpu()
would seem usable here: Once you visited all CPUs, you can be
certain a context switch occurred everywhere.
2) You could pause the current vCPU after scheduling all tasklets
and have the last one unpause it and do the necessary cleanup.
>>>>> + cont_wait:
>>>>> + /*
>>>>> + * Note that we may fail here if a CPU is hot-plugged while we are
>>>>> + * waiting. We will then time out.
>>>>> + */
>>>> And I continue to miss the handling of the hot-unplug case (or at the
>>>> very least a note on this being unimplemented [and going to crash],
>>>> to at least clarify matters to the curious reader).
>>> Where would we crash? I have no interest in that.
>> per_cpu() accesses are invalid for offline CPUs.
>
> Right.
>
> How about I get/put_cpu_maps() to prevent hotplug/unplug while we are
> doing this?
That's more the last resort solution. I'd prefer if you made your loops
simply a little more careful. Remember that hot-unplug can't happen
while your code is executing, it can only hit while you are awaiting a
continuation to occur.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for PV guests
2014-10-28 17:08 ` Boris Ostrovsky
@ 2014-10-29 8:19 ` Jan Beulich
0 siblings, 0 replies; 41+ messages in thread
From: Jan Beulich @ 2014-10-29 8:19 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 28.10.14 at 18:08, <boris.ostrovsky@oracle.com> wrote:
> On 10/28/2014 05:30 AM, Jan Beulich wrote:
>>>>> On 27.10.14 at 20:43, <boris.ostrovsky@oracle.com> wrote:
>>> On 10/27/2014 12:54 PM, Jan Beulich wrote:
>>>>>>> On 17.10.14 at 23:18, <boris.ostrovsky@oracle.com> wrote:
>>>>> --- a/xen/arch/x86/hvm/vpmu.c
>>>>> +++ b/xen/arch/x86/hvm/vpmu.c
>>>>> @@ -81,46 +81,206 @@ static void __init parse_vpmu_param(char *s)
>>>>>
>>>>> void vpmu_lvtpc_update(uint32_t val)
>>>>> {
>>>>> - struct vpmu_struct *vpmu = vcpu_vpmu(current);
>>>>> + struct vcpu *curr = current;
>>>>> + struct vpmu_struct *vpmu = vcpu_vpmu(curr);
>>>>>
>>>>> vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
>>>>> - apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
>>>>> +
>>>>> + /* Postpone APIC updates for PV(H) guests if PMU interrupt is pending
>>> */
>>>>> + if ( is_hvm_vcpu(curr) || !vpmu->xenpmu_data ||
>>>>> + !(vpmu->xenpmu_data->pmu.pmu_flags & PMU_CACHED) )
>>>> Isn't this the pointer that pvpmu_finish() deallocates (and needs to
>>>> clear? If so, there's a race between it being cleared and used. If you
>>>> need it in places like this, perhaps you'd be better off never clearing
>>>> it and leaving the MFN allocated?
>>> This will be one of the places that check for VPMU_CONTEXT_ALLOCATED.
>> But how will adding this check make this race free?
>
> This VCPU is paused while we are tearing down its pvpmu so we can't be
> in the middle if this (or other, such as vpmu_do_msr()) hypercall, can we?
>
> Or it's not paused if the VCPU is the same one that is doing the
> teardown. In which case we certainly are not in this hypercall.
>
> So, in fact, the check for VPMU_CONTEXT_ALLOCATED may not be needed at all.
Ah, sorry - I managed to overlook the pausing in pvpmu_finish().
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-29 8:14 ` Jan Beulich
@ 2014-10-29 14:22 ` Boris Ostrovsky
2014-10-29 16:50 ` Jan Beulich
0 siblings, 1 reply; 41+ messages in thread
From: Boris Ostrovsky @ 2014-10-29 14:22 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
On 10/29/2014 04:14 AM, Jan Beulich wrote:
>>>> On 28.10.14 at 17:56, <boris.ostrovsky@oracle.com> wrote:
>> On 10/28/2014 04:29 AM, Jan Beulich wrote:
>>> Also "I can set a bit in ..." is too vague to say whether that would end
>>> up being an acceptable approach. The rationale behind the final
>>> behavior we gave the XSA-97 fix was that if the operation is privileged
>>> enough, it is okay for any vCPU of the originating domain to continue
>>> the current one (including the non-determinism of which of them will
>>> see the final successful completion of the hypercall, should more than
>>> one of them race). I think you ought to follow that model here and
>>> store/check the domain rather than the vCPU, in which case I don't
>>> think you'll need any extra bit(s).
>> I am not sure just keeping domainID is sufficient in this case. True, it
>> doesn't matter which VCPU completes the operation but what we want to
>> avoid is to have two simultaneous (and possibly different) requests from
>> the same domain. If we keep it as some sort of a static variable (like I
>> do now with sync_vcpu) then it will be difficult to distinguish which
>> request is the continuation and which is a new one.
> A static variable may indeed be insufficient here. Did you look at
> the XSA-97 change at all, trying to mirror its logic here?
You mean storing this in domain structure? I don't want to add new
fields to such a common structure for an operation that is exceedingly
inferquent.
>
>> What I was suggesting is keeping some sort of state in the hypercall
>> argument making it unique to the call. I said "a bit" but it can be, for
>> example, setting the pad value in xen_pmu_params to some cookie
>> (although that's probably not a particularly good idea since then the
>> caller/domain would have to clear it before making the hypercall). So,
>> if we set, say, the upper bit in xen_pmu_params.val before creating
>> continuation then when we come back we will know for sure that this is
>> indeed the continuation and not a new call.
> Whatever state in the hypercall arguments you alter, a malicious or
> buggy caller could do the same to an original request.
>
> However, I wonder whether a model without continuations (and
> hence not along the lines of what we did for XSA-97) might not be
> better here after all:
>
> 1) Considering that you don't need access to the hypercall
> arguments after initial evaluation, continue_hypercall_on_cpu()
> would seem usable here: Once you visited all CPUs, you can be
> certain a context switch occurred everywhere.
>
> 2) You could pause the current vCPU after scheduling all tasklets
> and have the last one unpause it and do the necessary cleanup.
This sounds simpler than what I have now.
I don't think I will need the tasklets with this approach: they are all
part of continue_hypercall_on_cpu()?
As for pausing the VCPU? Won't the continue_hypercall_on_cpu() keep it
asleep until everyone has completed?
>
>>>>>> + cont_wait:
>>>>>> + /*
>>>>>> + * Note that we may fail here if a CPU is hot-plugged while we are
>>>>>> + * waiting. We will then time out.
>>>>>> + */
>>>>> And I continue to miss the handling of the hot-unplug case (or at the
>>>>> very least a note on this being unimplemented [and going to crash],
>>>>> to at least clarify matters to the curious reader).
>>>> Where would we crash? I have no interest in that.
>>> per_cpu() accesses are invalid for offline CPUs.
>> Right.
>>
>> How about I get/put_cpu_maps() to prevent hotplug/unplug while we are
>> doing this?
> That's more the last resort solution. I'd prefer if you made your loops
> simply a little more careful. Remember that hot-unplug can't happen
> while your code is executing, it can only hit while you are awaiting a
> continuation to occur.
I didn't realize that. But let me try what you suggested above.
-boris
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags
2014-10-29 14:22 ` Boris Ostrovsky
@ 2014-10-29 16:50 ` Jan Beulich
0 siblings, 0 replies; 41+ messages in thread
From: Jan Beulich @ 2014-10-29 16:50 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: kevin.tian, keir, suravee.suthikulpanit, andrew.cooper3, tim,
dietmar.hahn, xen-devel, Aravind.Gopalakrishnan, jun.nakajima,
dgdegra
>>> On 29.10.14 at 15:22, <boris.ostrovsky@oracle.com> wrote:
> On 10/29/2014 04:14 AM, Jan Beulich wrote:
>> A static variable may indeed be insufficient here. Did you look at
>> the XSA-97 change at all, trying to mirror its logic here?
>
> You mean storing this in domain structure? I don't want to add new
> fields to such a common structure for an operation that is exceedingly
> inferquent.
No matter how (in)frequent, you'd have to go that route if you
want to stick to that mechanism.
>> However, I wonder whether a model without continuations (and
>> hence not along the lines of what we did for XSA-97) might not be
>> better here after all:
>>
>> 1) Considering that you don't need access to the hypercall
>> arguments after initial evaluation, continue_hypercall_on_cpu()
>> would seem usable here: Once you visited all CPUs, you can be
>> certain a context switch occurred everywhere.
>>
>> 2) You could pause the current vCPU after scheduling all tasklets
>> and have the last one unpause it and do the necessary cleanup.
>
> This sounds simpler than what I have now.
>
> I don't think I will need the tasklets with this approach: they are all
> part of continue_hypercall_on_cpu()?
Right.
> As for pausing the VCPU? Won't the continue_hypercall_on_cpu() keep it
> asleep until everyone has completed?
This was a second possible approach I suggested, not connected
to the first one.
Jan
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2014-10-29 16:50 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-17 21:17 [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 01/21] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 02/21] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force() Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 03/21] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 04/21] x86/VPMU: Make vpmu macros a bit more efficient Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 05/21] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 06/21] vmx: Merge MSR management routines Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 07/21] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 08/21] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 09/21] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-10-24 16:00 ` Jan Beulich
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 10/21] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-10-17 21:17 ` [PATCH v14 for-xen-4.5 11/21] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-10-27 16:24 ` Jan Beulich
2014-10-27 18:52 ` Boris Ostrovsky
2014-10-28 8:29 ` Jan Beulich
2014-10-28 16:56 ` Boris Ostrovsky
2014-10-29 8:14 ` Jan Beulich
2014-10-29 14:22 ` Boris Ostrovsky
2014-10-29 16:50 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 12/21] x86/VPMU: Initialize AMD and Intel VPMU with __initcall Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 13/21] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
2014-10-27 16:38 ` Jan Beulich
2014-10-27 19:21 ` Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 14/21] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 15/21] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 16/21] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 17/21] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-10-27 16:54 ` Jan Beulich
2014-10-27 19:43 ` Boris Ostrovsky
2014-10-28 9:30 ` Jan Beulich
2014-10-28 17:08 ` Boris Ostrovsky
2014-10-29 8:19 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 18/21] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 19/21] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 20/21] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
2014-10-28 10:51 ` Jan Beulich
2014-10-17 21:18 ` [PATCH v14 for-xen-4.5 21/21] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-10-28 10:52 ` Jan Beulich
2014-10-27 7:38 ` [PATCH v14 for-xen-4.5 00/21] x86/PMU: Xen PMU PV(H) support Dietmar Hahn
2014-10-27 13:47 ` Boris Ostrovsky
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.