[PATCH 0/9] BYT DSI Dual Link Support

[PATCH 0/9] BYT DSI Dual Link Support

[Gaurav K Singh]

Hi,

These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.

v2: Commit message added to all patches. All review comments of Jani, Nikula
have been addressed in the second version of patches.

v3: for_each_dsi_port macro used instead of for loop for dual link support

Regards
Gaurav

Gaurav K Singh (9):
  drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
    reg
  drm/i915: Added port as parameter to the functions which does
    read/write of DSI Controller
  drm/i915: Add support for port enable/disable for dual link
    configuration
  drm/i915: Pixel Clock changes for DSI dual link
  drm/i915: Dual link needs Shutdown and Turn on packet for both ports
  drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
  drm/i915: MIPI Timings related changes for dual link
  drm/i915: Update the DSI disable path to support dual link panel
    disabling
  drm/i915: Update the DSI enable path to support dual link panel
    enabling

 drivers/gpu/drm/i915/i915_reg.h            |    5 +
 drivers/gpu/drm/i915/intel_bios.h          |    3 +-
 drivers/gpu/drm/i915/intel_dsi.c           |  415 +++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dsi.h           |    7 +
 drivers/gpu/drm/i915/intel_dsi_cmd.c       |  101 ++++---
 drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   49 +++-
 drivers/gpu/drm/i915/intel_dsi_pll.c       |    9 +-
 8 files changed, 383 insertions(+), 252 deletions(-)

-- 
1.7.9.5

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[PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg

[Gaurav K Singh]

This patch is in preparation for the DSI dual link
port enable and disable related changes.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   43 ++++++++++++++++++++++++++++----------
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 259cb4a..693736b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -102,6 +102,36 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void intel_dsi_port_enable(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	u32 temp;
+
+	/* assert ip_tg_enable signal */
+	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
+	temp = temp | intel_dsi->port_bits;
+	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+	POSTING_READ(MIPI_PORT_CTRL(port));
+}
+
+static void intel_dsi_port_disable(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	u32 temp;
+
+	/* de-assert ip_tg_enable signal */
+	temp = I915_READ(MIPI_PORT_CTRL(port));
+	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+	POSTING_READ(MIPI_PORT_CTRL(port));
+}
+
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -141,7 +171,6 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
-	u32 temp;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -157,11 +186,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 
 		wait_for_dsi_fifo_empty(intel_dsi);
 
-		/* assert ip_tg_enable signal */
-		temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
-		temp = temp | intel_dsi->port_bits;
-		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
+		intel_dsi_port_enable(encoder);
 	}
 }
 
@@ -245,11 +270,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 	if (is_vid_mode(intel_dsi)) {
 		wait_for_dsi_fifo_empty(intel_dsi);
 
-		/* de-assert ip_tg_enable signal */
-		temp = I915_READ(MIPI_PORT_CTRL(port));
-		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
-
+		intel_dsi_port_disable(encoder);
 		msleep(2);
 	}
 
-- 
1.7.9.5

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[PATCH 2/9] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller

[Gaurav K Singh]

This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the portno from MIPI Sequence Block#53, these sequences needs to be
sent accordingly.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_cmd.c       |   75 ++++++++++++----------------
 drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +++++++++--------
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++---
 3 files changed, 72 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 004fa91..8e30684 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -48,13 +48,11 @@
  * For memory writes, these should probably be used for performance.
  */
 
-static void print_stat(struct intel_dsi *intel_dsi)
+static void print_stat(struct intel_dsi *intel_dsi, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 val;
 
 	val = I915_READ(MIPI_INTR_STAT(port));
@@ -104,13 +102,12 @@ enum dsi_type {
 };
 
 /* enable or disable command mode hs transmissions */
-void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
+						enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 temp;
 	u32 mask = DBI_FIFO_EMPTY;
 
@@ -125,13 +122,11 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
 }
 
 static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
-			     u8 data_type, u16 data)
+			     u8 data_type, u16 data, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 ctrl_reg;
 	u32 ctrl;
 	u32 mask;
@@ -149,7 +144,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
 
 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
 		DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
-		print_stat(intel_dsi);
+		print_stat(intel_dsi, port);
 	}
 
 	/*
@@ -167,13 +162,11 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
 }
 
 static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
-			    u8 data_type, const u8 *data, int len)
+		u8 data_type, const u8 *data, int len, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 data_reg;
 	int i, j, n;
 	u32 mask;
@@ -204,12 +197,12 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
 		 * dwords, then wait for not set, then continue. */
 	}
 
-	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
+	return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
 }
 
 static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
 			       int channel, const u8 *data, int len,
-			       enum dsi_type type)
+			       enum dsi_type type, enum port port)
 {
 	int ret;
 
@@ -217,50 +210,54 @@ static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
 		BUG_ON(type == DSI_GENERIC);
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
-					0);
+					0, port);
 	} else if (len == 1) {
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					type == DSI_GENERIC ?
 					MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
-					MIPI_DSI_DCS_SHORT_WRITE, data[0]);
+					MIPI_DSI_DCS_SHORT_WRITE, data[0],
+					port);
 	} else if (len == 2) {
 		ret = dsi_vc_send_short(intel_dsi, channel,
 					type == DSI_GENERIC ?
 					MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
 					MIPI_DSI_DCS_SHORT_WRITE_PARAM,
-					(data[1] << 8) | data[0]);
+					(data[1] << 8) | data[0], port);
 	} else {
 		ret = dsi_vc_send_long(intel_dsi, channel,
-				       type == DSI_GENERIC ?
-				       MIPI_DSI_GENERIC_LONG_WRITE :
-				       MIPI_DSI_DCS_LONG_WRITE, data, len);
+					type == DSI_GENERIC ?
+					MIPI_DSI_GENERIC_LONG_WRITE :
+					MIPI_DSI_DCS_LONG_WRITE, data, len,
+					port);
 	}
 
 	return ret;
 }
 
 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
-		     const u8 *data, int len)
+		     const u8 *data, int len, enum port port)
 {
-	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
+	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
+									port);
 }
 
 int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
-			 const u8 *data, int len)
+			 const u8 *data, int len, enum port port)
 {
-	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
+	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
+									port);
 }
 
 static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
-					int channel, u8 dcs_cmd)
+				int channel, u8 dcs_cmd, enum port port)
 {
 	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
-				 dcs_cmd);
+				 dcs_cmd, port);
 }
 
 static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
 					    int channel, u8 *reqdata,
-					    int reqlen)
+					    int reqlen, enum port port)
 {
 	u16 data;
 	u8 data_type;
@@ -282,17 +279,15 @@ static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
 		BUG();
 	}
 
-	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
+	return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
 }
 
 static int dsi_read_data_return(struct intel_dsi *intel_dsi,
-				u8 *buf, int buflen)
+				u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	int i, len = 0;
 	u32 data_reg, val;
 
@@ -312,13 +307,11 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi,
 }
 
 int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
-		    u8 *buf, int buflen)
+		    u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 mask;
 	int ret;
 
@@ -329,7 +322,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 
 	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 
-	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
+	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
 	if (ret)
 		return ret;
 
@@ -337,7 +330,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 		DRM_ERROR("Timeout waiting for read data.\n");
 
-	ret = dsi_read_data_return(intel_dsi, buf, buflen);
+	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 	if (ret < 0)
 		return ret;
 
@@ -348,13 +341,11 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 }
 
 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
-			u8 *reqdata, int reqlen, u8 *buf, int buflen)
+		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 	u32 mask;
 	int ret;
 
@@ -366,7 +357,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 
 	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
-					       reqlen);
+					       reqlen, port);
 	if (ret)
 		return ret;
 
@@ -374,7 +365,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 		DRM_ERROR("Timeout waiting for read data.\n");
 
-	ret = dsi_read_data_return(intel_dsi, buf, buflen);
+	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 46aa1ac..326a5ac 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -36,77 +36,81 @@
 #define DPI_LP_MODE_EN	false
 #define DPI_HS_MODE_EN	true
 
-void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
+						enum port port);
 
 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
-		     const u8 *data, int len);
+		     const u8 *data, int len, enum port port);
 
 int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
-			 const u8 *data, int len);
+			 const u8 *data, int len, enum port port);
 
 int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
-		    u8 *buf, int buflen);
+		    u8 *buf, int buflen, enum port port);
 
 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
-			u8 *reqdata, int reqlen, u8 *buf, int buflen);
+		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
 
 int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
 
 /* XXX: questionable write helpers */
 static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
-				     int channel, u8 dcs_cmd)
+				     int channel, u8 dcs_cmd, enum port port)
 {
-	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
+	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
 }
 
 static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
-				     int channel, u8 dcs_cmd, u8 param)
+			int channel, u8 dcs_cmd, u8 param, enum port port)
 {
 	u8 buf[2] = { dcs_cmd, param };
-	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
+	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
 }
 
 static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
-					 int channel)
+					 int channel, enum port port)
 {
-	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
+	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
 }
 
 static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
-					 int channel, u8 param)
+					 int channel, u8 param, enum port port)
 {
-	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
+	return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
 }
 
 static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
-					 int channel, u8 param1, u8 param2)
+			int channel, u8 param1, u8 param2, enum port port)
 {
 	u8 buf[2] = { param1, param2 };
-	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
+	return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
 }
 
 /* XXX: questionable read helpers */
 static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
-					int channel, u8 *buf, int buflen)
+			int channel, u8 *buf, int buflen, enum port port)
 {
-	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
+									port);
 }
 
 static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
 					int channel, u8 param, u8 *buf,
-					int buflen)
+					int buflen, enum port port)
 {
-	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
+									port);
 }
 
 static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
 					int channel, u8 param1, u8 param2,
-					u8 *buf, int buflen)
+					u8 *buf, int buflen, enum port port)
 {
 	u8 req[2] = { param1, param2 };
 
-	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
+	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
+									port);
 }
 
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f6bdd44..612592f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -94,16 +94,23 @@ static struct gpio_table gtable[] = {
 	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 };
 
+static inline enum port intel_dsi_seq_port_to_port(u8 port)
+{
+	return port ? PORT_C : PORT_A;
+}
+
 static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 {
 	u8 type, byte, mode, vc, port;
 	u16 len;
+	enum port port_no;
 
 	byte = *data++;
 	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
 	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
 	port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 
+	port_no = intel_dsi_seq_port_to_port(port);
 	/* LP or HS mode */
 	intel_dsi->hs = mode;
 
@@ -115,13 +122,13 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 
 	switch (type) {
 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
-		dsi_vc_generic_write_0(intel_dsi, vc);
+		dsi_vc_generic_write_0(intel_dsi, vc, port);
 		break;
 	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
-		dsi_vc_generic_write_1(intel_dsi, vc, *data);
+		dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
 		break;
 	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
-		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
+		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
 		break;
 	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
@@ -129,19 +136,19 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 		DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 		break;
 	case MIPI_DSI_GENERIC_LONG_WRITE:
-		dsi_vc_generic_write(intel_dsi, vc, data, len);
+		dsi_vc_generic_write(intel_dsi, vc, data, len, port);
 		break;
 	case MIPI_DSI_DCS_SHORT_WRITE:
-		dsi_vc_dcs_write_0(intel_dsi, vc, *data);
+		dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
 		break;
 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
-		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
+		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
 		break;
 	case MIPI_DSI_DCS_READ:
 		DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 		break;
 	case MIPI_DSI_DCS_LONG_WRITE:
-		dsi_vc_dcs_write(intel_dsi, vc, data, len);
+		dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
 		break;
 	}
 
-- 
1.7.9.5

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[PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

[Gaurav K Singh]

For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.

v2: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    1 +
 drivers/gpu/drm/i915/intel_dsi.c           |   39 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dsi.h           |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 +++++
 4 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..c981f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6664,6 +6664,7 @@ enum punit_power_well {
 #define  DPI_ENABLE					(1 << 31) /* A + C */
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
+#define  DUAL_LINK_MODE_SHIFT				26
 #define  DUAL_LINK_MODE_MASK				(1 << 26)
 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 693736b..1163a5b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -108,28 +108,43 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
-	/* assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
-	temp = temp | intel_dsi->port_bits;
-	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+
+		if (intel_dsi->dual_link) {
+			if (port == PORT_A)
+				intel_dsi->port_bits |= intel_crtc->pipe ?
+					LANE_CONFIGURATION_DUAL_LINK_B :
+					LANE_CONFIGURATION_DUAL_LINK_A;
+			else
+				intel_dsi->port_bits = 0;
+		} else
+			temp &= ~LANE_CONFIGURATION_MASK;
+
+		/* assert ip_tg_enable signal */
+		temp = temp | intel_dsi->port_bits;
+		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 temp;
 
-	/* de-assert ip_tg_enable signal */
-	temp = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-	POSTING_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* de-assert ip_tg_enable signal */
+		temp = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+		POSTING_READ(MIPI_PORT_CTRL(port));
+	}
 }
 
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7f5d028..f2cc2fc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -104,6 +104,7 @@ struct intel_dsi {
 	u8 clock_stop;
 
 	u8 escape_clk_div;
+	u8 dual_link;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 612592f..7f1ba58 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -287,6 +287,13 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
+	intel_dsi->dual_link = mipi_config->dual_link;
+
+	if (intel_dsi->dual_link) {
+		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+		intel_dsi->port_bits = (intel_dsi->dual_link - 1)
+					<< DUAL_LINK_MODE_SHIFT;
+	}
 
 	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 		bits_per_pixel = 18;
-- 
1.7.9.5

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[PATCH 4/9] drm/i915: Pixel Clock changes for DSI dual link

[Gaurav K Singh]

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |    4 ++++
 drivers/gpu/drm/i915/intel_bios.h          |    3 ++-
 drivers/gpu/drm/i915/intel_dsi.c           |    8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.h           |    6 ++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++++++++++++++++++
 5 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c981f5d..87149ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6029,6 +6029,10 @@ enum punit_power_well {
 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
 #define VLV_PWRDWNUPCTL				0xA294
 
+#define VLV_CHICKEN_3				0x7040C
+#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
+#define  PIXEL_OVERLAP_CNT_SHIFT		30
+
 #define GEN6_PMISR				0x44020
 #define GEN6_PMIMR				0x44024 /* rps_lock */
 #define GEN6_PMIIR				0x44028
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index de01167..a6a8710 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -818,7 +818,8 @@ struct mipi_config {
 #define DUAL_LINK_PIXEL_ALT	2
 	u16 dual_link:2;
 	u16 lane_cnt:2;
-	u16 rsvd3:12;
+	u16 pixel_overlap:3;
+	u16 rsvd3:9;
 
 	u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1163a5b..e900f01 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -111,6 +111,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	enum port port;
 	u32 temp;
 
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		temp = I915_READ(VLV_CHICKEN_3);
+		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+					intel_dsi->pixel_overlap <<
+					PIXEL_OVERLAP_CNT_SHIFT;
+		I915_WRITE(VLV_CHICKEN_3, temp);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		temp = I915_READ(MIPI_PORT_CTRL(port));
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f2cc2fc..8fe2064 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -28,6 +28,11 @@
 #include <drm/drm_crtc.h>
 #include "intel_drv.h"
 
+/* Dual Link support */
+#define DSI_DUAL_LINK_NONE		0
+#define DSI_DUAL_LINK_FRONT_BACK	1
+#define DSI_DUAL_LINK_PIXEL_ALT		2
+
 struct intel_dsi_device {
 	unsigned int panel_id;
 	const char *name;
@@ -105,6 +110,7 @@ struct intel_dsi {
 
 	u8 escape_clk_div;
 	u8 dual_link;
+	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7f1ba58..f1417b9 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -288,6 +288,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 	intel_dsi->dual_link = mipi_config->dual_link;
+	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 
 	if (intel_dsi->dual_link) {
 		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
@@ -313,6 +314,20 @@ static bool generic_init(struct intel_dsi_device *dsi)
 
 	pclk = mode->clock;
 
+	/* In dual link mode each port needs half of pixel clock */
+	if (intel_dsi->dual_link) {
+		pclk = pclk / 2;
+
+		/* we can enable pixel_overlap if needed by panel. In this
+		 * case we need to increase the pixelclock for extra pixels
+		 */
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+			pclk += DIV_ROUND_UP(mode->vtotal *
+						intel_dsi->pixel_overlap *
+						60, 1000);
+		}
+	}
+
 	/* Burst Mode Ratio
 	 * Target ddr frequency from VBT / non burst ddr freq
 	 * multiply by 100 to preserve remainder
@@ -507,6 +522,12 @@ static bool generic_init(struct intel_dsi_device *dsi)
 	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 						"disabled" : "enabled");
 	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
+	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
+	else
+		DRM_DEBUG_KMS("Dual link: NONE\n");
 	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
-- 
1.7.9.5

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[PATCH 5/9] drm/i915: Dual link needs Shutdown and Turn on packet for both ports

[Gaurav K Singh]

For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_cmd.c |   26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 8e30684..562811c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -385,8 +385,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 mask;
 
 	/* XXX: pipe, hs */
@@ -395,18 +394,23 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 	else
 		cmd |= DPI_LP_MODE;
 
-	/* clear bit */
-	I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* clear bit */
+		I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 
-	/* XXX: old code skips write if control unchanged */
-	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
-		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+		/* XXX: old code skips write if control unchanged */
+		if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
+			DRM_ERROR("Same special packet %02x twice in a row.\n",
+									cmd);
 
-	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
+		I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 
-	mask = SPL_PKT_SENT_INTERRUPT;
-	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
-		DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+		mask = SPL_PKT_SENT_INTERRUPT;
+		if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
+									100))
+			DRM_ERROR("Video mode command 0x%08x send failed.\n",
+									cmd);
+	}
 
 	return 0;
 }
-- 
1.7.9.5

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[PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

[Gaurav K Singh]

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index fa7a6ca..93d8e9a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 
 	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
+	if (intel_dsi->dual_link)
+		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
 		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
 
@@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 	tmp |= DSI_PLL_VCO_EN;
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
 
-	mutex_unlock(&dev_priv->dpio_lock);
-
-	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
+	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
+					DSI_PLL_LOCK, 20)) {
 		DRM_ERROR("DSI PLL lock failed\n");
 		return;
 	}
+	mutex_unlock(&dev_priv->dpio_lock);
 
 	DRM_DEBUG_KMS("DSI PLL locked\n");
 }
-- 
1.7.9.5

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[PATCH 7/9] drm/i915: MIPI Timings related changes for dual link

[Gaurav K Singh]

hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   37 ++++++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e900f01..a2bb321 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -481,7 +481,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	unsigned int lane_count = intel_dsi->lane_count;
 
@@ -492,6 +492,15 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	hsync = mode->hsync_end - mode->hsync_start;
 	hbp = mode->htotal - mode->hsync_end;
 
+	if (intel_dsi->dual_link) {
+		hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			hactive += intel_dsi->pixel_overlap;
+		hfp /= 2;
+		hsync /= 2;
+		hbp /= 2;
+	}
+
 	vfp = mode->vsync_start - mode->vdisplay;
 	vsync = mode->vsync_end - mode->vsync_start;
 	vbp = mode->vtotal - mode->vsync_end;
@@ -504,18 +513,20 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 			    intel_dsi->burst_mode_ratio);
 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
-	I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
-	I915_WRITE(MIPI_HFP_COUNT(port), hfp);
-
-	/* meaningful for video mode non-burst sync pulse mode only, can be zero
-	 * for non-burst sync events and burst modes */
-	I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
-	I915_WRITE(MIPI_HBP_COUNT(port), hbp);
-
-	/* vertical values are in terms of lines */
-	I915_WRITE(MIPI_VFP_COUNT(port), vfp);
-	I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
-	I915_WRITE(MIPI_VBP_COUNT(port), vbp);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
+		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
+
+		/* meaningful for video mode non-burst sync pulse mode only,
+		 * can be zero for non-burst sync events and burst modes */
+		I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
+		I915_WRITE(MIPI_HBP_COUNT(port), hbp);
+
+		/* vertical values are in terms of lines */
+		I915_WRITE(MIPI_VFP_COUNT(port), vfp);
+		I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
+		I915_WRITE(MIPI_VBP_COUNT(port), vbp);
+	}
 }
 
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
-- 
1.7.9.5

_______________________________________________
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[PATCH 8/9] drm/i915: Update the DSI disable path to support dual link panel disabling

[Gaurav K Singh]

We need to program both port registers during dual link disable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   67 ++++++++++++++++++++------------------
 1 file changed, 36 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a2bb321..3e1e8dd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -283,9 +283,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	u32 temp;
 
 	DRM_DEBUG_KMS("\n");
@@ -297,23 +296,24 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		msleep(2);
 	}
 
-	/* Panel commands can be sent when clock is in LP11 */
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
-
-	temp = I915_READ(MIPI_CTRL(port));
-	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(port), temp |
-		   intel_dsi->escape_clk_div <<
-		   ESCAPE_CLOCK_DIVIDER_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* Panel commands can be sent when clock is in LP11 */
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+		temp = I915_READ(MIPI_CTRL(port));
+		temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(port), temp |
+			   intel_dsi->escape_clk_div <<
+			   ESCAPE_CLOCK_DIVIDER_SHIFT);
 
-	temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-	temp &= ~VID_MODE_FORMAT_MASK;
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+		temp &= ~VID_MODE_FORMAT_MASK;
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+	}
 	/* if disable packets are sent before sending shutdown packet then in
 	 * some next enable sequence send turn on packet error is observed */
 	if (intel_dsi->dev.dev_ops->disable)
@@ -325,31 +325,36 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_EXIT);
+		usleep_range(2000, 2500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+							ULPS_STATE_ENTER);
+		usleep_range(2000, 2500);
 
-	if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT)
-		      == 0x00000), 30))
-		DRM_ERROR("DSI LP not going Low\n");
+		if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
+							== 0x00000), 30))
+			DRM_ERROR("DSI LP not going Low\n");
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
-	usleep_range(2000, 2500);
+		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
+		usleep_range(2000, 2500);
+	}
 
 	vlv_disable_dsi_pll(encoder);
 }
-- 
1.7.9.5

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[PATCH 9/9] drm/i915: Update the DSI enable path to support dual link panel enabling

[Gaurav K Singh]

We need to program both port registers during dual link enable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |  251 +++++++++++++++++++++-----------------
 1 file changed, 136 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3e1e8dd..b51d212 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -158,8 +158,8 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -173,18 +173,21 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	/* bandgap reset is needed after everytime we do power gate */
 	band_gap_reset(dev_priv);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
-	usleep_range(2500, 3000);
+	for_each_dsi_port(port, intel_dsi->ports) {
 
-	val = I915_READ(MIPI_PORT_CTRL(port));
-	I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
-	usleep_range(1000, 1500);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
+		usleep_range(2500, 3000);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-	usleep_range(2500, 3000);
+		val = I915_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
 
-	I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
-	usleep_range(2500, 3000);
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
+		usleep_range(2500, 3000);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
+		usleep_range(2500, 3000);
+	}
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -543,32 +546,43 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
-	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+	enum port port;
 	unsigned int bpp = intel_crtc->config.pipe_bpp;
 	u32 val, tmp;
+	u16 mode_hactive;
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 
-	/* escape clock divider, 20MHz, shared for A and C. device ready must be
-	 * off when doing this! txclkesc? */
-	tmp = I915_READ(MIPI_CTRL(PORT_A));
-	tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-	I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
-	/* read request priority is per pipe */
-	tmp = I915_READ(MIPI_CTRL(port));
-	tmp &= ~READ_REQUEST_PRIORITY_MASK;
-	I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+	mode_hactive = adjusted_mode->hdisplay;
 
-	/* XXX: why here, why like this? handling in irq handler?! */
-	I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
-	I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
-
-	I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+	if (intel_dsi->dual_link) {
+		mode_hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			mode_hactive += intel_dsi->pixel_overlap;
+	}
 
-	I915_WRITE(MIPI_DPI_RESOLUTION(port),
-		   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
-		   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		/* escape clock divider, 20MHz, shared for A and C.
+		 * device ready must be off when doing this! txclkesc? */
+		tmp = I915_READ(MIPI_CTRL(PORT_A));
+		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+		/* read request priority is per pipe */
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~READ_REQUEST_PRIORITY_MASK;
+		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+		/* XXX: why here, why like this? handling in irq handler?! */
+		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
+		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
+
+		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
+
+		I915_WRITE(MIPI_DPI_RESOLUTION(port),
+			adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+			mode_hactive << HORIZONTAL_ADDRESS_SHIFT);
+	}
 
 	set_dsi_timings(encoder, adjusted_mode);
 
@@ -582,95 +596,102 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		/* XXX: cross-check bpp vs. pixel format? */
 		val |= intel_dsi->pixel_format;
 	}
-	I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-	/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
-	 * stop state. */
-
-	/*
-	 * In burst mode, value greater than one DPI line Time in byte clock
-	 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
-	 * recommended.
-	 *
-	 * In non-burst mode, Value greater than one DPI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 *
-	 * In DBI only mode, value greater than one DBI frame time in byte
-	 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
-	 * is recommended.
-	 */
-
-	if (is_vid_mode(intel_dsi) &&
-	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->htotal, bpp,
-				       intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	} else {
-		I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-			   txbyteclkhs(adjusted_mode->vtotal *
-				       adjusted_mode->htotal,
-				       bpp, intel_dsi->lane_count,
-				       intel_dsi->burst_mode_ratio) + 1);
-	}
-	I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
-	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
-	I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
-
-	/* dphy stuff */
-
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
-
-	val = 0;
+	tmp = 0;
 	if (intel_dsi->eotp_pkt == 0)
-		val |= EOT_DISABLE;
-
+		tmp |= EOT_DISABLE;
 	if (intel_dsi->clock_stop)
-		val |= CLOCKSTOP;
-
-	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(port), val);
-
-	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
-
-	/* in terms of txbyteclkhs. actual high to low switch +
-	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
-	 *
-	 * XXX: write MIPI_STOP_STATE_STALL?
-	 */
-	I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
-		   intel_dsi->hs_to_lp_count);
+		tmp |= CLOCKSTOP;
 
-	/* XXX: low power clock equivalence in terms of byte clock. the number
-	 * of byte clocks occupied in one low power clock. based on txbyteclkhs
-	 * and txclkesc. txclkesc time / txbyteclk time * (105 +
-	 * MIPI_STOP_STATE_STALL) / 105.???
-	 */
-	I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
-
-	/* the bw essential for transmitting 16 long packets containing 252
-	 * bytes meant for dcs write memory command is programmed in this
-	 * register in terms of byte clocks. based on dsi transfer rate and the
-	 * number of lanes configured the time taken to transmit 16 long packets
-	 * in a dsi stream varies. */
-	I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
-
-	I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
-		   intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
-		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
-
-	if (is_vid_mode(intel_dsi))
-		/* Some panels might have resolution which is not a multiple of
-		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
-		 * panels by default */
-		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
-			   intel_dsi->video_frmt_cfg_bits |
-			   intel_dsi->video_mode_format |
-			   IP_TG_CONFIG |
-			   RANDOM_DPI_DISPLAY_RESOLUTION);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
+
+		/* timeouts for recovery. one frame IIUC. if counter expires,
+		 * EOT and stop state. */
+
+		/*
+		 * In burst mode, value greater than one DPI line Time in byte
+		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In non-burst mode, Value greater than one DPI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 *
+		 * In DBI only mode, value greater than one DBI frame time in
+		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
+		 * said value is recommended.
+		 */
+
+		if (is_vid_mode(intel_dsi) &&
+			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->htotal, bpp,
+					intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		} else {
+			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
+				txbyteclkhs(adjusted_mode->vtotal *
+					adjusted_mode->htotal,
+					bpp, intel_dsi->lane_count,
+					intel_dsi->burst_mode_ratio) + 1);
+		}
+		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
+		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
+						intel_dsi->turn_arnd_val);
+		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
+						intel_dsi->rst_timer_val);
+
+		/* dphy stuff */
+
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port),
+				txclkesc(intel_dsi->escape_clk_div, 100));
+
+
+		/* recovery disables */
+		I915_WRITE(MIPI_EOT_DISABLE(port), val);
+
+		/* in terms of low power clock */
+		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
+
+		/* in terms of txbyteclkhs. actual high to low switch +
+		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+		 *
+		 * XXX: write MIPI_STOP_STATE_STALL?
+		 */
+		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
+						intel_dsi->hs_to_lp_count);
+
+		/* XXX: low power clock equivalence in terms of byte clock.
+		 * the number of byte clocks occupied in one low power clock.
+		 * based on txbyteclkhs and txclkesc.
+		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
+		 * ) / 105.???
+		 */
+		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+
+		/* the bw essential for transmitting 16 long packets containing
+		 * 252 bytes meant for dcs write memory command is programmed in
+		 * this register in terms of byte clocks. based on dsi transfer
+		 * rate and the number of lanes configured the time taken to
+		 * transmit 16 long packets in a dsi stream varies. */
+		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
+
+		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
+		intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
+		intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
+
+		if (is_vid_mode(intel_dsi))
+			/* Some panels might have resolution which is not a
+			 * multiple of 64 like 1366 x 768. Enable RANDOM
+			 * resolution support for such panels by default */
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				intel_dsi->video_frmt_cfg_bits |
+				intel_dsi->video_mode_format |
+				IP_TG_CONFIG |
+				RANDOM_DPI_DISPLAY_RESOLUTION);
+	}
 }
 
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
-- 
1.7.9.5

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Re: [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

[Jani Nikula]

On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h            |    1 +
>  drivers/gpu/drm/i915/intel_dsi.c           |   39 +++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 +++++
>  4 files changed, 36 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..c981f5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> +#define  DUAL_LINK_MODE_SHIFT				26
>  #define  DUAL_LINK_MODE_MASK				(1 << 26)
>  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 693736b..1163a5b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -108,28 +108,43 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	enum port port;
>  	u32 temp;
>  
> -	/* assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
> -	temp = temp | intel_dsi->port_bits;
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +
> +		if (intel_dsi->dual_link) {
> +			if (port == PORT_A)
> +				intel_dsi->port_bits |= intel_crtc->pipe ?
> +					LANE_CONFIGURATION_DUAL_LINK_B :
> +					LANE_CONFIGURATION_DUAL_LINK_A;
> +			else
> +				intel_dsi->port_bits = 0;

It feels wrong to clobber intel_dsi->port_bits here; the old code didn't
do that either. I think you should either set port_bits somewhere else
(or remove it altogether), and then modify temp depending on port.

Side note, it seems to me intel_dsi->dual_link is becoming redundant, as
intel_dsi->ports will have more than one bit set in the dual link
case. This can be a future cleanup though.

BR,
Jani.

> +		} else
> +			temp &= ~LANE_CONFIGURATION_MASK;
> +
> +		/* assert ip_tg_enable signal */
> +		temp = temp | intel_dsi->port_bits;
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 temp;
>  
> -	/* de-assert ip_tg_enable signal */
> -	temp = I915_READ(MIPI_PORT_CTRL(port));
> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> -	POSTING_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		/* de-assert ip_tg_enable signal */
> +		temp = I915_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> +		POSTING_READ(MIPI_PORT_CTRL(port));
> +	}
>  }
>  
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 7f5d028..f2cc2fc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -104,6 +104,7 @@ struct intel_dsi {
>  	u8 clock_stop;
>  
>  	u8 escape_clk_div;
> +	u8 dual_link;
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 612592f..7f1ba58 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -287,6 +287,13 @@ static bool generic_init(struct intel_dsi_device *dsi)
>  	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>  	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
> +	intel_dsi->dual_link = mipi_config->dual_link;
> +
> +	if (intel_dsi->dual_link) {
> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
> +		intel_dsi->port_bits = (intel_dsi->dual_link - 1)
> +					<< DUAL_LINK_MODE_SHIFT;
> +	}
>  
>  	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>  		bits_per_pixel = 18;
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

[Jani Nikula]

On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>
> v2: Address review comments by Jani
>     - Added wait time for PLL to be locked.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..93d8e9a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  
>  	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> +	if (intel_dsi->dual_link)
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>  		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>  
> @@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  	tmp |= DSI_PLL_VCO_EN;
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>  
> -	mutex_unlock(&dev_priv->dpio_lock);
> -
> -	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
> +	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
> +					DSI_PLL_LOCK, 20)) {
>  		DRM_ERROR("DSI PLL lock failed\n");
>  		return;
>  	}
> +	mutex_unlock(&dev_priv->dpio_lock);

This hunk seems to be an unrelated change, I think it should be a
separate patch.

BR,
Jani.

>  
>  	DRM_DEBUG_KMS("DSI PLL locked\n");
>  }
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/9] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller

[Jani Nikula]

On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> This patch is in preparation of DSI dual link panels. For dual link
> panels, few packets needs to be sent to Port A or Port C or both. Based
> on the portno from MIPI Sequence Block#53, these sequences needs to be
> sent accordingly.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_cmd.c       |   75 ++++++++++++----------------
>  drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +++++++++--------
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   21 +++++---
>  3 files changed, 72 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> index 004fa91..8e30684 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
> @@ -48,13 +48,11 @@
>   * For memory writes, these should probably be used for performance.
>   */
>  
> -static void print_stat(struct intel_dsi *intel_dsi)
> +static void print_stat(struct intel_dsi *intel_dsi, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 val;
>  
>  	val = I915_READ(MIPI_INTR_STAT(port));
> @@ -104,13 +102,12 @@ enum dsi_type {
>  };
>  
>  /* enable or disable command mode hs transmissions */
> -void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
> +void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
> +						enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 temp;
>  	u32 mask = DBI_FIFO_EMPTY;
>  
> @@ -125,13 +122,11 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
>  }
>  
>  static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
> -			     u8 data_type, u16 data)
> +			     u8 data_type, u16 data, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 ctrl_reg;
>  	u32 ctrl;
>  	u32 mask;
> @@ -149,7 +144,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
>  
>  	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
>  		DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
> -		print_stat(intel_dsi);
> +		print_stat(intel_dsi, port);
>  	}
>  
>  	/*
> @@ -167,13 +162,11 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
>  }
>  
>  static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
> -			    u8 data_type, const u8 *data, int len)
> +		u8 data_type, const u8 *data, int len, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 data_reg;
>  	int i, j, n;
>  	u32 mask;
> @@ -204,12 +197,12 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
>  		 * dwords, then wait for not set, then continue. */
>  	}
>  
> -	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
> +	return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
>  }
>  
>  static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
>  			       int channel, const u8 *data, int len,
> -			       enum dsi_type type)
> +			       enum dsi_type type, enum port port)
>  {
>  	int ret;
>  
> @@ -217,50 +210,54 @@ static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
>  		BUG_ON(type == DSI_GENERIC);
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
> -					0);
> +					0, port);
>  	} else if (len == 1) {
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					type == DSI_GENERIC ?
>  					MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
> -					MIPI_DSI_DCS_SHORT_WRITE, data[0]);
> +					MIPI_DSI_DCS_SHORT_WRITE, data[0],
> +					port);
>  	} else if (len == 2) {
>  		ret = dsi_vc_send_short(intel_dsi, channel,
>  					type == DSI_GENERIC ?
>  					MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
>  					MIPI_DSI_DCS_SHORT_WRITE_PARAM,
> -					(data[1] << 8) | data[0]);
> +					(data[1] << 8) | data[0], port);
>  	} else {
>  		ret = dsi_vc_send_long(intel_dsi, channel,
> -				       type == DSI_GENERIC ?
> -				       MIPI_DSI_GENERIC_LONG_WRITE :
> -				       MIPI_DSI_DCS_LONG_WRITE, data, len);
> +					type == DSI_GENERIC ?
> +					MIPI_DSI_GENERIC_LONG_WRITE :
> +					MIPI_DSI_DCS_LONG_WRITE, data, len,
> +					port);
>  	}
>  
>  	return ret;
>  }
>  
>  int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
> -		     const u8 *data, int len)
> +		     const u8 *data, int len, enum port port)
>  {
> -	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
> +	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
> +									port);
>  }
>  
>  int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
> -			 const u8 *data, int len)
> +			 const u8 *data, int len, enum port port)
>  {
> -	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
> +	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
> +									port);
>  }
>  
>  static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
> -					int channel, u8 dcs_cmd)
> +				int channel, u8 dcs_cmd, enum port port)
>  {
>  	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
> -				 dcs_cmd);
> +				 dcs_cmd, port);
>  }
>  
>  static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
>  					    int channel, u8 *reqdata,
> -					    int reqlen)
> +					    int reqlen, enum port port)
>  {
>  	u16 data;
>  	u8 data_type;
> @@ -282,17 +279,15 @@ static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
>  		BUG();
>  	}
>  
> -	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
> +	return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
>  }
>  
>  static int dsi_read_data_return(struct intel_dsi *intel_dsi,
> -				u8 *buf, int buflen)
> +				u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	int i, len = 0;
>  	u32 data_reg, val;
>  
> @@ -312,13 +307,11 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi,
>  }
>  
>  int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
> -		    u8 *buf, int buflen)
> +		    u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 mask;
>  	int ret;
>  
> @@ -329,7 +322,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  
>  	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
>  
> -	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
> +	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
>  	if (ret)
>  		return ret;
>  
> @@ -337,7 +330,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
>  		DRM_ERROR("Timeout waiting for read data.\n");
>  
> -	ret = dsi_read_data_return(intel_dsi, buf, buflen);
> +	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
>  	if (ret < 0)
>  		return ret;
>  
> @@ -348,13 +341,11 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
>  }
>  
>  int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
> -			u8 *reqdata, int reqlen, u8 *buf, int buflen)
> +		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>  	u32 mask;
>  	int ret;
>  
> @@ -366,7 +357,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
>  	I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
>  
>  	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
> -					       reqlen);
> +					       reqlen, port);
>  	if (ret)
>  		return ret;
>  
> @@ -374,7 +365,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
>  	if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
>  		DRM_ERROR("Timeout waiting for read data.\n");
>  
> -	ret = dsi_read_data_return(intel_dsi, buf, buflen);
> +	ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
>  	if (ret < 0)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
> index 46aa1ac..326a5ac 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
> +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
> @@ -36,77 +36,81 @@
>  #define DPI_LP_MODE_EN	false
>  #define DPI_HS_MODE_EN	true
>  
> -void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
> +void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
> +						enum port port);
>  
>  int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
> -		     const u8 *data, int len);
> +		     const u8 *data, int len, enum port port);
>  
>  int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
> -			 const u8 *data, int len);
> +			 const u8 *data, int len, enum port port);
>  
>  int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
> -		    u8 *buf, int buflen);
> +		    u8 *buf, int buflen, enum port port);
>  
>  int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
> -			u8 *reqdata, int reqlen, u8 *buf, int buflen);
> +		u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
>  
>  int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
>  void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
>  
>  /* XXX: questionable write helpers */
>  static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
> -				     int channel, u8 dcs_cmd)
> +				     int channel, u8 dcs_cmd, enum port port)
>  {
> -	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
> +	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
>  }
>  
>  static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
> -				     int channel, u8 dcs_cmd, u8 param)
> +			int channel, u8 dcs_cmd, u8 param, enum port port)
>  {
>  	u8 buf[2] = { dcs_cmd, param };
> -	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
> +	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
>  }
>  
>  static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
> -					 int channel)
> +					 int channel, enum port port)
>  {
> -	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
> +	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
>  }
>  
>  static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
> -					 int channel, u8 param)
> +					 int channel, u8 param, enum port port)
>  {
> -	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
> +	return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
>  }
>  
>  static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
> -					 int channel, u8 param1, u8 param2)
> +			int channel, u8 param1, u8 param2, enum port port)
>  {
>  	u8 buf[2] = { param1, param2 };
> -	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
> +	return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
>  }
>  
>  /* XXX: questionable read helpers */
>  static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
> -					int channel, u8 *buf, int buflen)
> +			int channel, u8 *buf, int buflen, enum port port)
>  {
> -	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
> +									port);
>  }
>  
>  static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
>  					int channel, u8 param, u8 *buf,
> -					int buflen)
> +					int buflen, enum port port)
>  {
> -	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
> +									port);
>  }
>  
>  static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
>  					int channel, u8 param1, u8 param2,
> -					u8 *buf, int buflen)
> +					u8 *buf, int buflen, enum port port)
>  {
>  	u8 req[2] = { param1, param2 };
>  
> -	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
> +	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
> +									port);
>  }
>  
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f6bdd44..612592f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -94,16 +94,23 @@ static struct gpio_table gtable[] = {
>  	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
>  };
>  
> +static inline enum port intel_dsi_seq_port_to_port(u8 port)
> +{
> +	return port ? PORT_C : PORT_A;
> +}
> +
>  static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  {
>  	u8 type, byte, mode, vc, port;

Please rename this port to seq_port or whatever describes it best.

>  	u16 len;
> +	enum port port_no;

And rename this to port, so "port" really means the hw port all around
the driver.

>  	byte = *data++;
>  	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
>  	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
>  	port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>  
> +	port_no = intel_dsi_seq_port_to_port(port);
>  	/* LP or HS mode */
>  	intel_dsi->hs = mode;
>  
> @@ -115,13 +122,13 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  
>  	switch (type) {
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
> -		dsi_vc_generic_write_0(intel_dsi, vc);
> +		dsi_vc_generic_write_0(intel_dsi, vc, port);

And once you've made the renames above, this and the calls below will
actually use the correct port!

BR,
Jani.

>  		break;
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
> -		dsi_vc_generic_write_1(intel_dsi, vc, *data);
> +		dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
>  		break;
>  	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
> -		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
> +		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
>  		break;
>  	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
>  	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
> @@ -129,19 +136,19 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>  		DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
>  		break;
>  	case MIPI_DSI_GENERIC_LONG_WRITE:
> -		dsi_vc_generic_write(intel_dsi, vc, data, len);
> +		dsi_vc_generic_write(intel_dsi, vc, data, len, port);
>  		break;
>  	case MIPI_DSI_DCS_SHORT_WRITE:
> -		dsi_vc_dcs_write_0(intel_dsi, vc, *data);
> +		dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
>  		break;
>  	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> -		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
> +		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
>  		break;
>  	case MIPI_DSI_DCS_READ:
>  		DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
>  		break;
>  	case MIPI_DSI_DCS_LONG_WRITE:
> -		dsi_vc_dcs_write(intel_dsi, vc, data, len);
> +		dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
>  		break;
>  	}
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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_______________________________________________
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Re: [PATCH 0/9] BYT DSI Dual Link Support

[Jani Nikula]

On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Hi,
>
> These set of patches build on top of the existing DSI Video mode support to
> enable dual link MIPI panels with high resolutions. These patches have been
> tested on a 25x16 panel and works well.

Good job, it's starting to look good. Please go ahead and start
addressing the review comments I made. I've glanced through all the
patches, but I'll still have a more in-depth look.

Thanks,
Jani.


>
> v2: Commit message added to all patches. All review comments of Jani, Nikula
> have been addressed in the second version of patches.
>
> v3: for_each_dsi_port macro used instead of for loop for dual link support
>
> Regards
> Gaurav
>
> Gaurav K Singh (9):
>   drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
>     reg
>   drm/i915: Added port as parameter to the functions which does
>     read/write of DSI Controller
>   drm/i915: Add support for port enable/disable for dual link
>     configuration
>   drm/i915: Pixel Clock changes for DSI dual link
>   drm/i915: Dual link needs Shutdown and Turn on packet for both ports
>   drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
>   drm/i915: MIPI Timings related changes for dual link
>   drm/i915: Update the DSI disable path to support dual link panel
>     disabling
>   drm/i915: Update the DSI enable path to support dual link panel
>     enabling
>
>  drivers/gpu/drm/i915/i915_reg.h            |    5 +
>  drivers/gpu/drm/i915/intel_bios.h          |    3 +-
>  drivers/gpu/drm/i915/intel_dsi.c           |  415 +++++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_dsi.h           |    7 +
>  drivers/gpu/drm/i915/intel_dsi_cmd.c       |  101 ++++---
>  drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +--
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   49 +++-
>  drivers/gpu/drm/i915/intel_dsi_pll.c       |    9 +-
>  8 files changed, 383 insertions(+), 252 deletions(-)
>
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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_______________________________________________
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Re: [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

[Jani Nikula]

On Mon, 01 Dec 2014, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> For Dual Link MIPI Panels, both Port A and Port C should be enabled
>> during the MIPI encoder enabling sequence. Similarly, during the
>> disabling sequence, both ports needs to be disabled.
>>
>> v2: Used for_each_dsi_port macro instead of for loop
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h            |    1 +
>>  drivers/gpu/drm/i915/intel_dsi.c           |   39 +++++++++++++++++++---------
>>  drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 +++++
>>  4 files changed, 36 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index dc03fac..c981f5d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
>> +#define  DUAL_LINK_MODE_SHIFT				26
>>  #define  DUAL_LINK_MODE_MASK				(1 << 26)
>>  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>>  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 693736b..1163a5b 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -108,28 +108,43 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>> +	enum port port;
>>  	u32 temp;
>>  
>> -	/* assert ip_tg_enable signal */
>> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
>> -	temp = temp | intel_dsi->port_bits;
>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>> +
>> +		if (intel_dsi->dual_link) {
>> +			if (port == PORT_A)
>> +				intel_dsi->port_bits |= intel_crtc->pipe ?
>> +					LANE_CONFIGURATION_DUAL_LINK_B :
>> +					LANE_CONFIGURATION_DUAL_LINK_A;
>> +			else
>> +				intel_dsi->port_bits = 0;
>
> It feels wrong to clobber intel_dsi->port_bits here; the old code didn't
> do that either. I think you should either set port_bits somewhere else
> (or remove it altogether), and then modify temp depending on port.
>
> Side note, it seems to me intel_dsi->dual_link is becoming redundant, as
> intel_dsi->ports will have more than one bit set in the dual link
> case. This can be a future cleanup though.

Okay, so it's becoming redundant for checking whether we are using dual
link or not, but it still has it's place for indicating which dual link
mode to use.

BR,
Jani.


>
> BR,
> Jani.
>
>> +		} else
>> +			temp &= ~LANE_CONFIGURATION_MASK;
>> +
>> +		/* assert ip_tg_enable signal */
>> +		temp = temp | intel_dsi->port_bits;
>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>> +	}
>>  }
>>  
>>  static void intel_dsi_port_disable(struct intel_encoder *encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	enum port port;
>>  	u32 temp;
>>  
>> -	/* de-assert ip_tg_enable signal */
>> -	temp = I915_READ(MIPI_PORT_CTRL(port));
>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		/* de-assert ip_tg_enable signal */
>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>> +	}
>>  }
>>  
>>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 7f5d028..f2cc2fc 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -104,6 +104,7 @@ struct intel_dsi {
>>  	u8 clock_stop;
>>  
>>  	u8 escape_clk_div;
>> +	u8 dual_link;
>>  	u32 port_bits;
>>  	u32 bw_timer;
>>  	u32 dphy_reg;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index 612592f..7f1ba58 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -287,6 +287,13 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>  	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>>  	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>  	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>> +	intel_dsi->dual_link = mipi_config->dual_link;
>> +
>> +	if (intel_dsi->dual_link) {
>> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>> +		intel_dsi->port_bits = (intel_dsi->dual_link - 1)
>> +					<< DUAL_LINK_MODE_SHIFT;
>> +	}
>>  
>>  	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>>  		bits_per_pixel = 18;
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
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Re: [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

[Singh, Gaurav K]

On 12/1/2014 6:57 PM, Jani Nikula wrote:
> On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>>
>> v2: Address review comments by Jani
>>      - Added wait time for PLL to be locked.
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi_pll.c |    9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index fa7a6ca..93d8e9a 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>>   
>>   	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>>   
>> +	if (intel_dsi->dual_link)
>> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
>> +
>>   	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>>   		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>>   
>> @@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>>   	tmp |= DSI_PLL_VCO_EN;
>>   	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>>   
>> -	mutex_unlock(&dev_priv->dpio_lock);
>> -
>> -	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
>> +	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
>> +					DSI_PLL_LOCK, 20)) {
>>   		DRM_ERROR("DSI PLL lock failed\n");
>>   		return;
>>   	}
>> +	mutex_unlock(&dev_priv->dpio_lock);
> This hunk seems to be an unrelated change, I think it should be a
> separate patch.
>
> BR,
> Jani.

Sure, will put this change as a separate patch.
>
>>   
>>   	DRM_DEBUG_KMS("DSI PLL locked\n");
>>   }
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

[Singh, Gaurav K]

On 12/1/2014 7:41 PM, Jani Nikula wrote:
> On Mon, 01 Dec 2014, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>> For Dual Link MIPI Panels, both Port A and Port C should be enabled
>>> during the MIPI encoder enabling sequence. Similarly, during the
>>> disabling sequence, both ports needs to be disabled.
>>>
>>> v2: Used for_each_dsi_port macro instead of for loop
>>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h            |    1 +
>>>   drivers/gpu/drm/i915/intel_dsi.c           |   39 +++++++++++++++++++---------
>>>   drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 +++++
>>>   4 files changed, 36 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index dc03fac..c981f5d 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>>>   #define  DPI_ENABLE					(1 << 31) /* A + C */
>>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
>>> +#define  DUAL_LINK_MODE_SHIFT				26
>>>   #define  DUAL_LINK_MODE_MASK				(1 << 26)
>>>   #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>>>   #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>> index 693736b..1163a5b 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>> @@ -108,28 +108,43 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>>   	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>>   	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>>> +	enum port port;
>>>   	u32 temp;
>>>   
>>> -	/* assert ip_tg_enable signal */
>>> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
>>> -	temp = temp | intel_dsi->port_bits;
>>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>>> +
>>> +		if (intel_dsi->dual_link) {
>>> +			if (port == PORT_A)
>>> +				intel_dsi->port_bits |= intel_crtc->pipe ?
>>> +					LANE_CONFIGURATION_DUAL_LINK_B :
>>> +					LANE_CONFIGURATION_DUAL_LINK_A;
>>> +			else
>>> +				intel_dsi->port_bits = 0;
>> It feels wrong to clobber intel_dsi->port_bits here; the old code didn't
>> do that either. I think you should either set port_bits somewhere else
>> (or remove it altogether), and then modify temp depending on port.
>>
>> Side note, it seems to me intel_dsi->dual_link is becoming redundant, as
>> intel_dsi->ports will have more than one bit set in the dual link
>> case. This can be a future cleanup though.
> Okay, so it's becoming redundant for checking whether we are using dual
> link or not, but it still has it's place for indicating which dual link
> mode to use.
>
> BR,
> Jani.
Hi Jani,
I preferred if (intel_dsi->dual_link) than if (intel_dsi->ports ==((1 << 
PORT_A) | (1 << PORT_C))), as it looks more cleaner than the second one.

Regarding port_bits, in the old code for single link DSI panels, this 
variable was always 0, and it did not had any use. But with dual link 
configuration, there are few more register bits which we need to 
configure, since the function name was intel_dsi_port_enable, i thought 
of setting the corresponding mipi port_bits variable in this function 
itself.

With regards,
Gaurav

>
>> BR,
>> Jani.
>>
>>> +		} else
>>> +			temp &= ~LANE_CONFIGURATION_MASK;
>>> +
>>> +		/* assert ip_tg_enable signal */
>>> +		temp = temp | intel_dsi->port_bits;
>>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>>> +	}
>>>   }
>>>   
>>>   static void intel_dsi_port_disable(struct intel_encoder *encoder)
>>>   {
>>>   	struct drm_device *dev = encoder->base.dev;
>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	enum port port;
>>>   	u32 temp;
>>>   
>>> -	/* de-assert ip_tg_enable signal */
>>> -	temp = I915_READ(MIPI_PORT_CTRL(port));
>>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		/* de-assert ip_tg_enable signal */
>>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>>> +	}
>>>   }
>>>   
>>>   static void intel_dsi_device_ready(struct intel_encoder *encoder)
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>> index 7f5d028..f2cc2fc 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>> @@ -104,6 +104,7 @@ struct intel_dsi {
>>>   	u8 clock_stop;
>>>   
>>>   	u8 escape_clk_div;
>>> +	u8 dual_link;
>>>   	u32 port_bits;
>>>   	u32 bw_timer;
>>>   	u32 dphy_reg;
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> index 612592f..7f1ba58 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> @@ -287,6 +287,13 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>   	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>>>   	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>   	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>> +	intel_dsi->dual_link = mipi_config->dual_link;
>>> +
>>> +	if (intel_dsi->dual_link) {
>>> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>> +		intel_dsi->port_bits = (intel_dsi->dual_link - 1)
>>> +					<< DUAL_LINK_MODE_SHIFT;
>>> +	}
>>>   
>>>   	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>>>   		bits_per_pixel = 18;
>>> -- 
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> -- 
>> Jani Nikula, Intel Open Source Technology Center

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Re: [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration

[Jani Nikula]

On Mon, 01 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> On 12/1/2014 7:41 PM, Jani Nikula wrote:
>> On Mon, 01 Dec 2014, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>> On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>>> For Dual Link MIPI Panels, both Port A and Port C should be enabled
>>>> during the MIPI encoder enabling sequence. Similarly, during the
>>>> disabling sequence, both ports needs to be disabled.
>>>>
>>>> v2: Used for_each_dsi_port macro instead of for loop
>>>>
>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/i915_reg.h            |    1 +
>>>>   drivers/gpu/drm/i915/intel_dsi.c           |   39 +++++++++++++++++++---------
>>>>   drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>>>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 +++++
>>>>   4 files changed, 36 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index dc03fac..c981f5d 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -6664,6 +6664,7 @@ enum punit_power_well {
>>>>   #define  DPI_ENABLE					(1 << 31) /* A + C */
>>>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>>>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
>>>> +#define  DUAL_LINK_MODE_SHIFT				26
>>>>   #define  DUAL_LINK_MODE_MASK				(1 << 26)
>>>>   #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>>>>   #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>>> index 693736b..1163a5b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>>> @@ -108,28 +108,43 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>>>   	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>>>   	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>>>> +	enum port port;
>>>>   	u32 temp;
>>>>   
>>>> -	/* assert ip_tg_enable signal */
>>>> -	temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
>>>> -	temp = temp | intel_dsi->port_bits;
>>>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>>>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>>>> +
>>>> +		if (intel_dsi->dual_link) {
>>>> +			if (port == PORT_A)
>>>> +				intel_dsi->port_bits |= intel_crtc->pipe ?
>>>> +					LANE_CONFIGURATION_DUAL_LINK_B :
>>>> +					LANE_CONFIGURATION_DUAL_LINK_A;
>>>> +			else
>>>> +				intel_dsi->port_bits = 0;
>>> It feels wrong to clobber intel_dsi->port_bits here; the old code didn't
>>> do that either. I think you should either set port_bits somewhere else
>>> (or remove it altogether), and then modify temp depending on port.
>>>
>>> Side note, it seems to me intel_dsi->dual_link is becoming redundant, as
>>> intel_dsi->ports will have more than one bit set in the dual link
>>> case. This can be a future cleanup though.
>> Okay, so it's becoming redundant for checking whether we are using dual
>> link or not, but it still has it's place for indicating which dual link
>> mode to use.
>>
>> BR,
>> Jani.
> Hi Jani,
> I preferred if (intel_dsi->dual_link) than if (intel_dsi->ports ==((1 << 
> PORT_A) | (1 << PORT_C))), as it looks more cleaner than the second one.

I was thinking we could add a helper for that, but let's leave it as it
is now.

> Regarding port_bits, in the old code for single link DSI panels, this 
> variable was always 0, and it did not had any use. But with dual link 
> configuration, there are few more register bits which we need to 
> configure, since the function name was intel_dsi_port_enable, i thought 
> of setting the corresponding mipi port_bits variable in this function 
> itself.

Here's my thinking:

If port_bits is (or will be) used in places other than
intel_dsi_port_enable, I think it needs to be set beforehand, because
otherwise the other users will depend on intel_dsi_port_enable having
been called.

On the other hand, if port_bits is not (and will not be) used in other
places, intel_dsi_port_enable has all the information to set
MIPI_PORT_CTRL, and the whole intel_dsi->port_bits field can be removed.

BR,
Jani.



>
> With regards,
> Gaurav
>
>>
>>> BR,
>>> Jani.
>>>
>>>> +		} else
>>>> +			temp &= ~LANE_CONFIGURATION_MASK;
>>>> +
>>>> +		/* assert ip_tg_enable signal */
>>>> +		temp = temp | intel_dsi->port_bits;
>>>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
>>>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>>>> +	}
>>>>   }
>>>>   
>>>>   static void intel_dsi_port_disable(struct intel_encoder *encoder)
>>>>   {
>>>>   	struct drm_device *dev = encoder->base.dev;
>>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>>> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>>> -	enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
>>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>> +	enum port port;
>>>>   	u32 temp;
>>>>   
>>>> -	/* de-assert ip_tg_enable signal */
>>>> -	temp = I915_READ(MIPI_PORT_CTRL(port));
>>>> -	I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>>>> -	POSTING_READ(MIPI_PORT_CTRL(port));
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		/* de-assert ip_tg_enable signal */
>>>> +		temp = I915_READ(MIPI_PORT_CTRL(port));
>>>> +		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
>>>> +		POSTING_READ(MIPI_PORT_CTRL(port));
>>>> +	}
>>>>   }
>>>>   
>>>>   static void intel_dsi_device_ready(struct intel_encoder *encoder)
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>>>> index 7f5d028..f2cc2fc 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>> @@ -104,6 +104,7 @@ struct intel_dsi {
>>>>   	u8 clock_stop;
>>>>   
>>>>   	u8 escape_clk_div;
>>>> +	u8 dual_link;
>>>>   	u32 port_bits;
>>>>   	u32 bw_timer;
>>>>   	u32 dphy_reg;
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> index 612592f..7f1ba58 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> @@ -287,6 +287,13 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>>>   	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
>>>>   	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>>>   	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>>> +	intel_dsi->dual_link = mipi_config->dual_link;
>>>> +
>>>> +	if (intel_dsi->dual_link) {
>>>> +		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
>>>> +		intel_dsi->port_bits = (intel_dsi->dual_link - 1)
>>>> +					<< DUAL_LINK_MODE_SHIFT;
>>>> +	}
>>>>   
>>>>   	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>>>>   		bits_per_pixel = 18;
>>>> -- 
>>>> 1.7.9.5
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>> -- 
>>> Jani Nikula, Intel Open Source Technology Center
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 9/9] drm/i915: Update the DSI enable path to support dual link panel enabling

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK              +1                 365/366              366/366
SNB                                  450/450              450/450
IVB                                  498/498              498/498
BYT                                  289/289              289/289
HSW                                  564/564              564/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 ILK  igt_kms_flip_wf_vblank-ts-check      DMESG_WARN(2, M26)PASS(14, M26M37)      PASS(1, M37)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 0/9] BYT DSI Dual Link Support

[Singh, Gaurav K]

On 12/1/2014 7:17 PM, Jani Nikula wrote:
> On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> Hi,
>>
>> These set of patches build on top of the existing DSI Video mode support to
>> enable dual link MIPI panels with high resolutions. These patches have been
>> tested on a 25x16 panel and works well.
> Good job, it's starting to look good. Please go ahead and start
> addressing the review comments I made. I've glanced through all the
> patches, but I'll still have a more in-depth look.
>
> Thanks,
> Jani.
Hi Jani,

Thanks for the review comments. I have addressed all your review 
comments and have uploaded the new patch set. Please review.

With regards,
Gaurav
>
>> v2: Commit message added to all patches. All review comments of Jani, Nikula
>> have been addressed in the second version of patches.
>>
>> v3: for_each_dsi_port macro used instead of for loop for dual link support
>>
>> Regards
>> Gaurav
>>
>> Gaurav K Singh (9):
>>    drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
>>      reg
>>    drm/i915: Added port as parameter to the functions which does
>>      read/write of DSI Controller
>>    drm/i915: Add support for port enable/disable for dual link
>>      configuration
>>    drm/i915: Pixel Clock changes for DSI dual link
>>    drm/i915: Dual link needs Shutdown and Turn on packet for both ports
>>    drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
>>    drm/i915: MIPI Timings related changes for dual link
>>    drm/i915: Update the DSI disable path to support dual link panel
>>      disabling
>>    drm/i915: Update the DSI enable path to support dual link panel
>>      enabling
>>
>>   drivers/gpu/drm/i915/i915_reg.h            |    5 +
>>   drivers/gpu/drm/i915/intel_bios.h          |    3 +-
>>   drivers/gpu/drm/i915/intel_dsi.c           |  415 +++++++++++++++++-----------
>>   drivers/gpu/drm/i915/intel_dsi.h           |    7 +
>>   drivers/gpu/drm/i915/intel_dsi_cmd.c       |  101 ++++---
>>   drivers/gpu/drm/i915/intel_dsi_cmd.h       |   46 +--
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   49 +++-
>>   drivers/gpu/drm/i915/intel_dsi_pll.c       |    9 +-
>>   8 files changed, 383 insertions(+), 252 deletions(-)
>>
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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