* [PATCH RESCEND v2] target-i386: Intel xsaves
@ 2014-12-03 2:36 ` Wanpeng Li
0 siblings, 0 replies; 4+ messages in thread
From: Wanpeng Li @ 2014-12-03 2:36 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: kvm, qemu-devel, Wanpeng Li
Add xsaves related definition, it also adds corresponding part
to kvm_get/put, and vmstate.
Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
---
v1 -> v2:
* use a subsection instead of bumping the version number.
target-i386/cpu.h | 2 ++
target-i386/kvm.c | 15 +++++++++++++++
target-i386/machine.c | 21 +++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 015f5b5..cff7433 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -389,6 +389,7 @@
#define MSR_VM_HSAVE_PA 0xc0010117
#define MSR_IA32_BNDCFGS 0x00000d90
+#define MSR_IA32_XSS 0x00000da0
#define XSTATE_FP (1ULL << 0)
#define XSTATE_SSE (1ULL << 1)
@@ -1019,6 +1020,7 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
uint64_t xcr0;
+ uint64_t xss;
TPRAccess tpr_access_type;
} CPUX86State;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index ccf36e8..c6fc417 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -80,6 +80,7 @@ static bool has_msr_hv_hypercall;
static bool has_msr_hv_vapic;
static bool has_msr_hv_tsc;
static bool has_msr_mtrr;
+static bool has_msr_xss;
static bool has_msr_architectural_pmu;
static uint32_t num_architectural_pmu_counters;
@@ -826,6 +827,10 @@ static int kvm_get_supported_msrs(KVMState *s)
has_msr_bndcfgs = true;
continue;
}
+ if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
+ has_msr_xss = true;
+ continue;
+ }
}
}
@@ -1224,6 +1229,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_bndcfgs) {
kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
}
+ if (has_msr_xss) {
+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
+ }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1570,6 +1578,10 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_bndcfgs) {
msrs[n++].index = MSR_IA32_BNDCFGS;
}
+ if (has_msr_xss) {
+ msrs[n++].index = MSR_IA32_XSS;
+ }
+
if (!env->tsc_valid) {
msrs[n++].index = MSR_IA32_TSC;
@@ -1717,6 +1729,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_BNDCFGS:
env->msr_bndcfgs = msrs[i].data;
break;
+ case MSR_IA32_XSS:
+ env->xss = msrs[i].data;
+ break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 1c13b14..722d62e 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -687,6 +687,24 @@ static const VMStateDescription vmstate_avx512 = {
}
};
+static bool xss_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->xss != 0;
+}
+
+static const VMStateDescription vmstate_xss = {
+ .name = "cpu/xss",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.xss, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -832,6 +850,9 @@ VMStateDescription vmstate_x86_cpu = {
}, {
.vmsd = &vmstate_avx512,
.needed = avx512_needed,
+ }, {
+ .vmsd = &vmstate_xss,
+ .needed = xss_needed,
} , {
/* empty */
}
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH RESCEND v2] target-i386: Intel xsaves
@ 2014-12-03 2:36 ` Wanpeng Li
0 siblings, 0 replies; 4+ messages in thread
From: Wanpeng Li @ 2014-12-03 2:36 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Wanpeng Li, qemu-devel, kvm
Add xsaves related definition, it also adds corresponding part
to kvm_get/put, and vmstate.
Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
---
v1 -> v2:
* use a subsection instead of bumping the version number.
target-i386/cpu.h | 2 ++
target-i386/kvm.c | 15 +++++++++++++++
target-i386/machine.c | 21 +++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 015f5b5..cff7433 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -389,6 +389,7 @@
#define MSR_VM_HSAVE_PA 0xc0010117
#define MSR_IA32_BNDCFGS 0x00000d90
+#define MSR_IA32_XSS 0x00000da0
#define XSTATE_FP (1ULL << 0)
#define XSTATE_SSE (1ULL << 1)
@@ -1019,6 +1020,7 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
uint64_t xcr0;
+ uint64_t xss;
TPRAccess tpr_access_type;
} CPUX86State;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index ccf36e8..c6fc417 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -80,6 +80,7 @@ static bool has_msr_hv_hypercall;
static bool has_msr_hv_vapic;
static bool has_msr_hv_tsc;
static bool has_msr_mtrr;
+static bool has_msr_xss;
static bool has_msr_architectural_pmu;
static uint32_t num_architectural_pmu_counters;
@@ -826,6 +827,10 @@ static int kvm_get_supported_msrs(KVMState *s)
has_msr_bndcfgs = true;
continue;
}
+ if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
+ has_msr_xss = true;
+ continue;
+ }
}
}
@@ -1224,6 +1229,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_bndcfgs) {
kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
}
+ if (has_msr_xss) {
+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
+ }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1570,6 +1578,10 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_bndcfgs) {
msrs[n++].index = MSR_IA32_BNDCFGS;
}
+ if (has_msr_xss) {
+ msrs[n++].index = MSR_IA32_XSS;
+ }
+
if (!env->tsc_valid) {
msrs[n++].index = MSR_IA32_TSC;
@@ -1717,6 +1729,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_BNDCFGS:
env->msr_bndcfgs = msrs[i].data;
break;
+ case MSR_IA32_XSS:
+ env->xss = msrs[i].data;
+ break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 1c13b14..722d62e 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -687,6 +687,24 @@ static const VMStateDescription vmstate_avx512 = {
}
};
+static bool xss_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->xss != 0;
+}
+
+static const VMStateDescription vmstate_xss = {
+ .name = "cpu/xss",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.xss, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -832,6 +850,9 @@ VMStateDescription vmstate_x86_cpu = {
}, {
.vmsd = &vmstate_avx512,
.needed = avx512_needed,
+ }, {
+ .vmsd = &vmstate_xss,
+ .needed = xss_needed,
} , {
/* empty */
}
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH RESCEND v2] target-i386: Intel xsaves
2014-12-03 2:36 ` [Qemu-devel] " Wanpeng Li
@ 2014-12-03 8:49 ` Paolo Bonzini
-1 siblings, 0 replies; 4+ messages in thread
From: Paolo Bonzini @ 2014-12-03 8:49 UTC (permalink / raw)
To: Wanpeng Li; +Cc: kvm, qemu-devel
On 03/12/2014 03:36, Wanpeng Li wrote:
> Add xsaves related definition, it also adds corresponding part
> to kvm_get/put, and vmstate.
>
> Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
> ---
> v1 -> v2:
> * use a subsection instead of bumping the version number.
>
> target-i386/cpu.h | 2 ++
> target-i386/kvm.c | 15 +++++++++++++++
> target-i386/machine.c | 21 +++++++++++++++++++++
> 3 files changed, 38 insertions(+)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 015f5b5..cff7433 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -389,6 +389,7 @@
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> #define MSR_IA32_BNDCFGS 0x00000d90
> +#define MSR_IA32_XSS 0x00000da0
>
> #define XSTATE_FP (1ULL << 0)
> #define XSTATE_SSE (1ULL << 1)
> @@ -1019,6 +1020,7 @@ typedef struct CPUX86State {
> uint64_t xstate_bv;
>
> uint64_t xcr0;
> + uint64_t xss;
>
> TPRAccess tpr_access_type;
> } CPUX86State;
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index ccf36e8..c6fc417 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -80,6 +80,7 @@ static bool has_msr_hv_hypercall;
> static bool has_msr_hv_vapic;
> static bool has_msr_hv_tsc;
> static bool has_msr_mtrr;
> +static bool has_msr_xss;
>
> static bool has_msr_architectural_pmu;
> static uint32_t num_architectural_pmu_counters;
> @@ -826,6 +827,10 @@ static int kvm_get_supported_msrs(KVMState *s)
> has_msr_bndcfgs = true;
> continue;
> }
> + if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
> + has_msr_xss = true;
> + continue;
> + }
> }
> }
>
> @@ -1224,6 +1229,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
> if (has_msr_bndcfgs) {
> kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
> }
> + if (has_msr_xss) {
> + kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
> + }
> #ifdef TARGET_X86_64
> if (lm_capable_kernel) {
> kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
> @@ -1570,6 +1578,10 @@ static int kvm_get_msrs(X86CPU *cpu)
> if (has_msr_bndcfgs) {
> msrs[n++].index = MSR_IA32_BNDCFGS;
> }
> + if (has_msr_xss) {
> + msrs[n++].index = MSR_IA32_XSS;
> + }
> +
>
> if (!env->tsc_valid) {
> msrs[n++].index = MSR_IA32_TSC;
> @@ -1717,6 +1729,9 @@ static int kvm_get_msrs(X86CPU *cpu)
> case MSR_IA32_BNDCFGS:
> env->msr_bndcfgs = msrs[i].data;
> break;
> + case MSR_IA32_XSS:
> + env->xss = msrs[i].data;
> + break;
> default:
> if (msrs[i].index >= MSR_MC0_CTL &&
> msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 1c13b14..722d62e 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -687,6 +687,24 @@ static const VMStateDescription vmstate_avx512 = {
> }
> };
>
> +static bool xss_needed(void *opaque)
> +{
> + X86CPU *cpu = opaque;
> + CPUX86State *env = &cpu->env;
> +
> + return env->xss != 0;
> +}
> +
> +static const VMStateDescription vmstate_xss = {
> + .name = "cpu/xss",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(env.xss, X86CPU),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> VMStateDescription vmstate_x86_cpu = {
> .name = "cpu",
> .version_id = 12,
> @@ -832,6 +850,9 @@ VMStateDescription vmstate_x86_cpu = {
> }, {
> .vmsd = &vmstate_avx512,
> .needed = avx512_needed,
> + }, {
> + .vmsd = &vmstate_xss,
> + .needed = xss_needed,
> } , {
> /* empty */
> }
>
Thanks, applied to uq/master.
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH RESCEND v2] target-i386: Intel xsaves
@ 2014-12-03 8:49 ` Paolo Bonzini
0 siblings, 0 replies; 4+ messages in thread
From: Paolo Bonzini @ 2014-12-03 8:49 UTC (permalink / raw)
To: Wanpeng Li; +Cc: qemu-devel, kvm
On 03/12/2014 03:36, Wanpeng Li wrote:
> Add xsaves related definition, it also adds corresponding part
> to kvm_get/put, and vmstate.
>
> Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
> ---
> v1 -> v2:
> * use a subsection instead of bumping the version number.
>
> target-i386/cpu.h | 2 ++
> target-i386/kvm.c | 15 +++++++++++++++
> target-i386/machine.c | 21 +++++++++++++++++++++
> 3 files changed, 38 insertions(+)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 015f5b5..cff7433 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -389,6 +389,7 @@
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> #define MSR_IA32_BNDCFGS 0x00000d90
> +#define MSR_IA32_XSS 0x00000da0
>
> #define XSTATE_FP (1ULL << 0)
> #define XSTATE_SSE (1ULL << 1)
> @@ -1019,6 +1020,7 @@ typedef struct CPUX86State {
> uint64_t xstate_bv;
>
> uint64_t xcr0;
> + uint64_t xss;
>
> TPRAccess tpr_access_type;
> } CPUX86State;
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index ccf36e8..c6fc417 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -80,6 +80,7 @@ static bool has_msr_hv_hypercall;
> static bool has_msr_hv_vapic;
> static bool has_msr_hv_tsc;
> static bool has_msr_mtrr;
> +static bool has_msr_xss;
>
> static bool has_msr_architectural_pmu;
> static uint32_t num_architectural_pmu_counters;
> @@ -826,6 +827,10 @@ static int kvm_get_supported_msrs(KVMState *s)
> has_msr_bndcfgs = true;
> continue;
> }
> + if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
> + has_msr_xss = true;
> + continue;
> + }
> }
> }
>
> @@ -1224,6 +1229,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
> if (has_msr_bndcfgs) {
> kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
> }
> + if (has_msr_xss) {
> + kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
> + }
> #ifdef TARGET_X86_64
> if (lm_capable_kernel) {
> kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
> @@ -1570,6 +1578,10 @@ static int kvm_get_msrs(X86CPU *cpu)
> if (has_msr_bndcfgs) {
> msrs[n++].index = MSR_IA32_BNDCFGS;
> }
> + if (has_msr_xss) {
> + msrs[n++].index = MSR_IA32_XSS;
> + }
> +
>
> if (!env->tsc_valid) {
> msrs[n++].index = MSR_IA32_TSC;
> @@ -1717,6 +1729,9 @@ static int kvm_get_msrs(X86CPU *cpu)
> case MSR_IA32_BNDCFGS:
> env->msr_bndcfgs = msrs[i].data;
> break;
> + case MSR_IA32_XSS:
> + env->xss = msrs[i].data;
> + break;
> default:
> if (msrs[i].index >= MSR_MC0_CTL &&
> msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 1c13b14..722d62e 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -687,6 +687,24 @@ static const VMStateDescription vmstate_avx512 = {
> }
> };
>
> +static bool xss_needed(void *opaque)
> +{
> + X86CPU *cpu = opaque;
> + CPUX86State *env = &cpu->env;
> +
> + return env->xss != 0;
> +}
> +
> +static const VMStateDescription vmstate_xss = {
> + .name = "cpu/xss",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(env.xss, X86CPU),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> VMStateDescription vmstate_x86_cpu = {
> .name = "cpu",
> .version_id = 12,
> @@ -832,6 +850,9 @@ VMStateDescription vmstate_x86_cpu = {
> }, {
> .vmsd = &vmstate_avx512,
> .needed = avx512_needed,
> + }, {
> + .vmsd = &vmstate_xss,
> + .needed = xss_needed,
> } , {
> /* empty */
> }
>
Thanks, applied to uq/master.
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-12-03 8:50 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-03 2:36 [PATCH RESCEND v2] target-i386: Intel xsaves Wanpeng Li
2014-12-03 2:36 ` [Qemu-devel] " Wanpeng Li
2014-12-03 8:49 ` Paolo Bonzini
2014-12-03 8:49 ` [Qemu-devel] " Paolo Bonzini
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