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* [U-Boot] [PATCH 5/5] B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
@ 2014-11-13  3:28 shh.xie at gmail.com
  2014-12-05 16:36 ` York Sun
  0 siblings, 1 reply; 2+ messages in thread
From: shh.xie at gmail.com @ 2014-11-13  3:28 UTC (permalink / raw)
  To: u-boot

From: Suresh Gupta <suresh.gupta@freescale.com>

In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 board/freescale/b4860qds/eth_b4860qds.c | 19 ++++++++++
 drivers/net/fm/b4860.c                  | 64 +++++++++++++++++++++++++++++++--
 2 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 595bb4c..501d4b3 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -407,6 +407,25 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			fdt_setprop(fdt, offset, "fixed-link", &f_link,
 				    sizeof(f_link));
 			break;
+		case 0x98: /* XAUI interface */
+			sprintf(alias, "phy_xaui_slot1");
+			fdt_status_okay_by_alias(fdt, alias);
+
+			sprintf(alias, "phy_xaui_slot2");
+			fdt_status_okay_by_alias(fdt, alias);
+			break;
+		case 0x9e: /* XAUI interface */
+		case 0x9a:
+		case 0x93:
+		case 0x91:
+			sprintf(alias, "phy_xaui_slot1");
+			fdt_status_okay_by_alias(fdt, alias);
+			break;
+		case 0x97: /* XAUI interface */
+		case 0xc3:
+			sprintf(alias, "phy_xaui_slot2");
+			fdt_status_okay_by_alias(fdt, alias);
+			break;
 		default:
 			break;
 		}
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 71285a8..eb058c9 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -10,6 +10,7 @@
 #include <asm/io.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_serdes.h>
+#include <hwconfig.h>
 
 u32 port_to_devdisr[] = {
 	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
@@ -46,17 +47,76 @@ void fman_enable_port(enum fm_port port)
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
+#if defined(CONFIG_B4860QDS)
+	u32 serdes2_prtcl;
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	char *buf = NULL;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
 	if (is_device_disabled(port))
 		return PHY_INTERFACE_MODE_NONE;
 
 	/*B4860 has two 10Gig Mac*/
 	if ((port == FM1_10GEC1 || port == FM1_10GEC2)	&&
 	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
-	     (is_serdes_configured(XAUI_FM1_MAC10))	||
+	     #if !defined(CONFIG_B4860QDS)
 	     (is_serdes_configured(XFI_FM1_MAC9))	||
-	     (is_serdes_configured(XFI_FM1_MAC10))))
+	     (is_serdes_configured(XFI_FM1_MAC10))	||
+	     #endif
+	     (is_serdes_configured(XAUI_FM1_MAC10))
+	     ))
 		return PHY_INTERFACE_MODE_XGMII;
 
+#if defined(CONFIG_B4860QDS)
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+	if (serdes2_prtcl) {
+		serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+		switch (serdes2_prtcl) {
+		case 0x80:
+		case 0x81:
+		case 0x82:
+		case 0x83:
+		case 0x84:
+		case 0x85:
+		case 0x86:
+		case 0x87:
+		case 0x88:
+		case 0x89:
+		case 0x8a:
+		case 0x8b:
+		case 0x8c:
+		case 0x8d:
+		case 0x8e:
+		case 0xb1:
+		case 0xb2:
+			/*
+			 * Extract hwconfig from environment since environment
+			 * is not setup yet
+			 */
+			getenv_f("hwconfig", buffer, sizeof(buffer));
+			buf = buffer;
+
+			/* check if XFI interface enable in hwconfig for 10g */
+			if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
+						  "sfp_amc", "sfp", buf)) {
+				if ((port == FM1_10GEC1 ||
+				     port == FM1_10GEC2) &&
+				    ((is_serdes_configured(XFI_FM1_MAC9)) ||
+				    (is_serdes_configured(XFI_FM1_MAC10))))
+					return PHY_INTERFACE_MODE_XGMII;
+				else if ((port == FM1_DTSEC1) ||
+					 (port == FM1_DTSEC2) ||
+					 (port == FM1_DTSEC3) ||
+					 (port == FM1_DTSEC4))
+					return PHY_INTERFACE_MODE_NONE;
+			}
+		}
+	}
+#endif
+
 	/* Fix me need to handle RGMII here first */
 
 	switch (port) {
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* [U-Boot] [PATCH 5/5] B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
  2014-11-13  3:28 [U-Boot] [PATCH 5/5] B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig shh.xie at gmail.com
@ 2014-12-05 16:36 ` York Sun
  0 siblings, 0 replies; 2+ messages in thread
From: York Sun @ 2014-12-05 16:36 UTC (permalink / raw)
  To: u-boot

On 11/12/2014 07:28 PM, shh.xie at gmail.com wrote:
> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
> slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
> Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
> string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
> respectively in hwconfig.
> 
> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> ---

Applied to u-boot-mpc85xx, awaiting upstream.

York

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2014-12-05 16:36 UTC | newest]

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2014-11-13  3:28 [U-Boot] [PATCH 5/5] B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig shh.xie at gmail.com
2014-12-05 16:36 ` York Sun

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