From: leroy christophe <christophe.leroy@c-s.fr> To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Cc: "scottwood@freescale.com" <scottwood@freescale.com>, "paulus@samba.org" <paulus@samba.org>, "mpe@ellerman.id.au" <mpe@ellerman.id.au>, "benh@kernel.crashing.org" <benh@kernel.crashing.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org> Subject: Re: [PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW Date: Tue, 06 Jan 2015 08:03:30 +0100 [thread overview] Message-ID: <54AB88C2.7040901@c-s.fr> (raw) In-Reply-To: <1420481520.25047.15.camel@transmode.se> Le 05/01/2015 19:12, Joakim Tjernlund a écrit : > On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote: >> On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages >> and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW >> >> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches > but got so little time :( > > This is very cool (not sure if there will be a performance gain) but .. I think every saved cycle is worth it. Before I did any modification: * ITLBMiss was 28 instructions. * DTLBMiss was 32 instructions. Now, (No MODULES, no CPU6, no CPU15): * ITLBMiss is 15 instructions * DTLBMiss is 24 instructions >> >> >> diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h >> index caf094a..b4e0c3b 100644 >> --- a/arch/powerpc/include/asm/pgtable-ppc32.h >> +++ b/arch/powerpc/include/asm/pgtable-ppc32.h >> @@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p, >> andc %1,%0,%5\n\ >> or %1,%1,%6\n\ >> /* 0x200 == Extended encoding, bit 22 */ \ >> - /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \ >> + /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \ >> rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \ >> - rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \ >> + rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RO */ \ >> + xori %3,%3,0x200\n \ >> or %1,%3,%1\n\ >> xori %1,%1,0x200\n" >> " stwcx. %1,0,%4\n\ > ... here I expected to loose the existing xori insn instead of adding one? > > Well, I could have xored the PAGE_USER bit instead, but in that case, it is not anymore an 'or' but an 'and' that has to be performed between the bits, and then all other bits must be set to 1, or the result of the 'and' shall be inserted using 'rlwimi'. So it would be more modifications than just adding an xori, and not less instructions. Christophe
WARNING: multiple messages have this Message-ID (diff)
From: leroy christophe <christophe.leroy@c-s.fr> To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "paulus@samba.org" <paulus@samba.org>, "scottwood@freescale.com" <scottwood@freescale.com>, "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org> Subject: Re: [PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW Date: Tue, 06 Jan 2015 08:03:30 +0100 [thread overview] Message-ID: <54AB88C2.7040901@c-s.fr> (raw) In-Reply-To: <1420481520.25047.15.camel@transmode.se> Le 05/01/2015 19:12, Joakim Tjernlund a écrit : > On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote: >> On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages >> and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW >> >> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches > but got so little time :( > > This is very cool (not sure if there will be a performance gain) but .. I think every saved cycle is worth it. Before I did any modification: * ITLBMiss was 28 instructions. * DTLBMiss was 32 instructions. Now, (No MODULES, no CPU6, no CPU15): * ITLBMiss is 15 instructions * DTLBMiss is 24 instructions >> >> >> diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h >> index caf094a..b4e0c3b 100644 >> --- a/arch/powerpc/include/asm/pgtable-ppc32.h >> +++ b/arch/powerpc/include/asm/pgtable-ppc32.h >> @@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p, >> andc %1,%0,%5\n\ >> or %1,%1,%6\n\ >> /* 0x200 == Extended encoding, bit 22 */ \ >> - /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \ >> + /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \ >> rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \ >> - rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \ >> + rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RO */ \ >> + xori %3,%3,0x200\n \ >> or %1,%3,%1\n\ >> xori %1,%1,0x200\n" >> " stwcx. %1,0,%4\n\ > ... here I expected to loose the existing xori insn instead of adding one? > > Well, I could have xored the PAGE_USER bit instead, but in that case, it is not anymore an 'or' but an 'and' that has to be performed between the bits, and then all other bits must be set to 1, or the result of the 'and' shall be inserted using 'rlwimi'. So it would be more modifications than just adding an xori, and not less instructions. Christophe
next prev parent reply other threads:[~2015-01-06 7:03 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-12-22 10:14 [PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW Christophe Leroy 2014-12-22 10:14 ` Christophe Leroy 2015-01-05 18:12 ` Joakim Tjernlund 2015-01-05 18:12 ` Joakim Tjernlund 2015-01-06 7:03 ` leroy christophe [this message] 2015-01-06 7:03 ` leroy christophe 2015-01-06 13:05 ` Joakim Tjernlund 2015-01-06 13:05 ` Joakim Tjernlund 2015-01-07 1:21 ` Scott Wood 2015-01-07 1:21 ` Scott Wood
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