RE: [PATCH] x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits

From: "Wang, Winston L" <winston.l.wang@intel.com>
To: Keir Fraser <keir.xen@gmail.com>, Jan Beulich <JBeulich@novell.com>
Cc: "Liu, Jinsong" <jinsong.liu@intel.com>,
	Dan Magenheimer <dan.magenheimer@oracle.com>,
	"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
	KeirFraser <keir@xen.org>,
	"Jiang, Yunhong" <yunhong.jiang@intel.com>,
	"Dugger, Donald D" <donald.d.dugger@intel.com>,
	"Li, Xin" <xin.li@intel.com>
Subject: RE: [PATCH] x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits
Date: Fri, 15 Apr 2011 07:49:41 -0700	[thread overview]
Message-ID: <54B2EB610B7F1340BB6A0D4CA04A4F100100CBCCAB@orsmsx505.amr.corp.intel.com> (raw)
In-Reply-To: <C9CDB443.1661B%keir.xen@gmail.com>

> -----Original Message-----
> From: Keir Fraser [mailto:keir.xen@gmail.com]
> Sent: Friday, April 15, 2011 12:37 AM
> On 15/04/2011 08:08, "Jan Beulich" <JBeulich@novell.com> wrote:
> 
> >> But the write is actually tsc + 4*(s32)(tmp-tsc), and tmp has 1U<<32
> ORed
> >> into it (because it was read after your second write to the TSC.
> Perhaps we
> >> should just write back the full original tsc and call that good
> enough?
> >
> > Again, note the (s32) cast.
> 
> Oh yes. Still the 4x is weird, and on this path (!TSC_RELIABLE, TSC is
> fully
> writable) we will sync all AP TSCs as they come up anyway. So writing
> back
> the original TSC value is good enough, as far as this matters at all
> (which
> it probably doesn't).
Agree, and new processor use for hot add should be upper 32 bit TSC is writeable, I don't think anyone want use those old ones (old model CPU ID before family [0FH]) which do not support up32 bit TSC write for hot add. 

Winston,